root / exec-all.h @ 14ce26e7
History | View | Annotate | Download (17.3 kB)
1 | d4e8164f | bellard | /*
|
---|---|---|---|
2 | d4e8164f | bellard | * internal execution defines for qemu
|
3 | d4e8164f | bellard | *
|
4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | d4e8164f | bellard | *
|
6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
|
7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
|
9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | d4e8164f | bellard | *
|
11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
|
12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | d4e8164f | bellard | * Lesser General Public License for more details.
|
15 | d4e8164f | bellard | *
|
16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
|
18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | d4e8164f | bellard | */
|
20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
|
22 | b346ff46 | bellard | #define DEBUG_DISAS
|
23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
|
25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
|
27 | 33417e70 | bellard | #define stringify(s) tostring(s)
|
28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
|
30 | 33417e70 | bellard | |
31 | 33417e70 | bellard | #if GCC_MAJOR < 3 |
32 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
|
33 | 33417e70 | bellard | #endif
|
34 | 33417e70 | bellard | |
35 | e2222c39 | bellard | #ifdef __i386__
|
36 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
|
37 | e2222c39 | bellard | #else
|
38 | e2222c39 | bellard | #define REGPARM(n)
|
39 | e2222c39 | bellard | #endif
|
40 | e2222c39 | bellard | |
41 | b346ff46 | bellard | /* is_jmp field values */
|
42 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
43 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
44 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
45 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
46 | b346ff46 | bellard | |
47 | b346ff46 | bellard | struct TranslationBlock;
|
48 | b346ff46 | bellard | |
49 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
|
50 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
51 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
52 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
|
53 | b346ff46 | bellard | |
54 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
55 | b346ff46 | bellard | |
56 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
|
57 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
|
58 | c27004ec | bellard | extern long gen_labels[OPC_BUF_SIZE]; |
59 | c27004ec | bellard | extern int nb_gen_labels; |
60 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
|
61 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
|
62 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
|
63 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
|
64 | b346ff46 | bellard | |
65 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
66 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
67 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
68 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
69 | 9886cc16 | bellard | |
70 | b346ff46 | bellard | #if defined(TARGET_I386)
|
71 | b346ff46 | bellard | |
72 | 33417e70 | bellard | void optimize_flags_init(void); |
73 | d4e8164f | bellard | |
74 | b346ff46 | bellard | #endif
|
75 | b346ff46 | bellard | |
76 | b346ff46 | bellard | extern FILE *logfile;
|
77 | b346ff46 | bellard | extern int loglevel; |
78 | b346ff46 | bellard | |
79 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
80 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
81 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
82 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
83 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
84 | 66e85a21 | bellard | int cpu_restore_state(struct TranslationBlock *tb, |
85 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
86 | 58fe2f10 | bellard | void *puc);
|
87 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
88 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
89 | 58fe2f10 | bellard | int cpu_restore_state_copy(struct TranslationBlock *tb, |
90 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
91 | 58fe2f10 | bellard | void *puc);
|
92 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
93 | b346ff46 | bellard | void cpu_exec_init(void); |
94 | 2e12669a | bellard | int page_unprotect(unsigned long address, unsigned long pc, void *puc); |
95 | 2e12669a | bellard | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
|
96 | 2e12669a | bellard | int is_cpu_write_access);
|
97 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
|
98 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
|
99 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
100 | 2e12669a | bellard | int tlb_set_page(CPUState *env, target_ulong vaddr,
|
101 | 2e12669a | bellard | target_phys_addr_t paddr, int prot,
|
102 | 4390df51 | bellard | int is_user, int is_softmmu); |
103 | d4e8164f | bellard | |
104 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
105 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
106 | d4e8164f | bellard | |
107 | d4e8164f | bellard | #define CODE_GEN_HASH_BITS 15 |
108 | d4e8164f | bellard | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
109 | d4e8164f | bellard | |
110 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
111 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
112 | 4390df51 | bellard | |
113 | d4e8164f | bellard | /* maximum total translate dcode allocated */
|
114 | 4390df51 | bellard | |
115 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
|
116 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
|
117 | 4390df51 | bellard | summary of the ranges:
|
118 | 4390df51 | bellard | |
119 | 4390df51 | bellard | i386 : signed 32 bits
|
120 | 4390df51 | bellard | arm : signed 26 bits
|
121 | 4390df51 | bellard | ppc : signed 24 bits
|
122 | 4390df51 | bellard | sparc : signed 32 bits
|
123 | 4390df51 | bellard | alpha : signed 23 bits
|
124 | 4390df51 | bellard | */
|
125 | 4390df51 | bellard | |
126 | 4390df51 | bellard | #if defined(__alpha__)
|
127 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
128 | 4390df51 | bellard | #elif defined(__powerpc__)
|
129 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
130 | 4390df51 | bellard | #else
|
131 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024) |
132 | 4390df51 | bellard | #endif
|
133 | 4390df51 | bellard | |
134 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
|
135 | d4e8164f | bellard | |
136 | 4390df51 | bellard | /* estimated block size for TB allocation */
|
137 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
|
138 | 4390df51 | bellard | according to the host CPU */
|
139 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
|
140 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
141 | 4390df51 | bellard | #else
|
142 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
143 | 4390df51 | bellard | #endif
|
144 | 4390df51 | bellard | |
145 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
|
146 | 4390df51 | bellard | |
147 | 4390df51 | bellard | #if defined(__powerpc__)
|
148 | 4390df51 | bellard | #define USE_DIRECT_JUMP
|
149 | 4390df51 | bellard | #endif
|
150 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
|
151 | d4e8164f | bellard | #define USE_DIRECT_JUMP
|
152 | d4e8164f | bellard | #endif
|
153 | d4e8164f | bellard | |
154 | d4e8164f | bellard | typedef struct TranslationBlock { |
155 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
|
156 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
|
157 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
158 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
|
159 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
|
160 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
|
161 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
162 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
163 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
164 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
165 | 58fe2f10 | bellard | |
166 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
|
167 | 4390df51 | bellard | struct TranslationBlock *hash_next; /* next matching tb for virtual address */ |
168 | 4390df51 | bellard | /* next matching tb for physical address. */
|
169 | 4390df51 | bellard | struct TranslationBlock *phys_hash_next;
|
170 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
|
171 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
|
172 | 4390df51 | bellard | struct TranslationBlock *page_next[2]; |
173 | 4390df51 | bellard | target_ulong page_addr[2];
|
174 | 4390df51 | bellard | |
175 | d4e8164f | bellard | /* the following data are used to directly call another TB from
|
176 | d4e8164f | bellard | the code of this one. */
|
177 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
178 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
|
179 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
180 | d4e8164f | bellard | #else
|
181 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
182 | d4e8164f | bellard | #endif
|
183 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
|
184 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
|
185 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
|
186 | d4e8164f | bellard | jmp_first */
|
187 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
188 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
|
189 | d4e8164f | bellard | } TranslationBlock; |
190 | d4e8164f | bellard | |
191 | c27004ec | bellard | static inline unsigned int tb_hash_func(target_ulong pc) |
192 | d4e8164f | bellard | { |
193 | d4e8164f | bellard | return pc & (CODE_GEN_HASH_SIZE - 1); |
194 | d4e8164f | bellard | } |
195 | d4e8164f | bellard | |
196 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
197 | 4390df51 | bellard | { |
198 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
199 | 4390df51 | bellard | } |
200 | 4390df51 | bellard | |
201 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
202 | 0124311e | bellard | void tb_flush(CPUState *env);
|
203 | d4e8164f | bellard | void tb_link(TranslationBlock *tb);
|
204 | 4390df51 | bellard | void tb_link_phys(TranslationBlock *tb,
|
205 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
206 | d4e8164f | bellard | |
207 | d4e8164f | bellard | extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
|
208 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
|
209 | d4e8164f | bellard | |
210 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
|
211 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
|
212 | d4e8164f | bellard | |
213 | d4e8164f | bellard | /* find a translation block in the translation cache. If not found,
|
214 | d4e8164f | bellard | return NULL and the pointer to the last element of the list in pptb */
|
215 | d4e8164f | bellard | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
216 | 2e12669a | bellard | target_ulong pc, |
217 | 2e12669a | bellard | target_ulong cs_base, |
218 | d4e8164f | bellard | unsigned int flags) |
219 | d4e8164f | bellard | { |
220 | d4e8164f | bellard | TranslationBlock **ptb, *tb; |
221 | d4e8164f | bellard | unsigned int h; |
222 | d4e8164f | bellard | |
223 | d4e8164f | bellard | h = tb_hash_func(pc); |
224 | d4e8164f | bellard | ptb = &tb_hash[h]; |
225 | d4e8164f | bellard | for(;;) {
|
226 | d4e8164f | bellard | tb = *ptb; |
227 | d4e8164f | bellard | if (!tb)
|
228 | d4e8164f | bellard | break;
|
229 | d4e8164f | bellard | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
|
230 | d4e8164f | bellard | return tb;
|
231 | d4e8164f | bellard | ptb = &tb->hash_next; |
232 | d4e8164f | bellard | } |
233 | d4e8164f | bellard | *pptb = ptb; |
234 | d4e8164f | bellard | return NULL; |
235 | d4e8164f | bellard | } |
236 | d4e8164f | bellard | |
237 | d4e8164f | bellard | |
238 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
|
239 | 4390df51 | bellard | |
240 | 4390df51 | bellard | #if defined(__powerpc__)
|
241 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
242 | d4e8164f | bellard | { |
243 | d4e8164f | bellard | uint32_t val, *ptr; |
244 | d4e8164f | bellard | |
245 | d4e8164f | bellard | /* patch the branch destination */
|
246 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
247 | d4e8164f | bellard | val = *ptr; |
248 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
249 | d4e8164f | bellard | *ptr = val; |
250 | d4e8164f | bellard | /* flush icache */
|
251 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
252 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
253 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
254 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
255 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
256 | d4e8164f | bellard | } |
257 | 4390df51 | bellard | #elif defined(__i386__)
|
258 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
259 | 4390df51 | bellard | { |
260 | 4390df51 | bellard | /* patch the branch destination */
|
261 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
|
262 | 4390df51 | bellard | /* no need to flush icache explicitely */
|
263 | 4390df51 | bellard | } |
264 | 4390df51 | bellard | #endif
|
265 | d4e8164f | bellard | |
266 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
267 | 4cbb86e1 | bellard | int n, unsigned long addr) |
268 | 4cbb86e1 | bellard | { |
269 | 4cbb86e1 | bellard | unsigned long offset; |
270 | 4cbb86e1 | bellard | |
271 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
272 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
273 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
|
274 | 4cbb86e1 | bellard | if (offset != 0xffff) |
275 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
276 | 4cbb86e1 | bellard | } |
277 | 4cbb86e1 | bellard | |
278 | d4e8164f | bellard | #else
|
279 | d4e8164f | bellard | |
280 | d4e8164f | bellard | /* set the jump target */
|
281 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
282 | d4e8164f | bellard | int n, unsigned long addr) |
283 | d4e8164f | bellard | { |
284 | 95f7652d | bellard | tb->tb_next[n] = addr; |
285 | d4e8164f | bellard | } |
286 | d4e8164f | bellard | |
287 | d4e8164f | bellard | #endif
|
288 | d4e8164f | bellard | |
289 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
290 | d4e8164f | bellard | TranslationBlock *tb_next) |
291 | d4e8164f | bellard | { |
292 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
|
293 | cf25629d | bellard | if (!tb->jmp_next[n]) {
|
294 | cf25629d | bellard | /* patch the native jump address */
|
295 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
296 | cf25629d | bellard | |
297 | cf25629d | bellard | /* add in TB jmp circular list */
|
298 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
299 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
|
300 | cf25629d | bellard | } |
301 | d4e8164f | bellard | } |
302 | d4e8164f | bellard | |
303 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
304 | a513fe19 | bellard | |
305 | d4e8164f | bellard | #ifndef offsetof
|
306 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
307 | d4e8164f | bellard | #endif
|
308 | d4e8164f | bellard | |
309 | d549f7d9 | bellard | #if defined(_WIN32)
|
310 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
311 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
312 | d549f7d9 | bellard | #elif defined(__APPLE__)
|
313 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
314 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
315 | d549f7d9 | bellard | #define ASM_NAME(x) "_" #x |
316 | d549f7d9 | bellard | #else
|
317 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
318 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
319 | d549f7d9 | bellard | #define ASM_NAME(x) stringify(x)
|
320 | d549f7d9 | bellard | #endif
|
321 | d549f7d9 | bellard | |
322 | b346ff46 | bellard | #if defined(__powerpc__)
|
323 | b346ff46 | bellard | |
324 | 4390df51 | bellard | /* we patch the jump instruction directly */
|
325 | 9257a9e4 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
|
326 | b346ff46 | bellard | do {\
|
327 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
328 | d549f7d9 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
329 | 9257a9e4 | bellard | ".long 1f\n"\
|
330 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
331 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
332 | 9257a9e4 | bellard | "1:\n");\
|
333 | b346ff46 | bellard | T0 = (long)(tbparam) + (n);\
|
334 | c27004ec | bellard | EIP = (int32_t)eip;\ |
335 | 31e8f3c8 | bellard | EXIT_TB();\ |
336 | b346ff46 | bellard | } while (0) |
337 | b346ff46 | bellard | |
338 | 4cbb86e1 | bellard | #define JUMP_TB2(opname, tbparam, n)\
|
339 | 4cbb86e1 | bellard | do {\
|
340 | d549f7d9 | bellard | asm volatile ("b " ASM_NAME(__op_jmp) #n "\n");\ |
341 | 4390df51 | bellard | } while (0) |
342 | 4390df51 | bellard | |
343 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
|
344 | 4390df51 | bellard | |
345 | 4390df51 | bellard | /* we patch the jump instruction directly */
|
346 | c27004ec | bellard | #define GOTO_TB(opname, n)\
|
347 | c27004ec | bellard | do {\
|
348 | c27004ec | bellard | asm volatile (".section .data\n"\ |
349 | c27004ec | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
350 | c27004ec | bellard | ".long 1f\n"\
|
351 | c27004ec | bellard | ASM_PREVIOUS_SECTION \ |
352 | c27004ec | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
353 | c27004ec | bellard | "1:\n");\
|
354 | c27004ec | bellard | } while (0) |
355 | c27004ec | bellard | |
356 | 4390df51 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
|
357 | 4390df51 | bellard | do {\
|
358 | 67b915a5 | bellard | asm volatile (".section .data\n"\ |
359 | d549f7d9 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
360 | 4390df51 | bellard | ".long 1f\n"\
|
361 | 67b915a5 | bellard | ASM_PREVIOUS_SECTION \ |
362 | d549f7d9 | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
363 | 4390df51 | bellard | "1:\n");\
|
364 | 4390df51 | bellard | T0 = (long)(tbparam) + (n);\
|
365 | c27004ec | bellard | EIP = (int32_t)eip;\ |
366 | 4390df51 | bellard | EXIT_TB();\ |
367 | 4390df51 | bellard | } while (0) |
368 | 4390df51 | bellard | |
369 | 4390df51 | bellard | #define JUMP_TB2(opname, tbparam, n)\
|
370 | 4390df51 | bellard | do {\
|
371 | d549f7d9 | bellard | asm volatile ("jmp " ASM_NAME(__op_jmp) #n "\n");\ |
372 | 4cbb86e1 | bellard | } while (0) |
373 | 4cbb86e1 | bellard | |
374 | b346ff46 | bellard | #else
|
375 | b346ff46 | bellard | |
376 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
|
377 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
|
378 | 9257a9e4 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
|
379 | b346ff46 | bellard | do {\
|
380 | b346ff46 | bellard | static void __attribute__((unused)) *__op_label ## n = &&label ## n;\ |
381 | 2f62b397 | bellard | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
382 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
383 | b346ff46 | bellard | label ## n:\ |
384 | b346ff46 | bellard | T0 = (long)(tbparam) + (n);\
|
385 | c27004ec | bellard | EIP = (int32_t)eip;\ |
386 | 2f62b397 | bellard | dummy_label ## n:\ |
387 | 9621339d | bellard | EXIT_TB();\ |
388 | b346ff46 | bellard | } while (0) |
389 | b346ff46 | bellard | |
390 | 4cbb86e1 | bellard | /* second jump to same destination 'n' */
|
391 | 4cbb86e1 | bellard | #define JUMP_TB2(opname, tbparam, n)\
|
392 | 4cbb86e1 | bellard | do {\
|
393 | 4390df51 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\ |
394 | 4cbb86e1 | bellard | } while (0) |
395 | 4cbb86e1 | bellard | |
396 | b346ff46 | bellard | #endif
|
397 | b346ff46 | bellard | |
398 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
399 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
400 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
401 | 33417e70 | bellard | |
402 | d4e8164f | bellard | #ifdef __powerpc__
|
403 | d4e8164f | bellard | static inline int testandset (int *p) |
404 | d4e8164f | bellard | { |
405 | d4e8164f | bellard | int ret;
|
406 | d4e8164f | bellard | __asm__ __volatile__ ( |
407 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
|
408 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
|
409 | 02e1ec9b | bellard | " bne 1f\n"
|
410 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
|
411 | 02e1ec9b | bellard | " bne- 0b\n"
|
412 | d4e8164f | bellard | "1: "
|
413 | d4e8164f | bellard | : "=&r" (ret)
|
414 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
415 | d4e8164f | bellard | : "cr0", "memory"); |
416 | d4e8164f | bellard | return ret;
|
417 | d4e8164f | bellard | } |
418 | d4e8164f | bellard | #endif
|
419 | d4e8164f | bellard | |
420 | d4e8164f | bellard | #ifdef __i386__
|
421 | d4e8164f | bellard | static inline int testandset (int *p) |
422 | d4e8164f | bellard | { |
423 | d4e8164f | bellard | char ret;
|
424 | d4e8164f | bellard | long int readval; |
425 | d4e8164f | bellard | |
426 | d4e8164f | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
|
427 | d4e8164f | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
428 | d4e8164f | bellard | : "r" (1), "m" (*p), "a" (0) |
429 | d4e8164f | bellard | : "memory");
|
430 | d4e8164f | bellard | return ret;
|
431 | d4e8164f | bellard | } |
432 | d4e8164f | bellard | #endif
|
433 | d4e8164f | bellard | |
434 | bc51c5c9 | bellard | #ifdef __x86_64__
|
435 | bc51c5c9 | bellard | static inline int testandset (int *p) |
436 | bc51c5c9 | bellard | { |
437 | bc51c5c9 | bellard | char ret;
|
438 | bc51c5c9 | bellard | int readval;
|
439 | bc51c5c9 | bellard | |
440 | bc51c5c9 | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
|
441 | bc51c5c9 | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
442 | bc51c5c9 | bellard | : "r" (1), "m" (*p), "a" (0) |
443 | bc51c5c9 | bellard | : "memory");
|
444 | bc51c5c9 | bellard | return ret;
|
445 | bc51c5c9 | bellard | } |
446 | bc51c5c9 | bellard | #endif
|
447 | bc51c5c9 | bellard | |
448 | d4e8164f | bellard | #ifdef __s390__
|
449 | d4e8164f | bellard | static inline int testandset (int *p) |
450 | d4e8164f | bellard | { |
451 | d4e8164f | bellard | int ret;
|
452 | d4e8164f | bellard | |
453 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
454 | d4e8164f | bellard | " jl 0b"
|
455 | d4e8164f | bellard | : "=&d" (ret)
|
456 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
457 | d4e8164f | bellard | : "cc", "memory" ); |
458 | d4e8164f | bellard | return ret;
|
459 | d4e8164f | bellard | } |
460 | d4e8164f | bellard | #endif
|
461 | d4e8164f | bellard | |
462 | d4e8164f | bellard | #ifdef __alpha__
|
463 | 2f87c607 | bellard | static inline int testandset (int *p) |
464 | d4e8164f | bellard | { |
465 | d4e8164f | bellard | int ret;
|
466 | d4e8164f | bellard | unsigned long one; |
467 | d4e8164f | bellard | |
468 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
|
469 | d4e8164f | bellard | " ldl_l %0,%1\n"
|
470 | d4e8164f | bellard | " stl_c %2,%1\n"
|
471 | d4e8164f | bellard | " beq %2,1f\n"
|
472 | d4e8164f | bellard | ".subsection 2\n"
|
473 | d4e8164f | bellard | "1: br 0b\n"
|
474 | d4e8164f | bellard | ".previous"
|
475 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
476 | d4e8164f | bellard | : "m" (*p));
|
477 | d4e8164f | bellard | return ret;
|
478 | d4e8164f | bellard | } |
479 | d4e8164f | bellard | #endif
|
480 | d4e8164f | bellard | |
481 | d4e8164f | bellard | #ifdef __sparc__
|
482 | d4e8164f | bellard | static inline int testandset (int *p) |
483 | d4e8164f | bellard | { |
484 | d4e8164f | bellard | int ret;
|
485 | d4e8164f | bellard | |
486 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
487 | d4e8164f | bellard | : "=r" (ret)
|
488 | d4e8164f | bellard | : "r" (p)
|
489 | d4e8164f | bellard | : "memory");
|
490 | d4e8164f | bellard | |
491 | d4e8164f | bellard | return (ret ? 1 : 0); |
492 | d4e8164f | bellard | } |
493 | d4e8164f | bellard | #endif
|
494 | d4e8164f | bellard | |
495 | a95c6790 | bellard | #ifdef __arm__
|
496 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
497 | a95c6790 | bellard | { |
498 | a95c6790 | bellard | register unsigned int ret; |
499 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
|
500 | a95c6790 | bellard | : "=r"(ret)
|
501 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
502 | a95c6790 | bellard | |
503 | a95c6790 | bellard | return ret;
|
504 | a95c6790 | bellard | } |
505 | a95c6790 | bellard | #endif
|
506 | a95c6790 | bellard | |
507 | 38e584a0 | bellard | #ifdef __mc68000
|
508 | 38e584a0 | bellard | static inline int testandset (int *p) |
509 | 38e584a0 | bellard | { |
510 | 38e584a0 | bellard | char ret;
|
511 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
512 | 38e584a0 | bellard | : "=r" (ret)
|
513 | 38e584a0 | bellard | : "m" (p)
|
514 | 38e584a0 | bellard | : "cc","memory"); |
515 | 38e584a0 | bellard | return ret == 0; |
516 | 38e584a0 | bellard | } |
517 | 38e584a0 | bellard | #endif
|
518 | 38e584a0 | bellard | |
519 | d4e8164f | bellard | typedef int spinlock_t; |
520 | d4e8164f | bellard | |
521 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
522 | d4e8164f | bellard | |
523 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
524 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
525 | d4e8164f | bellard | { |
526 | d4e8164f | bellard | while (testandset(lock));
|
527 | d4e8164f | bellard | } |
528 | d4e8164f | bellard | |
529 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
530 | d4e8164f | bellard | { |
531 | d4e8164f | bellard | *lock = 0;
|
532 | d4e8164f | bellard | } |
533 | d4e8164f | bellard | |
534 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
535 | d4e8164f | bellard | { |
536 | d4e8164f | bellard | return !testandset(lock);
|
537 | d4e8164f | bellard | } |
538 | 3c1cf9fa | bellard | #else
|
539 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
540 | 3c1cf9fa | bellard | { |
541 | 3c1cf9fa | bellard | } |
542 | 3c1cf9fa | bellard | |
543 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
544 | 3c1cf9fa | bellard | { |
545 | 3c1cf9fa | bellard | } |
546 | 3c1cf9fa | bellard | |
547 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
548 | 3c1cf9fa | bellard | { |
549 | 3c1cf9fa | bellard | return 1; |
550 | 3c1cf9fa | bellard | } |
551 | 3c1cf9fa | bellard | #endif
|
552 | d4e8164f | bellard | |
553 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
554 | d4e8164f | bellard | |
555 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
556 | 6e59c1db | bellard | |
557 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
558 | 6e59c1db | bellard | |
559 | c27004ec | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, |
560 | 6e59c1db | bellard | void *retaddr);
|
561 | 6e59c1db | bellard | |
562 | 6e59c1db | bellard | #define ACCESS_TYPE 3 |
563 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
564 | 6e59c1db | bellard | #define env cpu_single_env
|
565 | 6e59c1db | bellard | |
566 | 6e59c1db | bellard | #define DATA_SIZE 1 |
567 | 6e59c1db | bellard | #include "softmmu_header.h" |
568 | 6e59c1db | bellard | |
569 | 6e59c1db | bellard | #define DATA_SIZE 2 |
570 | 6e59c1db | bellard | #include "softmmu_header.h" |
571 | 6e59c1db | bellard | |
572 | 6e59c1db | bellard | #define DATA_SIZE 4 |
573 | 6e59c1db | bellard | #include "softmmu_header.h" |
574 | 6e59c1db | bellard | |
575 | c27004ec | bellard | #define DATA_SIZE 8 |
576 | c27004ec | bellard | #include "softmmu_header.h" |
577 | c27004ec | bellard | |
578 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
579 | 6e59c1db | bellard | #undef MEMSUFFIX
|
580 | 6e59c1db | bellard | #undef env
|
581 | 6e59c1db | bellard | |
582 | 6e59c1db | bellard | #endif
|
583 | 4390df51 | bellard | |
584 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
585 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
586 | 4390df51 | bellard | { |
587 | 4390df51 | bellard | return addr;
|
588 | 4390df51 | bellard | } |
589 | 4390df51 | bellard | #else
|
590 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
591 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
592 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
593 | 4390df51 | bellard | /* XXX: i386 target specific */
|
594 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
595 | 4390df51 | bellard | { |
596 | c27004ec | bellard | int is_user, index, pd;
|
597 | 4390df51 | bellard | |
598 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
599 | 3f5dcc34 | bellard | #if defined(TARGET_I386)
|
600 | 4390df51 | bellard | is_user = ((env->hflags & HF_CPL_MASK) == 3);
|
601 | 3f5dcc34 | bellard | #elif defined (TARGET_PPC)
|
602 | 3f5dcc34 | bellard | is_user = msr_pr; |
603 | e95c8d51 | bellard | #elif defined (TARGET_SPARC)
|
604 | e95c8d51 | bellard | is_user = (env->psrs == 0);
|
605 | 3f5dcc34 | bellard | #else
|
606 | 3f5dcc34 | bellard | #error "Unimplemented !" |
607 | 3f5dcc34 | bellard | #endif
|
608 | 4390df51 | bellard | if (__builtin_expect(env->tlb_read[is_user][index].address !=
|
609 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
610 | c27004ec | bellard | ldub_code(addr); |
611 | c27004ec | bellard | } |
612 | c27004ec | bellard | pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK; |
613 | c27004ec | bellard | if (pd > IO_MEM_ROM) {
|
614 | c27004ec | bellard | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
|
615 | 4390df51 | bellard | } |
616 | 4390df51 | bellard | return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base; |
617 | 4390df51 | bellard | } |
618 | 4390df51 | bellard | #endif |