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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 virtual CPU header
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_I386_H
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21 | 2c0262af | bellard | #define CPU_I386_H
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22 | 2c0262af | bellard | |
23 | 14ce26e7 | bellard | #include "config.h" |
24 | 14ce26e7 | bellard | |
25 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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26 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 64 |
27 | 14ce26e7 | bellard | #else
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28 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
29 | 14ce26e7 | bellard | #endif
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30 | 3cf1e035 | bellard | |
31 | d720b93d | bellard | /* target supports implicit self modifying code */
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32 | d720b93d | bellard | #define TARGET_HAS_SMC
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33 | d720b93d | bellard | /* support for self modifying code even if the modified instruction is
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34 | d720b93d | bellard | close to the modifying instruction */
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35 | d720b93d | bellard | #define TARGET_HAS_PRECISE_SMC
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36 | d720b93d | bellard | |
37 | 2c0262af | bellard | #include "cpu-defs.h" |
38 | 2c0262af | bellard | |
39 | 58fe2f10 | bellard | #if defined(__i386__) && !defined(CONFIG_SOFTMMU)
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40 | 58fe2f10 | bellard | #define USE_CODE_COPY
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41 | 58fe2f10 | bellard | #endif
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42 | 58fe2f10 | bellard | |
43 | 2c0262af | bellard | #define R_EAX 0 |
44 | 2c0262af | bellard | #define R_ECX 1 |
45 | 2c0262af | bellard | #define R_EDX 2 |
46 | 2c0262af | bellard | #define R_EBX 3 |
47 | 2c0262af | bellard | #define R_ESP 4 |
48 | 2c0262af | bellard | #define R_EBP 5 |
49 | 2c0262af | bellard | #define R_ESI 6 |
50 | 2c0262af | bellard | #define R_EDI 7 |
51 | 2c0262af | bellard | |
52 | 2c0262af | bellard | #define R_AL 0 |
53 | 2c0262af | bellard | #define R_CL 1 |
54 | 2c0262af | bellard | #define R_DL 2 |
55 | 2c0262af | bellard | #define R_BL 3 |
56 | 2c0262af | bellard | #define R_AH 4 |
57 | 2c0262af | bellard | #define R_CH 5 |
58 | 2c0262af | bellard | #define R_DH 6 |
59 | 2c0262af | bellard | #define R_BH 7 |
60 | 2c0262af | bellard | |
61 | 2c0262af | bellard | #define R_ES 0 |
62 | 2c0262af | bellard | #define R_CS 1 |
63 | 2c0262af | bellard | #define R_SS 2 |
64 | 2c0262af | bellard | #define R_DS 3 |
65 | 2c0262af | bellard | #define R_FS 4 |
66 | 2c0262af | bellard | #define R_GS 5 |
67 | 2c0262af | bellard | |
68 | 2c0262af | bellard | /* segment descriptor fields */
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69 | 2c0262af | bellard | #define DESC_G_MASK (1 << 23) |
70 | 2c0262af | bellard | #define DESC_B_SHIFT 22 |
71 | 2c0262af | bellard | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
72 | 14ce26e7 | bellard | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
73 | 14ce26e7 | bellard | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
74 | 2c0262af | bellard | #define DESC_AVL_MASK (1 << 20) |
75 | 2c0262af | bellard | #define DESC_P_MASK (1 << 15) |
76 | 2c0262af | bellard | #define DESC_DPL_SHIFT 13 |
77 | 2c0262af | bellard | #define DESC_S_MASK (1 << 12) |
78 | 2c0262af | bellard | #define DESC_TYPE_SHIFT 8 |
79 | 2c0262af | bellard | #define DESC_A_MASK (1 << 8) |
80 | 2c0262af | bellard | |
81 | e670b89e | bellard | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
82 | e670b89e | bellard | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
83 | e670b89e | bellard | #define DESC_R_MASK (1 << 9) /* code: readable */ |
84 | 2c0262af | bellard | |
85 | e670b89e | bellard | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
86 | e670b89e | bellard | #define DESC_W_MASK (1 << 9) /* data: writable */ |
87 | e670b89e | bellard | |
88 | e670b89e | bellard | #define DESC_TSS_BUSY_MASK (1 << 9) |
89 | 2c0262af | bellard | |
90 | 2c0262af | bellard | /* eflags masks */
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91 | 2c0262af | bellard | #define CC_C 0x0001 |
92 | 2c0262af | bellard | #define CC_P 0x0004 |
93 | 2c0262af | bellard | #define CC_A 0x0010 |
94 | 2c0262af | bellard | #define CC_Z 0x0040 |
95 | 2c0262af | bellard | #define CC_S 0x0080 |
96 | 2c0262af | bellard | #define CC_O 0x0800 |
97 | 2c0262af | bellard | |
98 | 2c0262af | bellard | #define TF_SHIFT 8 |
99 | 2c0262af | bellard | #define IOPL_SHIFT 12 |
100 | 2c0262af | bellard | #define VM_SHIFT 17 |
101 | 2c0262af | bellard | |
102 | 2c0262af | bellard | #define TF_MASK 0x00000100 |
103 | 2c0262af | bellard | #define IF_MASK 0x00000200 |
104 | 2c0262af | bellard | #define DF_MASK 0x00000400 |
105 | 2c0262af | bellard | #define IOPL_MASK 0x00003000 |
106 | 2c0262af | bellard | #define NT_MASK 0x00004000 |
107 | 2c0262af | bellard | #define RF_MASK 0x00010000 |
108 | 2c0262af | bellard | #define VM_MASK 0x00020000 |
109 | 2c0262af | bellard | #define AC_MASK 0x00040000 |
110 | 2c0262af | bellard | #define VIF_MASK 0x00080000 |
111 | 2c0262af | bellard | #define VIP_MASK 0x00100000 |
112 | 2c0262af | bellard | #define ID_MASK 0x00200000 |
113 | 2c0262af | bellard | |
114 | 2c0262af | bellard | /* hidden flags - used internally by qemu to represent additionnal cpu
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115 | 2c0262af | bellard | states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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116 | 2c0262af | bellard | using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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117 | 2c0262af | bellard | with eflags. */
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118 | 2c0262af | bellard | /* current cpl */
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119 | 2c0262af | bellard | #define HF_CPL_SHIFT 0 |
120 | 2c0262af | bellard | /* true if soft mmu is being used */
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121 | 2c0262af | bellard | #define HF_SOFTMMU_SHIFT 2 |
122 | 2c0262af | bellard | /* true if hardware interrupts must be disabled for next instruction */
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123 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_SHIFT 3 |
124 | 2c0262af | bellard | /* 16 or 32 segments */
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125 | 2c0262af | bellard | #define HF_CS32_SHIFT 4 |
126 | 2c0262af | bellard | #define HF_SS32_SHIFT 5 |
127 | dc196a57 | bellard | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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128 | 2c0262af | bellard | #define HF_ADDSEG_SHIFT 6 |
129 | 65262d57 | bellard | /* copy of CR0.PE (protected mode) */
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130 | 65262d57 | bellard | #define HF_PE_SHIFT 7 |
131 | 65262d57 | bellard | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
132 | 7eee2a50 | bellard | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
133 | 7eee2a50 | bellard | #define HF_EM_SHIFT 10 |
134 | 7eee2a50 | bellard | #define HF_TS_SHIFT 11 |
135 | 65262d57 | bellard | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
136 | 14ce26e7 | bellard | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
137 | 14ce26e7 | bellard | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
138 | 65262d57 | bellard | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
139 | 2c0262af | bellard | |
140 | 2c0262af | bellard | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
141 | 2c0262af | bellard | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
142 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
143 | 2c0262af | bellard | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
144 | 2c0262af | bellard | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
145 | 2c0262af | bellard | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
146 | 65262d57 | bellard | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
147 | 58fe2f10 | bellard | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
148 | 7eee2a50 | bellard | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
149 | 7eee2a50 | bellard | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
150 | 7eee2a50 | bellard | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
151 | 14ce26e7 | bellard | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
152 | 14ce26e7 | bellard | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
153 | 2c0262af | bellard | |
154 | 2c0262af | bellard | #define CR0_PE_MASK (1 << 0) |
155 | 7eee2a50 | bellard | #define CR0_MP_MASK (1 << 1) |
156 | 7eee2a50 | bellard | #define CR0_EM_MASK (1 << 2) |
157 | 2c0262af | bellard | #define CR0_TS_MASK (1 << 3) |
158 | 2ee73ac3 | bellard | #define CR0_ET_MASK (1 << 4) |
159 | 7eee2a50 | bellard | #define CR0_NE_MASK (1 << 5) |
160 | 2c0262af | bellard | #define CR0_WP_MASK (1 << 16) |
161 | 2c0262af | bellard | #define CR0_AM_MASK (1 << 18) |
162 | 2c0262af | bellard | #define CR0_PG_MASK (1 << 31) |
163 | 2c0262af | bellard | |
164 | 2c0262af | bellard | #define CR4_VME_MASK (1 << 0) |
165 | 2c0262af | bellard | #define CR4_PVI_MASK (1 << 1) |
166 | 2c0262af | bellard | #define CR4_TSD_MASK (1 << 2) |
167 | 2c0262af | bellard | #define CR4_DE_MASK (1 << 3) |
168 | 2c0262af | bellard | #define CR4_PSE_MASK (1 << 4) |
169 | 64a595f2 | bellard | #define CR4_PAE_MASK (1 << 5) |
170 | 64a595f2 | bellard | #define CR4_PGE_MASK (1 << 7) |
171 | 14ce26e7 | bellard | #define CR4_PCE_MASK (1 << 8) |
172 | 14ce26e7 | bellard | #define CR4_OSFXSR_MASK (1 << 9) |
173 | 14ce26e7 | bellard | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
174 | 2c0262af | bellard | |
175 | 2c0262af | bellard | #define PG_PRESENT_BIT 0 |
176 | 2c0262af | bellard | #define PG_RW_BIT 1 |
177 | 2c0262af | bellard | #define PG_USER_BIT 2 |
178 | 2c0262af | bellard | #define PG_PWT_BIT 3 |
179 | 2c0262af | bellard | #define PG_PCD_BIT 4 |
180 | 2c0262af | bellard | #define PG_ACCESSED_BIT 5 |
181 | 2c0262af | bellard | #define PG_DIRTY_BIT 6 |
182 | 2c0262af | bellard | #define PG_PSE_BIT 7 |
183 | 2c0262af | bellard | #define PG_GLOBAL_BIT 8 |
184 | 2c0262af | bellard | |
185 | 2c0262af | bellard | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
186 | 2c0262af | bellard | #define PG_RW_MASK (1 << PG_RW_BIT) |
187 | 2c0262af | bellard | #define PG_USER_MASK (1 << PG_USER_BIT) |
188 | 2c0262af | bellard | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
189 | 2c0262af | bellard | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
190 | 2c0262af | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
191 | 2c0262af | bellard | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
192 | 2c0262af | bellard | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
193 | 2c0262af | bellard | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
194 | 2c0262af | bellard | |
195 | 2c0262af | bellard | #define PG_ERROR_W_BIT 1 |
196 | 2c0262af | bellard | |
197 | 2c0262af | bellard | #define PG_ERROR_P_MASK 0x01 |
198 | 2c0262af | bellard | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
199 | 2c0262af | bellard | #define PG_ERROR_U_MASK 0x04 |
200 | 2c0262af | bellard | #define PG_ERROR_RSVD_MASK 0x08 |
201 | 2c0262af | bellard | |
202 | 2c0262af | bellard | #define MSR_IA32_APICBASE 0x1b |
203 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BSP (1<<8) |
204 | 2c0262af | bellard | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
205 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
206 | 2c0262af | bellard | |
207 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_CS 0x174 |
208 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_ESP 0x175 |
209 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_EIP 0x176 |
210 | 2c0262af | bellard | |
211 | 14ce26e7 | bellard | #define MSR_EFER 0xc0000080 |
212 | 14ce26e7 | bellard | |
213 | 14ce26e7 | bellard | #define MSR_EFER_SCE (1 << 0) |
214 | 14ce26e7 | bellard | #define MSR_EFER_LME (1 << 8) |
215 | 14ce26e7 | bellard | #define MSR_EFER_LMA (1 << 10) |
216 | 14ce26e7 | bellard | #define MSR_EFER_NXE (1 << 11) |
217 | 14ce26e7 | bellard | #define MSR_EFER_FFXSR (1 << 14) |
218 | 14ce26e7 | bellard | |
219 | 14ce26e7 | bellard | #define MSR_STAR 0xc0000081 |
220 | 14ce26e7 | bellard | #define MSR_LSTAR 0xc0000082 |
221 | 14ce26e7 | bellard | #define MSR_CSTAR 0xc0000083 |
222 | 14ce26e7 | bellard | #define MSR_FMASK 0xc0000084 |
223 | 14ce26e7 | bellard | #define MSR_FSBASE 0xc0000100 |
224 | 14ce26e7 | bellard | #define MSR_GSBASE 0xc0000101 |
225 | 14ce26e7 | bellard | #define MSR_KERNELGSBASE 0xc0000102 |
226 | 14ce26e7 | bellard | |
227 | 14ce26e7 | bellard | /* cpuid_features bits */
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228 | 14ce26e7 | bellard | #define CPUID_FP87 (1 << 0) |
229 | 14ce26e7 | bellard | #define CPUID_VME (1 << 1) |
230 | 14ce26e7 | bellard | #define CPUID_DE (1 << 2) |
231 | 14ce26e7 | bellard | #define CPUID_PSE (1 << 3) |
232 | 14ce26e7 | bellard | #define CPUID_TSC (1 << 4) |
233 | 14ce26e7 | bellard | #define CPUID_MSR (1 << 5) |
234 | 14ce26e7 | bellard | #define CPUID_PAE (1 << 6) |
235 | 14ce26e7 | bellard | #define CPUID_MCE (1 << 7) |
236 | 14ce26e7 | bellard | #define CPUID_CX8 (1 << 8) |
237 | 14ce26e7 | bellard | #define CPUID_APIC (1 << 9) |
238 | 14ce26e7 | bellard | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
239 | 14ce26e7 | bellard | #define CPUID_MTRR (1 << 12) |
240 | 14ce26e7 | bellard | #define CPUID_PGE (1 << 13) |
241 | 14ce26e7 | bellard | #define CPUID_MCA (1 << 14) |
242 | 14ce26e7 | bellard | #define CPUID_CMOV (1 << 15) |
243 | 14ce26e7 | bellard | /* ... */
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244 | 14ce26e7 | bellard | #define CPUID_MMX (1 << 23) |
245 | 14ce26e7 | bellard | #define CPUID_FXSR (1 << 24) |
246 | 14ce26e7 | bellard | #define CPUID_SSE (1 << 25) |
247 | 14ce26e7 | bellard | #define CPUID_SSE2 (1 << 26) |
248 | 14ce26e7 | bellard | |
249 | 2c0262af | bellard | #define EXCP00_DIVZ 0 |
250 | 2c0262af | bellard | #define EXCP01_SSTP 1 |
251 | 2c0262af | bellard | #define EXCP02_NMI 2 |
252 | 2c0262af | bellard | #define EXCP03_INT3 3 |
253 | 2c0262af | bellard | #define EXCP04_INTO 4 |
254 | 2c0262af | bellard | #define EXCP05_BOUND 5 |
255 | 2c0262af | bellard | #define EXCP06_ILLOP 6 |
256 | 2c0262af | bellard | #define EXCP07_PREX 7 |
257 | 2c0262af | bellard | #define EXCP08_DBLE 8 |
258 | 2c0262af | bellard | #define EXCP09_XERR 9 |
259 | 2c0262af | bellard | #define EXCP0A_TSS 10 |
260 | 2c0262af | bellard | #define EXCP0B_NOSEG 11 |
261 | 2c0262af | bellard | #define EXCP0C_STACK 12 |
262 | 2c0262af | bellard | #define EXCP0D_GPF 13 |
263 | 2c0262af | bellard | #define EXCP0E_PAGE 14 |
264 | 2c0262af | bellard | #define EXCP10_COPR 16 |
265 | 2c0262af | bellard | #define EXCP11_ALGN 17 |
266 | 2c0262af | bellard | #define EXCP12_MCHK 18 |
267 | 2c0262af | bellard | |
268 | 2c0262af | bellard | enum {
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269 | 2c0262af | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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270 | 2c0262af | bellard | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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271 | d36cd60e | bellard | |
272 | d36cd60e | bellard | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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273 | d36cd60e | bellard | CC_OP_MULW, |
274 | d36cd60e | bellard | CC_OP_MULL, |
275 | 14ce26e7 | bellard | CC_OP_MULQ, |
276 | 2c0262af | bellard | |
277 | 2c0262af | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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278 | 2c0262af | bellard | CC_OP_ADDW, |
279 | 2c0262af | bellard | CC_OP_ADDL, |
280 | 14ce26e7 | bellard | CC_OP_ADDQ, |
281 | 2c0262af | bellard | |
282 | 2c0262af | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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283 | 2c0262af | bellard | CC_OP_ADCW, |
284 | 2c0262af | bellard | CC_OP_ADCL, |
285 | 14ce26e7 | bellard | CC_OP_ADCQ, |
286 | 2c0262af | bellard | |
287 | 2c0262af | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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288 | 2c0262af | bellard | CC_OP_SUBW, |
289 | 2c0262af | bellard | CC_OP_SUBL, |
290 | 14ce26e7 | bellard | CC_OP_SUBQ, |
291 | 2c0262af | bellard | |
292 | 2c0262af | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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293 | 2c0262af | bellard | CC_OP_SBBW, |
294 | 2c0262af | bellard | CC_OP_SBBL, |
295 | 14ce26e7 | bellard | CC_OP_SBBQ, |
296 | 2c0262af | bellard | |
297 | 2c0262af | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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298 | 2c0262af | bellard | CC_OP_LOGICW, |
299 | 2c0262af | bellard | CC_OP_LOGICL, |
300 | 14ce26e7 | bellard | CC_OP_LOGICQ, |
301 | 2c0262af | bellard | |
302 | 2c0262af | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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303 | 2c0262af | bellard | CC_OP_INCW, |
304 | 2c0262af | bellard | CC_OP_INCL, |
305 | 14ce26e7 | bellard | CC_OP_INCQ, |
306 | 2c0262af | bellard | |
307 | 2c0262af | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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308 | 2c0262af | bellard | CC_OP_DECW, |
309 | 2c0262af | bellard | CC_OP_DECL, |
310 | 14ce26e7 | bellard | CC_OP_DECQ, |
311 | 2c0262af | bellard | |
312 | 6b652794 | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
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313 | 2c0262af | bellard | CC_OP_SHLW, |
314 | 2c0262af | bellard | CC_OP_SHLL, |
315 | 14ce26e7 | bellard | CC_OP_SHLQ, |
316 | 2c0262af | bellard | |
317 | 2c0262af | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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318 | 2c0262af | bellard | CC_OP_SARW, |
319 | 2c0262af | bellard | CC_OP_SARL, |
320 | 14ce26e7 | bellard | CC_OP_SARQ, |
321 | 2c0262af | bellard | |
322 | 2c0262af | bellard | CC_OP_NB, |
323 | 2c0262af | bellard | }; |
324 | 2c0262af | bellard | |
325 | 7d3505c5 | bellard | #if (defined(__i386__) || defined(__x86_64__)) && !defined(_BSD)
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326 | 2c0262af | bellard | #define USE_X86LDOUBLE
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327 | 2c0262af | bellard | #endif
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328 | 2c0262af | bellard | |
329 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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330 | 2c0262af | bellard | typedef long double CPU86_LDouble; |
331 | 2c0262af | bellard | #else
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332 | 2c0262af | bellard | typedef double CPU86_LDouble; |
333 | 2c0262af | bellard | #endif
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334 | 2c0262af | bellard | |
335 | 2c0262af | bellard | typedef struct SegmentCache { |
336 | 2c0262af | bellard | uint32_t selector; |
337 | 14ce26e7 | bellard | target_ulong base; |
338 | 2c0262af | bellard | uint32_t limit; |
339 | 2c0262af | bellard | uint32_t flags; |
340 | 2c0262af | bellard | } SegmentCache; |
341 | 2c0262af | bellard | |
342 | 14ce26e7 | bellard | typedef struct { |
343 | 14ce26e7 | bellard | union {
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344 | 14ce26e7 | bellard | uint8_t b[16];
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345 | 14ce26e7 | bellard | uint16_t w[8];
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346 | 14ce26e7 | bellard | uint32_t l[4];
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347 | 14ce26e7 | bellard | uint64_t q[2];
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348 | 14ce26e7 | bellard | } u; |
349 | 14ce26e7 | bellard | } XMMReg; |
350 | 14ce26e7 | bellard | |
351 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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352 | 14ce26e7 | bellard | #define CPU_NB_REGS 16 |
353 | 14ce26e7 | bellard | #else
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354 | 14ce26e7 | bellard | #define CPU_NB_REGS 8 |
355 | 14ce26e7 | bellard | #endif
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356 | 14ce26e7 | bellard | |
357 | 2c0262af | bellard | typedef struct CPUX86State { |
358 | 14ce26e7 | bellard | #if TARGET_LONG_BITS > HOST_LONG_BITS
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359 | 14ce26e7 | bellard | /* temporaries if we cannot store them in host registers */
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360 | 14ce26e7 | bellard | target_ulong t0, t1, t2; |
361 | 14ce26e7 | bellard | #endif
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362 | 14ce26e7 | bellard | |
363 | 2c0262af | bellard | /* standard registers */
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364 | 14ce26e7 | bellard | target_ulong regs[CPU_NB_REGS]; |
365 | 14ce26e7 | bellard | target_ulong eip; |
366 | 14ce26e7 | bellard | target_ulong eflags; /* eflags register. During CPU emulation, CC
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367 | 2c0262af | bellard | flags and DF are set to zero because they are
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368 | 2c0262af | bellard | stored elsewhere */
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369 | 2c0262af | bellard | |
370 | 2c0262af | bellard | /* emulator internal eflags handling */
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371 | 14ce26e7 | bellard | target_ulong cc_src; |
372 | 14ce26e7 | bellard | target_ulong cc_dst; |
373 | 2c0262af | bellard | uint32_t cc_op; |
374 | 2c0262af | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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375 | 2c0262af | bellard | uint32_t hflags; /* hidden flags, see HF_xxx constants */
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376 | 2c0262af | bellard | |
377 | 2c0262af | bellard | /* FPU state */
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378 | 2c0262af | bellard | unsigned int fpstt; /* top of stack index */ |
379 | 2c0262af | bellard | unsigned int fpus; |
380 | 2c0262af | bellard | unsigned int fpuc; |
381 | 2c0262af | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
382 | 7eee2a50 | bellard | CPU86_LDouble fpregs[8];
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383 | 2c0262af | bellard | |
384 | 2c0262af | bellard | /* emulator internal variables */
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385 | 2c0262af | bellard | CPU86_LDouble ft0; |
386 | 2c0262af | bellard | union {
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387 | 2c0262af | bellard | float f;
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388 | 2c0262af | bellard | double d;
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389 | 2c0262af | bellard | int i32;
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390 | 2c0262af | bellard | int64_t i64; |
391 | 2c0262af | bellard | } fp_convert; |
392 | 2c0262af | bellard | |
393 | 2c0262af | bellard | /* segments */
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394 | 2c0262af | bellard | SegmentCache segs[6]; /* selector values */ |
395 | 2c0262af | bellard | SegmentCache ldt; |
396 | 2c0262af | bellard | SegmentCache tr; |
397 | 2c0262af | bellard | SegmentCache gdt; /* only base and limit are used */
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398 | 2c0262af | bellard | SegmentCache idt; /* only base and limit are used */
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399 | 2c0262af | bellard | |
400 | 14ce26e7 | bellard | XMMReg xmm_regs[CPU_NB_REGS]; |
401 | 14ce26e7 | bellard | XMMReg xmm_t0; |
402 | 14ce26e7 | bellard | |
403 | 2c0262af | bellard | /* sysenter registers */
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404 | 2c0262af | bellard | uint32_t sysenter_cs; |
405 | 2c0262af | bellard | uint32_t sysenter_esp; |
406 | 2c0262af | bellard | uint32_t sysenter_eip; |
407 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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408 | 14ce26e7 | bellard | target_ulong efer; |
409 | 14ce26e7 | bellard | target_ulong star; |
410 | 14ce26e7 | bellard | target_ulong lstar; |
411 | 14ce26e7 | bellard | target_ulong cstar; |
412 | 14ce26e7 | bellard | target_ulong fmask; |
413 | 14ce26e7 | bellard | target_ulong kernelgsbase; |
414 | 14ce26e7 | bellard | #endif
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415 | 58fe2f10 | bellard | |
416 | 58fe2f10 | bellard | /* temporary data for USE_CODE_COPY mode */
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417 | 7eee2a50 | bellard | #ifdef USE_CODE_COPY
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418 | 58fe2f10 | bellard | uint32_t tmp0; |
419 | 58fe2f10 | bellard | uint32_t saved_esp; |
420 | 7eee2a50 | bellard | int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
421 | 7eee2a50 | bellard | #endif
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422 | 2c0262af | bellard | |
423 | 2c0262af | bellard | /* exception/interrupt handling */
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424 | 2c0262af | bellard | jmp_buf jmp_env; |
425 | 2c0262af | bellard | int exception_index;
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426 | 2c0262af | bellard | int error_code;
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427 | 2c0262af | bellard | int exception_is_int;
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428 | 2c0262af | bellard | int exception_next_eip;
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429 | 2c0262af | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
430 | 14ce26e7 | bellard | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
431 | 14ce26e7 | bellard | target_ulong dr[8]; /* debug registers */ |
432 | 2c0262af | bellard | int interrupt_request;
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433 | 2c0262af | bellard | int user_mode_only; /* user mode only simulation */ |
434 | 2c0262af | bellard | |
435 | 64a595f2 | bellard | uint32_t a20_mask; |
436 | d720b93d | bellard | |
437 | d720b93d | bellard | /* soft mmu support */
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438 | d720b93d | bellard | /* in order to avoid passing too many arguments to the memory
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439 | d720b93d | bellard | write helpers, we store some rarely used information in the CPU
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440 | d720b93d | bellard | context) */
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441 | d720b93d | bellard | unsigned long mem_write_pc; /* host pc at which the memory was |
442 | d720b93d | bellard | written */
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443 | 14ce26e7 | bellard | target_ulong mem_write_vaddr; /* target virtual addr at which the
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444 | 14ce26e7 | bellard | memory was written */
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445 | 2c0262af | bellard | /* 0 = kernel, 1 = user */
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446 | 2c0262af | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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447 | 2c0262af | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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448 | 2c0262af | bellard | |
449 | ffddfee3 | bellard | /* from this point: preserved by CPU reset */
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450 | 2c0262af | bellard | /* ice debug support */
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451 | 14ce26e7 | bellard | target_ulong breakpoints[MAX_BREAKPOINTS]; |
452 | 2c0262af | bellard | int nb_breakpoints;
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453 | 2c0262af | bellard | int singlestep_enabled;
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454 | 2c0262af | bellard | |
455 | 14ce26e7 | bellard | /* processor features (e.g. for CPUID insn) */
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456 | 14ce26e7 | bellard | uint32_t cpuid_vendor1; |
457 | 14ce26e7 | bellard | uint32_t cpuid_vendor2; |
458 | 14ce26e7 | bellard | uint32_t cpuid_vendor3; |
459 | 14ce26e7 | bellard | uint32_t cpuid_version; |
460 | 14ce26e7 | bellard | uint32_t cpuid_features; |
461 | 14ce26e7 | bellard | |
462 | 14ce26e7 | bellard | /* in order to simplify APIC support, we leave this pointer to the
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463 | 14ce26e7 | bellard | user */
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464 | 14ce26e7 | bellard | struct APICState *apic_state;
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465 | 2c0262af | bellard | /* user data */
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466 | 2c0262af | bellard | void *opaque;
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467 | 2c0262af | bellard | } CPUX86State; |
468 | 2c0262af | bellard | |
469 | 2c0262af | bellard | #ifndef IN_OP_I386
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470 | 2c0262af | bellard | void cpu_x86_outb(CPUX86State *env, int addr, int val); |
471 | 2c0262af | bellard | void cpu_x86_outw(CPUX86State *env, int addr, int val); |
472 | 2c0262af | bellard | void cpu_x86_outl(CPUX86State *env, int addr, int val); |
473 | 2c0262af | bellard | int cpu_x86_inb(CPUX86State *env, int addr); |
474 | 2c0262af | bellard | int cpu_x86_inw(CPUX86State *env, int addr); |
475 | 2c0262af | bellard | int cpu_x86_inl(CPUX86State *env, int addr); |
476 | 2c0262af | bellard | #endif
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477 | 2c0262af | bellard | |
478 | 2c0262af | bellard | CPUX86State *cpu_x86_init(void);
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479 | 2c0262af | bellard | int cpu_x86_exec(CPUX86State *s);
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480 | 2c0262af | bellard | void cpu_x86_close(CPUX86State *s);
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481 | d720b93d | bellard | int cpu_get_pic_interrupt(CPUX86State *s);
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482 | 2ee73ac3 | bellard | /* MSDOS compatibility mode FPU exception support */
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483 | 2ee73ac3 | bellard | void cpu_set_ferr(CPUX86State *s);
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484 | 2c0262af | bellard | |
485 | 2c0262af | bellard | /* this function must always be used to load data in the segment
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486 | 2c0262af | bellard | cache: it synchronizes the hflags with the segment cache values */
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487 | 2c0262af | bellard | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
488 | 2c0262af | bellard | int seg_reg, unsigned int selector, |
489 | 14ce26e7 | bellard | uint32_t base, unsigned int limit, |
490 | 2c0262af | bellard | unsigned int flags) |
491 | 2c0262af | bellard | { |
492 | 2c0262af | bellard | SegmentCache *sc; |
493 | 2c0262af | bellard | unsigned int new_hflags; |
494 | 2c0262af | bellard | |
495 | 2c0262af | bellard | sc = &env->segs[seg_reg]; |
496 | 2c0262af | bellard | sc->selector = selector; |
497 | 2c0262af | bellard | sc->base = base; |
498 | 2c0262af | bellard | sc->limit = limit; |
499 | 2c0262af | bellard | sc->flags = flags; |
500 | 2c0262af | bellard | |
501 | 2c0262af | bellard | /* update the hidden flags */
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502 | 14ce26e7 | bellard | { |
503 | 14ce26e7 | bellard | if (seg_reg == R_CS) {
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504 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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505 | 14ce26e7 | bellard | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
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506 | 14ce26e7 | bellard | /* long mode */
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507 | 14ce26e7 | bellard | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
508 | 14ce26e7 | bellard | env->hflags &= ~(HF_ADDSEG_MASK); |
509 | 14ce26e7 | bellard | } else
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510 | 14ce26e7 | bellard | #endif
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511 | 14ce26e7 | bellard | { |
512 | 14ce26e7 | bellard | /* legacy / compatibility case */
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513 | 14ce26e7 | bellard | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
514 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
515 | 14ce26e7 | bellard | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
516 | 14ce26e7 | bellard | new_hflags; |
517 | 14ce26e7 | bellard | } |
518 | 14ce26e7 | bellard | } |
519 | 14ce26e7 | bellard | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
520 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
521 | 14ce26e7 | bellard | if (env->hflags & HF_CS64_MASK) {
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522 | 14ce26e7 | bellard | /* zero base assumed for DS, ES and SS in long mode */
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523 | 14ce26e7 | bellard | } else if (!(env->cr[0] & CR0_PE_MASK) || |
524 | 14ce26e7 | bellard | (env->eflags & VM_MASK) || |
525 | 14ce26e7 | bellard | !(new_hflags & HF_CS32_MASK)) { |
526 | 14ce26e7 | bellard | /* XXX: try to avoid this test. The problem comes from the
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527 | 14ce26e7 | bellard | fact that is real mode or vm86 mode we only modify the
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528 | 14ce26e7 | bellard | 'base' and 'selector' fields of the segment cache to go
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529 | 14ce26e7 | bellard | faster. A solution may be to force addseg to one in
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530 | 14ce26e7 | bellard | translate-i386.c. */
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531 | 14ce26e7 | bellard | new_hflags |= HF_ADDSEG_MASK; |
532 | 14ce26e7 | bellard | } else {
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533 | 14ce26e7 | bellard | new_hflags |= (((unsigned long)env->segs[R_DS].base | |
534 | 14ce26e7 | bellard | (unsigned long)env->segs[R_ES].base | |
535 | 14ce26e7 | bellard | (unsigned long)env->segs[R_SS].base) != 0) << |
536 | 14ce26e7 | bellard | HF_ADDSEG_SHIFT; |
537 | 14ce26e7 | bellard | } |
538 | 14ce26e7 | bellard | env->hflags = (env->hflags & |
539 | 14ce26e7 | bellard | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
540 | 2c0262af | bellard | } |
541 | 2c0262af | bellard | } |
542 | 2c0262af | bellard | |
543 | 2c0262af | bellard | /* wrapper, just in case memory mappings must be changed */
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544 | 2c0262af | bellard | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
545 | 2c0262af | bellard | { |
546 | 2c0262af | bellard | #if HF_CPL_MASK == 3 |
547 | 2c0262af | bellard | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
548 | 2c0262af | bellard | #else
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549 | 2c0262af | bellard | #error HF_CPL_MASK is hardcoded
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550 | 2c0262af | bellard | #endif
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551 | 2c0262af | bellard | } |
552 | 2c0262af | bellard | |
553 | 1f1af9fd | bellard | /* used for debug or cpu save/restore */
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554 | 1f1af9fd | bellard | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
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555 | 1f1af9fd | bellard | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); |
556 | 1f1af9fd | bellard | |
557 | 2c0262af | bellard | /* the following helpers are only usable in user mode simulation as
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558 | 2c0262af | bellard | they can trigger unexpected exceptions */
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559 | 2c0262af | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
560 | 2c0262af | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); |
561 | 2c0262af | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); |
562 | 2c0262af | bellard | |
563 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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564 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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565 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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566 | 2c0262af | bellard | struct siginfo;
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567 | 2c0262af | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
568 | 2c0262af | bellard | void *puc);
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569 | 461c0471 | bellard | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
570 | 2c0262af | bellard | |
571 | 28ab0e2e | bellard | uint64_t cpu_get_tsc(CPUX86State *env); |
572 | 28ab0e2e | bellard | |
573 | 14ce26e7 | bellard | void cpu_set_apic_base(CPUX86State *env, uint64_t val);
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574 | 14ce26e7 | bellard | uint64_t cpu_get_apic_base(CPUX86State *env); |
575 | 14ce26e7 | bellard | |
576 | 64a595f2 | bellard | /* will be suppressed */
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577 | 64a595f2 | bellard | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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578 | 64a595f2 | bellard | |
579 | 2c0262af | bellard | /* used to debug */
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580 | 2c0262af | bellard | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
581 | 2c0262af | bellard | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
582 | 2c0262af | bellard | |
583 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
584 | 2c0262af | bellard | #include "cpu-all.h" |
585 | 2c0262af | bellard | |
586 | 2c0262af | bellard | #endif /* CPU_I386_H */ |