Revision 14ce26e7 target-i386/cpu.h

b/target-i386/cpu.h
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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25 31
/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
......
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
......
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
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#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
129 139

  
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
......
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
......
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_PGE_MASK  (1 << 7)
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#define CR4_PCE_MASK  (1 << 8)
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#define CR4_OSFXSR_MASK (1 << 9)
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#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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#define PG_PRESENT_BIT	0
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#define PG_RW_BIT	1
......
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_EFER                        0xc0000080
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#define MSR_EFER_SCE   (1 << 0)
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#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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/* cpuid_features bits */
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#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
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#define CPUID_PGE  (1 << 13)
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#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
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/* ... */
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#define CPUID_MMX  (1 << 23)
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#define CPUID_FXSR (1 << 24)
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#define CPUID_SSE  (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define EXCP00_DIVZ	0
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#define EXCP01_SSTP	1
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#define EXCP02_NMI	2
......
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    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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    CC_OP_MULW,
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    CC_OP_MULL,
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    CC_OP_MULQ,
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    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADDW,
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    CC_OP_ADDL,
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    CC_OP_ADDQ,
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    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADCW,
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    CC_OP_ADCL,
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    CC_OP_ADCQ,
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    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUBW,
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    CC_OP_SUBL,
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    CC_OP_SUBQ,
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    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SBBW,
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    CC_OP_SBBL,
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    CC_OP_SBBQ,
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    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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    CC_OP_LOGICW,
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    CC_OP_LOGICL,
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    CC_OP_LOGICQ,
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    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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    CC_OP_INCW,
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    CC_OP_INCL,
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    CC_OP_INCQ,
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    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
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    CC_OP_DECW,
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    CC_OP_DECL,
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    CC_OP_DECQ,
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    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
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    CC_OP_SHLW,
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    CC_OP_SHLL,
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    CC_OP_SHLQ,
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    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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    CC_OP_SARW,
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    CC_OP_SARL,
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    CC_OP_SARQ,
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    CC_OP_NB,
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};
......
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typedef struct SegmentCache {
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    uint32_t selector;
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    uint8_t *base;
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    target_ulong base;
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    uint32_t limit;
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    uint32_t flags;
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} SegmentCache;
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typedef struct {
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    union {
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        uint8_t b[16];
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        uint16_t w[8];
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        uint32_t l[4];
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        uint64_t q[2];
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    } u;
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} XMMReg;
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#ifdef TARGET_X86_64
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#define CPU_NB_REGS 16
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#else
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#define CPU_NB_REGS 8
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#endif
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typedef struct CPUX86State {
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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    /* temporaries if we cannot store them in host registers */
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    target_ulong t0, t1, t2;
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#endif
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    /* standard registers */
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    uint32_t regs[8];
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    uint32_t eip;
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    uint32_t eflags; /* eflags register. During CPU emulation, CC
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    target_ulong regs[CPU_NB_REGS];
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    target_ulong eip;
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    target_ulong eflags; /* eflags register. During CPU emulation, CC
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                        flags and DF are set to zero because they are
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                        stored elsewhere */
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    /* emulator internal eflags handling */
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    uint32_t cc_src;
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    uint32_t cc_dst;
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    target_ulong cc_src;
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    target_ulong cc_dst;
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    uint32_t cc_op;
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    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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    uint32_t hflags; /* hidden flags, see HF_xxx constants */
......
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    SegmentCache gdt; /* only base and limit are used */
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    SegmentCache idt; /* only base and limit are used */
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    XMMReg xmm_regs[CPU_NB_REGS];
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    XMMReg xmm_t0;
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    /* sysenter registers */
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    uint32_t sysenter_cs;
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    uint32_t sysenter_esp;
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    uint32_t sysenter_eip;
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#ifdef TARGET_X86_64
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    target_ulong efer;
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    target_ulong star;
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    target_ulong lstar;
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    target_ulong cstar;
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    target_ulong fmask;
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    target_ulong kernelgsbase;
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#endif
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    /* temporary data for USE_CODE_COPY mode */
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#ifdef USE_CODE_COPY
......
333 427
    int exception_is_int;
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    int exception_next_eip;
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    struct TranslationBlock *current_tb; /* currently executing TB */
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    uint32_t cr[5]; /* NOTE: cr1 is unused */
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    uint32_t dr[8]; /* debug registers */
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    target_ulong cr[5]; /* NOTE: cr1 is unused */
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    target_ulong dr[8]; /* debug registers */
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    int interrupt_request; 
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    int user_mode_only; /* user mode only simulation */
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......
346 440
       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    target_ulong mem_write_vaddr; /* target virtual addr at which the
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                                     memory was written */
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    /* 0 = kernel, 1 = user */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    /* from this point: preserved by CPU reset */
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    /* ice debug support */
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    uint32_t breakpoints[MAX_BREAKPOINTS];
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled;
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    /* processor features (e.g. for CPUID insn) */
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    uint32_t cpuid_vendor1;
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    uint32_t cpuid_vendor2;
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    uint32_t cpuid_vendor3;
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    uint32_t cpuid_version;
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    uint32_t cpuid_features;
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    /* in order to simplify APIC support, we leave this pointer to the
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       user */
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    struct APICState *apic_state;
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    /* user data */
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    void *opaque;
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} CPUX86State;
......
382 486
   cache: it synchronizes the hflags with the segment cache values */
383 487
static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
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                                          int seg_reg, unsigned int selector,
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                                          uint8_t *base, unsigned int limit, 
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                                          uint32_t base, unsigned int limit, 
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                                          unsigned int flags)
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{
388 492
    SegmentCache *sc;
......
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    sc->flags = flags;
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    /* update the hidden flags */
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    new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
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        >> (DESC_B_SHIFT - HF_CS32_SHIFT);
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    new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
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        >> (DESC_B_SHIFT - HF_SS32_SHIFT);
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    if (!(env->cr[0] & CR0_PE_MASK) || 
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        (env->eflags & VM_MASK) ||
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        !(new_hflags & HF_CS32_MASK)) {
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        /* XXX: try to avoid this test. The problem comes from the
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           fact that is real mode or vm86 mode we only modify the
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           'base' and 'selector' fields of the segment cache to go
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           faster. A solution may be to force addseg to one in
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           translate-i386.c. */
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        new_hflags |= HF_ADDSEG_MASK;
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    } else {
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        new_hflags |= (((unsigned long)env->segs[R_DS].base | 
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                        (unsigned long)env->segs[R_ES].base |
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                        (unsigned long)env->segs[R_SS].base) != 0) << 
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            HF_ADDSEG_SHIFT;
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    {
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        if (seg_reg == R_CS) {
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#ifdef TARGET_X86_64
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            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
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                /* long mode */
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                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
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                env->hflags &= ~(HF_ADDSEG_MASK);
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            } else 
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#endif
511
            {
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                /* legacy / compatibility case */
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                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
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                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
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                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
516
                    new_hflags;
517
            }
518
        }
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        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
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            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
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        if (env->hflags & HF_CS64_MASK) {
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            /* zero base assumed for DS, ES and SS in long mode */
523
        } else if (!(env->cr[0] & CR0_PE_MASK) || 
524
            (env->eflags & VM_MASK) ||
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            !(new_hflags & HF_CS32_MASK)) {
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            /* XXX: try to avoid this test. The problem comes from the
527
               fact that is real mode or vm86 mode we only modify the
528
               'base' and 'selector' fields of the segment cache to go
529
               faster. A solution may be to force addseg to one in
530
               translate-i386.c. */
531
            new_hflags |= HF_ADDSEG_MASK;
532
        } else {
533
            new_hflags |= (((unsigned long)env->segs[R_DS].base | 
534
                            (unsigned long)env->segs[R_ES].base |
535
                            (unsigned long)env->segs[R_SS].base) != 0) << 
536
                HF_ADDSEG_SHIFT;
537
        }
538
        env->hflags = (env->hflags & 
539
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
416 540
    }
417
    env->hflags = (env->hflags & 
418
                   ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
419 541
}
420 542

  
421 543
/* wrapper, just in case memory mappings must be changed */
......
448 570

  
449 571
uint64_t cpu_get_tsc(CPUX86State *env);
450 572

  
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void cpu_set_apic_base(CPUX86State *env, uint64_t val);
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uint64_t cpu_get_apic_base(CPUX86State *env);
575

  
451 576
/* will be suppressed */
452 577
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
453 578

  

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