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1
/*
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 * i386 virtual CPU header
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_I386_H
21
#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
30

    
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
34
   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#include "cpu-defs.h"
38

    
39
#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
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#define USE_CODE_COPY
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#endif
42

    
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
84

    
85
#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
87

    
88
#define DESC_TSS_BUSY_MASK (1 << 9)
89

    
90
/* eflags masks */
91
#define CC_C           0x0001
92
#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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102
#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000 
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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114
/* hidden flags - used internally by qemu to represent additionnal cpu
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   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
116
   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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   with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
120
/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
137
#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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140
#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
141
#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
142
#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
144
#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
147
#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
150
#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
152
#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
156
#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
159
#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
162
#define CR0_PG_MASK  (1 << 31)
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164
#define CR4_VME_MASK  (1 << 0)
165
#define CR4_PVI_MASK  (1 << 1)
166
#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
169
#define CR4_PAE_MASK  (1 << 5)
170
#define CR4_PGE_MASK  (1 << 7)
171
#define CR4_PCE_MASK  (1 << 8)
172
#define CR4_OSFXSR_MASK (1 << 9)
173
#define CR4_OSXMMEXCPT_MASK  (1 << 10)
174

    
175
#define PG_PRESENT_BIT        0
176
#define PG_RW_BIT        1
177
#define PG_USER_BIT        2
178
#define PG_PWT_BIT        3
179
#define PG_PCD_BIT        4
180
#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
182
#define PG_PSE_BIT        7
183
#define PG_GLOBAL_BIT        8
184

    
185
#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
187
#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
192
#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
194

    
195
#define PG_ERROR_W_BIT     1
196

    
197
#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
199
#define PG_ERROR_U_MASK    0x04
200
#define PG_ERROR_RSVD_MASK 0x08
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#define MSR_IA32_APICBASE               0x1b
203
#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_EFER                        0xc0000080
212

    
213
#define MSR_EFER_SCE   (1 << 0)
214
#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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227
/* cpuid_features bits */
228
#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
240
#define CPUID_PGE  (1 << 13)
241
#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
243
/* ... */
244
#define CPUID_MMX  (1 << 23)
245
#define CPUID_FXSR (1 << 24)
246
#define CPUID_SSE  (1 << 25)
247
#define CPUID_SSE2 (1 << 26)
248

    
249
#define EXCP00_DIVZ        0
250
#define EXCP01_SSTP        1
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#define EXCP02_NMI        2
252
#define EXCP03_INT3        3
253
#define EXCP04_INTO        4
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#define EXCP05_BOUND        5
255
#define EXCP06_ILLOP        6
256
#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
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#define EXCP09_XERR        9
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#define EXCP0A_TSS        10
260
#define EXCP0B_NOSEG        11
261
#define EXCP0C_STACK        12
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#define EXCP0D_GPF        13
263
#define EXCP0E_PAGE        14
264
#define EXCP10_COPR        16
265
#define EXCP11_ALGN        17
266
#define EXCP12_MCHK        18
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268
enum {
269
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
270
    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
271

    
272
    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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    CC_OP_MULW,
274
    CC_OP_MULL,
275
    CC_OP_MULQ,
276

    
277
    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
278
    CC_OP_ADDW,
279
    CC_OP_ADDL,
280
    CC_OP_ADDQ,
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282
    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
283
    CC_OP_ADCW,
284
    CC_OP_ADCL,
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    CC_OP_ADCQ,
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287
    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
288
    CC_OP_SUBW,
289
    CC_OP_SUBL,
290
    CC_OP_SUBQ,
291

    
292
    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
293
    CC_OP_SBBW,
294
    CC_OP_SBBL,
295
    CC_OP_SBBQ,
296

    
297
    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
298
    CC_OP_LOGICW,
299
    CC_OP_LOGICL,
300
    CC_OP_LOGICQ,
301

    
302
    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
303
    CC_OP_INCW,
304
    CC_OP_INCL,
305
    CC_OP_INCQ,
306

    
307
    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
308
    CC_OP_DECW,
309
    CC_OP_DECL,
310
    CC_OP_DECQ,
311

    
312
    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
313
    CC_OP_SHLW,
314
    CC_OP_SHLL,
315
    CC_OP_SHLQ,
316

    
317
    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
318
    CC_OP_SARW,
319
    CC_OP_SARL,
320
    CC_OP_SARQ,
321

    
322
    CC_OP_NB,
323
};
324

    
325
#if (defined(__i386__) || defined(__x86_64__)) && !defined(_BSD)
326
#define USE_X86LDOUBLE
327
#endif
328

    
329
#ifdef USE_X86LDOUBLE
330
typedef long double CPU86_LDouble;
331
#else
332
typedef double CPU86_LDouble;
333
#endif
334

    
335
typedef struct SegmentCache {
336
    uint32_t selector;
337
    target_ulong base;
338
    uint32_t limit;
339
    uint32_t flags;
340
} SegmentCache;
341

    
342
typedef struct {
343
    union {
344
        uint8_t b[16];
345
        uint16_t w[8];
346
        uint32_t l[4];
347
        uint64_t q[2];
348
    } u;
349
} XMMReg;
350

    
351
#ifdef TARGET_X86_64
352
#define CPU_NB_REGS 16
353
#else
354
#define CPU_NB_REGS 8
355
#endif
356

    
357
typedef struct CPUX86State {
358
#if TARGET_LONG_BITS > HOST_LONG_BITS
359
    /* temporaries if we cannot store them in host registers */
360
    target_ulong t0, t1, t2;
361
#endif
362

    
363
    /* standard registers */
364
    target_ulong regs[CPU_NB_REGS];
365
    target_ulong eip;
366
    target_ulong eflags; /* eflags register. During CPU emulation, CC
367
                        flags and DF are set to zero because they are
368
                        stored elsewhere */
369

    
370
    /* emulator internal eflags handling */
371
    target_ulong cc_src;
372
    target_ulong cc_dst;
373
    uint32_t cc_op;
374
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
375
    uint32_t hflags; /* hidden flags, see HF_xxx constants */
376

    
377
    /* FPU state */
378
    unsigned int fpstt; /* top of stack index */
379
    unsigned int fpus;
380
    unsigned int fpuc;
381
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
382
    CPU86_LDouble fpregs[8];
383

    
384
    /* emulator internal variables */
385
    CPU86_LDouble ft0;
386
    union {
387
        float f;
388
        double d;
389
        int i32;
390
        int64_t i64;
391
    } fp_convert;
392
    
393
    /* segments */
394
    SegmentCache segs[6]; /* selector values */
395
    SegmentCache ldt;
396
    SegmentCache tr;
397
    SegmentCache gdt; /* only base and limit are used */
398
    SegmentCache idt; /* only base and limit are used */
399
    
400
    XMMReg xmm_regs[CPU_NB_REGS];
401
    XMMReg xmm_t0;
402

    
403
    /* sysenter registers */
404
    uint32_t sysenter_cs;
405
    uint32_t sysenter_esp;
406
    uint32_t sysenter_eip;
407
#ifdef TARGET_X86_64
408
    target_ulong efer;
409
    target_ulong star;
410
    target_ulong lstar;
411
    target_ulong cstar;
412
    target_ulong fmask;
413
    target_ulong kernelgsbase;
414
#endif
415

    
416
    /* temporary data for USE_CODE_COPY mode */
417
#ifdef USE_CODE_COPY
418
    uint32_t tmp0;
419
    uint32_t saved_esp;
420
    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
421
#endif
422
    
423
    /* exception/interrupt handling */
424
    jmp_buf jmp_env;
425
    int exception_index;
426
    int error_code;
427
    int exception_is_int;
428
    int exception_next_eip;
429
    struct TranslationBlock *current_tb; /* currently executing TB */
430
    target_ulong cr[5]; /* NOTE: cr1 is unused */
431
    target_ulong dr[8]; /* debug registers */
432
    int interrupt_request; 
433
    int user_mode_only; /* user mode only simulation */
434

    
435
    uint32_t a20_mask;
436

    
437
    /* soft mmu support */
438
    /* in order to avoid passing too many arguments to the memory
439
       write helpers, we store some rarely used information in the CPU
440
       context) */
441
    unsigned long mem_write_pc; /* host pc at which the memory was
442
                                   written */
443
    target_ulong mem_write_vaddr; /* target virtual addr at which the
444
                                     memory was written */
445
    /* 0 = kernel, 1 = user */
446
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
447
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
448
    
449
    /* from this point: preserved by CPU reset */
450
    /* ice debug support */
451
    target_ulong breakpoints[MAX_BREAKPOINTS];
452
    int nb_breakpoints;
453
    int singlestep_enabled;
454

    
455
    /* processor features (e.g. for CPUID insn) */
456
    uint32_t cpuid_vendor1;
457
    uint32_t cpuid_vendor2;
458
    uint32_t cpuid_vendor3;
459
    uint32_t cpuid_version;
460
    uint32_t cpuid_features;
461

    
462
    /* in order to simplify APIC support, we leave this pointer to the
463
       user */
464
    struct APICState *apic_state;
465
    /* user data */
466
    void *opaque;
467
} CPUX86State;
468

    
469
#ifndef IN_OP_I386
470
void cpu_x86_outb(CPUX86State *env, int addr, int val);
471
void cpu_x86_outw(CPUX86State *env, int addr, int val);
472
void cpu_x86_outl(CPUX86State *env, int addr, int val);
473
int cpu_x86_inb(CPUX86State *env, int addr);
474
int cpu_x86_inw(CPUX86State *env, int addr);
475
int cpu_x86_inl(CPUX86State *env, int addr);
476
#endif
477

    
478
CPUX86State *cpu_x86_init(void);
479
int cpu_x86_exec(CPUX86State *s);
480
void cpu_x86_close(CPUX86State *s);
481
int cpu_get_pic_interrupt(CPUX86State *s);
482
/* MSDOS compatibility mode FPU exception support */
483
void cpu_set_ferr(CPUX86State *s);
484

    
485
/* this function must always be used to load data in the segment
486
   cache: it synchronizes the hflags with the segment cache values */
487
static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
488
                                          int seg_reg, unsigned int selector,
489
                                          uint32_t base, unsigned int limit, 
490
                                          unsigned int flags)
491
{
492
    SegmentCache *sc;
493
    unsigned int new_hflags;
494
    
495
    sc = &env->segs[seg_reg];
496
    sc->selector = selector;
497
    sc->base = base;
498
    sc->limit = limit;
499
    sc->flags = flags;
500

    
501
    /* update the hidden flags */
502
    {
503
        if (seg_reg == R_CS) {
504
#ifdef TARGET_X86_64
505
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
506
                /* long mode */
507
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
508
                env->hflags &= ~(HF_ADDSEG_MASK);
509
            } else 
510
#endif
511
            {
512
                /* legacy / compatibility case */
513
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
514
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
515
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
516
                    new_hflags;
517
            }
518
        }
519
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
520
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
521
        if (env->hflags & HF_CS64_MASK) {
522
            /* zero base assumed for DS, ES and SS in long mode */
523
        } else if (!(env->cr[0] & CR0_PE_MASK) || 
524
            (env->eflags & VM_MASK) ||
525
            !(new_hflags & HF_CS32_MASK)) {
526
            /* XXX: try to avoid this test. The problem comes from the
527
               fact that is real mode or vm86 mode we only modify the
528
               'base' and 'selector' fields of the segment cache to go
529
               faster. A solution may be to force addseg to one in
530
               translate-i386.c. */
531
            new_hflags |= HF_ADDSEG_MASK;
532
        } else {
533
            new_hflags |= (((unsigned long)env->segs[R_DS].base | 
534
                            (unsigned long)env->segs[R_ES].base |
535
                            (unsigned long)env->segs[R_SS].base) != 0) << 
536
                HF_ADDSEG_SHIFT;
537
        }
538
        env->hflags = (env->hflags & 
539
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
540
    }
541
}
542

    
543
/* wrapper, just in case memory mappings must be changed */
544
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
545
{
546
#if HF_CPL_MASK == 3
547
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
548
#else
549
#error HF_CPL_MASK is hardcoded
550
#endif
551
}
552

    
553
/* used for debug or cpu save/restore */
554
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
555
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
556

    
557
/* the following helpers are only usable in user mode simulation as
558
   they can trigger unexpected exceptions */
559
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
560
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
561
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
562

    
563
/* you can call this signal handler from your SIGBUS and SIGSEGV
564
   signal handlers to inform the virtual CPU of exceptions. non zero
565
   is returned if the signal was handled by the virtual CPU.  */
566
struct siginfo;
567
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
568
                           void *puc);
569
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
570

    
571
uint64_t cpu_get_tsc(CPUX86State *env);
572

    
573
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
574
uint64_t cpu_get_apic_base(CPUX86State *env);
575

    
576
/* will be suppressed */
577
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
578

    
579
/* used to debug */
580
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
581
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
582

    
583
#define TARGET_PAGE_BITS 12
584
#include "cpu-all.h"
585

    
586
#endif /* CPU_I386_H */