Revision 15656e09 mips-dis.c
| b/mips-dis.c | ||
|---|---|---|
| 565 | 565 |
/* DSP R2 ASE */ |
| 566 | 566 |
#define INSN_DSPR2 0x20000000 |
| 567 | 567 |
|
| 568 |
/* ST Microelectronics Loongson 2E. */ |
|
| 569 |
#define INSN_LOONGSON_2E 0x40000000 |
|
| 570 |
/* ST Microelectronics Loongson 2F. */ |
|
| 571 |
#define INSN_LOONGSON_2F 0x80000000 |
|
| 572 |
|
|
| 568 | 573 |
/* MIPS ISA defines, use instead of hardcoding ISA level. */ |
| 569 | 574 |
|
| 570 | 575 |
#define ISA_UNKNOWN 0 /* Gas internal use. */ |
| ... | ... | |
| 1129 | 1134 |
/* MIPS64 MDMX ASE support. */ |
| 1130 | 1135 |
#define MX INSN_MDMX |
| 1131 | 1136 |
|
| 1137 |
#define IL2E (INSN_LOONGSON_2E) |
|
| 1138 |
#define IL2F (INSN_LOONGSON_2F) |
|
| 1139 |
|
|
| 1132 | 1140 |
#define P3 INSN_4650 |
| 1133 | 1141 |
#define L1 INSN_4010 |
| 1134 | 1142 |
#define V1 (INSN_4100 | INSN_4111 | INSN_4120) |
| ... | ... | |
| 2719 | 2727 |
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
| 2720 | 2728 |
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
| 2721 | 2729 |
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
| 2730 |
/* ST Microelectronics Loongson-2E and -2F. */ |
|
| 2731 |
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
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|
| 2732 |
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2733 |
{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2734 |
{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2735 |
{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2736 |
{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2737 |
{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2738 |
{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2739 |
{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2740 |
{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2741 |
{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2742 |
{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2743 |
{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2744 |
{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2745 |
{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2746 |
{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2747 |
{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2748 |
{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2749 |
{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2750 |
{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2751 |
{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
|
| 2752 |
{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2753 |
{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
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|
| 2754 |
{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
|
| 2722 | 2755 |
}; |
| 2723 | 2756 |
|
| 2724 | 2757 |
#define MIPS_NUM_OPCODES \ |
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