root / tcg / tcg-op.h @ 15824571
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg.h" |
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#ifdef CONFIG_DYNGEN_OP
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/* legacy dyngen operations */
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#include "gen-op.h" |
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#endif
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int gen_new_label(void); |
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static inline void tcg_gen_op1(int opc, TCGv arg1) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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} |
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|
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static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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} |
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|
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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} |
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|
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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|
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static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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*gen_opparam_ptr++ = arg2; |
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} |
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|
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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} |
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|
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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|
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGv arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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} |
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGArg arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, |
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TCGArg arg4) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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} |
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5, TCGv arg6) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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*gen_opparam_ptr++ = GET_TCGV(arg6); |
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} |
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5, TCGArg arg6) |
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{
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void gen_set_label(int n) |
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{
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tcg_gen_op1i(INDEX_op_set_label, n); |
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} |
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static inline void tcg_gen_br(int label) |
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{
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tcg_gen_op1i(INDEX_op_br, label); |
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} |
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg) |
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{
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if (GET_TCGV(ret) != GET_TCGV(arg))
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tcg_gen_op2(INDEX_op_mov_i32, ret, arg); |
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} |
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg) |
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{
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tcg_gen_op2i(INDEX_op_movi_i32, ret, arg); |
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} |
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0 |
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|
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static inline void tcg_gen_helper_0_0(void *func) |
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{
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TCGv t0; |
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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0, NULL, 0, NULL); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg) |
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{
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TCGv t0; |
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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0, NULL, 1, &arg); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2) |
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{
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TCGv args[2];
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TCGv t0; |
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args[0] = arg1;
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args[1] = arg2;
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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0, NULL, 2, args); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_0_3(void *func, |
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TCGv arg1, TCGv arg2, TCGv arg3) |
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{
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TCGv args[3];
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TCGv t0; |
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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0, NULL, 3, args); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4) |
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{
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TCGv args[4];
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TCGv t0; |
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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args[3] = arg4;
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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0, NULL, 4, args); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_1_0(void *func, TCGv ret) |
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{
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TCGv t0; |
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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1, &ret, 0, NULL); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1) |
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{
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TCGv t0; |
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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1, &ret, 1, &arg1); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2) |
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{
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TCGv args[2];
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TCGv t0; |
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args[0] = arg1;
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args[1] = arg2;
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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1, &ret, 2, args); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_1_3(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2, TCGv arg3) |
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{
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TCGv args[3];
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TCGv t0; |
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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1, &ret, 3, args); |
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tcg_temp_free(t0); |
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} |
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static inline void tcg_gen_helper_1_4(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGv arg4) |
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{
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TCGv args[4];
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TCGv t0; |
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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args[3] = arg4;
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t0 = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_call(&tcg_ctx, |
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t0, TCG_HELPER_CALL_FLAGS, |
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1, &ret, 4, args); |
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tcg_temp_free(t0); |
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} |
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|
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/* 32 bit ops */
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|
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset); |
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} |
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|
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset); |
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} |
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|
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset); |
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} |
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|
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset); |
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} |
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|
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset); |
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} |
| 342 |
|
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset); |
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} |
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|
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
|
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tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset); |
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} |
| 352 |
|
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{
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tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset); |
| 356 |
} |
| 357 |
|
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{
|
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tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2); |
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} |
| 362 |
|
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{
|
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/* some cases can be optimized here */
|
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
| 368 |
} else {
|
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TCGv t0 = tcg_const_i32(arg2); |
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tcg_gen_add_i32(ret, arg1, t0); |
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tcg_temp_free(t0); |
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} |
| 373 |
} |
| 374 |
|
| 375 |
static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 376 |
{
|
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tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2); |
| 378 |
} |
| 379 |
|
| 380 |
static inline void tcg_gen_subfi_i32(TCGv ret, int32_t arg1, TCGv arg2) |
| 381 |
{
|
| 382 |
TCGv t0 = tcg_const_i32(arg1); |
| 383 |
tcg_gen_sub_i32(ret, t0, arg2); |
| 384 |
tcg_temp_free(t0); |
| 385 |
} |
| 386 |
|
| 387 |
static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 388 |
{
|
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/* some cases can be optimized here */
|
| 390 |
if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
| 392 |
} else {
|
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TCGv t0 = tcg_const_i32(arg2); |
| 394 |
tcg_gen_sub_i32(ret, arg1, t0); |
| 395 |
tcg_temp_free(t0); |
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} |
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} |
| 398 |
|
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 400 |
{
|
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tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2); |
| 402 |
} |
| 403 |
|
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 405 |
{
|
| 406 |
/* some cases can be optimized here */
|
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if (arg2 == 0) { |
| 408 |
tcg_gen_movi_i32(ret, 0);
|
| 409 |
} else if (arg2 == 0xffffffff) { |
| 410 |
tcg_gen_mov_i32(ret, arg1); |
| 411 |
} else {
|
| 412 |
TCGv t0 = tcg_const_i32(arg2); |
| 413 |
tcg_gen_and_i32(ret, arg1, t0); |
| 414 |
tcg_temp_free(t0); |
| 415 |
} |
| 416 |
} |
| 417 |
|
| 418 |
static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 419 |
{
|
| 420 |
tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2); |
| 421 |
} |
| 422 |
|
| 423 |
static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 424 |
{
|
| 425 |
/* some cases can be optimized here */
|
| 426 |
if (arg2 == 0xffffffff) { |
| 427 |
tcg_gen_movi_i32(ret, 0xffffffff);
|
| 428 |
} else if (arg2 == 0) { |
| 429 |
tcg_gen_mov_i32(ret, arg1); |
| 430 |
} else {
|
| 431 |
TCGv t0 = tcg_const_i32(arg2); |
| 432 |
tcg_gen_or_i32(ret, arg1, t0); |
| 433 |
tcg_temp_free(t0); |
| 434 |
} |
| 435 |
} |
| 436 |
|
| 437 |
static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 438 |
{
|
| 439 |
tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2); |
| 440 |
} |
| 441 |
|
| 442 |
static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 443 |
{
|
| 444 |
/* some cases can be optimized here */
|
| 445 |
if (arg2 == 0) { |
| 446 |
tcg_gen_mov_i32(ret, arg1); |
| 447 |
} else {
|
| 448 |
TCGv t0 = tcg_const_i32(arg2); |
| 449 |
tcg_gen_xor_i32(ret, arg1, t0); |
| 450 |
tcg_temp_free(t0); |
| 451 |
} |
| 452 |
} |
| 453 |
|
| 454 |
static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 455 |
{
|
| 456 |
tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2); |
| 457 |
} |
| 458 |
|
| 459 |
static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 460 |
{
|
| 461 |
if (arg2 == 0) { |
| 462 |
tcg_gen_mov_i32(ret, arg1); |
| 463 |
} else {
|
| 464 |
TCGv t0 = tcg_const_i32(arg2); |
| 465 |
tcg_gen_shl_i32(ret, arg1, t0); |
| 466 |
tcg_temp_free(t0); |
| 467 |
} |
| 468 |
} |
| 469 |
|
| 470 |
static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 471 |
{
|
| 472 |
tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2); |
| 473 |
} |
| 474 |
|
| 475 |
static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 476 |
{
|
| 477 |
if (arg2 == 0) { |
| 478 |
tcg_gen_mov_i32(ret, arg1); |
| 479 |
} else {
|
| 480 |
TCGv t0 = tcg_const_i32(arg2); |
| 481 |
tcg_gen_shr_i32(ret, arg1, t0); |
| 482 |
tcg_temp_free(t0); |
| 483 |
} |
| 484 |
} |
| 485 |
|
| 486 |
static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 487 |
{
|
| 488 |
tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2); |
| 489 |
} |
| 490 |
|
| 491 |
static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 492 |
{
|
| 493 |
if (arg2 == 0) { |
| 494 |
tcg_gen_mov_i32(ret, arg1); |
| 495 |
} else {
|
| 496 |
TCGv t0 = tcg_const_i32(arg2); |
| 497 |
tcg_gen_sar_i32(ret, arg1, t0); |
| 498 |
tcg_temp_free(t0); |
| 499 |
} |
| 500 |
} |
| 501 |
|
| 502 |
static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, |
| 503 |
int label_index)
|
| 504 |
{
|
| 505 |
tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
| 506 |
} |
| 507 |
|
| 508 |
static inline void tcg_gen_brcondi_i32(int cond, TCGv arg1, int32_t arg2, |
| 509 |
int label_index)
|
| 510 |
{
|
| 511 |
TCGv t0 = tcg_const_i32(arg2); |
| 512 |
tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
| 513 |
tcg_temp_free(t0); |
| 514 |
} |
| 515 |
|
| 516 |
static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 517 |
{
|
| 518 |
tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2); |
| 519 |
} |
| 520 |
|
| 521 |
static inline void tcg_gen_muli_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 522 |
{
|
| 523 |
TCGv t0 = tcg_const_i32(arg2); |
| 524 |
tcg_gen_mul_i32(ret, arg1, t0); |
| 525 |
tcg_temp_free(t0); |
| 526 |
} |
| 527 |
|
| 528 |
#ifdef TCG_TARGET_HAS_div_i32
|
| 529 |
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 530 |
{
|
| 531 |
tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2); |
| 532 |
} |
| 533 |
|
| 534 |
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 535 |
{
|
| 536 |
tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2); |
| 537 |
} |
| 538 |
|
| 539 |
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 540 |
{
|
| 541 |
tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2); |
| 542 |
} |
| 543 |
|
| 544 |
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 545 |
{
|
| 546 |
tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2); |
| 547 |
} |
| 548 |
#else
|
| 549 |
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 550 |
{
|
| 551 |
TCGv t0; |
| 552 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 553 |
tcg_gen_sari_i32(t0, arg1, 31);
|
| 554 |
tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
| 555 |
tcg_temp_free(t0); |
| 556 |
} |
| 557 |
|
| 558 |
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 559 |
{
|
| 560 |
TCGv t0; |
| 561 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 562 |
tcg_gen_sari_i32(t0, arg1, 31);
|
| 563 |
tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
| 564 |
tcg_temp_free(t0); |
| 565 |
} |
| 566 |
|
| 567 |
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 568 |
{
|
| 569 |
TCGv t0; |
| 570 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 571 |
tcg_gen_movi_i32(t0, 0);
|
| 572 |
tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
| 573 |
tcg_temp_free(t0); |
| 574 |
} |
| 575 |
|
| 576 |
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 577 |
{
|
| 578 |
TCGv t0; |
| 579 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 580 |
tcg_gen_movi_i32(t0, 0);
|
| 581 |
tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
| 582 |
tcg_temp_free(t0); |
| 583 |
} |
| 584 |
#endif
|
| 585 |
|
| 586 |
#if TCG_TARGET_REG_BITS == 32 |
| 587 |
|
| 588 |
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
| 589 |
{
|
| 590 |
if (GET_TCGV(ret) != GET_TCGV(arg)) {
|
| 591 |
tcg_gen_mov_i32(ret, arg); |
| 592 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 593 |
} |
| 594 |
} |
| 595 |
|
| 596 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
| 597 |
{
|
| 598 |
tcg_gen_movi_i32(ret, arg); |
| 599 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
| 600 |
} |
| 601 |
|
| 602 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 603 |
{
|
| 604 |
tcg_gen_ld8u_i32(ret, arg2, offset); |
| 605 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 606 |
} |
| 607 |
|
| 608 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 609 |
{
|
| 610 |
tcg_gen_ld8s_i32(ret, arg2, offset); |
| 611 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 612 |
} |
| 613 |
|
| 614 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 615 |
{
|
| 616 |
tcg_gen_ld16u_i32(ret, arg2, offset); |
| 617 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 618 |
} |
| 619 |
|
| 620 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 621 |
{
|
| 622 |
tcg_gen_ld16s_i32(ret, arg2, offset); |
| 623 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 624 |
} |
| 625 |
|
| 626 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 627 |
{
|
| 628 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 629 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 630 |
} |
| 631 |
|
| 632 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 633 |
{
|
| 634 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 635 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 636 |
} |
| 637 |
|
| 638 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 639 |
{
|
| 640 |
/* since arg2 and ret have different types, they cannot be the
|
| 641 |
same temporary */
|
| 642 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
| 643 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
| 644 |
tcg_gen_ld_i32(ret, arg2, offset + 4);
|
| 645 |
#else
|
| 646 |
tcg_gen_ld_i32(ret, arg2, offset); |
| 647 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
| 648 |
#endif
|
| 649 |
} |
| 650 |
|
| 651 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 652 |
{
|
| 653 |
tcg_gen_st8_i32(arg1, arg2, offset); |
| 654 |
} |
| 655 |
|
| 656 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 657 |
{
|
| 658 |
tcg_gen_st16_i32(arg1, arg2, offset); |
| 659 |
} |
| 660 |
|
| 661 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 662 |
{
|
| 663 |
tcg_gen_st_i32(arg1, arg2, offset); |
| 664 |
} |
| 665 |
|
| 666 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 667 |
{
|
| 668 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
| 669 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
| 670 |
tcg_gen_st_i32(arg1, arg2, offset + 4);
|
| 671 |
#else
|
| 672 |
tcg_gen_st_i32(arg1, arg2, offset); |
| 673 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
| 674 |
#endif
|
| 675 |
} |
| 676 |
|
| 677 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 678 |
{
|
| 679 |
tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), |
| 680 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
| 681 |
} |
| 682 |
|
| 683 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 684 |
{
|
| 685 |
tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), |
| 686 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
| 687 |
} |
| 688 |
|
| 689 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 690 |
{
|
| 691 |
tcg_gen_and_i32(ret, arg1, arg2); |
| 692 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 693 |
} |
| 694 |
|
| 695 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 696 |
{
|
| 697 |
tcg_gen_andi_i32(ret, arg1, arg2); |
| 698 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 699 |
} |
| 700 |
|
| 701 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 702 |
{
|
| 703 |
tcg_gen_or_i32(ret, arg1, arg2); |
| 704 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 705 |
} |
| 706 |
|
| 707 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 708 |
{
|
| 709 |
tcg_gen_ori_i32(ret, arg1, arg2); |
| 710 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 711 |
} |
| 712 |
|
| 713 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 714 |
{
|
| 715 |
tcg_gen_xor_i32(ret, arg1, arg2); |
| 716 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
| 717 |
} |
| 718 |
|
| 719 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 720 |
{
|
| 721 |
tcg_gen_xori_i32(ret, arg1, arg2); |
| 722 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
| 723 |
} |
| 724 |
|
| 725 |
/* XXX: use generic code when basic block handling is OK or CPU
|
| 726 |
specific code (x86) */
|
| 727 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 728 |
{
|
| 729 |
tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2); |
| 730 |
} |
| 731 |
|
| 732 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 733 |
{
|
| 734 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
| 735 |
} |
| 736 |
|
| 737 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 738 |
{
|
| 739 |
tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2); |
| 740 |
} |
| 741 |
|
| 742 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 743 |
{
|
| 744 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
| 745 |
} |
| 746 |
|
| 747 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 748 |
{
|
| 749 |
tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2); |
| 750 |
} |
| 751 |
|
| 752 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 753 |
{
|
| 754 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
| 755 |
} |
| 756 |
|
| 757 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
| 758 |
int label_index)
|
| 759 |
{
|
| 760 |
tcg_gen_op6ii(INDEX_op_brcond2_i32, |
| 761 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2), |
| 762 |
cond, label_index); |
| 763 |
} |
| 764 |
|
| 765 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 766 |
{
|
| 767 |
TCGv t0, t1; |
| 768 |
|
| 769 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 770 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 771 |
|
| 772 |
tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2); |
| 773 |
|
| 774 |
tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2)); |
| 775 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
| 776 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2); |
| 777 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
| 778 |
|
| 779 |
tcg_gen_mov_i64(ret, t0); |
| 780 |
tcg_temp_free(t0); |
| 781 |
tcg_temp_free(t1); |
| 782 |
} |
| 783 |
|
| 784 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 785 |
{
|
| 786 |
tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2); |
| 787 |
} |
| 788 |
|
| 789 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 790 |
{
|
| 791 |
tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2); |
| 792 |
} |
| 793 |
|
| 794 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 795 |
{
|
| 796 |
tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2); |
| 797 |
} |
| 798 |
|
| 799 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 800 |
{
|
| 801 |
tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2); |
| 802 |
} |
| 803 |
|
| 804 |
#else
|
| 805 |
|
| 806 |
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
| 807 |
{
|
| 808 |
if (GET_TCGV(ret) != GET_TCGV(arg))
|
| 809 |
tcg_gen_op2(INDEX_op_mov_i64, ret, arg); |
| 810 |
} |
| 811 |
|
| 812 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
| 813 |
{
|
| 814 |
tcg_gen_op2i(INDEX_op_movi_i64, ret, arg); |
| 815 |
} |
| 816 |
|
| 817 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, |
| 818 |
tcg_target_long offset) |
| 819 |
{
|
| 820 |
tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset); |
| 821 |
} |
| 822 |
|
| 823 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, |
| 824 |
tcg_target_long offset) |
| 825 |
{
|
| 826 |
tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset); |
| 827 |
} |
| 828 |
|
| 829 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, |
| 830 |
tcg_target_long offset) |
| 831 |
{
|
| 832 |
tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset); |
| 833 |
} |
| 834 |
|
| 835 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, |
| 836 |
tcg_target_long offset) |
| 837 |
{
|
| 838 |
tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset); |
| 839 |
} |
| 840 |
|
| 841 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, |
| 842 |
tcg_target_long offset) |
| 843 |
{
|
| 844 |
tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset); |
| 845 |
} |
| 846 |
|
| 847 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, |
| 848 |
tcg_target_long offset) |
| 849 |
{
|
| 850 |
tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset); |
| 851 |
} |
| 852 |
|
| 853 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
| 854 |
{
|
| 855 |
tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset); |
| 856 |
} |
| 857 |
|
| 858 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, |
| 859 |
tcg_target_long offset) |
| 860 |
{
|
| 861 |
tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset); |
| 862 |
} |
| 863 |
|
| 864 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, |
| 865 |
tcg_target_long offset) |
| 866 |
{
|
| 867 |
tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset); |
| 868 |
} |
| 869 |
|
| 870 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, |
| 871 |
tcg_target_long offset) |
| 872 |
{
|
| 873 |
tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset); |
| 874 |
} |
| 875 |
|
| 876 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
| 877 |
{
|
| 878 |
tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset); |
| 879 |
} |
| 880 |
|
| 881 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 882 |
{
|
| 883 |
tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2); |
| 884 |
} |
| 885 |
|
| 886 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 887 |
{
|
| 888 |
tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2); |
| 889 |
} |
| 890 |
|
| 891 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 892 |
{
|
| 893 |
tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2); |
| 894 |
} |
| 895 |
|
| 896 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 897 |
{
|
| 898 |
TCGv t0 = tcg_const_i64(arg2); |
| 899 |
tcg_gen_and_i64(ret, arg1, t0); |
| 900 |
tcg_temp_free(t0); |
| 901 |
} |
| 902 |
|
| 903 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 904 |
{
|
| 905 |
tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2); |
| 906 |
} |
| 907 |
|
| 908 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 909 |
{
|
| 910 |
TCGv t0 = tcg_const_i64(arg2); |
| 911 |
tcg_gen_or_i64(ret, arg1, t0); |
| 912 |
tcg_temp_free(t0); |
| 913 |
} |
| 914 |
|
| 915 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 916 |
{
|
| 917 |
tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2); |
| 918 |
} |
| 919 |
|
| 920 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 921 |
{
|
| 922 |
TCGv t0 = tcg_const_i64(arg2); |
| 923 |
tcg_gen_xor_i64(ret, arg1, t0); |
| 924 |
tcg_temp_free(t0); |
| 925 |
} |
| 926 |
|
| 927 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 928 |
{
|
| 929 |
tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2); |
| 930 |
} |
| 931 |
|
| 932 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 933 |
{
|
| 934 |
if (arg2 == 0) { |
| 935 |
tcg_gen_mov_i64(ret, arg1); |
| 936 |
} else {
|
| 937 |
TCGv t0 = tcg_const_i64(arg2); |
| 938 |
tcg_gen_shl_i64(ret, arg1, t0); |
| 939 |
tcg_temp_free(t0); |
| 940 |
} |
| 941 |
} |
| 942 |
|
| 943 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 944 |
{
|
| 945 |
tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2); |
| 946 |
} |
| 947 |
|
| 948 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 949 |
{
|
| 950 |
if (arg2 == 0) { |
| 951 |
tcg_gen_mov_i64(ret, arg1); |
| 952 |
} else {
|
| 953 |
TCGv t0 = tcg_const_i64(arg2); |
| 954 |
tcg_gen_shr_i64(ret, arg1, t0); |
| 955 |
tcg_temp_free(t0); |
| 956 |
} |
| 957 |
} |
| 958 |
|
| 959 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 960 |
{
|
| 961 |
tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2); |
| 962 |
} |
| 963 |
|
| 964 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 965 |
{
|
| 966 |
if (arg2 == 0) { |
| 967 |
tcg_gen_mov_i64(ret, arg1); |
| 968 |
} else {
|
| 969 |
TCGv t0 = tcg_const_i64(arg2); |
| 970 |
tcg_gen_sar_i64(ret, arg1, t0); |
| 971 |
tcg_temp_free(t0); |
| 972 |
} |
| 973 |
} |
| 974 |
|
| 975 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
| 976 |
int label_index)
|
| 977 |
{
|
| 978 |
tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
| 979 |
} |
| 980 |
|
| 981 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 982 |
{
|
| 983 |
tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2); |
| 984 |
} |
| 985 |
|
| 986 |
#ifdef TCG_TARGET_HAS_div_i64
|
| 987 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 988 |
{
|
| 989 |
tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2); |
| 990 |
} |
| 991 |
|
| 992 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 993 |
{
|
| 994 |
tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2); |
| 995 |
} |
| 996 |
|
| 997 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 998 |
{
|
| 999 |
tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2); |
| 1000 |
} |
| 1001 |
|
| 1002 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1003 |
{
|
| 1004 |
tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2); |
| 1005 |
} |
| 1006 |
#else
|
| 1007 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1008 |
{
|
| 1009 |
TCGv t0; |
| 1010 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1011 |
tcg_gen_sari_i64(t0, arg1, 63);
|
| 1012 |
tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
| 1013 |
tcg_temp_free(t0); |
| 1014 |
} |
| 1015 |
|
| 1016 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1017 |
{
|
| 1018 |
TCGv t0; |
| 1019 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1020 |
tcg_gen_sari_i64(t0, arg1, 63);
|
| 1021 |
tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
| 1022 |
tcg_temp_free(t0); |
| 1023 |
} |
| 1024 |
|
| 1025 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1026 |
{
|
| 1027 |
TCGv t0; |
| 1028 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1029 |
tcg_gen_movi_i64(t0, 0);
|
| 1030 |
tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
| 1031 |
tcg_temp_free(t0); |
| 1032 |
} |
| 1033 |
|
| 1034 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1035 |
{
|
| 1036 |
TCGv t0; |
| 1037 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1038 |
tcg_gen_movi_i64(t0, 0);
|
| 1039 |
tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
| 1040 |
tcg_temp_free(t0); |
| 1041 |
} |
| 1042 |
#endif
|
| 1043 |
|
| 1044 |
#endif
|
| 1045 |
|
| 1046 |
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 1047 |
{
|
| 1048 |
/* some cases can be optimized here */
|
| 1049 |
if (arg2 == 0) { |
| 1050 |
tcg_gen_mov_i64(ret, arg1); |
| 1051 |
} else {
|
| 1052 |
TCGv t0 = tcg_const_i64(arg2); |
| 1053 |
tcg_gen_add_i64(ret, arg1, t0); |
| 1054 |
tcg_temp_free(t0); |
| 1055 |
} |
| 1056 |
} |
| 1057 |
|
| 1058 |
static inline void tcg_gen_subfi_i64(TCGv ret, int64_t arg1, TCGv arg2) |
| 1059 |
{
|
| 1060 |
TCGv t0 = tcg_const_i64(arg1); |
| 1061 |
tcg_gen_sub_i64(ret, t0, arg2); |
| 1062 |
tcg_temp_free(t0); |
| 1063 |
} |
| 1064 |
|
| 1065 |
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 1066 |
{
|
| 1067 |
/* some cases can be optimized here */
|
| 1068 |
if (arg2 == 0) { |
| 1069 |
tcg_gen_mov_i64(ret, arg1); |
| 1070 |
} else {
|
| 1071 |
TCGv t0 = tcg_const_i64(arg2); |
| 1072 |
tcg_gen_sub_i64(ret, arg1, t0); |
| 1073 |
tcg_temp_free(t0); |
| 1074 |
} |
| 1075 |
} |
| 1076 |
static inline void tcg_gen_brcondi_i64(int cond, TCGv arg1, int64_t arg2, |
| 1077 |
int label_index)
|
| 1078 |
{
|
| 1079 |
TCGv t0 = tcg_const_i64(arg2); |
| 1080 |
tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
| 1081 |
tcg_temp_free(t0); |
| 1082 |
} |
| 1083 |
|
| 1084 |
static inline void tcg_gen_muli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 1085 |
{
|
| 1086 |
TCGv t0 = tcg_const_i64(arg2); |
| 1087 |
tcg_gen_mul_i64(ret, arg1, t0); |
| 1088 |
tcg_temp_free(t0); |
| 1089 |
} |
| 1090 |
|
| 1091 |
|
| 1092 |
/***************************************/
|
| 1093 |
/* optional operations */
|
| 1094 |
|
| 1095 |
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg) |
| 1096 |
{
|
| 1097 |
#ifdef TCG_TARGET_HAS_ext8s_i32
|
| 1098 |
tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg); |
| 1099 |
#else
|
| 1100 |
tcg_gen_shli_i32(ret, arg, 24);
|
| 1101 |
tcg_gen_sari_i32(ret, ret, 24);
|
| 1102 |
#endif
|
| 1103 |
} |
| 1104 |
|
| 1105 |
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg) |
| 1106 |
{
|
| 1107 |
#ifdef TCG_TARGET_HAS_ext16s_i32
|
| 1108 |
tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg); |
| 1109 |
#else
|
| 1110 |
tcg_gen_shli_i32(ret, arg, 16);
|
| 1111 |
tcg_gen_sari_i32(ret, ret, 16);
|
| 1112 |
#endif
|
| 1113 |
} |
| 1114 |
|
| 1115 |
/* These are currently just for convenience.
|
| 1116 |
We assume a target will recognise these automatically . */
|
| 1117 |
static inline void tcg_gen_ext8u_i32(TCGv ret, TCGv arg) |
| 1118 |
{
|
| 1119 |
tcg_gen_andi_i32(ret, arg, 0xffu);
|
| 1120 |
} |
| 1121 |
|
| 1122 |
static inline void tcg_gen_ext16u_i32(TCGv ret, TCGv arg) |
| 1123 |
{
|
| 1124 |
tcg_gen_andi_i32(ret, arg, 0xffffu);
|
| 1125 |
} |
| 1126 |
|
| 1127 |
/* Note: we assume the two high bytes are set to zero */
|
| 1128 |
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg) |
| 1129 |
{
|
| 1130 |
#ifdef TCG_TARGET_HAS_bswap16_i32
|
| 1131 |
tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg); |
| 1132 |
#else
|
| 1133 |
TCGv t0, t1; |
| 1134 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1135 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1136 |
|
| 1137 |
tcg_gen_shri_i32(t0, arg, 8);
|
| 1138 |
tcg_gen_andi_i32(t1, arg, 0x000000ff);
|
| 1139 |
tcg_gen_shli_i32(t1, t1, 8);
|
| 1140 |
tcg_gen_or_i32(ret, t0, t1); |
| 1141 |
tcg_temp_free(t0); |
| 1142 |
tcg_temp_free(t1); |
| 1143 |
#endif
|
| 1144 |
} |
| 1145 |
|
| 1146 |
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg) |
| 1147 |
{
|
| 1148 |
#ifdef TCG_TARGET_HAS_bswap_i32
|
| 1149 |
tcg_gen_op2(INDEX_op_bswap_i32, ret, arg); |
| 1150 |
#else
|
| 1151 |
TCGv t0, t1; |
| 1152 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1153 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1154 |
|
| 1155 |
tcg_gen_shli_i32(t0, arg, 24);
|
| 1156 |
|
| 1157 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
| 1158 |
tcg_gen_shli_i32(t1, t1, 8);
|
| 1159 |
tcg_gen_or_i32(t0, t0, t1); |
| 1160 |
|
| 1161 |
tcg_gen_shri_i32(t1, arg, 8);
|
| 1162 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
| 1163 |
tcg_gen_or_i32(t0, t0, t1); |
| 1164 |
|
| 1165 |
tcg_gen_shri_i32(t1, arg, 24);
|
| 1166 |
tcg_gen_or_i32(ret, t0, t1); |
| 1167 |
tcg_temp_free(t0); |
| 1168 |
tcg_temp_free(t1); |
| 1169 |
#endif
|
| 1170 |
} |
| 1171 |
|
| 1172 |
#if TCG_TARGET_REG_BITS == 32 |
| 1173 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
| 1174 |
{
|
| 1175 |
tcg_gen_ext8s_i32(ret, arg); |
| 1176 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1177 |
} |
| 1178 |
|
| 1179 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
| 1180 |
{
|
| 1181 |
tcg_gen_ext16s_i32(ret, arg); |
| 1182 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1183 |
} |
| 1184 |
|
| 1185 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
| 1186 |
{
|
| 1187 |
tcg_gen_mov_i32(ret, arg); |
| 1188 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1189 |
} |
| 1190 |
|
| 1191 |
static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg) |
| 1192 |
{
|
| 1193 |
tcg_gen_ext8u_i32(ret, arg); |
| 1194 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1195 |
} |
| 1196 |
|
| 1197 |
static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg) |
| 1198 |
{
|
| 1199 |
tcg_gen_ext16u_i32(ret, arg); |
| 1200 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1201 |
} |
| 1202 |
|
| 1203 |
static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg) |
| 1204 |
{
|
| 1205 |
tcg_gen_mov_i32(ret, arg); |
| 1206 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1207 |
} |
| 1208 |
|
| 1209 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
| 1210 |
{
|
| 1211 |
tcg_gen_mov_i32(ret, arg); |
| 1212 |
} |
| 1213 |
|
| 1214 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
| 1215 |
{
|
| 1216 |
tcg_gen_mov_i32(ret, arg); |
| 1217 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1218 |
} |
| 1219 |
|
| 1220 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
| 1221 |
{
|
| 1222 |
tcg_gen_mov_i32(ret, arg); |
| 1223 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1224 |
} |
| 1225 |
|
| 1226 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
| 1227 |
{
|
| 1228 |
TCGv t0, t1; |
| 1229 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1230 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1231 |
|
| 1232 |
tcg_gen_bswap_i32(t0, arg); |
| 1233 |
tcg_gen_bswap_i32(t1, TCGV_HIGH(arg)); |
| 1234 |
tcg_gen_mov_i32(ret, t1); |
| 1235 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
| 1236 |
tcg_temp_free(t0); |
| 1237 |
tcg_temp_free(t1); |
| 1238 |
} |
| 1239 |
#else
|
| 1240 |
|
| 1241 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
| 1242 |
{
|
| 1243 |
#ifdef TCG_TARGET_HAS_ext8s_i64
|
| 1244 |
tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg); |
| 1245 |
#else
|
| 1246 |
tcg_gen_shli_i64(ret, arg, 56);
|
| 1247 |
tcg_gen_sari_i64(ret, ret, 56);
|
| 1248 |
#endif
|
| 1249 |
} |
| 1250 |
|
| 1251 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
| 1252 |
{
|
| 1253 |
#ifdef TCG_TARGET_HAS_ext16s_i64
|
| 1254 |
tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg); |
| 1255 |
#else
|
| 1256 |
tcg_gen_shli_i64(ret, arg, 48);
|
| 1257 |
tcg_gen_sari_i64(ret, ret, 48);
|
| 1258 |
#endif
|
| 1259 |
} |
| 1260 |
|
| 1261 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
| 1262 |
{
|
| 1263 |
#ifdef TCG_TARGET_HAS_ext32s_i64
|
| 1264 |
tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg); |
| 1265 |
#else
|
| 1266 |
tcg_gen_shli_i64(ret, arg, 32);
|
| 1267 |
tcg_gen_sari_i64(ret, ret, 32);
|
| 1268 |
#endif
|
| 1269 |
} |
| 1270 |
|
| 1271 |
static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg) |
| 1272 |
{
|
| 1273 |
tcg_gen_andi_i64(ret, arg, 0xffu);
|
| 1274 |
} |
| 1275 |
|
| 1276 |
static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg) |
| 1277 |
{
|
| 1278 |
tcg_gen_andi_i64(ret, arg, 0xffffu);
|
| 1279 |
} |
| 1280 |
|
| 1281 |
static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg) |
| 1282 |
{
|
| 1283 |
tcg_gen_andi_i64(ret, arg, 0xffffffffu);
|
| 1284 |
} |
| 1285 |
|
| 1286 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1287 |
registers. This will probably break MIPS64 targets. */
|
| 1288 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
| 1289 |
{
|
| 1290 |
tcg_gen_mov_i32(ret, arg); |
| 1291 |
} |
| 1292 |
|
| 1293 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1294 |
registers */
|
| 1295 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
| 1296 |
{
|
| 1297 |
tcg_gen_andi_i64(ret, arg, 0xffffffffu);
|
| 1298 |
} |
| 1299 |
|
| 1300 |
/* Note: we assume the target supports move between 32 and 64 bit
|
| 1301 |
registers */
|
| 1302 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
| 1303 |
{
|
| 1304 |
tcg_gen_ext32s_i64(ret, arg); |
| 1305 |
} |
| 1306 |
|
| 1307 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
| 1308 |
{
|
| 1309 |
#ifdef TCG_TARGET_HAS_bswap_i64
|
| 1310 |
tcg_gen_op2(INDEX_op_bswap_i64, ret, arg); |
| 1311 |
#else
|
| 1312 |
TCGv t0, t1; |
| 1313 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1314 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1315 |
|
| 1316 |
tcg_gen_shli_i64(t0, arg, 56);
|
| 1317 |
|
| 1318 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
| 1319 |
tcg_gen_shli_i64(t1, t1, 40);
|
| 1320 |
tcg_gen_or_i64(t0, t0, t1); |
| 1321 |
|
| 1322 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
| 1323 |
tcg_gen_shli_i64(t1, t1, 24);
|
| 1324 |
tcg_gen_or_i64(t0, t0, t1); |
| 1325 |
|
| 1326 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
| 1327 |
tcg_gen_shli_i64(t1, t1, 8);
|
| 1328 |
tcg_gen_or_i64(t0, t0, t1); |
| 1329 |
|
| 1330 |
tcg_gen_shri_i64(t1, arg, 8);
|
| 1331 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
| 1332 |
tcg_gen_or_i64(t0, t0, t1); |
| 1333 |
|
| 1334 |
tcg_gen_shri_i64(t1, arg, 24);
|
| 1335 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
| 1336 |
tcg_gen_or_i64(t0, t0, t1); |
| 1337 |
|
| 1338 |
tcg_gen_shri_i64(t1, arg, 40);
|
| 1339 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
| 1340 |
tcg_gen_or_i64(t0, t0, t1); |
| 1341 |
|
| 1342 |
tcg_gen_shri_i64(t1, arg, 56);
|
| 1343 |
tcg_gen_or_i64(ret, t0, t1); |
| 1344 |
tcg_temp_free(t0); |
| 1345 |
tcg_temp_free(t1); |
| 1346 |
#endif
|
| 1347 |
} |
| 1348 |
|
| 1349 |
#endif
|
| 1350 |
|
| 1351 |
static inline void tcg_gen_neg_i32(TCGv ret, TCGv arg) |
| 1352 |
{
|
| 1353 |
#ifdef TCG_TARGET_HAS_neg_i32
|
| 1354 |
tcg_gen_op2(INDEX_op_neg_i32, ret, arg); |
| 1355 |
#else
|
| 1356 |
TCGv t0 = tcg_const_i32(0);
|
| 1357 |
tcg_gen_sub_i32(ret, t0, arg); |
| 1358 |
tcg_temp_free(t0); |
| 1359 |
#endif
|
| 1360 |
} |
| 1361 |
|
| 1362 |
static inline void tcg_gen_neg_i64(TCGv ret, TCGv arg) |
| 1363 |
{
|
| 1364 |
#ifdef TCG_TARGET_HAS_neg_i64
|
| 1365 |
tcg_gen_op2(INDEX_op_neg_i64, ret, arg); |
| 1366 |
#else
|
| 1367 |
TCGv t0 = tcg_const_i64(0);
|
| 1368 |
tcg_gen_sub_i64(ret, t0, arg); |
| 1369 |
tcg_temp_free(t0); |
| 1370 |
#endif
|
| 1371 |
} |
| 1372 |
|
| 1373 |
static inline void tcg_gen_not_i32(TCGv ret, TCGv arg) |
| 1374 |
{
|
| 1375 |
tcg_gen_xori_i32(ret, arg, -1);
|
| 1376 |
} |
| 1377 |
|
| 1378 |
static inline void tcg_gen_not_i64(TCGv ret, TCGv arg) |
| 1379 |
{
|
| 1380 |
tcg_gen_xori_i64(ret, arg, -1);
|
| 1381 |
} |
| 1382 |
|
| 1383 |
static inline void tcg_gen_discard_i32(TCGv arg) |
| 1384 |
{
|
| 1385 |
tcg_gen_op1(INDEX_op_discard, arg); |
| 1386 |
} |
| 1387 |
|
| 1388 |
#if TCG_TARGET_REG_BITS == 32 |
| 1389 |
static inline void tcg_gen_discard_i64(TCGv arg) |
| 1390 |
{
|
| 1391 |
tcg_gen_discard_i32(arg); |
| 1392 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
| 1393 |
} |
| 1394 |
#else
|
| 1395 |
static inline void tcg_gen_discard_i64(TCGv arg) |
| 1396 |
{
|
| 1397 |
tcg_gen_op1(INDEX_op_discard, arg); |
| 1398 |
} |
| 1399 |
#endif
|
| 1400 |
|
| 1401 |
static inline void tcg_gen_concat_i32_i64(TCGv dest, TCGv low, TCGv high) |
| 1402 |
{
|
| 1403 |
#if TCG_TARGET_REG_BITS == 32 |
| 1404 |
tcg_gen_mov_i32(dest, low); |
| 1405 |
tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
| 1406 |
#else
|
| 1407 |
TCGv tmp = tcg_temp_new (TCG_TYPE_I64); |
| 1408 |
/* This extension is only needed for type correctness.
|
| 1409 |
We may be able to do better given target specific information. */
|
| 1410 |
tcg_gen_extu_i32_i64(tmp, high); |
| 1411 |
tcg_gen_shli_i64(tmp, tmp, 32);
|
| 1412 |
tcg_gen_extu_i32_i64(dest, low); |
| 1413 |
tcg_gen_or_i64(dest, dest, tmp); |
| 1414 |
tcg_temp_free(tmp); |
| 1415 |
#endif
|
| 1416 |
} |
| 1417 |
|
| 1418 |
static inline void tcg_gen_concat32_i64(TCGv dest, TCGv low, TCGv high) |
| 1419 |
{
|
| 1420 |
#if TCG_TARGET_REG_BITS == 32 |
| 1421 |
tcg_gen_concat_i32_i64(dest, low, high); |
| 1422 |
#else
|
| 1423 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
| 1424 |
tcg_gen_ext32u_i64(dest, low); |
| 1425 |
tcg_gen_shli_i64(tmp, high, 32);
|
| 1426 |
tcg_gen_or_i64(dest, dest, tmp); |
| 1427 |
tcg_temp_free(tmp); |
| 1428 |
#endif
|
| 1429 |
} |
| 1430 |
|
| 1431 |
static inline void tcg_gen_andc_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 1432 |
{
|
| 1433 |
TCGv t0; |
| 1434 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1435 |
tcg_gen_not_i32(t0, arg2); |
| 1436 |
tcg_gen_and_i32(ret, arg1, t0); |
| 1437 |
tcg_temp_free(t0); |
| 1438 |
} |
| 1439 |
|
| 1440 |
static inline void tcg_gen_andc_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1441 |
{
|
| 1442 |
TCGv t0; |
| 1443 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1444 |
tcg_gen_not_i64(t0, arg2); |
| 1445 |
tcg_gen_and_i64(ret, arg1, t0); |
| 1446 |
tcg_temp_free(t0); |
| 1447 |
} |
| 1448 |
|
| 1449 |
static inline void tcg_gen_eqv_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 1450 |
{
|
| 1451 |
TCGv t0; |
| 1452 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1453 |
tcg_gen_xor_i32(t0, arg1, arg2); |
| 1454 |
tcg_gen_not_i32(ret, t0); |
| 1455 |
tcg_temp_free(t0); |
| 1456 |
} |
| 1457 |
|
| 1458 |
static inline void tcg_gen_eqv_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1459 |
{
|
| 1460 |
TCGv t0; |
| 1461 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1462 |
tcg_gen_xor_i64(t0, arg1, arg2); |
| 1463 |
tcg_gen_not_i64(ret, t0); |
| 1464 |
tcg_temp_free(t0); |
| 1465 |
} |
| 1466 |
|
| 1467 |
static inline void tcg_gen_nand_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 1468 |
{
|
| 1469 |
TCGv t0; |
| 1470 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1471 |
tcg_gen_and_i32(t0, arg1, arg2); |
| 1472 |
tcg_gen_not_i32(ret, t0); |
| 1473 |
tcg_temp_free(t0); |
| 1474 |
} |
| 1475 |
|
| 1476 |
static inline void tcg_gen_nand_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1477 |
{
|
| 1478 |
TCGv t0; |
| 1479 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1480 |
tcg_gen_and_i64(t0, arg1, arg2); |
| 1481 |
tcg_gen_not_i64(ret, t0); |
| 1482 |
tcg_temp_free(t0); |
| 1483 |
} |
| 1484 |
|
| 1485 |
static inline void tcg_gen_nor_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 1486 |
{
|
| 1487 |
TCGv t0; |
| 1488 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1489 |
tcg_gen_or_i32(t0, arg1, arg2); |
| 1490 |
tcg_gen_not_i32(ret, t0); |
| 1491 |
tcg_temp_free(t0); |
| 1492 |
} |
| 1493 |
|
| 1494 |
static inline void tcg_gen_nor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1495 |
{
|
| 1496 |
TCGv t0; |
| 1497 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1498 |
tcg_gen_or_i64(t0, arg1, arg2); |
| 1499 |
tcg_gen_not_i64(ret, t0); |
| 1500 |
tcg_temp_free(t0); |
| 1501 |
} |
| 1502 |
|
| 1503 |
static inline void tcg_gen_orc_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 1504 |
{
|
| 1505 |
TCGv t0; |
| 1506 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1507 |
tcg_gen_not_i32(t0, arg2); |
| 1508 |
tcg_gen_or_i32(ret, arg1, t0); |
| 1509 |
tcg_temp_free(t0); |
| 1510 |
} |
| 1511 |
|
| 1512 |
static inline void tcg_gen_orc_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1513 |
{
|
| 1514 |
TCGv t0; |
| 1515 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1516 |
tcg_gen_not_i64(t0, arg2); |
| 1517 |
tcg_gen_or_i64(ret, arg1, t0); |
| 1518 |
tcg_temp_free(t0); |
| 1519 |
} |
| 1520 |
|
| 1521 |
static inline void tcg_gen_rotl_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 1522 |
{
|
| 1523 |
TCGv t0, t1; |
| 1524 |
|
| 1525 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1526 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1527 |
tcg_gen_shl_i32(t0, arg1, arg2); |
| 1528 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
| 1529 |
tcg_gen_shr_i32(t1, arg1, t1); |
| 1530 |
tcg_gen_or_i32(ret, t0, t1); |
| 1531 |
tcg_temp_free(t0); |
| 1532 |
tcg_temp_free(t1); |
| 1533 |
} |
| 1534 |
|
| 1535 |
static inline void tcg_gen_rotl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1536 |
{
|
| 1537 |
TCGv t0, t1; |
| 1538 |
|
| 1539 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1540 |
t1 = tcg_temp_new(TCG_TYPE_I64); |
| 1541 |
tcg_gen_shl_i64(t0, arg1, arg2); |
| 1542 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
| 1543 |
tcg_gen_shr_i64(t1, arg1, t1); |
| 1544 |
tcg_gen_or_i64(ret, t0, t1); |
| 1545 |
tcg_temp_free(t0); |
| 1546 |
tcg_temp_free(t1); |
| 1547 |
} |
| 1548 |
|
| 1549 |
static inline void tcg_gen_rotli_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 1550 |
{
|
| 1551 |
/* some cases can be optimized here */
|
| 1552 |
if (arg2 == 0) { |
| 1553 |
tcg_gen_mov_i32(ret, arg1); |
| 1554 |
} else {
|
| 1555 |
TCGv t0, t1; |
| 1556 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1557 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1558 |
tcg_gen_shli_i32(t0, arg1, arg2); |
| 1559 |
tcg_gen_shri_i32(t1, arg1, 32 - arg2);
|
| 1560 |
tcg_gen_or_i32(ret, t0, t1); |
| 1561 |
tcg_temp_free(t0); |
| 1562 |
tcg_temp_free(t1); |
| 1563 |
} |
| 1564 |
} |
| 1565 |
|
| 1566 |
static inline void tcg_gen_rotli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 1567 |
{
|
| 1568 |
/* some cases can be optimized here */
|
| 1569 |
if (arg2 == 0) { |
| 1570 |
tcg_gen_mov_i64(ret, arg1); |
| 1571 |
} else {
|
| 1572 |
TCGv t0, t1; |
| 1573 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1574 |
t1 = tcg_temp_new(TCG_TYPE_I64); |
| 1575 |
tcg_gen_shli_i64(t0, arg1, arg2); |
| 1576 |
tcg_gen_shri_i64(t1, arg1, 64 - arg2);
|
| 1577 |
tcg_gen_or_i64(ret, t0, t1); |
| 1578 |
tcg_temp_free(t0); |
| 1579 |
tcg_temp_free(t1); |
| 1580 |
} |
| 1581 |
} |
| 1582 |
|
| 1583 |
static inline void tcg_gen_rotr_i32(TCGv ret, TCGv arg1, TCGv arg2) |
| 1584 |
{
|
| 1585 |
TCGv t0, t1; |
| 1586 |
|
| 1587 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
| 1588 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
| 1589 |
tcg_gen_shr_i32(t0, arg1, arg2); |
| 1590 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
| 1591 |
tcg_gen_shl_i32(t1, arg1, t1); |
| 1592 |
tcg_gen_or_i32(ret, t0, t1); |
| 1593 |
tcg_temp_free(t0); |
| 1594 |
tcg_temp_free(t1); |
| 1595 |
} |
| 1596 |
|
| 1597 |
static inline void tcg_gen_rotr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
| 1598 |
{
|
| 1599 |
TCGv t0, t1; |
| 1600 |
|
| 1601 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
| 1602 |
t1 = tcg_temp_new(TCG_TYPE_I64); |
| 1603 |
tcg_gen_shl_i64(t0, arg1, arg2); |
| 1604 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
| 1605 |
tcg_gen_shl_i64(t1, arg1, t1); |
| 1606 |
tcg_gen_or_i64(ret, t0, t1); |
| 1607 |
tcg_temp_free(t0); |
| 1608 |
tcg_temp_free(t1); |
| 1609 |
} |
| 1610 |
|
| 1611 |
static inline void tcg_gen_rotri_i32(TCGv ret, TCGv arg1, int32_t arg2) |
| 1612 |
{
|
| 1613 |
/* some cases can be optimized here */
|
| 1614 |
if (arg2 == 0) { |
| 1615 |
tcg_gen_mov_i32(ret, arg1); |
| 1616 |
} else {
|
| 1617 |
tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
|
| 1618 |
} |
| 1619 |
} |
| 1620 |
|
| 1621 |
static inline void tcg_gen_rotri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
| 1622 |
{
|
| 1623 |
/* some cases can be optimized here */
|
| 1624 |
if (arg2 == 0) { |
| 1625 |
tcg_gen_mov_i32(ret, arg1); |
| 1626 |
} else {
|
| 1627 |
tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
|
| 1628 |
} |
| 1629 |
} |
| 1630 |
|
| 1631 |
/***************************************/
|
| 1632 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
| 1633 |
type. */
|
| 1634 |
#ifndef TARGET_LONG_BITS
|
| 1635 |
#error must include QEMU headers
|
| 1636 |
#endif
|
| 1637 |
|
| 1638 |
/* debug info: write the PC of the corresponding QEMU CPU instruction */
|
| 1639 |
static inline void tcg_gen_debug_insn_start(uint64_t pc) |
| 1640 |
{
|
| 1641 |
/* XXX: must really use a 32 bit size for TCGArg in all cases */
|
| 1642 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
| 1643 |
tcg_gen_op2ii(INDEX_op_debug_insn_start, |
| 1644 |
(uint32_t)(pc), (uint32_t)(pc >> 32));
|
| 1645 |
#else
|
| 1646 |
tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
| 1647 |
#endif
|
| 1648 |
} |
| 1649 |
|
| 1650 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
| 1651 |
{
|
| 1652 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
| 1653 |
} |
| 1654 |
|
| 1655 |
static inline void tcg_gen_goto_tb(int idx) |
| 1656 |
{
|
| 1657 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
| 1658 |
} |
| 1659 |
|
| 1660 |
#if TCG_TARGET_REG_BITS == 32 |
| 1661 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
| 1662 |
{
|
| 1663 |
#if TARGET_LONG_BITS == 32 |
| 1664 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
| 1665 |
#else
|
| 1666 |
tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1667 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1668 |
#endif
|
| 1669 |
} |
| 1670 |
|
| 1671 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
| 1672 |
{
|
| 1673 |
#if TARGET_LONG_BITS == 32 |
| 1674 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
| 1675 |
#else
|
| 1676 |
tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1677 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1678 |
#endif
|
| 1679 |
} |
| 1680 |
|
| 1681 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
| 1682 |
{
|
| 1683 |
#if TARGET_LONG_BITS == 32 |
| 1684 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
| 1685 |
#else
|
| 1686 |
tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1687 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1688 |
#endif
|
| 1689 |
} |
| 1690 |
|
| 1691 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
| 1692 |
{
|
| 1693 |
#if TARGET_LONG_BITS == 32 |
| 1694 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
| 1695 |
#else
|
| 1696 |
tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1697 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1698 |
#endif
|
| 1699 |
} |
| 1700 |
|
| 1701 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
| 1702 |
{
|
| 1703 |
#if TARGET_LONG_BITS == 32 |
| 1704 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1705 |
#else
|
| 1706 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1707 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
| 1708 |
#endif
|
| 1709 |
} |
| 1710 |
|
| 1711 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
| 1712 |
{
|
| 1713 |
#if TARGET_LONG_BITS == 32 |
| 1714 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1715 |
#else
|
| 1716 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
| 1717 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
| 1718 |
#endif
|
| 1719 |
} |
| 1720 |
|
| 1721 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
| 1722 |
{
|
| 1723 |
#if TARGET_LONG_BITS == 32 |
| 1724 |
tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index); |
| 1725 |
#else
|
| 1726 |
tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), |
| 1727 |
addr, TCGV_HIGH(addr), mem_index); |
| 1728 |
#endif
|
| 1729 |
} |
| 1730 |
|
| 1731 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
| 1732 |
{
|
| 1733 |
#if TARGET_LONG_BITS == 32 |
| 1734 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
| 1735 |
#else
|
| 1736 |
tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1737 |
#endif
|
| 1738 |
} |
| 1739 |
|
| 1740 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
| 1741 |
{
|
| 1742 |
#if TARGET_LONG_BITS == 32 |
| 1743 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
| 1744 |
#else
|
| 1745 |
tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1746 |
#endif
|
| 1747 |
} |
| 1748 |
|
| 1749 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
| 1750 |
{
|
| 1751 |
#if TARGET_LONG_BITS == 32 |
| 1752 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
| 1753 |
#else
|
| 1754 |
tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index); |
| 1755 |
#endif
|
| 1756 |
} |
| 1757 |
|
| 1758 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
| 1759 |
{
|
| 1760 |
#if TARGET_LONG_BITS == 32 |
| 1761 |
tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index); |
| 1762 |
#else
|
| 1763 |
tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), |
| 1764 |
addr, TCGV_HIGH(addr), mem_index); |
| 1765 |
#endif
|
| 1766 |
} |
| 1767 |
|
| 1768 |
#define tcg_gen_ld_ptr tcg_gen_ld_i32
|
| 1769 |
#define tcg_gen_discard_ptr tcg_gen_discard_i32
|
| 1770 |
|
| 1771 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
| 1772 |
|
| 1773 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
| 1774 |
{
|
| 1775 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
| 1776 |
} |
| 1777 |
|
| 1778 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
| 1779 |
{
|
| 1780 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
| 1781 |
} |
| 1782 |
|
| 1783 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
| 1784 |
{
|
| 1785 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
| 1786 |
} |
| 1787 |
|
| 1788 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
| 1789 |
{
|
| 1790 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
| 1791 |
} |
| 1792 |
|
| 1793 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
| 1794 |
{
|
| 1795 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
| 1796 |
} |
| 1797 |
|
| 1798 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
| 1799 |
{
|
| 1800 |
tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
| 1801 |
} |
| 1802 |
|
| 1803 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
| 1804 |
{
|
| 1805 |
tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index); |
| 1806 |
} |
| 1807 |
|
| 1808 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
| 1809 |
{
|
| 1810 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
| 1811 |
} |
| 1812 |
|
| 1813 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
| 1814 |
{
|
| 1815 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
| 1816 |
} |
| 1817 |
|
| 1818 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
| 1819 |
{
|
| 1820 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
| 1821 |
} |
| 1822 |
|
| 1823 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
| 1824 |
{
|
| 1825 |
tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index); |
| 1826 |
} |
| 1827 |
|
| 1828 |
#define tcg_gen_ld_ptr tcg_gen_ld_i64
|
| 1829 |
#define tcg_gen_discard_ptr tcg_gen_discard_i64
|
| 1830 |
|
| 1831 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
| 1832 |
|
| 1833 |
#if TARGET_LONG_BITS == 64 |
| 1834 |
#define TCG_TYPE_TL TCG_TYPE_I64
|
| 1835 |
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
| 1836 |
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
| 1837 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
| 1838 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
| 1839 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
| 1840 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
| 1841 |
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
| 1842 |
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
| 1843 |
#define tcg_gen_ld_tl tcg_gen_ld_i64
|
| 1844 |
#define tcg_gen_st8_tl tcg_gen_st8_i64
|
| 1845 |
#define tcg_gen_st16_tl tcg_gen_st16_i64
|
| 1846 |
#define tcg_gen_st32_tl tcg_gen_st32_i64
|
| 1847 |
#define tcg_gen_st_tl tcg_gen_st_i64
|
| 1848 |
#define tcg_gen_add_tl tcg_gen_add_i64
|
| 1849 |
#define tcg_gen_addi_tl tcg_gen_addi_i64
|
| 1850 |
#define tcg_gen_sub_tl tcg_gen_sub_i64
|
| 1851 |
#define tcg_gen_neg_tl tcg_gen_neg_i64
|
| 1852 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
|
| 1853 |
#define tcg_gen_subi_tl tcg_gen_subi_i64
|
| 1854 |
#define tcg_gen_and_tl tcg_gen_and_i64
|
| 1855 |
#define tcg_gen_andi_tl tcg_gen_andi_i64
|
| 1856 |
#define tcg_gen_or_tl tcg_gen_or_i64
|
| 1857 |
#define tcg_gen_ori_tl tcg_gen_ori_i64
|
| 1858 |
#define tcg_gen_xor_tl tcg_gen_xor_i64
|
| 1859 |
#define tcg_gen_xori_tl tcg_gen_xori_i64
|
| 1860 |
#define tcg_gen_not_tl tcg_gen_not_i64
|
| 1861 |
#define tcg_gen_shl_tl tcg_gen_shl_i64
|
| 1862 |
#define tcg_gen_shli_tl tcg_gen_shli_i64
|
| 1863 |
#define tcg_gen_shr_tl tcg_gen_shr_i64
|
| 1864 |
#define tcg_gen_shri_tl tcg_gen_shri_i64
|
| 1865 |
#define tcg_gen_sar_tl tcg_gen_sar_i64
|
| 1866 |
#define tcg_gen_sari_tl tcg_gen_sari_i64
|
| 1867 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
| 1868 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
|
| 1869 |
#define tcg_gen_mul_tl tcg_gen_mul_i64
|
| 1870 |
#define tcg_gen_muli_tl tcg_gen_muli_i64
|
| 1871 |
#define tcg_gen_discard_tl tcg_gen_discard_i64
|
| 1872 |
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
| 1873 |
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
| 1874 |
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
| 1875 |
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
| 1876 |
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
| 1877 |
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
| 1878 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
|
| 1879 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
|
| 1880 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
|
| 1881 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
|
| 1882 |
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
|
| 1883 |
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
|
| 1884 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
|
| 1885 |
#define tcg_gen_andc_tl tcg_gen_andc_i64
|
| 1886 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
|
| 1887 |
#define tcg_gen_nand_tl tcg_gen_nand_i64
|
| 1888 |
#define tcg_gen_nor_tl tcg_gen_nor_i64
|
| 1889 |
#define tcg_gen_orc_tl tcg_gen_orc_i64
|
| 1890 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
|
| 1891 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
|
| 1892 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
|
| 1893 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
|
| 1894 |
#define tcg_const_tl tcg_const_i64
|
| 1895 |
#define tcg_const_local_tl tcg_const_local_i64
|
| 1896 |
#else
|
| 1897 |
#define TCG_TYPE_TL TCG_TYPE_I32
|
| 1898 |
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
| 1899 |
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
| 1900 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
| 1901 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
| 1902 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
| 1903 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
| 1904 |
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
| 1905 |
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
| 1906 |
#define tcg_gen_ld_tl tcg_gen_ld_i32
|
| 1907 |
#define tcg_gen_st8_tl tcg_gen_st8_i32
|
| 1908 |
#define tcg_gen_st16_tl tcg_gen_st16_i32
|
| 1909 |
#define tcg_gen_st32_tl tcg_gen_st_i32
|
| 1910 |
#define tcg_gen_st_tl tcg_gen_st_i32
|
| 1911 |
#define tcg_gen_add_tl tcg_gen_add_i32
|
| 1912 |
#define tcg_gen_addi_tl tcg_gen_addi_i32
|
| 1913 |
#define tcg_gen_sub_tl tcg_gen_sub_i32
|
| 1914 |
#define tcg_gen_neg_tl tcg_gen_neg_i32
|
| 1915 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
|
| 1916 |
#define tcg_gen_subi_tl tcg_gen_subi_i32
|
| 1917 |
#define tcg_gen_and_tl tcg_gen_and_i32
|
| 1918 |
#define tcg_gen_andi_tl tcg_gen_andi_i32
|
| 1919 |
#define tcg_gen_or_tl tcg_gen_or_i32
|
| 1920 |
#define tcg_gen_ori_tl tcg_gen_ori_i32
|
| 1921 |
#define tcg_gen_xor_tl tcg_gen_xor_i32
|
| 1922 |
#define tcg_gen_xori_tl tcg_gen_xori_i32
|
| 1923 |
#define tcg_gen_not_tl tcg_gen_not_i32
|
| 1924 |
#define tcg_gen_shl_tl tcg_gen_shl_i32
|
| 1925 |
#define tcg_gen_shli_tl tcg_gen_shli_i32
|
| 1926 |
#define tcg_gen_shr_tl tcg_gen_shr_i32
|
| 1927 |
#define tcg_gen_shri_tl tcg_gen_shri_i32
|
| 1928 |
#define tcg_gen_sar_tl tcg_gen_sar_i32
|
| 1929 |
#define tcg_gen_sari_tl tcg_gen_sari_i32
|
| 1930 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
| 1931 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
|
| 1932 |
#define tcg_gen_mul_tl tcg_gen_mul_i32
|
| 1933 |
#define tcg_gen_muli_tl tcg_gen_muli_i32
|
| 1934 |
#define tcg_gen_discard_tl tcg_gen_discard_i32
|
| 1935 |
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
| 1936 |
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
| 1937 |
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
| 1938 |
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
| 1939 |
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
| 1940 |
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
| 1941 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
|
| 1942 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
|
| 1943 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
|
| 1944 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
|
| 1945 |
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
|
| 1946 |
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
|
| 1947 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
|
| 1948 |
#define tcg_gen_andc_tl tcg_gen_andc_i32
|
| 1949 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
|
| 1950 |
#define tcg_gen_nand_tl tcg_gen_nand_i32
|
| 1951 |
#define tcg_gen_nor_tl tcg_gen_nor_i32
|
| 1952 |
#define tcg_gen_orc_tl tcg_gen_orc_i32
|
| 1953 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
|
| 1954 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
|
| 1955 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
|
| 1956 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
|
| 1957 |
#define tcg_const_tl tcg_const_i32
|
| 1958 |
#define tcg_const_local_tl tcg_const_local_i32
|
| 1959 |
#endif
|
| 1960 |
|
| 1961 |
#if TCG_TARGET_REG_BITS == 32 |
| 1962 |
#define tcg_gen_add_ptr tcg_gen_add_i32
|
| 1963 |
#define tcg_gen_addi_ptr tcg_gen_addi_i32
|
| 1964 |
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
|
| 1965 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
| 1966 |
#define tcg_gen_add_ptr tcg_gen_add_i64
|
| 1967 |
#define tcg_gen_addi_ptr tcg_gen_addi_i64
|
| 1968 |
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
|
| 1969 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
| 1970 |
|