Revision 15e89f59 hw/eepro100.c
| b/hw/eepro100.c | ||
|---|---|---|
| 48 | 48 |
#include "net.h" |
| 49 | 49 |
#include "eeprom93xx.h" |
| 50 | 50 |
|
| 51 |
/* Common declarations for all PCI devices. */ |
|
| 52 |
|
|
| 53 |
#define PCI_CONFIG_8(offset, value) \ |
|
| 54 |
(pci_conf[offset] = (value)) |
|
| 55 |
#define PCI_CONFIG_16(offset, value) \ |
|
| 56 |
(*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) |
|
| 57 |
#define PCI_CONFIG_32(offset, value) \ |
|
| 58 |
(*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) |
|
| 59 |
|
|
| 60 | 51 |
#define KiB 1024 |
| 61 | 52 |
|
| 62 | 53 |
/* Debug EEPRO100 card. */ |
| ... | ... | |
| 467 | 458 |
/* PCI Vendor ID */ |
| 468 | 459 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
| 469 | 460 |
/* PCI Device ID depends on device and is set below. */ |
| 470 |
/* PCI Command */ |
|
| 471 |
/* TODO: this is the default, do not override. */ |
|
| 472 |
PCI_CONFIG_16(PCI_COMMAND, 0x0000); |
|
| 473 | 461 |
/* PCI Status */ |
| 474 |
/* TODO: Value at RST# should be 0. */ |
|
| 475 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); |
|
| 462 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); |
|
| 476 | 463 |
/* PCI Revision ID */ |
| 477 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x08); |
|
| 478 |
/* TODO: this is the default, do not override. */ |
|
| 479 |
/* PCI Class Code */ |
|
| 480 |
PCI_CONFIG_8(PCI_CLASS_PROG, 0x00); |
|
| 464 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08); |
|
| 481 | 465 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
| 482 |
/* PCI Cache Line Size */ |
|
| 483 |
/* check cache line size!!! */ |
|
| 484 |
#if 0 |
|
| 485 |
PCI_CONFIG_8(0x0c, 0x00); |
|
| 486 |
#endif |
|
| 487 | 466 |
/* PCI Latency Timer */ |
| 488 |
PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ |
|
| 489 |
/* PCI Header Type */ |
|
| 490 |
/* BIST (built-in self test) */ |
|
| 491 |
/* Expansion ROM Base Address (depends on boot disable!!!) */ |
|
| 492 |
/* TODO: not needed, set when BAR is registered */ |
|
| 493 |
PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY); |
|
| 467 |
pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ |
|
| 494 | 468 |
/* Capability Pointer */ |
| 495 | 469 |
/* TODO: revisions with power_management 1 use this but |
| 496 | 470 |
* do not set new capability list bit in status register. */ |
| 497 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc); |
|
| 498 |
/* Interrupt Line */ |
|
| 499 |
/* Interrupt Pin */ |
|
| 500 |
/* TODO: RST# value should be 0 */ |
|
| 501 |
PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); /* interrupt pin 0 */ |
|
| 471 |
pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0xdc); |
|
| 502 | 472 |
/* Minimum Grant */ |
| 503 |
PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
|
|
| 473 |
pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
|
|
| 504 | 474 |
/* Maximum Latency */ |
| 505 |
PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
|
|
| 475 |
pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
|
|
| 506 | 476 |
|
| 507 | 477 |
switch (device) {
|
| 508 | 478 |
case i82550: |
| 509 | 479 |
/* TODO: check device id. */ |
| 510 | 480 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 511 | 481 |
/* Revision ID: 0x0c, 0x0d, 0x0e. */ |
| 512 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
|
|
| 482 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
|
|
| 513 | 483 |
/* TODO: check size of statistical counters. */ |
| 514 | 484 |
s->stats_size = 80; |
| 515 | 485 |
/* TODO: check extended tcb support. */ |
| ... | ... | |
| 518 | 488 |
case i82551: |
| 519 | 489 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 520 | 490 |
/* Revision ID: 0x0f, 0x10. */ |
| 521 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
|
|
| 491 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0f);
|
|
| 522 | 492 |
/* TODO: check size of statistical counters. */ |
| 523 | 493 |
s->stats_size = 80; |
| 524 | 494 |
s->has_extended_tcb_support = 1; |
| 525 | 495 |
break; |
| 526 | 496 |
case i82557A: |
| 527 | 497 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 528 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
|
|
| 529 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
|
|
| 498 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x01);
|
|
| 499 |
pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
|
|
| 530 | 500 |
power_management = 0; |
| 531 | 501 |
break; |
| 532 | 502 |
case i82557B: |
| 533 | 503 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 534 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
|
|
| 535 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
|
|
| 504 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x02);
|
|
| 505 |
pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
|
|
| 536 | 506 |
power_management = 0; |
| 537 | 507 |
break; |
| 538 | 508 |
case i82557C: |
| 539 | 509 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 540 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
|
|
| 541 |
PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
|
|
| 510 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x03);
|
|
| 511 |
pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
|
|
| 542 | 512 |
power_management = 0; |
| 543 | 513 |
break; |
| 544 | 514 |
case i82558A: |
| 545 | 515 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 546 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 516 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 547 | 517 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
| 548 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
|
|
| 518 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x04);
|
|
| 549 | 519 |
s->stats_size = 76; |
| 550 | 520 |
s->has_extended_tcb_support = 1; |
| 551 | 521 |
break; |
| 552 | 522 |
case i82558B: |
| 553 | 523 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 554 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 524 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 555 | 525 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
| 556 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
|
|
| 526 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x05);
|
|
| 557 | 527 |
s->stats_size = 76; |
| 558 | 528 |
s->has_extended_tcb_support = 1; |
| 559 | 529 |
break; |
| 560 | 530 |
case i82559A: |
| 561 | 531 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 562 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 532 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 563 | 533 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
| 564 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
|
|
| 534 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x06);
|
|
| 565 | 535 |
s->stats_size = 80; |
| 566 | 536 |
s->has_extended_tcb_support = 1; |
| 567 | 537 |
break; |
| 568 | 538 |
case i82559B: |
| 569 | 539 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 570 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 540 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 571 | 541 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
| 572 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
|
|
| 542 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x07);
|
|
| 573 | 543 |
s->stats_size = 80; |
| 574 | 544 |
s->has_extended_tcb_support = 1; |
| 575 | 545 |
break; |
| 576 | 546 |
case i82559C: |
| 577 | 547 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557); |
| 578 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 548 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 579 | 549 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
| 580 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
|
| 550 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08);
|
|
| 581 | 551 |
/* TODO: Windows wants revision id 0x0c. */ |
| 582 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
|
|
| 552 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0c);
|
|
| 583 | 553 |
#if EEPROM_SIZE > 0 |
| 584 |
PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
|
|
| 585 |
PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
|
|
| 554 |
pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
|
|
| 555 |
pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
|
|
| 586 | 556 |
#endif |
| 587 | 557 |
s->stats_size = 80; |
| 588 | 558 |
s->has_extended_tcb_support = 1; |
| 589 | 559 |
break; |
| 590 | 560 |
case i82559ER: |
| 591 | 561 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 592 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 562 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
|
|
| 593 | 563 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
| 594 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
|
|
| 564 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x09);
|
|
| 595 | 565 |
s->stats_size = 80; |
| 596 | 566 |
s->has_extended_tcb_support = 1; |
| 597 | 567 |
break; |
| ... | ... | |
| 599 | 569 |
/* TODO: check device id. */ |
| 600 | 570 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 601 | 571 |
/* TODO: wrong revision id. */ |
| 602 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
|
|
| 572 |
pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
|
|
| 603 | 573 |
s->stats_size = 80; |
| 604 | 574 |
s->has_extended_tcb_support = 1; |
| 605 | 575 |
break; |
| ... | ... | |
| 633 | 603 |
|
| 634 | 604 |
if (power_management) {
|
| 635 | 605 |
/* Power Management Capabilities */ |
| 636 |
PCI_CONFIG_8(0xdc, 0x01);
|
|
| 606 |
pci_set_byte(pci_conf + 0xdc, 0x01);
|
|
| 637 | 607 |
/* Next Item Pointer */ |
| 638 | 608 |
/* Capability ID */ |
| 639 |
PCI_CONFIG_16(0xde, 0x7e21);
|
|
| 609 |
pci_set_word(pci_conf + 0xde, 0x7e21);
|
|
| 640 | 610 |
/* TODO: Power Management Control / Status. */ |
| 641 | 611 |
/* TODO: Ethernet Power Consumption Registers (i82559 and later). */ |
| 642 | 612 |
} |
Also available in: Unified diff