Revision 1632dc6a
| b/hw/i8259.c | ||
|---|---|---|
| 60 | 60 |
PicState pics[2]; |
| 61 | 61 |
qemu_irq parent_irq; |
| 62 | 62 |
void *irq_request_opaque; |
| 63 |
/* IOAPIC callback support */ |
|
| 64 |
SetIRQFunc *alt_irq_func; |
|
| 65 |
void *alt_irq_opaque; |
|
| 66 | 63 |
}; |
| 67 | 64 |
|
| 68 | 65 |
#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) |
| ... | ... | |
| 203 | 200 |
} |
| 204 | 201 |
#endif |
| 205 | 202 |
pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); |
| 206 |
/* used for IOAPIC irqs */ |
|
| 207 |
if (s->alt_irq_func) |
|
| 208 |
s->alt_irq_func(s->alt_irq_opaque, irq, level); |
|
| 209 | 203 |
pic_update_irq(s); |
| 210 | 204 |
} |
| 211 | 205 |
|
| ... | ... | |
| 562 | 556 |
isa_pic = s; |
| 563 | 557 |
return qemu_allocate_irqs(i8259_set_irq, s, 16); |
| 564 | 558 |
} |
| 565 |
|
|
| 566 |
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func, |
|
| 567 |
void *alt_irq_opaque) |
|
| 568 |
{
|
|
| 569 |
s->alt_irq_func = alt_irq_func; |
|
| 570 |
s->alt_irq_opaque = alt_irq_opaque; |
|
| 571 |
} |
|
| b/hw/ioapic.c | ||
|---|---|---|
| 241 | 241 |
ioapic_mem_writel, |
| 242 | 242 |
}; |
| 243 | 243 |
|
| 244 |
IOAPICState *ioapic_init(void)
|
|
| 244 |
qemu_irq *ioapic_init(void)
|
|
| 245 | 245 |
{
|
| 246 | 246 |
IOAPICState *s; |
| 247 |
qemu_irq *irq; |
|
| 247 | 248 |
int io_memory; |
| 248 | 249 |
|
| 249 | 250 |
s = qemu_mallocz(sizeof(IOAPICState)); |
| ... | ... | |
| 255 | 256 |
|
| 256 | 257 |
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
|
| 257 | 258 |
qemu_register_reset(ioapic_reset, s); |
| 259 |
irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS); |
|
| 258 | 260 |
|
| 259 |
return s;
|
|
| 261 |
return irq;
|
|
| 260 | 262 |
} |
| b/hw/pc.c | ||
|---|---|---|
| 61 | 61 |
static fdctrl_t *floppy_controller; |
| 62 | 62 |
static RTCState *rtc_state; |
| 63 | 63 |
static PITState *pit; |
| 64 |
static IOAPICState *ioapic; |
|
| 65 | 64 |
static PCIDevice *i440fx_state; |
| 66 | 65 |
|
| 67 | 66 |
typedef struct rom_reset_data {
|
| ... | ... | |
| 90 | 89 |
|
| 91 | 90 |
typedef struct isa_irq_state {
|
| 92 | 91 |
qemu_irq *i8259; |
| 92 |
qemu_irq *ioapic; |
|
| 93 | 93 |
} IsaIrqState; |
| 94 | 94 |
|
| 95 | 95 |
static void isa_irq_handler(void *opaque, int n, int level) |
| 96 | 96 |
{
|
| 97 | 97 |
IsaIrqState *isa = (IsaIrqState *)opaque; |
| 98 | 98 |
|
| 99 |
qemu_set_irq(isa->i8259[n], level); |
|
| 100 |
} |
|
| 99 |
if (n < 16) {
|
|
| 100 |
qemu_set_irq(isa->i8259[n], level); |
|
| 101 |
} |
|
| 102 |
qemu_set_irq(isa->ioapic[n], level); |
|
| 103 |
}; |
|
| 101 | 104 |
|
| 102 | 105 |
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
| 103 | 106 |
{
|
| ... | ... | |
| 1282 | 1285 |
i8259 = i8259_init(cpu_irq[0]); |
| 1283 | 1286 |
isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state)); |
| 1284 | 1287 |
isa_irq_state->i8259 = i8259; |
| 1285 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 16);
|
|
| 1288 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
|
|
| 1286 | 1289 |
ferr_irq = isa_irq[13]; |
| 1287 | 1290 |
|
| 1288 | 1291 |
if (pci_enabled) {
|
| ... | ... | |
| 1324 | 1327 |
register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
| 1325 | 1328 |
|
| 1326 | 1329 |
if (pci_enabled) {
|
| 1327 |
ioapic = ioapic_init(); |
|
| 1330 |
isa_irq_state->ioapic = ioapic_init();
|
|
| 1328 | 1331 |
} |
| 1329 | 1332 |
pit = pit_init(0x40, isa_irq[0]); |
| 1330 | 1333 |
pcspk_init(pit); |
| 1331 | 1334 |
if (!no_hpet) {
|
| 1332 | 1335 |
hpet_init(isa_irq); |
| 1333 | 1336 |
} |
| 1334 |
if (pci_enabled) {
|
|
| 1335 |
pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); |
|
| 1336 |
} |
|
| 1337 | 1337 |
|
| 1338 | 1338 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
|
| 1339 | 1339 |
if (serial_hds[i]) {
|
| b/hw/pc.h | ||
|---|---|---|
| 26 | 26 |
void pic_set_irq(int irq, int level); |
| 27 | 27 |
void pic_set_irq_new(void *opaque, int irq, int level); |
| 28 | 28 |
qemu_irq *i8259_init(qemu_irq parent_irq); |
| 29 |
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func, |
|
| 30 |
void *alt_irq_opaque); |
|
| 31 | 29 |
int pic_read_irq(PicState2 *s); |
| 32 | 30 |
void pic_update_irq(PicState2 *s); |
| 33 | 31 |
uint32_t pic_intack_read(PicState2 *s); |
| ... | ... | |
| 44 | 42 |
int apic_accept_pic_intr(CPUState *env); |
| 45 | 43 |
void apic_deliver_pic_intr(CPUState *env, int level); |
| 46 | 44 |
int apic_get_interrupt(CPUState *env); |
| 47 |
IOAPICState *ioapic_init(void);
|
|
| 45 |
qemu_irq *ioapic_init(void);
|
|
| 48 | 46 |
void ioapic_set_irq(void *opaque, int vector, int level); |
| 49 | 47 |
void apic_reset_irq_delivered(void); |
| 50 | 48 |
int apic_get_irq_delivered(void); |
Also available in: Unified diff