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/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "fdc.h" |
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#include "pci.h" |
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#include "block.h" |
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#include "sysemu.h" |
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#include "audio/audio.h" |
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#include "net.h" |
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#include "smbus.h" |
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#include "boards.h" |
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#include "monitor.h" |
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#include "fw_cfg.h" |
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#include "hpet_emul.h" |
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#include "watchdog.h" |
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#include "smbios.h" |
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|
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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|
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/* Show multiboot debug output */
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//#define DEBUG_MULTIBOOT
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#define BIOS_FILENAME "bios.bin" |
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#define VGABIOS_FILENAME "vgabios.bin" |
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#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
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|
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
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|
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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#define ACPI_DATA_SIZE 0x10000 |
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#define BIOS_CFG_IOPORT 0x510 |
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
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|
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#define MAX_IDE_BUS 2 |
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|
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static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
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static PITState *pit;
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static PCIDevice *i440fx_state;
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|
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typedef struct rom_reset_data { |
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uint8_t *data; |
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target_phys_addr_t addr; |
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unsigned size;
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} RomResetData; |
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static void option_rom_reset(void *_rrd) |
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{ |
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RomResetData *rrd = _rrd; |
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cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size); |
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} |
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|
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static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size) |
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{ |
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RomResetData *rrd = qemu_malloc(sizeof *rrd);
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|
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rrd->data = qemu_malloc(size); |
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cpu_physical_memory_read(addr, rrd->data, size); |
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rrd->addr = addr; |
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rrd->size = size; |
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qemu_register_reset(option_rom_reset, rrd); |
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} |
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|
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typedef struct isa_irq_state { |
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qemu_irq *i8259; |
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qemu_irq *ioapic; |
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} IsaIrqState; |
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|
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static void isa_irq_handler(void *opaque, int n, int level) |
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{ |
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IsaIrqState *isa = (IsaIrqState *)opaque; |
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if (n < 16) { |
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qemu_set_irq(isa->i8259[n], level); |
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} |
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qemu_set_irq(isa->ioapic[n], level); |
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}; |
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|
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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} |
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{ |
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qemu_irq_raise(ferr_irq); |
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} |
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|
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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qemu_irq_lower(ferr_irq); |
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} |
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|
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env) |
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{ |
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/* Note: when using kqemu, it is more logical to return the host TSC
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because kqemu does not trap the RDTSC instruction for
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performance reasons */
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#ifdef CONFIG_KQEMU
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if (env->kqemu_enabled) {
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return cpu_get_real_ticks();
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} else
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#endif
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{ |
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return cpu_get_ticks();
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} |
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} |
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/* SMM support */
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void cpu_smm_update(CPUState *env)
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{ |
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if (i440fx_state && env == first_cpu)
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i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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} |
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{ |
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int intno;
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intno = apic_get_interrupt(env); |
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if (intno >= 0) { |
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/* set irq request if a PIC irq is still pending */
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/* XXX: improve that */
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pic_update_irq(isa_pic); |
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return intno;
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} |
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(env))
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return -1; |
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intno = pic_read_irq(isa_pic); |
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return intno;
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} |
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static void pic_irq_request(void *opaque, int irq, int level) |
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{ |
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CPUState *env = first_cpu; |
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if (env->apic_state) {
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while (env) {
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if (apic_accept_pic_intr(env))
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apic_deliver_pic_intr(env, level); |
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env = env->next_cpu; |
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} |
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} else {
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if (level)
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14 |
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static int cmos_get_fd_drive_type(int fd0) |
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{ |
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int val;
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switch (fd0) {
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case 0: |
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/* 1.44 Mb 3"5 drive */
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val = 4;
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break;
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case 1: |
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/* 2.88 Mb 3"5 drive */
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val = 5;
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break;
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case 2: |
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/* 1.2 Mb 5"5 drive */
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val = 2;
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break;
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default:
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val = 0;
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break;
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} |
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return val;
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} |
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
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{ |
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RTCState *s = rtc_state; |
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int cylinders, heads, sectors;
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bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
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rtc_set_memory(s, type_ofs, 47);
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rtc_set_memory(s, info_ofs, cylinders); |
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rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 2, heads);
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rtc_set_memory(s, info_ofs + 3, 0xff); |
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rtc_set_memory(s, info_ofs + 4, 0xff); |
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rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
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rtc_set_memory(s, info_ofs + 6, cylinders);
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rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 8, sectors);
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} |
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|
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device) |
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{ |
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switch(boot_device) {
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case 'a': |
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case 'b': |
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return 0x01; /* floppy boot */ |
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case 'c': |
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return 0x02; /* hard drive boot */ |
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case 'd': |
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return 0x03; /* CD-ROM boot */ |
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case 'n': |
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return 0x04; /* Network boot */ |
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} |
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return 0; |
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} |
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/* copy/pasted from cmos_init, should be made a general function
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and used there as well */
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static int pc_boot_set(void *opaque, const char *boot_device) |
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{ |
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Monitor *mon = cur_mon; |
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#define PC_MAX_BOOT_DEVICES 3 |
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RTCState *s = (RTCState *)opaque; |
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int nbds, bds[3] = { 0, }; |
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int i;
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nbds = strlen(boot_device); |
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if (nbds > PC_MAX_BOOT_DEVICES) {
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monitor_printf(mon, "Too many boot devices for PC\n");
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return(1); |
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} |
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for (i = 0; i < nbds; i++) { |
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bds[i] = boot_device2nibble(boot_device[i]); |
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if (bds[i] == 0) { |
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monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
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boot_device[i]); |
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return(1); |
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} |
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} |
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
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rtc_set_memory(s, 0x38, (bds[2] << 4)); |
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return(0); |
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} |
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|
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/* hd_table must contain 4 block drivers */
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
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const char *boot_device, BlockDriverState **hd_table) |
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{ |
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RTCState *s = rtc_state; |
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int nbds, bds[3] = { 0, }; |
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int val;
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int fd0, fd1, nb;
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int i;
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|
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/* various important CMOS locations needed by PC/Bochs bios */
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|
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/* memory size */
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val = 640; /* base memory in K */ |
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rtc_set_memory(s, 0x15, val);
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rtc_set_memory(s, 0x16, val >> 8); |
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val = (ram_size / 1024) - 1024; |
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if (val > 65535) |
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val = 65535;
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rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8); |
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rtc_set_memory(s, 0x30, val);
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rtc_set_memory(s, 0x31, val >> 8); |
298 |
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if (above_4g_mem_size) {
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rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
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rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
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rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
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} |
304 |
|
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if (ram_size > (16 * 1024 * 1024)) |
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val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
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else
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val = 0;
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if (val > 65535) |
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val = 65535;
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rtc_set_memory(s, 0x34, val);
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rtc_set_memory(s, 0x35, val >> 8); |
313 |
|
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/* set the number of CPU */
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rtc_set_memory(s, 0x5f, smp_cpus - 1); |
316 |
|
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/* set boot devices, and disable floppy signature check if requested */
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#define PC_MAX_BOOT_DEVICES 3 |
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nbds = strlen(boot_device); |
320 |
if (nbds > PC_MAX_BOOT_DEVICES) {
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fprintf(stderr, "Too many boot devices for PC\n");
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exit(1);
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} |
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for (i = 0; i < nbds; i++) { |
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bds[i] = boot_device2nibble(boot_device[i]); |
326 |
if (bds[i] == 0) { |
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fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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boot_device[i]); |
329 |
exit(1);
|
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} |
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} |
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
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rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
334 |
|
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/* floppy type */
|
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|
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fd0 = fdctrl_get_drive_type(floppy_controller, 0);
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fd1 = fdctrl_get_drive_type(floppy_controller, 1);
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|
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val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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rtc_set_memory(s, 0x10, val);
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|
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val = 0;
|
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nb = 0;
|
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if (fd0 < 3) |
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nb++; |
347 |
if (fd1 < 3) |
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nb++; |
349 |
switch (nb) {
|
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case 0: |
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break;
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case 1: |
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val |= 0x01; /* 1 drive, ready for boot */ |
354 |
break;
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case 2: |
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val |= 0x41; /* 2 drives, ready for boot */ |
357 |
break;
|
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} |
359 |
val |= 0x02; /* FPU is there */ |
360 |
val |= 0x04; /* PS/2 mouse installed */ |
361 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
362 |
|
363 |
/* hard drives */
|
364 |
|
365 |
rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
366 |
if (hd_table[0]) |
367 |
cmos_init_hd(0x19, 0x1b, hd_table[0]); |
368 |
if (hd_table[1]) |
369 |
cmos_init_hd(0x1a, 0x24, hd_table[1]); |
370 |
|
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val = 0;
|
372 |
for (i = 0; i < 4; i++) { |
373 |
if (hd_table[i]) {
|
374 |
int cylinders, heads, sectors, translation;
|
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/* NOTE: bdrv_get_geometry_hint() returns the physical
|
376 |
geometry. It is always such that: 1 <= sects <= 63, 1
|
377 |
<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
378 |
geometry can be different if a translation is done. */
|
379 |
translation = bdrv_get_translation_hint(hd_table[i]); |
380 |
if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
381 |
bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); |
382 |
if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
383 |
/* No translation. */
|
384 |
translation = 0;
|
385 |
} else {
|
386 |
/* LBA translation. */
|
387 |
translation = 1;
|
388 |
} |
389 |
} else {
|
390 |
translation--; |
391 |
} |
392 |
val |= translation << (i * 2);
|
393 |
} |
394 |
} |
395 |
rtc_set_memory(s, 0x39, val);
|
396 |
} |
397 |
|
398 |
void ioport_set_a20(int enable) |
399 |
{ |
400 |
/* XXX: send to all CPUs ? */
|
401 |
cpu_x86_set_a20(first_cpu, enable); |
402 |
} |
403 |
|
404 |
int ioport_get_a20(void) |
405 |
{ |
406 |
return ((first_cpu->a20_mask >> 20) & 1); |
407 |
} |
408 |
|
409 |
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
410 |
{ |
411 |
ioport_set_a20((val >> 1) & 1); |
412 |
/* XXX: bit 0 is fast reset */
|
413 |
} |
414 |
|
415 |
static uint32_t ioport92_read(void *opaque, uint32_t addr) |
416 |
{ |
417 |
return ioport_get_a20() << 1; |
418 |
} |
419 |
|
420 |
/***********************************************************/
|
421 |
/* Bochs BIOS debug ports */
|
422 |
|
423 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
424 |
{ |
425 |
static const char shutdown_str[8] = "Shutdown"; |
426 |
static int shutdown_index = 0; |
427 |
|
428 |
switch(addr) {
|
429 |
/* Bochs BIOS messages */
|
430 |
case 0x400: |
431 |
case 0x401: |
432 |
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
433 |
exit(1);
|
434 |
case 0x402: |
435 |
case 0x403: |
436 |
#ifdef DEBUG_BIOS
|
437 |
fprintf(stderr, "%c", val);
|
438 |
#endif
|
439 |
break;
|
440 |
case 0x8900: |
441 |
/* same as Bochs power off */
|
442 |
if (val == shutdown_str[shutdown_index]) {
|
443 |
shutdown_index++; |
444 |
if (shutdown_index == 8) { |
445 |
shutdown_index = 0;
|
446 |
qemu_system_shutdown_request(); |
447 |
} |
448 |
} else {
|
449 |
shutdown_index = 0;
|
450 |
} |
451 |
break;
|
452 |
|
453 |
/* LGPL'ed VGA BIOS messages */
|
454 |
case 0x501: |
455 |
case 0x502: |
456 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
457 |
exit(1);
|
458 |
case 0x500: |
459 |
case 0x503: |
460 |
#ifdef DEBUG_BIOS
|
461 |
fprintf(stderr, "%c", val);
|
462 |
#endif
|
463 |
break;
|
464 |
} |
465 |
} |
466 |
|
467 |
extern uint64_t node_cpumask[MAX_NODES];
|
468 |
|
469 |
static void *bochs_bios_init(void) |
470 |
{ |
471 |
void *fw_cfg;
|
472 |
uint8_t *smbios_table; |
473 |
size_t smbios_len; |
474 |
uint64_t *numa_fw_cfg; |
475 |
int i, j;
|
476 |
|
477 |
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
478 |
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
479 |
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
480 |
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
481 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
482 |
|
483 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
484 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
485 |
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
486 |
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
487 |
|
488 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
489 |
|
490 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
491 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
492 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
493 |
acpi_tables_len); |
494 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
|
495 |
|
496 |
smbios_table = smbios_get_table(&smbios_len); |
497 |
if (smbios_table)
|
498 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
499 |
smbios_table, smbios_len); |
500 |
|
501 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
502 |
* of nodes, one word for each VCPU->node and one word for each node to
|
503 |
* hold the amount of memory.
|
504 |
*/
|
505 |
numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
506 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
507 |
for (i = 0; i < smp_cpus; i++) { |
508 |
for (j = 0; j < nb_numa_nodes; j++) { |
509 |
if (node_cpumask[j] & (1 << i)) { |
510 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
511 |
break;
|
512 |
} |
513 |
} |
514 |
} |
515 |
for (i = 0; i < nb_numa_nodes; i++) { |
516 |
numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
517 |
} |
518 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
519 |
(1 + smp_cpus + nb_numa_nodes) * 8); |
520 |
|
521 |
return fw_cfg;
|
522 |
} |
523 |
|
524 |
/* Generate an initial boot sector which sets state and jump to
|
525 |
a specified vector */
|
526 |
static void generate_bootsect(target_phys_addr_t option_rom, |
527 |
uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
528 |
{ |
529 |
uint8_t rom[512], *p, *reloc;
|
530 |
uint8_t sum; |
531 |
int i;
|
532 |
|
533 |
memset(rom, 0, sizeof(rom)); |
534 |
|
535 |
p = rom; |
536 |
/* Make sure we have an option rom signature */
|
537 |
*p++ = 0x55;
|
538 |
*p++ = 0xaa;
|
539 |
|
540 |
/* ROM size in sectors*/
|
541 |
*p++ = 1;
|
542 |
|
543 |
/* Hook int19 */
|
544 |
|
545 |
*p++ = 0x50; /* push ax */ |
546 |
*p++ = 0x1e; /* push ds */ |
547 |
*p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ |
548 |
*p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ |
549 |
|
550 |
*p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ |
551 |
*p++ = 0x64; *p++ = 0x00; |
552 |
reloc = p; |
553 |
*p++ = 0x00; *p++ = 0x00; |
554 |
|
555 |
*p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ |
556 |
*p++ = 0x66; *p++ = 0x00; |
557 |
|
558 |
*p++ = 0x1f; /* pop ds */ |
559 |
*p++ = 0x58; /* pop ax */ |
560 |
*p++ = 0xcb; /* lret */ |
561 |
|
562 |
/* Actual code */
|
563 |
*reloc = (p - rom); |
564 |
|
565 |
*p++ = 0xfa; /* CLI */ |
566 |
*p++ = 0xfc; /* CLD */ |
567 |
|
568 |
for (i = 0; i < 6; i++) { |
569 |
if (i == 1) /* Skip CS */ |
570 |
continue;
|
571 |
|
572 |
*p++ = 0xb8; /* MOV AX,imm16 */ |
573 |
*p++ = segs[i]; |
574 |
*p++ = segs[i] >> 8;
|
575 |
*p++ = 0x8e; /* MOV <seg>,AX */ |
576 |
*p++ = 0xc0 + (i << 3); |
577 |
} |
578 |
|
579 |
for (i = 0; i < 8; i++) { |
580 |
*p++ = 0x66; /* 32-bit operand size */ |
581 |
*p++ = 0xb8 + i; /* MOV <reg>,imm32 */ |
582 |
*p++ = gpr[i]; |
583 |
*p++ = gpr[i] >> 8;
|
584 |
*p++ = gpr[i] >> 16;
|
585 |
*p++ = gpr[i] >> 24;
|
586 |
} |
587 |
|
588 |
*p++ = 0xea; /* JMP FAR */ |
589 |
*p++ = ip; /* IP */
|
590 |
*p++ = ip >> 8;
|
591 |
*p++ = segs[1]; /* CS */ |
592 |
*p++ = segs[1] >> 8; |
593 |
|
594 |
/* sign rom */
|
595 |
sum = 0;
|
596 |
for (i = 0; i < (sizeof(rom) - 1); i++) |
597 |
sum += rom[i]; |
598 |
rom[sizeof(rom) - 1] = -sum; |
599 |
|
600 |
cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
|
601 |
option_rom_setup_reset(option_rom, sizeof (rom));
|
602 |
} |
603 |
|
604 |
static long get_file_size(FILE *f) |
605 |
{ |
606 |
long where, size;
|
607 |
|
608 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
609 |
|
610 |
where = ftell(f); |
611 |
fseek(f, 0, SEEK_END);
|
612 |
size = ftell(f); |
613 |
fseek(f, where, SEEK_SET); |
614 |
|
615 |
return size;
|
616 |
} |
617 |
|
618 |
#define MULTIBOOT_STRUCT_ADDR 0x9000 |
619 |
|
620 |
#if MULTIBOOT_STRUCT_ADDR > 0xf0000 |
621 |
#error multiboot struct needs to fit in 16 bit real mode |
622 |
#endif
|
623 |
|
624 |
static int load_multiboot(void *fw_cfg, |
625 |
FILE *f, |
626 |
const char *kernel_filename, |
627 |
const char *initrd_filename, |
628 |
const char *kernel_cmdline, |
629 |
uint8_t *header) |
630 |
{ |
631 |
int i, t, is_multiboot = 0; |
632 |
uint32_t flags = 0;
|
633 |
uint32_t mh_entry_addr; |
634 |
uint32_t mh_load_addr; |
635 |
uint32_t mb_kernel_size; |
636 |
uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR; |
637 |
uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
|
638 |
uint32_t mb_cmdline = mb_bootinfo + 0x200;
|
639 |
uint32_t mb_mod_end; |
640 |
|
641 |
/* Ok, let's see if it is a multiboot image.
|
642 |
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
|
643 |
for (i = 0; i < (8192 - 48); i += 4) { |
644 |
if (ldl_p(header+i) == 0x1BADB002) { |
645 |
uint32_t checksum = ldl_p(header+i+8);
|
646 |
flags = ldl_p(header+i+4);
|
647 |
checksum += flags; |
648 |
checksum += (uint32_t)0x1BADB002;
|
649 |
if (!checksum) {
|
650 |
is_multiboot = 1;
|
651 |
break;
|
652 |
} |
653 |
} |
654 |
} |
655 |
|
656 |
if (!is_multiboot)
|
657 |
return 0; /* no multiboot */ |
658 |
|
659 |
#ifdef DEBUG_MULTIBOOT
|
660 |
fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
|
661 |
#endif
|
662 |
|
663 |
if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */ |
664 |
fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
|
665 |
} |
666 |
if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */ |
667 |
uint64_t elf_entry; |
668 |
int kernel_size;
|
669 |
fclose(f); |
670 |
kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
671 |
if (kernel_size < 0) { |
672 |
fprintf(stderr, "Error while loading elf kernel\n");
|
673 |
exit(1);
|
674 |
} |
675 |
mh_load_addr = mh_entry_addr = elf_entry; |
676 |
mb_kernel_size = kernel_size; |
677 |
|
678 |
#ifdef DEBUG_MULTIBOOT
|
679 |
fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
|
680 |
mb_kernel_size, (size_t)mh_entry_addr); |
681 |
#endif
|
682 |
} else {
|
683 |
/* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
|
684 |
uint32_t mh_header_addr = ldl_p(header+i+12);
|
685 |
mh_load_addr = ldl_p(header+i+16);
|
686 |
#ifdef DEBUG_MULTIBOOT
|
687 |
uint32_t mh_load_end_addr = ldl_p(header+i+20);
|
688 |
uint32_t mh_bss_end_addr = ldl_p(header+i+24);
|
689 |
#endif
|
690 |
uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr); |
691 |
|
692 |
mh_entry_addr = ldl_p(header+i+28);
|
693 |
mb_kernel_size = get_file_size(f) - mb_kernel_text_offset; |
694 |
|
695 |
/* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
|
696 |
uint32_t mh_mode_type = ldl_p(header+i+32);
|
697 |
uint32_t mh_width = ldl_p(header+i+36);
|
698 |
uint32_t mh_height = ldl_p(header+i+40);
|
699 |
uint32_t mh_depth = ldl_p(header+i+44); */
|
700 |
|
701 |
#ifdef DEBUG_MULTIBOOT
|
702 |
fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
|
703 |
fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
|
704 |
fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
|
705 |
fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
|
706 |
#endif
|
707 |
|
708 |
fseek(f, mb_kernel_text_offset, SEEK_SET); |
709 |
|
710 |
#ifdef DEBUG_MULTIBOOT
|
711 |
fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
|
712 |
mb_kernel_size, mh_load_addr); |
713 |
#endif
|
714 |
|
715 |
if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
|
716 |
fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
|
717 |
kernel_filename, mb_kernel_size); |
718 |
exit(1);
|
719 |
} |
720 |
fclose(f); |
721 |
} |
722 |
|
723 |
/* blob size is only the kernel for now */
|
724 |
mb_mod_end = mh_load_addr + mb_kernel_size; |
725 |
|
726 |
/* load modules */
|
727 |
stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */ |
728 |
if (initrd_filename) {
|
729 |
uint32_t mb_mod_info = mb_bootinfo + 0x100;
|
730 |
uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
|
731 |
uint32_t mb_mod_start = mh_load_addr; |
732 |
uint32_t mb_mod_length = mb_kernel_size; |
733 |
char *next_initrd;
|
734 |
char *next_space;
|
735 |
int mb_mod_count = 0; |
736 |
|
737 |
do {
|
738 |
next_initrd = strchr(initrd_filename, ',');
|
739 |
if (next_initrd)
|
740 |
*next_initrd = '\0';
|
741 |
/* if a space comes after the module filename, treat everything
|
742 |
after that as parameters */
|
743 |
cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename, |
744 |
strlen(initrd_filename) + 1);
|
745 |
stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */ |
746 |
mb_mod_cmdline += strlen(initrd_filename) + 1;
|
747 |
if ((next_space = strchr(initrd_filename, ' '))) |
748 |
*next_space = '\0';
|
749 |
#ifdef DEBUG_MULTIBOOT
|
750 |
printf("multiboot loading module: %s\n", initrd_filename);
|
751 |
#endif
|
752 |
f = fopen(initrd_filename, "rb");
|
753 |
if (f) {
|
754 |
mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
|
755 |
& (TARGET_PAGE_MASK); |
756 |
mb_mod_length = get_file_size(f); |
757 |
mb_mod_end = mb_mod_start + mb_mod_length; |
758 |
|
759 |
if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
|
760 |
fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
|
761 |
initrd_filename, mb_mod_length); |
762 |
exit(1);
|
763 |
} |
764 |
|
765 |
mb_mod_count++; |
766 |
stl_phys(mb_mod_info + 0, mb_mod_start);
|
767 |
stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
|
768 |
#ifdef DEBUG_MULTIBOOT
|
769 |
printf("mod_start: %#x\nmod_end: %#x\n", mb_mod_start,
|
770 |
mb_mod_start + mb_mod_length); |
771 |
#endif
|
772 |
stl_phys(mb_mod_info + 12, 0x0); /* reserved */ |
773 |
} |
774 |
initrd_filename = next_initrd+1;
|
775 |
mb_mod_info += 16;
|
776 |
} while (next_initrd);
|
777 |
stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */ |
778 |
stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */ |
779 |
} |
780 |
|
781 |
/* Make sure we're getting kernel + modules back after reset */
|
782 |
option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr); |
783 |
|
784 |
/* Commandline support */
|
785 |
stl_phys(mb_bootinfo + 16, mb_cmdline);
|
786 |
t = strlen(kernel_filename); |
787 |
cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t); |
788 |
mb_cmdline += t; |
789 |
stb_phys(mb_cmdline++, ' ');
|
790 |
t = strlen(kernel_cmdline) + 1;
|
791 |
cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t); |
792 |
|
793 |
/* the kernel is where we want it to be now */
|
794 |
|
795 |
#define MULTIBOOT_FLAGS_MEMORY (1 << 0) |
796 |
#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1) |
797 |
#define MULTIBOOT_FLAGS_CMDLINE (1 << 2) |
798 |
#define MULTIBOOT_FLAGS_MODULES (1 << 3) |
799 |
#define MULTIBOOT_FLAGS_MMAP (1 << 6) |
800 |
stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY |
801 |
| MULTIBOOT_FLAGS_BOOT_DEVICE |
802 |
| MULTIBOOT_FLAGS_CMDLINE |
803 |
| MULTIBOOT_FLAGS_MODULES |
804 |
| MULTIBOOT_FLAGS_MMAP); |
805 |
stl_phys(mb_bootinfo + 4, 640); /* mem_lower */ |
806 |
stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */ |
807 |
stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */ |
808 |
stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */ |
809 |
|
810 |
#ifdef DEBUG_MULTIBOOT
|
811 |
fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
|
812 |
#endif
|
813 |
|
814 |
/* Pass variables to option rom */
|
815 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr); |
816 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo); |
817 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr); |
818 |
|
819 |
/* Make sure we're getting the config space back after reset */
|
820 |
option_rom_setup_reset(mb_bootinfo, 0x500);
|
821 |
|
822 |
option_rom[nb_option_roms] = "multiboot.bin";
|
823 |
nb_option_roms++; |
824 |
|
825 |
return 1; /* yes, we are multiboot */ |
826 |
} |
827 |
|
828 |
static void load_linux(void *fw_cfg, |
829 |
target_phys_addr_t option_rom, |
830 |
const char *kernel_filename, |
831 |
const char *initrd_filename, |
832 |
const char *kernel_cmdline, |
833 |
target_phys_addr_t max_ram_size) |
834 |
{ |
835 |
uint16_t protocol; |
836 |
uint32_t gpr[8];
|
837 |
uint16_t seg[6];
|
838 |
uint16_t real_seg; |
839 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
840 |
uint32_t initrd_max; |
841 |
uint8_t header[8192];
|
842 |
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
843 |
FILE *f, *fi; |
844 |
char *vmode;
|
845 |
|
846 |
/* Align to 16 bytes as a paranoia measure */
|
847 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
848 |
|
849 |
/* load the kernel header */
|
850 |
f = fopen(kernel_filename, "rb");
|
851 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
852 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
853 |
MIN(ARRAY_SIZE(header), kernel_size)) { |
854 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
855 |
kernel_filename); |
856 |
exit(1);
|
857 |
} |
858 |
|
859 |
/* kernel protocol version */
|
860 |
#if 0
|
861 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
862 |
#endif
|
863 |
if (ldl_p(header+0x202) == 0x53726448) |
864 |
protocol = lduw_p(header+0x206);
|
865 |
else {
|
866 |
/* This looks like a multiboot kernel. If it is, let's stop
|
867 |
treating it like a Linux kernel. */
|
868 |
if (load_multiboot(fw_cfg, f, kernel_filename,
|
869 |
initrd_filename, kernel_cmdline, header)) |
870 |
return;
|
871 |
protocol = 0;
|
872 |
} |
873 |
|
874 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
875 |
/* Low kernel */
|
876 |
real_addr = 0x90000;
|
877 |
cmdline_addr = 0x9a000 - cmdline_size;
|
878 |
prot_addr = 0x10000;
|
879 |
} else if (protocol < 0x202) { |
880 |
/* High but ancient kernel */
|
881 |
real_addr = 0x90000;
|
882 |
cmdline_addr = 0x9a000 - cmdline_size;
|
883 |
prot_addr = 0x100000;
|
884 |
} else {
|
885 |
/* High and recent kernel */
|
886 |
real_addr = 0x10000;
|
887 |
cmdline_addr = 0x20000;
|
888 |
prot_addr = 0x100000;
|
889 |
} |
890 |
|
891 |
#if 0
|
892 |
fprintf(stderr,
|
893 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
894 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
895 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
896 |
real_addr,
|
897 |
cmdline_addr,
|
898 |
prot_addr);
|
899 |
#endif
|
900 |
|
901 |
/* highest address for loading the initrd */
|
902 |
if (protocol >= 0x203) |
903 |
initrd_max = ldl_p(header+0x22c);
|
904 |
else
|
905 |
initrd_max = 0x37ffffff;
|
906 |
|
907 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
908 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
909 |
|
910 |
/* kernel command line */
|
911 |
pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
|
912 |
|
913 |
if (protocol >= 0x202) { |
914 |
stl_p(header+0x228, cmdline_addr);
|
915 |
} else {
|
916 |
stw_p(header+0x20, 0xA33F); |
917 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
918 |
} |
919 |
|
920 |
/* handle vga= parameter */
|
921 |
vmode = strstr(kernel_cmdline, "vga=");
|
922 |
if (vmode) {
|
923 |
unsigned int video_mode; |
924 |
/* skip "vga=" */
|
925 |
vmode += 4;
|
926 |
if (!strncmp(vmode, "normal", 6)) { |
927 |
video_mode = 0xffff;
|
928 |
} else if (!strncmp(vmode, "ext", 3)) { |
929 |
video_mode = 0xfffe;
|
930 |
} else if (!strncmp(vmode, "ask", 3)) { |
931 |
video_mode = 0xfffd;
|
932 |
} else {
|
933 |
video_mode = strtol(vmode, NULL, 0); |
934 |
} |
935 |
stw_p(header+0x1fa, video_mode);
|
936 |
} |
937 |
|
938 |
/* loader type */
|
939 |
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
940 |
If this code is substantially changed, you may want to consider
|
941 |
incrementing the revision. */
|
942 |
if (protocol >= 0x200) |
943 |
header[0x210] = 0xB0; |
944 |
|
945 |
/* heap */
|
946 |
if (protocol >= 0x201) { |
947 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
948 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
949 |
} |
950 |
|
951 |
/* load initrd */
|
952 |
if (initrd_filename) {
|
953 |
if (protocol < 0x200) { |
954 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
955 |
exit(1);
|
956 |
} |
957 |
|
958 |
fi = fopen(initrd_filename, "rb");
|
959 |
if (!fi) {
|
960 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
961 |
initrd_filename); |
962 |
exit(1);
|
963 |
} |
964 |
|
965 |
initrd_size = get_file_size(fi); |
966 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
967 |
|
968 |
if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
|
969 |
fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
|
970 |
initrd_filename); |
971 |
exit(1);
|
972 |
} |
973 |
fclose(fi); |
974 |
|
975 |
stl_p(header+0x218, initrd_addr);
|
976 |
stl_p(header+0x21c, initrd_size);
|
977 |
} |
978 |
|
979 |
/* store the finalized header and load the rest of the kernel */
|
980 |
cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header)); |
981 |
|
982 |
setup_size = header[0x1f1];
|
983 |
if (setup_size == 0) |
984 |
setup_size = 4;
|
985 |
|
986 |
setup_size = (setup_size+1)*512; |
987 |
/* Size of protected-mode code */
|
988 |
kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header); |
989 |
|
990 |
/* In case we have read too much already, copy that over */
|
991 |
if (setup_size < ARRAY_SIZE(header)) {
|
992 |
cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size); |
993 |
prot_addr += (ARRAY_SIZE(header) - setup_size); |
994 |
setup_size = ARRAY_SIZE(header); |
995 |
} |
996 |
|
997 |
if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
|
998 |
setup_size - ARRAY_SIZE(header), f) || |
999 |
!fread_targphys_ok(prot_addr, kernel_size, f)) { |
1000 |
fprintf(stderr, "qemu: read error on kernel '%s'\n",
|
1001 |
kernel_filename); |
1002 |
exit(1);
|
1003 |
} |
1004 |
fclose(f); |
1005 |
|
1006 |
/* generate bootsector to set up the initial register state */
|
1007 |
real_seg = real_addr >> 4;
|
1008 |
seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
1009 |
seg[1] = real_seg+0x20; /* CS */ |
1010 |
memset(gpr, 0, sizeof gpr); |
1011 |
gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ |
1012 |
|
1013 |
option_rom_setup_reset(real_addr, setup_size); |
1014 |
option_rom_setup_reset(prot_addr, kernel_size); |
1015 |
option_rom_setup_reset(cmdline_addr, cmdline_size); |
1016 |
if (initrd_filename)
|
1017 |
option_rom_setup_reset(initrd_addr, initrd_size); |
1018 |
|
1019 |
generate_bootsect(option_rom, gpr, seg, 0);
|
1020 |
} |
1021 |
|
1022 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
1023 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
1024 |
static const int ide_irq[2] = { 14, 15 }; |
1025 |
|
1026 |
#define NE2000_NB_MAX 6 |
1027 |
|
1028 |
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
1029 |
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
1030 |
|
1031 |
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
1032 |
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
1033 |
|
1034 |
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
1035 |
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
1036 |
|
1037 |
#ifdef HAS_AUDIO
|
1038 |
static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
1039 |
{ |
1040 |
struct soundhw *c;
|
1041 |
|
1042 |
for (c = soundhw; c->name; ++c) {
|
1043 |
if (c->enabled) {
|
1044 |
if (c->isa) {
|
1045 |
c->init.init_isa(pic); |
1046 |
} else {
|
1047 |
if (pci_bus) {
|
1048 |
c->init.init_pci(pci_bus); |
1049 |
} |
1050 |
} |
1051 |
} |
1052 |
} |
1053 |
} |
1054 |
#endif
|
1055 |
|
1056 |
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
1057 |
{ |
1058 |
static int nb_ne2k = 0; |
1059 |
|
1060 |
if (nb_ne2k == NE2000_NB_MAX)
|
1061 |
return;
|
1062 |
isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
1063 |
nb_ne2k++; |
1064 |
} |
1065 |
|
1066 |
static int load_option_rom(const char *oprom, target_phys_addr_t start, |
1067 |
target_phys_addr_t end) |
1068 |
{ |
1069 |
int size;
|
1070 |
char *filename;
|
1071 |
|
1072 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom); |
1073 |
if (filename) {
|
1074 |
size = get_image_size(filename); |
1075 |
if (size > 0 && start + size > end) { |
1076 |
fprintf(stderr, "Not enough space to load option rom '%s'\n",
|
1077 |
oprom); |
1078 |
exit(1);
|
1079 |
} |
1080 |
size = load_image_targphys(filename, start, end - start); |
1081 |
qemu_free(filename); |
1082 |
} else {
|
1083 |
size = -1;
|
1084 |
} |
1085 |
if (size < 0) { |
1086 |
fprintf(stderr, "Could not load option rom '%s'\n", oprom);
|
1087 |
exit(1);
|
1088 |
} |
1089 |
/* Round up optiom rom size to the next 2k boundary */
|
1090 |
size = (size + 2047) & ~2047; |
1091 |
option_rom_setup_reset(start, size); |
1092 |
return size;
|
1093 |
} |
1094 |
|
1095 |
int cpu_is_bsp(CPUState *env)
|
1096 |
{ |
1097 |
return env->cpuid_apic_id == 0; |
1098 |
} |
1099 |
|
1100 |
static CPUState *pc_new_cpu(const char *cpu_model) |
1101 |
{ |
1102 |
CPUState *env; |
1103 |
|
1104 |
env = cpu_init(cpu_model); |
1105 |
if (!env) {
|
1106 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
1107 |
exit(1);
|
1108 |
} |
1109 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
1110 |
env->cpuid_apic_id = env->cpu_index; |
1111 |
/* APIC reset callback resets cpu */
|
1112 |
apic_init(env); |
1113 |
} else {
|
1114 |
qemu_register_reset((QEMUResetHandler*)cpu_reset, env); |
1115 |
} |
1116 |
return env;
|
1117 |
} |
1118 |
|
1119 |
/* PC hardware initialisation */
|
1120 |
static void pc_init1(ram_addr_t ram_size, |
1121 |
const char *boot_device, |
1122 |
const char *kernel_filename, |
1123 |
const char *kernel_cmdline, |
1124 |
const char *initrd_filename, |
1125 |
const char *cpu_model, |
1126 |
int pci_enabled)
|
1127 |
{ |
1128 |
char *filename;
|
1129 |
int ret, linux_boot, i;
|
1130 |
ram_addr_t ram_addr, bios_offset, option_rom_offset; |
1131 |
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
1132 |
int bios_size, isa_bios_size, oprom_area_size;
|
1133 |
PCIBus *pci_bus; |
1134 |
PCIDevice *pci_dev; |
1135 |
ISADevice *isa_dev; |
1136 |
int piix3_devfn = -1; |
1137 |
CPUState *env; |
1138 |
qemu_irq *cpu_irq; |
1139 |
qemu_irq *isa_irq; |
1140 |
qemu_irq *i8259; |
1141 |
IsaIrqState *isa_irq_state; |
1142 |
DriveInfo *dinfo; |
1143 |
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
1144 |
BlockDriverState *fd[MAX_FD]; |
1145 |
int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
|
1146 |
void *fw_cfg;
|
1147 |
|
1148 |
if (ram_size >= 0xe0000000 ) { |
1149 |
above_4g_mem_size = ram_size - 0xe0000000;
|
1150 |
below_4g_mem_size = 0xe0000000;
|
1151 |
} else {
|
1152 |
below_4g_mem_size = ram_size; |
1153 |
} |
1154 |
|
1155 |
linux_boot = (kernel_filename != NULL);
|
1156 |
|
1157 |
/* init CPUs */
|
1158 |
if (cpu_model == NULL) { |
1159 |
#ifdef TARGET_X86_64
|
1160 |
cpu_model = "qemu64";
|
1161 |
#else
|
1162 |
cpu_model = "qemu32";
|
1163 |
#endif
|
1164 |
} |
1165 |
|
1166 |
for (i = 0; i < smp_cpus; i++) { |
1167 |
env = pc_new_cpu(cpu_model); |
1168 |
} |
1169 |
|
1170 |
vmport_init(); |
1171 |
|
1172 |
/* allocate RAM */
|
1173 |
ram_addr = qemu_ram_alloc(0xa0000);
|
1174 |
cpu_register_physical_memory(0, 0xa0000, ram_addr); |
1175 |
|
1176 |
/* Allocate, even though we won't register, so we don't break the
|
1177 |
* phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
|
1178 |
* and some bios areas, which will be registered later
|
1179 |
*/
|
1180 |
ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); |
1181 |
ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
|
1182 |
cpu_register_physical_memory(0x100000,
|
1183 |
below_4g_mem_size - 0x100000,
|
1184 |
ram_addr); |
1185 |
|
1186 |
/* above 4giga memory allocation */
|
1187 |
if (above_4g_mem_size > 0) { |
1188 |
#if TARGET_PHYS_ADDR_BITS == 32 |
1189 |
hw_error("To much RAM for 32-bit physical address");
|
1190 |
#else
|
1191 |
ram_addr = qemu_ram_alloc(above_4g_mem_size); |
1192 |
cpu_register_physical_memory(0x100000000ULL,
|
1193 |
above_4g_mem_size, |
1194 |
ram_addr); |
1195 |
#endif
|
1196 |
} |
1197 |
|
1198 |
|
1199 |
/* BIOS load */
|
1200 |
if (bios_name == NULL) |
1201 |
bios_name = BIOS_FILENAME; |
1202 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
1203 |
if (filename) {
|
1204 |
bios_size = get_image_size(filename); |
1205 |
} else {
|
1206 |
bios_size = -1;
|
1207 |
} |
1208 |
if (bios_size <= 0 || |
1209 |
(bios_size % 65536) != 0) { |
1210 |
goto bios_error;
|
1211 |
} |
1212 |
bios_offset = qemu_ram_alloc(bios_size); |
1213 |
ret = load_image(filename, qemu_get_ram_ptr(bios_offset)); |
1214 |
if (ret != bios_size) {
|
1215 |
bios_error:
|
1216 |
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
1217 |
exit(1);
|
1218 |
} |
1219 |
if (filename) {
|
1220 |
qemu_free(filename); |
1221 |
} |
1222 |
/* map the last 128KB of the BIOS in ISA space */
|
1223 |
isa_bios_size = bios_size; |
1224 |
if (isa_bios_size > (128 * 1024)) |
1225 |
isa_bios_size = 128 * 1024; |
1226 |
cpu_register_physical_memory(0x100000 - isa_bios_size,
|
1227 |
isa_bios_size, |
1228 |
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
1229 |
|
1230 |
|
1231 |
|
1232 |
option_rom_offset = qemu_ram_alloc(0x20000);
|
1233 |
oprom_area_size = 0;
|
1234 |
cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); |
1235 |
|
1236 |
if (using_vga) {
|
1237 |
const char *vgabios_filename; |
1238 |
/* VGA BIOS load */
|
1239 |
if (cirrus_vga_enabled) {
|
1240 |
vgabios_filename = VGABIOS_CIRRUS_FILENAME; |
1241 |
} else {
|
1242 |
vgabios_filename = VGABIOS_FILENAME; |
1243 |
} |
1244 |
oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000); |
1245 |
} |
1246 |
/* Although video roms can grow larger than 0x8000, the area between
|
1247 |
* 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
|
1248 |
* for any other kind of option rom inside this area */
|
1249 |
if (oprom_area_size < 0x8000) |
1250 |
oprom_area_size = 0x8000;
|
1251 |
|
1252 |
/* map all the bios at the top of memory */
|
1253 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
1254 |
bios_size, bios_offset | IO_MEM_ROM); |
1255 |
|
1256 |
fw_cfg = bochs_bios_init(); |
1257 |
|
1258 |
if (linux_boot) {
|
1259 |
load_linux(fw_cfg, 0xc0000 + oprom_area_size,
|
1260 |
kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
1261 |
oprom_area_size += 2048;
|
1262 |
} |
1263 |
|
1264 |
for (i = 0; i < nb_option_roms; i++) { |
1265 |
oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
|
1266 |
0xe0000);
|
1267 |
} |
1268 |
|
1269 |
for (i = 0; i < nb_nics; i++) { |
1270 |
char nic_oprom[1024]; |
1271 |
const char *model = nd_table[i].model; |
1272 |
|
1273 |
if (!nd_table[i].bootable)
|
1274 |
continue;
|
1275 |
|
1276 |
if (model == NULL) |
1277 |
model = "ne2k_pci";
|
1278 |
snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model); |
1279 |
|
1280 |
oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
|
1281 |
0xe0000);
|
1282 |
} |
1283 |
|
1284 |
cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
1285 |
i8259 = i8259_init(cpu_irq[0]);
|
1286 |
isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
|
1287 |
isa_irq_state->i8259 = i8259; |
1288 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
|
1289 |
ferr_irq = isa_irq[13];
|
1290 |
|
1291 |
if (pci_enabled) {
|
1292 |
pci_bus = i440fx_init(&i440fx_state, isa_irq); |
1293 |
piix3_devfn = piix3_init(pci_bus, -1);
|
1294 |
} else {
|
1295 |
pci_bus = NULL;
|
1296 |
} |
1297 |
|
1298 |
/* init basic PC hardware */
|
1299 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
1300 |
|
1301 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
1302 |
|
1303 |
if (cirrus_vga_enabled) {
|
1304 |
if (pci_enabled) {
|
1305 |
pci_cirrus_vga_init(pci_bus); |
1306 |
} else {
|
1307 |
isa_cirrus_vga_init(); |
1308 |
} |
1309 |
} else if (vmsvga_enabled) { |
1310 |
if (pci_enabled)
|
1311 |
pci_vmsvga_init(pci_bus); |
1312 |
else
|
1313 |
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
1314 |
} else if (std_vga_enabled) { |
1315 |
if (pci_enabled) {
|
1316 |
pci_vga_init(pci_bus, 0, 0); |
1317 |
} else {
|
1318 |
isa_vga_init(); |
1319 |
} |
1320 |
} |
1321 |
|
1322 |
rtc_state = rtc_init(0x70, isa_irq[8], 2000); |
1323 |
|
1324 |
qemu_register_boot_set(pc_boot_set, rtc_state); |
1325 |
|
1326 |
register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
1327 |
register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
1328 |
|
1329 |
if (pci_enabled) {
|
1330 |
isa_irq_state->ioapic = ioapic_init(); |
1331 |
} |
1332 |
pit = pit_init(0x40, isa_irq[0]); |
1333 |
pcspk_init(pit); |
1334 |
if (!no_hpet) {
|
1335 |
hpet_init(isa_irq); |
1336 |
} |
1337 |
|
1338 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
1339 |
if (serial_hds[i]) {
|
1340 |
serial_init(serial_io[i], isa_irq[serial_irq[i]], 115200,
|
1341 |
serial_hds[i]); |
1342 |
} |
1343 |
} |
1344 |
|
1345 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
1346 |
if (parallel_hds[i]) {
|
1347 |
parallel_init(parallel_io[i], isa_irq[parallel_irq[i]], |
1348 |
parallel_hds[i]); |
1349 |
} |
1350 |
} |
1351 |
|
1352 |
watchdog_pc_init(pci_bus); |
1353 |
|
1354 |
for(i = 0; i < nb_nics; i++) { |
1355 |
NICInfo *nd = &nd_table[i]; |
1356 |
|
1357 |
if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) |
1358 |
pc_init_ne2k_isa(nd, isa_irq); |
1359 |
else
|
1360 |
pci_nic_init(nd, "ne2k_pci", NULL); |
1361 |
} |
1362 |
|
1363 |
piix4_acpi_system_hot_add_init(); |
1364 |
|
1365 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
1366 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
1367 |
exit(1);
|
1368 |
} |
1369 |
|
1370 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
1371 |
dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
1372 |
hd[i] = dinfo ? dinfo->bdrv : NULL;
|
1373 |
} |
1374 |
|
1375 |
if (pci_enabled) {
|
1376 |
pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, isa_irq);
|
1377 |
} else {
|
1378 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
1379 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], isa_irq[ide_irq[i]], |
1380 |
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
1381 |
} |
1382 |
} |
1383 |
|
1384 |
isa_dev = isa_create_simple("i8042", 0x60, 0x64); |
1385 |
isa_connect_irq(isa_dev, 0, isa_irq[1]); |
1386 |
isa_connect_irq(isa_dev, 1, isa_irq[12]); |
1387 |
DMA_init(0);
|
1388 |
#ifdef HAS_AUDIO
|
1389 |
audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
|
1390 |
#endif
|
1391 |
|
1392 |
for(i = 0; i < MAX_FD; i++) { |
1393 |
dinfo = drive_get(IF_FLOPPY, 0, i);
|
1394 |
fd[i] = dinfo ? dinfo->bdrv : NULL;
|
1395 |
} |
1396 |
floppy_controller = fdctrl_init(isa_irq[6], 2, 0, 0x3f0, fd); |
1397 |
|
1398 |
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
1399 |
|
1400 |
if (pci_enabled && usb_enabled) {
|
1401 |
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
1402 |
} |
1403 |
|
1404 |
if (pci_enabled && acpi_enabled) {
|
1405 |
uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
1406 |
i2c_bus *smbus; |
1407 |
|
1408 |
/* TODO: Populate SPD eeprom data. */
|
1409 |
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, isa_irq[9]); |
1410 |
for (i = 0; i < 8; i++) { |
1411 |
DeviceState *eeprom; |
1412 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
|
1413 |
qdev_prop_set_uint32(eeprom, "address", 0x50 + i); |
1414 |
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
1415 |
qdev_init(eeprom); |
1416 |
} |
1417 |
} |
1418 |
|
1419 |
if (i440fx_state) {
|
1420 |
i440fx_init_memory_mappings(i440fx_state); |
1421 |
} |
1422 |
|
1423 |
if (pci_enabled) {
|
1424 |
int max_bus;
|
1425 |
int bus;
|
1426 |
|
1427 |
max_bus = drive_get_max_bus(IF_SCSI); |
1428 |
for (bus = 0; bus <= max_bus; bus++) { |
1429 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1430 |
} |
1431 |
} |
1432 |
|
1433 |
/* Add virtio balloon device */
|
1434 |
if (pci_enabled && virtio_balloon) {
|
1435 |
pci_dev = pci_create("virtio-balloon-pci", virtio_balloon_devaddr);
|
1436 |
qdev_init(&pci_dev->qdev); |
1437 |
} |
1438 |
|
1439 |
/* Add virtio console devices */
|
1440 |
if (pci_enabled) {
|
1441 |
for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { |
1442 |
if (virtcon_hds[i]) {
|
1443 |
pci_create_simple(pci_bus, -1, "virtio-console-pci"); |
1444 |
} |
1445 |
} |
1446 |
} |
1447 |
} |
1448 |
|
1449 |
static void pc_init_pci(ram_addr_t ram_size, |
1450 |
const char *boot_device, |
1451 |
const char *kernel_filename, |
1452 |
const char *kernel_cmdline, |
1453 |
const char *initrd_filename, |
1454 |
const char *cpu_model) |
1455 |
{ |
1456 |
pc_init1(ram_size, boot_device, |
1457 |
kernel_filename, kernel_cmdline, |
1458 |
initrd_filename, cpu_model, 1);
|
1459 |
} |
1460 |
|
1461 |
static void pc_init_isa(ram_addr_t ram_size, |
1462 |
const char *boot_device, |
1463 |
const char *kernel_filename, |
1464 |
const char *kernel_cmdline, |
1465 |
const char *initrd_filename, |
1466 |
const char *cpu_model) |
1467 |
{ |
1468 |
pc_init1(ram_size, boot_device, |
1469 |
kernel_filename, kernel_cmdline, |
1470 |
initrd_filename, cpu_model, 0);
|
1471 |
} |
1472 |
|
1473 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
1474 |
BIOS will read it and start S3 resume at POST Entry */
|
1475 |
void cmos_set_s3_resume(void) |
1476 |
{ |
1477 |
if (rtc_state)
|
1478 |
rtc_set_memory(rtc_state, 0xF, 0xFE); |
1479 |
} |
1480 |
|
1481 |
static QEMUMachine pc_machine = {
|
1482 |
.name = "pc-0.11",
|
1483 |
.alias = "pc",
|
1484 |
.desc = "Standard PC",
|
1485 |
.init = pc_init_pci, |
1486 |
.max_cpus = 255,
|
1487 |
.is_default = 1,
|
1488 |
}; |
1489 |
|
1490 |
static QEMUMachine pc_machine_v0_10 = {
|
1491 |
.name = "pc-0.10",
|
1492 |
.desc = "Standard PC, qemu 0.10",
|
1493 |
.init = pc_init_pci, |
1494 |
.max_cpus = 255,
|
1495 |
.compat_props = (CompatProperty[]) { |
1496 |
{ |
1497 |
.driver = "virtio-blk-pci",
|
1498 |
.property = "class",
|
1499 |
.value = stringify(PCI_CLASS_STORAGE_OTHER), |
1500 |
},{ |
1501 |
.driver = "virtio-console-pci",
|
1502 |
.property = "class",
|
1503 |
.value = stringify(PCI_CLASS_DISPLAY_OTHER), |
1504 |
},{ |
1505 |
.driver = "virtio-net-pci",
|
1506 |
.property = "vectors",
|
1507 |
.value = stringify(0),
|
1508 |
}, |
1509 |
{ /* end of list */ }
|
1510 |
}, |
1511 |
}; |
1512 |
|
1513 |
static QEMUMachine isapc_machine = {
|
1514 |
.name = "isapc",
|
1515 |
.desc = "ISA-only PC",
|
1516 |
.init = pc_init_isa, |
1517 |
.max_cpus = 1,
|
1518 |
}; |
1519 |
|
1520 |
static void pc_machine_init(void) |
1521 |
{ |
1522 |
qemu_register_machine(&pc_machine); |
1523 |
qemu_register_machine(&pc_machine_v0_10); |
1524 |
qemu_register_machine(&isapc_machine); |
1525 |
} |
1526 |
|
1527 |
machine_init(pc_machine_init); |