Revision 16f62432

b/hw/dma.c
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#define ldebug(...)
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#endif
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#define MEM_REAL(addr) ((addr)+(uint32_t)(phys_ram_base))
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#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
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struct dma_regs {
......
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    uint8_t page;
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    uint8_t dack;
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    uint8_t eop;
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    DMA_read_handler read_handler;
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    DMA_misc_handler misc_handler;
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    DMA_transfer_handler transfer_handler;
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    void *opaque;
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};
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#define ADDR 0
......
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{
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    struct dma_regs *r;
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    int n;
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    int irq;
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    uint32_t addr;
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    target_ulong addr;
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/*     int ai, dir; */
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    r = dma_controllers[ncont].regs + ichan;
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/*   ai = r->mode & 16; */
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/*   dir = r->mode & 32 ? -1 : 1; */
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    addr = MEM_REAL ((r->page << 16) | r->now[ADDR]);
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    irq = -1;
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    n = r->read_handler (addr, (r->base[COUNT] << ncont) + (1 << ncont), &irq);
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    addr = (r->page << 16) | r->now[ADDR];
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    n = r->transfer_handler (r->opaque, addr, 
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                             (r->base[COUNT] << ncont) + (1 << ncont));
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    r->now[COUNT] = n;
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    ldebug ("dma_pos %d irq %d size %d\n",
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            n, irq, (r->base[1] << ncont) + (1 << ncont));
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    if (-1 != irq) {
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        pic_set_irq (irq, 1);
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    }
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    ldebug ("dma_pos %d size %d\n",
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            n, (r->base[1] << ncont) + (1 << ncont));
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}
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void DMA_run (void)
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{
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    static int in_dma;
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    struct dma_cont *d;
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    int icont, ichan;
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    if (in_dma) {
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        log ("attempt to re-enter dma\n");
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        return;
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    }
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    in_dma = 1;
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    d = dma_controllers;
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    for (icont = 0; icont < 2; icont++, d++) {
......
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                channel_run (icont, ichan);
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        }
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    }
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    in_dma = 0;
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}
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void DMA_register_channel (int nchan,
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                           DMA_read_handler read_handler,
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                           DMA_misc_handler misc_handler)
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                           DMA_transfer_handler transfer_handler, 
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                           void *opaque)
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{
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    struct dma_regs *r;
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    int ichan, ncont;
......
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    ichan = nchan & 3;
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    r = dma_controllers[ncont].regs + ichan;
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    r->read_handler = read_handler;
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    r->misc_handler = misc_handler;
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    r->transfer_handler = transfer_handler;
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    r->opaque = opaque;
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}
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/* request the emulator to transfer a new DMA memory block ASAP */
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void DMA_schedule(int nchan)
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{
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    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
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}
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void DMA_init (void)
b/vl.h
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#ifndef VL_H
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#define VL_H
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#include "cpu.h"
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/* vl.c */
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struct CPUState;
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extern int reset_requested;
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extern int64_t ticks_per_sec;
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......
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void AUD_init (void);
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/* dma.c */
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typedef int (*DMA_read_handler) (uint32_t addr, int size, int *irq);
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typedef int (*DMA_misc_handler) (int);
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typedef int (*DMA_transfer_handler) (void *opaque, target_ulong addr, int size);
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int DMA_get_channel_mode (int nchan);
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void DMA_hold_DREQ (int nchan);
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void DMA_release_DREQ (int nchan);
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void DMA_schedule(int nchan);
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void DMA_run (void);
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void DMA_init (void);
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void DMA_register_channel (int nchan,
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                           DMA_read_handler read_handler,
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                           DMA_misc_handler misc_handler);
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                           DMA_transfer_handler transfer_handler, void *opaque);
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/* sb16.c */
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void SB16_run (void);

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