Revision 173a543b hw/pci.c

b/hw/pci.c
729 729
    s->dev.config[0x07] = 0x00; // status = fast devsel
730 730
    s->dev.config[0x08] = 0x00; // revision
731 731
    s->dev.config[0x09] = 0x00; // programming i/f
732
    s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
733
    s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
732
    pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
734 733
    s->dev.config[0x0D] = 0x10; // latency_timer
735 734
    s->dev.config[0x0E] = 0x81; // header_type
736 735
    s->dev.config[0x1E] = 0xa0; // secondary status

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