Revision 173a543b hw/unin_pci.c
| b/hw/unin_pci.c | ||
|---|---|---|
| 177 | 177 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
| 178 | 178 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI); |
| 179 | 179 |
d->config[0x08] = 0x00; // revision |
| 180 |
d->config[0x0A] = 0x00; // class_sub = pci host |
|
| 181 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
|
| 180 |
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
|
| 182 | 181 |
d->config[0x0C] = 0x08; // cache_line_size |
| 183 | 182 |
d->config[0x0D] = 0x10; // latency_timer |
| 184 | 183 |
d->config[0x0E] = 0x00; // header_type |
| ... | ... | |
| 191 | 190 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC); |
| 192 | 191 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); |
| 193 | 192 |
d->config[0x08] = 0x05; // revision |
| 194 |
d->config[0x0A] = 0x04; // class_sub = pci2pci |
|
| 195 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
|
| 193 |
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); |
|
| 196 | 194 |
d->config[0x0C] = 0x08; // cache_line_size |
| 197 | 195 |
d->config[0x0D] = 0x20; // latency_timer |
| 198 | 196 |
d->config[0x0E] = 0x01; // header_type |
| ... | ... | |
| 228 | 226 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
| 229 | 227 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP); |
| 230 | 228 |
d->config[0x08] = 0x00; // revision |
| 231 |
d->config[0x0A] = 0x00; // class_sub = pci host |
|
| 232 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
|
| 229 |
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
|
| 233 | 230 |
d->config[0x0C] = 0x08; // cache_line_size |
| 234 | 231 |
d->config[0x0D] = 0x10; // latency_timer |
| 235 | 232 |
d->config[0x0E] = 0x00; // header_type |
| ... | ... | |
| 251 | 248 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
| 252 | 249 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI); |
| 253 | 250 |
d->config[0x08] = 0x00; // revision |
| 254 |
d->config[0x0A] = 0x00; // class_sub = pci host |
|
| 255 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
|
| 251 |
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
|
| 256 | 252 |
d->config[0x0C] = 0x08; // cache_line_size |
| 257 | 253 |
d->config[0x0D] = 0x10; // latency_timer |
| 258 | 254 |
d->config[0x0E] = 0x00; // header_type |
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