root / hw / isa_mmio.c @ 17786d52
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1 | aef445bd | pbrook | /*
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2 | aef445bd | pbrook | * Memory mapped access to ISA IO space.
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3 | aef445bd | pbrook | *
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4 | aef445bd | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | aef445bd | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | aef445bd | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | aef445bd | pbrook | * in the Software without restriction, including without limitation the rights
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9 | aef445bd | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | aef445bd | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | aef445bd | pbrook | * furnished to do so, subject to the following conditions:
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12 | aef445bd | pbrook | *
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13 | aef445bd | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | aef445bd | pbrook | * all copies or substantial portions of the Software.
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15 | aef445bd | pbrook | *
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16 | aef445bd | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | aef445bd | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | aef445bd | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | aef445bd | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | aef445bd | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | aef445bd | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | aef445bd | pbrook | * THE SOFTWARE.
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23 | aef445bd | pbrook | */
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24 | aef445bd | pbrook | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | aef445bd | pbrook | |
28 | c227f099 | Anthony Liguori | static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr, |
29 | aef445bd | pbrook | uint32_t val) |
30 | aef445bd | pbrook | { |
31 | afcea8cb | Blue Swirl | cpu_outb(addr & IOPORTS_MASK, val); |
32 | aef445bd | pbrook | } |
33 | aef445bd | pbrook | |
34 | 84108e12 | Blue Swirl | static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr, |
35 | 84108e12 | Blue Swirl | uint32_t val) |
36 | aef445bd | pbrook | { |
37 | aef445bd | pbrook | val = bswap16(val); |
38 | afcea8cb | Blue Swirl | cpu_outw(addr & IOPORTS_MASK, val); |
39 | aef445bd | pbrook | } |
40 | aef445bd | pbrook | |
41 | 84108e12 | Blue Swirl | static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr, |
42 | 84108e12 | Blue Swirl | uint32_t val) |
43 | 84108e12 | Blue Swirl | { |
44 | 84108e12 | Blue Swirl | cpu_outw(addr & IOPORTS_MASK, val); |
45 | 84108e12 | Blue Swirl | } |
46 | 84108e12 | Blue Swirl | |
47 | 84108e12 | Blue Swirl | static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr, |
48 | 84108e12 | Blue Swirl | uint32_t val) |
49 | aef445bd | pbrook | { |
50 | aef445bd | pbrook | val = bswap32(val); |
51 | 84108e12 | Blue Swirl | cpu_outl(addr & IOPORTS_MASK, val); |
52 | 84108e12 | Blue Swirl | } |
53 | 84108e12 | Blue Swirl | |
54 | 84108e12 | Blue Swirl | static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr, |
55 | 84108e12 | Blue Swirl | uint32_t val) |
56 | 84108e12 | Blue Swirl | { |
57 | afcea8cb | Blue Swirl | cpu_outl(addr & IOPORTS_MASK, val); |
58 | aef445bd | pbrook | } |
59 | aef445bd | pbrook | |
60 | c227f099 | Anthony Liguori | static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) |
61 | aef445bd | pbrook | { |
62 | aef445bd | pbrook | uint32_t val; |
63 | aef445bd | pbrook | |
64 | afcea8cb | Blue Swirl | val = cpu_inb(addr & IOPORTS_MASK); |
65 | aef445bd | pbrook | return val;
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66 | aef445bd | pbrook | } |
67 | aef445bd | pbrook | |
68 | 84108e12 | Blue Swirl | static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr) |
69 | aef445bd | pbrook | { |
70 | aef445bd | pbrook | uint32_t val; |
71 | aef445bd | pbrook | |
72 | afcea8cb | Blue Swirl | val = cpu_inw(addr & IOPORTS_MASK); |
73 | aef445bd | pbrook | val = bswap16(val); |
74 | aef445bd | pbrook | return val;
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75 | aef445bd | pbrook | } |
76 | aef445bd | pbrook | |
77 | 84108e12 | Blue Swirl | static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr) |
78 | 84108e12 | Blue Swirl | { |
79 | 84108e12 | Blue Swirl | uint32_t val; |
80 | 84108e12 | Blue Swirl | |
81 | 84108e12 | Blue Swirl | val = cpu_inw(addr & IOPORTS_MASK); |
82 | 84108e12 | Blue Swirl | return val;
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83 | 84108e12 | Blue Swirl | } |
84 | 84108e12 | Blue Swirl | |
85 | 84108e12 | Blue Swirl | static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr) |
86 | aef445bd | pbrook | { |
87 | aef445bd | pbrook | uint32_t val; |
88 | aef445bd | pbrook | |
89 | afcea8cb | Blue Swirl | val = cpu_inl(addr & IOPORTS_MASK); |
90 | aef445bd | pbrook | val = bswap32(val); |
91 | aef445bd | pbrook | return val;
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92 | aef445bd | pbrook | } |
93 | aef445bd | pbrook | |
94 | 84108e12 | Blue Swirl | static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr) |
95 | 84108e12 | Blue Swirl | { |
96 | 84108e12 | Blue Swirl | uint32_t val; |
97 | 84108e12 | Blue Swirl | |
98 | 84108e12 | Blue Swirl | val = cpu_inl(addr & IOPORTS_MASK); |
99 | 84108e12 | Blue Swirl | return val;
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100 | 84108e12 | Blue Swirl | } |
101 | 84108e12 | Blue Swirl | |
102 | 84108e12 | Blue Swirl | static CPUWriteMemoryFunc * const isa_mmio_write_be[] = { |
103 | 84108e12 | Blue Swirl | &isa_mmio_writeb, |
104 | 84108e12 | Blue Swirl | &isa_mmio_writew_be, |
105 | 84108e12 | Blue Swirl | &isa_mmio_writel_be, |
106 | 84108e12 | Blue Swirl | }; |
107 | 84108e12 | Blue Swirl | |
108 | 84108e12 | Blue Swirl | static CPUReadMemoryFunc * const isa_mmio_read_be[] = { |
109 | 84108e12 | Blue Swirl | &isa_mmio_readb, |
110 | 84108e12 | Blue Swirl | &isa_mmio_readw_be, |
111 | 84108e12 | Blue Swirl | &isa_mmio_readl_be, |
112 | 84108e12 | Blue Swirl | }; |
113 | 84108e12 | Blue Swirl | |
114 | 84108e12 | Blue Swirl | static CPUWriteMemoryFunc * const isa_mmio_write_le[] = { |
115 | aef445bd | pbrook | &isa_mmio_writeb, |
116 | 84108e12 | Blue Swirl | &isa_mmio_writew_le, |
117 | 84108e12 | Blue Swirl | &isa_mmio_writel_le, |
118 | aef445bd | pbrook | }; |
119 | aef445bd | pbrook | |
120 | 84108e12 | Blue Swirl | static CPUReadMemoryFunc * const isa_mmio_read_le[] = { |
121 | aef445bd | pbrook | &isa_mmio_readb, |
122 | 84108e12 | Blue Swirl | &isa_mmio_readw_le, |
123 | 84108e12 | Blue Swirl | &isa_mmio_readl_le, |
124 | aef445bd | pbrook | }; |
125 | aef445bd | pbrook | |
126 | aef445bd | pbrook | static int isa_mmio_iomemtype = 0; |
127 | aef445bd | pbrook | |
128 | 84108e12 | Blue Swirl | void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) |
129 | aef445bd | pbrook | { |
130 | aef445bd | pbrook | if (!isa_mmio_iomemtype) {
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131 | 84108e12 | Blue Swirl | if (be) {
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132 | 84108e12 | Blue Swirl | isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be, |
133 | 84108e12 | Blue Swirl | isa_mmio_write_be, |
134 | 84108e12 | Blue Swirl | NULL);
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135 | 84108e12 | Blue Swirl | } else {
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136 | 84108e12 | Blue Swirl | isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le, |
137 | 84108e12 | Blue Swirl | isa_mmio_write_le, |
138 | 84108e12 | Blue Swirl | NULL);
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139 | 84108e12 | Blue Swirl | } |
140 | aef445bd | pbrook | } |
141 | aef445bd | pbrook | cpu_register_physical_memory(base, size, isa_mmio_iomemtype); |
142 | aef445bd | pbrook | } |