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1 | 7f132a21 | cmchao | /*
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2 | 7f132a21 | cmchao | * TI OMAP interrupt controller emulation.
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3 | 7f132a21 | cmchao | *
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4 | 7f132a21 | cmchao | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | 7f132a21 | cmchao | * Copyright (C) 2007-2008 Nokia Corporation
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6 | 7f132a21 | cmchao | *
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7 | 7f132a21 | cmchao | * This program is free software; you can redistribute it and/or
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8 | 7f132a21 | cmchao | * modify it under the terms of the GNU General Public License as
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9 | 7f132a21 | cmchao | * published by the Free Software Foundation; either version 2 or
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10 | 7f132a21 | cmchao | * (at your option) version 3 of the License.
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11 | 7f132a21 | cmchao | *
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12 | 7f132a21 | cmchao | * This program is distributed in the hope that it will be useful,
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13 | 7f132a21 | cmchao | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7f132a21 | cmchao | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 7f132a21 | cmchao | * GNU General Public License for more details.
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16 | 7f132a21 | cmchao | *
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17 | 7f132a21 | cmchao | * You should have received a copy of the GNU General Public License along
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18 | 7f132a21 | cmchao | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 7f132a21 | cmchao | */
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20 | 7f132a21 | cmchao | #include "hw.h" |
21 | 7f132a21 | cmchao | #include "omap.h" |
22 | 7f132a21 | cmchao | |
23 | 7f132a21 | cmchao | /* Interrupt Handlers */
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24 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s {
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25 | 7f132a21 | cmchao | uint32_t irqs; |
26 | 7f132a21 | cmchao | uint32_t inputs; |
27 | 7f132a21 | cmchao | uint32_t mask; |
28 | 7f132a21 | cmchao | uint32_t fiq; |
29 | 7f132a21 | cmchao | uint32_t sens_edge; |
30 | 7f132a21 | cmchao | uint32_t swi; |
31 | 7f132a21 | cmchao | unsigned char priority[32]; |
32 | 7f132a21 | cmchao | }; |
33 | 7f132a21 | cmchao | |
34 | 7f132a21 | cmchao | struct omap_intr_handler_s {
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35 | 7f132a21 | cmchao | qemu_irq *pins; |
36 | 7f132a21 | cmchao | qemu_irq parent_intr[2];
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37 | 7f132a21 | cmchao | unsigned char nbanks; |
38 | 7f132a21 | cmchao | int level_only;
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39 | 7f132a21 | cmchao | |
40 | 7f132a21 | cmchao | /* state */
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41 | 7f132a21 | cmchao | uint32_t new_agr[2];
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42 | 7f132a21 | cmchao | int sir_intr[2]; |
43 | 7f132a21 | cmchao | int autoidle;
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44 | 7f132a21 | cmchao | uint32_t mask; |
45 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s bank[];
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46 | 7f132a21 | cmchao | }; |
47 | 7f132a21 | cmchao | |
48 | 7f132a21 | cmchao | inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n) |
49 | 7f132a21 | cmchao | { |
50 | 7f132a21 | cmchao | return s->pins[n];
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51 | 7f132a21 | cmchao | } |
52 | 7f132a21 | cmchao | |
53 | 7f132a21 | cmchao | static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) |
54 | 7f132a21 | cmchao | { |
55 | 7f132a21 | cmchao | int i, j, sir_intr, p_intr, p, f;
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56 | 7f132a21 | cmchao | uint32_t level; |
57 | 7f132a21 | cmchao | sir_intr = 0;
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58 | 7f132a21 | cmchao | p_intr = 255;
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59 | 7f132a21 | cmchao | |
60 | 7f132a21 | cmchao | /* Find the interrupt line with the highest dynamic priority.
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61 | 7f132a21 | cmchao | * Note: 0 denotes the hightest priority.
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62 | 7f132a21 | cmchao | * If all interrupts have the same priority, the default order is IRQ_N,
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63 | 7f132a21 | cmchao | * IRQ_N-1,...,IRQ_0. */
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64 | 7f132a21 | cmchao | for (j = 0; j < s->nbanks; ++j) { |
65 | 7f132a21 | cmchao | level = s->bank[j].irqs & ~s->bank[j].mask & |
66 | 7f132a21 | cmchao | (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); |
67 | 7f132a21 | cmchao | for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, |
68 | 7f132a21 | cmchao | level >>= f) { |
69 | 7f132a21 | cmchao | p = s->bank[j].priority[i]; |
70 | 7f132a21 | cmchao | if (p <= p_intr) {
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71 | 7f132a21 | cmchao | p_intr = p; |
72 | 7f132a21 | cmchao | sir_intr = 32 * j + i;
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73 | 7f132a21 | cmchao | } |
74 | 7f132a21 | cmchao | f = ffs(level >> 1);
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75 | 7f132a21 | cmchao | } |
76 | 7f132a21 | cmchao | } |
77 | 7f132a21 | cmchao | s->sir_intr[is_fiq] = sir_intr; |
78 | 7f132a21 | cmchao | } |
79 | 7f132a21 | cmchao | |
80 | 7f132a21 | cmchao | static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) |
81 | 7f132a21 | cmchao | { |
82 | 7f132a21 | cmchao | int i;
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83 | 7f132a21 | cmchao | uint32_t has_intr = 0;
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84 | 7f132a21 | cmchao | |
85 | 7f132a21 | cmchao | for (i = 0; i < s->nbanks; ++i) |
86 | 7f132a21 | cmchao | has_intr |= s->bank[i].irqs & ~s->bank[i].mask & |
87 | 7f132a21 | cmchao | (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); |
88 | 7f132a21 | cmchao | |
89 | 7f132a21 | cmchao | if (s->new_agr[is_fiq] & has_intr & s->mask) {
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90 | 7f132a21 | cmchao | s->new_agr[is_fiq] = 0;
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91 | 7f132a21 | cmchao | omap_inth_sir_update(s, is_fiq); |
92 | 7f132a21 | cmchao | qemu_set_irq(s->parent_intr[is_fiq], 1);
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93 | 7f132a21 | cmchao | } |
94 | 7f132a21 | cmchao | } |
95 | 7f132a21 | cmchao | |
96 | 7f132a21 | cmchao | #define INT_FALLING_EDGE 0 |
97 | 7f132a21 | cmchao | #define INT_LOW_LEVEL 1 |
98 | 7f132a21 | cmchao | |
99 | 7f132a21 | cmchao | static void omap_set_intr(void *opaque, int irq, int req) |
100 | 7f132a21 | cmchao | { |
101 | 7f132a21 | cmchao | struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
102 | 7f132a21 | cmchao | uint32_t rise; |
103 | 7f132a21 | cmchao | |
104 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
105 | 7f132a21 | cmchao | int n = irq & 31; |
106 | 7f132a21 | cmchao | |
107 | 7f132a21 | cmchao | if (req) {
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108 | 7f132a21 | cmchao | rise = ~bank->irqs & (1 << n);
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109 | 7f132a21 | cmchao | if (~bank->sens_edge & (1 << n)) |
110 | 7f132a21 | cmchao | rise &= ~bank->inputs; |
111 | 7f132a21 | cmchao | |
112 | 7f132a21 | cmchao | bank->inputs |= (1 << n);
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113 | 7f132a21 | cmchao | if (rise) {
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114 | 7f132a21 | cmchao | bank->irqs |= rise; |
115 | 7f132a21 | cmchao | omap_inth_update(ih, 0);
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116 | 7f132a21 | cmchao | omap_inth_update(ih, 1);
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117 | 7f132a21 | cmchao | } |
118 | 7f132a21 | cmchao | } else {
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119 | 7f132a21 | cmchao | rise = bank->sens_edge & bank->irqs & (1 << n);
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120 | 7f132a21 | cmchao | bank->irqs &= ~rise; |
121 | 7f132a21 | cmchao | bank->inputs &= ~(1 << n);
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122 | 7f132a21 | cmchao | } |
123 | 7f132a21 | cmchao | } |
124 | 7f132a21 | cmchao | |
125 | 7f132a21 | cmchao | /* Simplified version with no edge detection */
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126 | 7f132a21 | cmchao | static void omap_set_intr_noedge(void *opaque, int irq, int req) |
127 | 7f132a21 | cmchao | { |
128 | 7f132a21 | cmchao | struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
129 | 7f132a21 | cmchao | uint32_t rise; |
130 | 7f132a21 | cmchao | |
131 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
132 | 7f132a21 | cmchao | int n = irq & 31; |
133 | 7f132a21 | cmchao | |
134 | 7f132a21 | cmchao | if (req) {
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135 | 7f132a21 | cmchao | rise = ~bank->inputs & (1 << n);
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136 | 7f132a21 | cmchao | if (rise) {
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137 | 7f132a21 | cmchao | bank->irqs |= bank->inputs |= rise; |
138 | 7f132a21 | cmchao | omap_inth_update(ih, 0);
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139 | 7f132a21 | cmchao | omap_inth_update(ih, 1);
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140 | 7f132a21 | cmchao | } |
141 | 7f132a21 | cmchao | } else
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142 | 7f132a21 | cmchao | bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
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143 | 7f132a21 | cmchao | } |
144 | 7f132a21 | cmchao | |
145 | 7f132a21 | cmchao | static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
146 | 7f132a21 | cmchao | { |
147 | 7f132a21 | cmchao | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
148 | 7f132a21 | cmchao | int i, offset = addr;
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149 | 7f132a21 | cmchao | int bank_no = offset >> 8; |
150 | 7f132a21 | cmchao | int line_no;
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151 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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152 | 7f132a21 | cmchao | offset &= 0xff;
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153 | 7f132a21 | cmchao | |
154 | 7f132a21 | cmchao | switch (offset) {
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155 | 7f132a21 | cmchao | case 0x00: /* ITR */ |
156 | 7f132a21 | cmchao | return bank->irqs;
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157 | 7f132a21 | cmchao | |
158 | 7f132a21 | cmchao | case 0x04: /* MIR */ |
159 | 7f132a21 | cmchao | return bank->mask;
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160 | 7f132a21 | cmchao | |
161 | 7f132a21 | cmchao | case 0x10: /* SIR_IRQ_CODE */ |
162 | 7f132a21 | cmchao | case 0x14: /* SIR_FIQ_CODE */ |
163 | 7f132a21 | cmchao | if (bank_no != 0) |
164 | 7f132a21 | cmchao | break;
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165 | 7f132a21 | cmchao | line_no = s->sir_intr[(offset - 0x10) >> 2]; |
166 | 7f132a21 | cmchao | bank = &s->bank[line_no >> 5];
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167 | 7f132a21 | cmchao | i = line_no & 31;
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168 | 7f132a21 | cmchao | if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) |
169 | 7f132a21 | cmchao | bank->irqs &= ~(1 << i);
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170 | 7f132a21 | cmchao | return line_no;
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171 | 7f132a21 | cmchao | |
172 | 7f132a21 | cmchao | case 0x18: /* CONTROL_REG */ |
173 | 7f132a21 | cmchao | if (bank_no != 0) |
174 | 7f132a21 | cmchao | break;
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175 | 7f132a21 | cmchao | return 0; |
176 | 7f132a21 | cmchao | |
177 | 7f132a21 | cmchao | case 0x1c: /* ILR0 */ |
178 | 7f132a21 | cmchao | case 0x20: /* ILR1 */ |
179 | 7f132a21 | cmchao | case 0x24: /* ILR2 */ |
180 | 7f132a21 | cmchao | case 0x28: /* ILR3 */ |
181 | 7f132a21 | cmchao | case 0x2c: /* ILR4 */ |
182 | 7f132a21 | cmchao | case 0x30: /* ILR5 */ |
183 | 7f132a21 | cmchao | case 0x34: /* ILR6 */ |
184 | 7f132a21 | cmchao | case 0x38: /* ILR7 */ |
185 | 7f132a21 | cmchao | case 0x3c: /* ILR8 */ |
186 | 7f132a21 | cmchao | case 0x40: /* ILR9 */ |
187 | 7f132a21 | cmchao | case 0x44: /* ILR10 */ |
188 | 7f132a21 | cmchao | case 0x48: /* ILR11 */ |
189 | 7f132a21 | cmchao | case 0x4c: /* ILR12 */ |
190 | 7f132a21 | cmchao | case 0x50: /* ILR13 */ |
191 | 7f132a21 | cmchao | case 0x54: /* ILR14 */ |
192 | 7f132a21 | cmchao | case 0x58: /* ILR15 */ |
193 | 7f132a21 | cmchao | case 0x5c: /* ILR16 */ |
194 | 7f132a21 | cmchao | case 0x60: /* ILR17 */ |
195 | 7f132a21 | cmchao | case 0x64: /* ILR18 */ |
196 | 7f132a21 | cmchao | case 0x68: /* ILR19 */ |
197 | 7f132a21 | cmchao | case 0x6c: /* ILR20 */ |
198 | 7f132a21 | cmchao | case 0x70: /* ILR21 */ |
199 | 7f132a21 | cmchao | case 0x74: /* ILR22 */ |
200 | 7f132a21 | cmchao | case 0x78: /* ILR23 */ |
201 | 7f132a21 | cmchao | case 0x7c: /* ILR24 */ |
202 | 7f132a21 | cmchao | case 0x80: /* ILR25 */ |
203 | 7f132a21 | cmchao | case 0x84: /* ILR26 */ |
204 | 7f132a21 | cmchao | case 0x88: /* ILR27 */ |
205 | 7f132a21 | cmchao | case 0x8c: /* ILR28 */ |
206 | 7f132a21 | cmchao | case 0x90: /* ILR29 */ |
207 | 7f132a21 | cmchao | case 0x94: /* ILR30 */ |
208 | 7f132a21 | cmchao | case 0x98: /* ILR31 */ |
209 | 7f132a21 | cmchao | i = (offset - 0x1c) >> 2; |
210 | 7f132a21 | cmchao | return (bank->priority[i] << 2) | |
211 | 7f132a21 | cmchao | (((bank->sens_edge >> i) & 1) << 1) | |
212 | 7f132a21 | cmchao | ((bank->fiq >> i) & 1);
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213 | 7f132a21 | cmchao | |
214 | 7f132a21 | cmchao | case 0x9c: /* ISR */ |
215 | 7f132a21 | cmchao | return 0x00000000; |
216 | 7f132a21 | cmchao | |
217 | 7f132a21 | cmchao | } |
218 | 7f132a21 | cmchao | OMAP_BAD_REG(addr); |
219 | 7f132a21 | cmchao | return 0; |
220 | 7f132a21 | cmchao | } |
221 | 7f132a21 | cmchao | |
222 | 7f132a21 | cmchao | static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
223 | 7f132a21 | cmchao | uint32_t value) |
224 | 7f132a21 | cmchao | { |
225 | 7f132a21 | cmchao | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
226 | 7f132a21 | cmchao | int i, offset = addr;
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227 | 7f132a21 | cmchao | int bank_no = offset >> 8; |
228 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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229 | 7f132a21 | cmchao | offset &= 0xff;
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230 | 7f132a21 | cmchao | |
231 | 7f132a21 | cmchao | switch (offset) {
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232 | 7f132a21 | cmchao | case 0x00: /* ITR */ |
233 | 7f132a21 | cmchao | /* Important: ignore the clearing if the IRQ is level-triggered and
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234 | 7f132a21 | cmchao | the input bit is 1 */
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235 | 7f132a21 | cmchao | bank->irqs &= value | (bank->inputs & bank->sens_edge); |
236 | 7f132a21 | cmchao | return;
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237 | 7f132a21 | cmchao | |
238 | 7f132a21 | cmchao | case 0x04: /* MIR */ |
239 | 7f132a21 | cmchao | bank->mask = value; |
240 | 7f132a21 | cmchao | omap_inth_update(s, 0);
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241 | 7f132a21 | cmchao | omap_inth_update(s, 1);
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242 | 7f132a21 | cmchao | return;
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243 | 7f132a21 | cmchao | |
244 | 7f132a21 | cmchao | case 0x10: /* SIR_IRQ_CODE */ |
245 | 7f132a21 | cmchao | case 0x14: /* SIR_FIQ_CODE */ |
246 | 7f132a21 | cmchao | OMAP_RO_REG(addr); |
247 | 7f132a21 | cmchao | break;
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248 | 7f132a21 | cmchao | |
249 | 7f132a21 | cmchao | case 0x18: /* CONTROL_REG */ |
250 | 7f132a21 | cmchao | if (bank_no != 0) |
251 | 7f132a21 | cmchao | break;
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252 | 7f132a21 | cmchao | if (value & 2) { |
253 | 7f132a21 | cmchao | qemu_set_irq(s->parent_intr[1], 0); |
254 | 7f132a21 | cmchao | s->new_agr[1] = ~0; |
255 | 7f132a21 | cmchao | omap_inth_update(s, 1);
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256 | 7f132a21 | cmchao | } |
257 | 7f132a21 | cmchao | if (value & 1) { |
258 | 7f132a21 | cmchao | qemu_set_irq(s->parent_intr[0], 0); |
259 | 7f132a21 | cmchao | s->new_agr[0] = ~0; |
260 | 7f132a21 | cmchao | omap_inth_update(s, 0);
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261 | 7f132a21 | cmchao | } |
262 | 7f132a21 | cmchao | return;
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263 | 7f132a21 | cmchao | |
264 | 7f132a21 | cmchao | case 0x1c: /* ILR0 */ |
265 | 7f132a21 | cmchao | case 0x20: /* ILR1 */ |
266 | 7f132a21 | cmchao | case 0x24: /* ILR2 */ |
267 | 7f132a21 | cmchao | case 0x28: /* ILR3 */ |
268 | 7f132a21 | cmchao | case 0x2c: /* ILR4 */ |
269 | 7f132a21 | cmchao | case 0x30: /* ILR5 */ |
270 | 7f132a21 | cmchao | case 0x34: /* ILR6 */ |
271 | 7f132a21 | cmchao | case 0x38: /* ILR7 */ |
272 | 7f132a21 | cmchao | case 0x3c: /* ILR8 */ |
273 | 7f132a21 | cmchao | case 0x40: /* ILR9 */ |
274 | 7f132a21 | cmchao | case 0x44: /* ILR10 */ |
275 | 7f132a21 | cmchao | case 0x48: /* ILR11 */ |
276 | 7f132a21 | cmchao | case 0x4c: /* ILR12 */ |
277 | 7f132a21 | cmchao | case 0x50: /* ILR13 */ |
278 | 7f132a21 | cmchao | case 0x54: /* ILR14 */ |
279 | 7f132a21 | cmchao | case 0x58: /* ILR15 */ |
280 | 7f132a21 | cmchao | case 0x5c: /* ILR16 */ |
281 | 7f132a21 | cmchao | case 0x60: /* ILR17 */ |
282 | 7f132a21 | cmchao | case 0x64: /* ILR18 */ |
283 | 7f132a21 | cmchao | case 0x68: /* ILR19 */ |
284 | 7f132a21 | cmchao | case 0x6c: /* ILR20 */ |
285 | 7f132a21 | cmchao | case 0x70: /* ILR21 */ |
286 | 7f132a21 | cmchao | case 0x74: /* ILR22 */ |
287 | 7f132a21 | cmchao | case 0x78: /* ILR23 */ |
288 | 7f132a21 | cmchao | case 0x7c: /* ILR24 */ |
289 | 7f132a21 | cmchao | case 0x80: /* ILR25 */ |
290 | 7f132a21 | cmchao | case 0x84: /* ILR26 */ |
291 | 7f132a21 | cmchao | case 0x88: /* ILR27 */ |
292 | 7f132a21 | cmchao | case 0x8c: /* ILR28 */ |
293 | 7f132a21 | cmchao | case 0x90: /* ILR29 */ |
294 | 7f132a21 | cmchao | case 0x94: /* ILR30 */ |
295 | 7f132a21 | cmchao | case 0x98: /* ILR31 */ |
296 | 7f132a21 | cmchao | i = (offset - 0x1c) >> 2; |
297 | 7f132a21 | cmchao | bank->priority[i] = (value >> 2) & 0x1f; |
298 | 7f132a21 | cmchao | bank->sens_edge &= ~(1 << i);
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299 | 7f132a21 | cmchao | bank->sens_edge |= ((value >> 1) & 1) << i; |
300 | 7f132a21 | cmchao | bank->fiq &= ~(1 << i);
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301 | 7f132a21 | cmchao | bank->fiq |= (value & 1) << i;
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302 | 7f132a21 | cmchao | return;
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303 | 7f132a21 | cmchao | |
304 | 7f132a21 | cmchao | case 0x9c: /* ISR */ |
305 | 7f132a21 | cmchao | for (i = 0; i < 32; i ++) |
306 | 7f132a21 | cmchao | if (value & (1 << i)) { |
307 | 7f132a21 | cmchao | omap_set_intr(s, 32 * bank_no + i, 1); |
308 | 7f132a21 | cmchao | return;
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309 | 7f132a21 | cmchao | } |
310 | 7f132a21 | cmchao | return;
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311 | 7f132a21 | cmchao | } |
312 | 7f132a21 | cmchao | OMAP_BAD_REG(addr); |
313 | 7f132a21 | cmchao | } |
314 | 7f132a21 | cmchao | |
315 | 7f132a21 | cmchao | static CPUReadMemoryFunc * const omap_inth_readfn[] = { |
316 | 7f132a21 | cmchao | omap_badwidth_read32, |
317 | 7f132a21 | cmchao | omap_badwidth_read32, |
318 | 7f132a21 | cmchao | omap_inth_read, |
319 | 7f132a21 | cmchao | }; |
320 | 7f132a21 | cmchao | |
321 | 7f132a21 | cmchao | static CPUWriteMemoryFunc * const omap_inth_writefn[] = { |
322 | 7f132a21 | cmchao | omap_inth_write, |
323 | 7f132a21 | cmchao | omap_inth_write, |
324 | 7f132a21 | cmchao | omap_inth_write, |
325 | 7f132a21 | cmchao | }; |
326 | 7f132a21 | cmchao | |
327 | 7f132a21 | cmchao | void omap_inth_reset(struct omap_intr_handler_s *s) |
328 | 7f132a21 | cmchao | { |
329 | 7f132a21 | cmchao | int i;
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330 | 7f132a21 | cmchao | |
331 | 7f132a21 | cmchao | for (i = 0; i < s->nbanks; ++i){ |
332 | 7f132a21 | cmchao | s->bank[i].irqs = 0x00000000;
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333 | 7f132a21 | cmchao | s->bank[i].mask = 0xffffffff;
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334 | 7f132a21 | cmchao | s->bank[i].sens_edge = 0x00000000;
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335 | 7f132a21 | cmchao | s->bank[i].fiq = 0x00000000;
|
336 | 7f132a21 | cmchao | s->bank[i].inputs = 0x00000000;
|
337 | 7f132a21 | cmchao | s->bank[i].swi = 0x00000000;
|
338 | 7f132a21 | cmchao | memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); |
339 | 7f132a21 | cmchao | |
340 | 7f132a21 | cmchao | if (s->level_only)
|
341 | 7f132a21 | cmchao | s->bank[i].sens_edge = 0xffffffff;
|
342 | 7f132a21 | cmchao | } |
343 | 7f132a21 | cmchao | |
344 | 7f132a21 | cmchao | s->new_agr[0] = ~0; |
345 | 7f132a21 | cmchao | s->new_agr[1] = ~0; |
346 | 7f132a21 | cmchao | s->sir_intr[0] = 0; |
347 | 7f132a21 | cmchao | s->sir_intr[1] = 0; |
348 | 7f132a21 | cmchao | s->autoidle = 0;
|
349 | 7f132a21 | cmchao | s->mask = ~0;
|
350 | 7f132a21 | cmchao | |
351 | 7f132a21 | cmchao | qemu_set_irq(s->parent_intr[0], 0); |
352 | 7f132a21 | cmchao | qemu_set_irq(s->parent_intr[1], 0); |
353 | 7f132a21 | cmchao | } |
354 | 7f132a21 | cmchao | |
355 | 7f132a21 | cmchao | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
356 | 7f132a21 | cmchao | unsigned long size, unsigned char nbanks, qemu_irq **pins, |
357 | 7f132a21 | cmchao | qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) |
358 | 7f132a21 | cmchao | { |
359 | 7f132a21 | cmchao | int iomemtype;
|
360 | 7f132a21 | cmchao | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
361 | 7f132a21 | cmchao | qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
362 | 7f132a21 | cmchao | sizeof(struct omap_intr_handler_bank_s) * nbanks); |
363 | 7f132a21 | cmchao | |
364 | 7f132a21 | cmchao | s->parent_intr[0] = parent_irq;
|
365 | 7f132a21 | cmchao | s->parent_intr[1] = parent_fiq;
|
366 | 7f132a21 | cmchao | s->nbanks = nbanks; |
367 | 7f132a21 | cmchao | s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
|
368 | 7f132a21 | cmchao | if (pins)
|
369 | 7f132a21 | cmchao | *pins = s->pins; |
370 | 7f132a21 | cmchao | |
371 | 7f132a21 | cmchao | omap_inth_reset(s); |
372 | 7f132a21 | cmchao | |
373 | 7f132a21 | cmchao | iomemtype = cpu_register_io_memory(omap_inth_readfn, |
374 | 7f132a21 | cmchao | omap_inth_writefn, s); |
375 | 7f132a21 | cmchao | cpu_register_physical_memory(base, size, iomemtype); |
376 | 7f132a21 | cmchao | |
377 | 7f132a21 | cmchao | return s;
|
378 | 7f132a21 | cmchao | } |
379 | 7f132a21 | cmchao | |
380 | 7f132a21 | cmchao | static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) |
381 | 7f132a21 | cmchao | { |
382 | 7f132a21 | cmchao | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
383 | 7f132a21 | cmchao | int offset = addr;
|
384 | 7f132a21 | cmchao | int bank_no, line_no;
|
385 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s *bank = NULL; |
386 | 7f132a21 | cmchao | |
387 | 7f132a21 | cmchao | if ((offset & 0xf80) == 0x80) { |
388 | 7f132a21 | cmchao | bank_no = (offset & 0x60) >> 5; |
389 | 7f132a21 | cmchao | if (bank_no < s->nbanks) {
|
390 | 7f132a21 | cmchao | offset &= ~0x60;
|
391 | 7f132a21 | cmchao | bank = &s->bank[bank_no]; |
392 | 7f132a21 | cmchao | } |
393 | 7f132a21 | cmchao | } |
394 | 7f132a21 | cmchao | |
395 | 7f132a21 | cmchao | switch (offset) {
|
396 | 7f132a21 | cmchao | case 0x00: /* INTC_REVISION */ |
397 | 7f132a21 | cmchao | return 0x21; |
398 | 7f132a21 | cmchao | |
399 | 7f132a21 | cmchao | case 0x10: /* INTC_SYSCONFIG */ |
400 | 7f132a21 | cmchao | return (s->autoidle >> 2) & 1; |
401 | 7f132a21 | cmchao | |
402 | 7f132a21 | cmchao | case 0x14: /* INTC_SYSSTATUS */ |
403 | 7f132a21 | cmchao | return 1; /* RESETDONE */ |
404 | 7f132a21 | cmchao | |
405 | 7f132a21 | cmchao | case 0x40: /* INTC_SIR_IRQ */ |
406 | 7f132a21 | cmchao | return s->sir_intr[0]; |
407 | 7f132a21 | cmchao | |
408 | 7f132a21 | cmchao | case 0x44: /* INTC_SIR_FIQ */ |
409 | 7f132a21 | cmchao | return s->sir_intr[1]; |
410 | 7f132a21 | cmchao | |
411 | 7f132a21 | cmchao | case 0x48: /* INTC_CONTROL */ |
412 | 7f132a21 | cmchao | return (!s->mask) << 2; /* GLOBALMASK */ |
413 | 7f132a21 | cmchao | |
414 | 7f132a21 | cmchao | case 0x4c: /* INTC_PROTECTION */ |
415 | 7f132a21 | cmchao | return 0; |
416 | 7f132a21 | cmchao | |
417 | 7f132a21 | cmchao | case 0x50: /* INTC_IDLE */ |
418 | 7f132a21 | cmchao | return s->autoidle & 3; |
419 | 7f132a21 | cmchao | |
420 | 7f132a21 | cmchao | /* Per-bank registers */
|
421 | 7f132a21 | cmchao | case 0x80: /* INTC_ITR */ |
422 | 7f132a21 | cmchao | return bank->inputs;
|
423 | 7f132a21 | cmchao | |
424 | 7f132a21 | cmchao | case 0x84: /* INTC_MIR */ |
425 | 7f132a21 | cmchao | return bank->mask;
|
426 | 7f132a21 | cmchao | |
427 | 7f132a21 | cmchao | case 0x88: /* INTC_MIR_CLEAR */ |
428 | 7f132a21 | cmchao | case 0x8c: /* INTC_MIR_SET */ |
429 | 7f132a21 | cmchao | return 0; |
430 | 7f132a21 | cmchao | |
431 | 7f132a21 | cmchao | case 0x90: /* INTC_ISR_SET */ |
432 | 7f132a21 | cmchao | return bank->swi;
|
433 | 7f132a21 | cmchao | |
434 | 7f132a21 | cmchao | case 0x94: /* INTC_ISR_CLEAR */ |
435 | 7f132a21 | cmchao | return 0; |
436 | 7f132a21 | cmchao | |
437 | 7f132a21 | cmchao | case 0x98: /* INTC_PENDING_IRQ */ |
438 | 7f132a21 | cmchao | return bank->irqs & ~bank->mask & ~bank->fiq;
|
439 | 7f132a21 | cmchao | |
440 | 7f132a21 | cmchao | case 0x9c: /* INTC_PENDING_FIQ */ |
441 | 7f132a21 | cmchao | return bank->irqs & ~bank->mask & bank->fiq;
|
442 | 7f132a21 | cmchao | |
443 | 7f132a21 | cmchao | /* Per-line registers */
|
444 | 7f132a21 | cmchao | case 0x100 ... 0x300: /* INTC_ILR */ |
445 | 7f132a21 | cmchao | bank_no = (offset - 0x100) >> 7; |
446 | 7f132a21 | cmchao | if (bank_no > s->nbanks)
|
447 | 7f132a21 | cmchao | break;
|
448 | 7f132a21 | cmchao | bank = &s->bank[bank_no]; |
449 | 7f132a21 | cmchao | line_no = (offset & 0x7f) >> 2; |
450 | 7f132a21 | cmchao | return (bank->priority[line_no] << 2) | |
451 | 7f132a21 | cmchao | ((bank->fiq >> line_no) & 1);
|
452 | 7f132a21 | cmchao | } |
453 | 7f132a21 | cmchao | OMAP_BAD_REG(addr); |
454 | 7f132a21 | cmchao | return 0; |
455 | 7f132a21 | cmchao | } |
456 | 7f132a21 | cmchao | |
457 | 7f132a21 | cmchao | static void omap2_inth_write(void *opaque, target_phys_addr_t addr, |
458 | 7f132a21 | cmchao | uint32_t value) |
459 | 7f132a21 | cmchao | { |
460 | 7f132a21 | cmchao | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
461 | 7f132a21 | cmchao | int offset = addr;
|
462 | 7f132a21 | cmchao | int bank_no, line_no;
|
463 | 7f132a21 | cmchao | struct omap_intr_handler_bank_s *bank = NULL; |
464 | 7f132a21 | cmchao | |
465 | 7f132a21 | cmchao | if ((offset & 0xf80) == 0x80) { |
466 | 7f132a21 | cmchao | bank_no = (offset & 0x60) >> 5; |
467 | 7f132a21 | cmchao | if (bank_no < s->nbanks) {
|
468 | 7f132a21 | cmchao | offset &= ~0x60;
|
469 | 7f132a21 | cmchao | bank = &s->bank[bank_no]; |
470 | 7f132a21 | cmchao | } |
471 | 7f132a21 | cmchao | } |
472 | 7f132a21 | cmchao | |
473 | 7f132a21 | cmchao | switch (offset) {
|
474 | 7f132a21 | cmchao | case 0x10: /* INTC_SYSCONFIG */ |
475 | 7f132a21 | cmchao | s->autoidle &= 4;
|
476 | 7f132a21 | cmchao | s->autoidle |= (value & 1) << 2; |
477 | 7f132a21 | cmchao | if (value & 2) /* SOFTRESET */ |
478 | 7f132a21 | cmchao | omap_inth_reset(s); |
479 | 7f132a21 | cmchao | return;
|
480 | 7f132a21 | cmchao | |
481 | 7f132a21 | cmchao | case 0x48: /* INTC_CONTROL */ |
482 | 7f132a21 | cmchao | s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ |
483 | 7f132a21 | cmchao | if (value & 2) { /* NEWFIQAGR */ |
484 | 7f132a21 | cmchao | qemu_set_irq(s->parent_intr[1], 0); |
485 | 7f132a21 | cmchao | s->new_agr[1] = ~0; |
486 | 7f132a21 | cmchao | omap_inth_update(s, 1);
|
487 | 7f132a21 | cmchao | } |
488 | 7f132a21 | cmchao | if (value & 1) { /* NEWIRQAGR */ |
489 | 7f132a21 | cmchao | qemu_set_irq(s->parent_intr[0], 0); |
490 | 7f132a21 | cmchao | s->new_agr[0] = ~0; |
491 | 7f132a21 | cmchao | omap_inth_update(s, 0);
|
492 | 7f132a21 | cmchao | } |
493 | 7f132a21 | cmchao | return;
|
494 | 7f132a21 | cmchao | |
495 | 7f132a21 | cmchao | case 0x4c: /* INTC_PROTECTION */ |
496 | 7f132a21 | cmchao | /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
|
497 | 7f132a21 | cmchao | * for every register, see Chapter 3 and 4 for privileged mode. */
|
498 | 7f132a21 | cmchao | if (value & 1) |
499 | 7f132a21 | cmchao | fprintf(stderr, "%s: protection mode enable attempt\n",
|
500 | 7f132a21 | cmchao | __FUNCTION__); |
501 | 7f132a21 | cmchao | return;
|
502 | 7f132a21 | cmchao | |
503 | 7f132a21 | cmchao | case 0x50: /* INTC_IDLE */ |
504 | 7f132a21 | cmchao | s->autoidle &= ~3;
|
505 | 7f132a21 | cmchao | s->autoidle |= value & 3;
|
506 | 7f132a21 | cmchao | return;
|
507 | 7f132a21 | cmchao | |
508 | 7f132a21 | cmchao | /* Per-bank registers */
|
509 | 7f132a21 | cmchao | case 0x84: /* INTC_MIR */ |
510 | 7f132a21 | cmchao | bank->mask = value; |
511 | 7f132a21 | cmchao | omap_inth_update(s, 0);
|
512 | 7f132a21 | cmchao | omap_inth_update(s, 1);
|
513 | 7f132a21 | cmchao | return;
|
514 | 7f132a21 | cmchao | |
515 | 7f132a21 | cmchao | case 0x88: /* INTC_MIR_CLEAR */ |
516 | 7f132a21 | cmchao | bank->mask &= ~value; |
517 | 7f132a21 | cmchao | omap_inth_update(s, 0);
|
518 | 7f132a21 | cmchao | omap_inth_update(s, 1);
|
519 | 7f132a21 | cmchao | return;
|
520 | 7f132a21 | cmchao | |
521 | 7f132a21 | cmchao | case 0x8c: /* INTC_MIR_SET */ |
522 | 7f132a21 | cmchao | bank->mask |= value; |
523 | 7f132a21 | cmchao | return;
|
524 | 7f132a21 | cmchao | |
525 | 7f132a21 | cmchao | case 0x90: /* INTC_ISR_SET */ |
526 | 7f132a21 | cmchao | bank->irqs |= bank->swi |= value; |
527 | 7f132a21 | cmchao | omap_inth_update(s, 0);
|
528 | 7f132a21 | cmchao | omap_inth_update(s, 1);
|
529 | 7f132a21 | cmchao | return;
|
530 | 7f132a21 | cmchao | |
531 | 7f132a21 | cmchao | case 0x94: /* INTC_ISR_CLEAR */ |
532 | 7f132a21 | cmchao | bank->swi &= ~value; |
533 | 7f132a21 | cmchao | bank->irqs = bank->swi & bank->inputs; |
534 | 7f132a21 | cmchao | return;
|
535 | 7f132a21 | cmchao | |
536 | 7f132a21 | cmchao | /* Per-line registers */
|
537 | 7f132a21 | cmchao | case 0x100 ... 0x300: /* INTC_ILR */ |
538 | 7f132a21 | cmchao | bank_no = (offset - 0x100) >> 7; |
539 | 7f132a21 | cmchao | if (bank_no > s->nbanks)
|
540 | 7f132a21 | cmchao | break;
|
541 | 7f132a21 | cmchao | bank = &s->bank[bank_no]; |
542 | 7f132a21 | cmchao | line_no = (offset & 0x7f) >> 2; |
543 | 7f132a21 | cmchao | bank->priority[line_no] = (value >> 2) & 0x3f; |
544 | 7f132a21 | cmchao | bank->fiq &= ~(1 << line_no);
|
545 | 7f132a21 | cmchao | bank->fiq |= (value & 1) << line_no;
|
546 | 7f132a21 | cmchao | return;
|
547 | 7f132a21 | cmchao | |
548 | 7f132a21 | cmchao | case 0x00: /* INTC_REVISION */ |
549 | 7f132a21 | cmchao | case 0x14: /* INTC_SYSSTATUS */ |
550 | 7f132a21 | cmchao | case 0x40: /* INTC_SIR_IRQ */ |
551 | 7f132a21 | cmchao | case 0x44: /* INTC_SIR_FIQ */ |
552 | 7f132a21 | cmchao | case 0x80: /* INTC_ITR */ |
553 | 7f132a21 | cmchao | case 0x98: /* INTC_PENDING_IRQ */ |
554 | 7f132a21 | cmchao | case 0x9c: /* INTC_PENDING_FIQ */ |
555 | 7f132a21 | cmchao | OMAP_RO_REG(addr); |
556 | 7f132a21 | cmchao | return;
|
557 | 7f132a21 | cmchao | } |
558 | 7f132a21 | cmchao | OMAP_BAD_REG(addr); |
559 | 7f132a21 | cmchao | } |
560 | 7f132a21 | cmchao | |
561 | 7f132a21 | cmchao | static CPUReadMemoryFunc * const omap2_inth_readfn[] = { |
562 | 7f132a21 | cmchao | omap_badwidth_read32, |
563 | 7f132a21 | cmchao | omap_badwidth_read32, |
564 | 7f132a21 | cmchao | omap2_inth_read, |
565 | 7f132a21 | cmchao | }; |
566 | 7f132a21 | cmchao | |
567 | 7f132a21 | cmchao | static CPUWriteMemoryFunc * const omap2_inth_writefn[] = { |
568 | 7f132a21 | cmchao | omap2_inth_write, |
569 | 7f132a21 | cmchao | omap2_inth_write, |
570 | 7f132a21 | cmchao | omap2_inth_write, |
571 | 7f132a21 | cmchao | }; |
572 | 7f132a21 | cmchao | |
573 | 7f132a21 | cmchao | struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
|
574 | 7f132a21 | cmchao | int size, int nbanks, qemu_irq **pins, |
575 | 7f132a21 | cmchao | qemu_irq parent_irq, qemu_irq parent_fiq, |
576 | 7f132a21 | cmchao | omap_clk fclk, omap_clk iclk) |
577 | 7f132a21 | cmchao | { |
578 | 7f132a21 | cmchao | int iomemtype;
|
579 | 7f132a21 | cmchao | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
580 | 7f132a21 | cmchao | qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
581 | 7f132a21 | cmchao | sizeof(struct omap_intr_handler_bank_s) * nbanks); |
582 | 7f132a21 | cmchao | |
583 | 7f132a21 | cmchao | s->parent_intr[0] = parent_irq;
|
584 | 7f132a21 | cmchao | s->parent_intr[1] = parent_fiq;
|
585 | 7f132a21 | cmchao | s->nbanks = nbanks; |
586 | 7f132a21 | cmchao | s->level_only = 1;
|
587 | 7f132a21 | cmchao | s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
|
588 | 7f132a21 | cmchao | if (pins)
|
589 | 7f132a21 | cmchao | *pins = s->pins; |
590 | 7f132a21 | cmchao | |
591 | 7f132a21 | cmchao | omap_inth_reset(s); |
592 | 7f132a21 | cmchao | |
593 | 7f132a21 | cmchao | iomemtype = cpu_register_io_memory(omap2_inth_readfn, |
594 | 7f132a21 | cmchao | omap2_inth_writefn, s); |
595 | 7f132a21 | cmchao | cpu_register_physical_memory(base, size, iomemtype); |
596 | 7f132a21 | cmchao | |
597 | 7f132a21 | cmchao | return s;
|
598 | 7f132a21 | cmchao | } |