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/*
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 * TI OMAP processor's Multichannel SPI emulation.
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 *
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 * Copyright (C) 2007-2009 Nokia Corporation
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 *
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 * Original code for OMAP2 by Andrzej Zaborowski <andrew@openedhand.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) any later version of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, write to the Free Software Foundation, Inc.,
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 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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 */
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#include "hw.h"
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#include "omap.h"
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/* Multichannel SPI */
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struct omap_mcspi_s {
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    qemu_irq irq;
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    int chnum;
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    uint32_t sysconfig;
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    uint32_t systest;
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    uint32_t irqst;
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    uint32_t irqen;
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    uint32_t wken;
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    uint32_t control;
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    struct omap_mcspi_ch_s {
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        qemu_irq txdrq;
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        qemu_irq rxdrq;
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        uint32_t (*txrx)(void *opaque, uint32_t, int);
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        void *opaque;
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        uint32_t tx;
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        uint32_t rx;
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        uint32_t config;
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        uint32_t status;
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        uint32_t control;
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    } ch[4];
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};
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static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
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{
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    qemu_set_irq(s->irq, s->irqst & s->irqen);
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}
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static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
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{
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    qemu_set_irq(ch->txdrq,
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                    (ch->control & 1) &&                /* EN */
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                    (ch->config & (1 << 14)) &&                /* DMAW */
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                    (ch->status & (1 << 1)) &&                /* TXS */
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                    ((ch->config >> 12) & 3) != 1);        /* TRM */
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    qemu_set_irq(ch->rxdrq,
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                    (ch->control & 1) &&                /* EN */
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                    (ch->config & (1 << 15)) &&                /* DMAW */
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                    (ch->status & (1 << 0)) &&                /* RXS */
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                    ((ch->config >> 12) & 3) != 2);        /* TRM */
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}
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static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
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{
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    struct omap_mcspi_ch_s *ch = s->ch + chnum;
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    if (!(ch->control & 1))                                /* EN */
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        return;
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    if ((ch->status & (1 << 0)) &&                        /* RXS */
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                    ((ch->config >> 12) & 3) != 2 &&        /* TRM */
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                    !(ch->config & (1 << 19)))                /* TURBO */
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        goto intr_update;
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    if ((ch->status & (1 << 1)) &&                        /* TXS */
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                    ((ch->config >> 12) & 3) != 1)        /* TRM */
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        goto intr_update;
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    if (!(s->control & 1) ||                                /* SINGLE */
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                    (ch->config & (1 << 20))) {                /* FORCE */
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        if (ch->txrx)
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            ch->rx = ch->txrx(ch->opaque, ch->tx,        /* WL */
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                            1 + (0x1f & (ch->config >> 7)));
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    }
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    ch->tx = 0;
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    ch->status |= 1 << 2;                                /* EOT */
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    ch->status |= 1 << 1;                                /* TXS */
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    if (((ch->config >> 12) & 3) != 2)                        /* TRM */
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        ch->status |= 1 << 0;                                /* RXS */
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intr_update:
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    if ((ch->status & (1 << 0)) &&                        /* RXS */
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                    ((ch->config >> 12) & 3) != 2 &&        /* TRM */
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                    !(ch->config & (1 << 19)))                /* TURBO */
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        s->irqst |= 1 << (2 + 4 * chnum);                /* RX_FULL */
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    if ((ch->status & (1 << 1)) &&                        /* TXS */
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                    ((ch->config >> 12) & 3) != 1)        /* TRM */
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        s->irqst |= 1 << (0 + 4 * chnum);                /* TX_EMPTY */
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    omap_mcspi_interrupt_update(s);
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    omap_mcspi_dmarequest_update(ch);
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}
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void omap_mcspi_reset(struct omap_mcspi_s *s)
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{
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    int ch;
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    s->sysconfig = 0;
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    s->systest = 0;
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    s->irqst = 0;
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    s->irqen = 0;
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    s->wken = 0;
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    s->control = 4;
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    for (ch = 0; ch < 4; ch ++) {
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        s->ch[ch].config = 0x060000;
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        s->ch[ch].status = 2;                                /* TXS */
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        s->ch[ch].control = 0;
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        omap_mcspi_dmarequest_update(s->ch + ch);
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    }
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    omap_mcspi_interrupt_update(s);
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}
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static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
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{
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    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
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    int ch = 0;
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    uint32_t ret;
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    switch (addr) {
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    case 0x00:        /* MCSPI_REVISION */
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        return 0x91;
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    case 0x10:        /* MCSPI_SYSCONFIG */
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        return s->sysconfig;
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    case 0x14:        /* MCSPI_SYSSTATUS */
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        return 1;                                        /* RESETDONE */
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    case 0x18:        /* MCSPI_IRQSTATUS */
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        return s->irqst;
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    case 0x1c:        /* MCSPI_IRQENABLE */
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        return s->irqen;
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    case 0x20:        /* MCSPI_WAKEUPENABLE */
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        return s->wken;
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    case 0x24:        /* MCSPI_SYST */
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        return s->systest;
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    case 0x28:        /* MCSPI_MODULCTRL */
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        return s->control;
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    case 0x68: ch ++;
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    case 0x54: ch ++;
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    case 0x40: ch ++;
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    case 0x2c:        /* MCSPI_CHCONF */
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        return s->ch[ch].config;
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    case 0x6c: ch ++;
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    case 0x58: ch ++;
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    case 0x44: ch ++;
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    case 0x30:        /* MCSPI_CHSTAT */
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        return s->ch[ch].status;
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    case 0x70: ch ++;
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    case 0x5c: ch ++;
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    case 0x48: ch ++;
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    case 0x34:        /* MCSPI_CHCTRL */
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        return s->ch[ch].control;
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    case 0x74: ch ++;
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    case 0x60: ch ++;
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    case 0x4c: ch ++;
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    case 0x38:        /* MCSPI_TX */
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        return s->ch[ch].tx;
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    case 0x78: ch ++;
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    case 0x64: ch ++;
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    case 0x50: ch ++;
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    case 0x3c:        /* MCSPI_RX */
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        s->ch[ch].status &= ~(1 << 0);                        /* RXS */
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        ret = s->ch[ch].rx;
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        omap_mcspi_transfer_run(s, ch);
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        return ret;
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    }
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    OMAP_BAD_REG(addr);
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    return 0;
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}
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static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
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                uint32_t value)
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{
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    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
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    int ch = 0;
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    switch (addr) {
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    case 0x00:        /* MCSPI_REVISION */
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    case 0x14:        /* MCSPI_SYSSTATUS */
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    case 0x30:        /* MCSPI_CHSTAT0 */
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    case 0x3c:        /* MCSPI_RX0 */
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    case 0x44:        /* MCSPI_CHSTAT1 */
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    case 0x50:        /* MCSPI_RX1 */
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    case 0x58:        /* MCSPI_CHSTAT2 */
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    case 0x64:        /* MCSPI_RX2 */
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    case 0x6c:        /* MCSPI_CHSTAT3 */
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    case 0x78:        /* MCSPI_RX3 */
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        OMAP_RO_REG(addr);
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        return;
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    case 0x10:        /* MCSPI_SYSCONFIG */
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        if (value & (1 << 1))                                /* SOFTRESET */
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            omap_mcspi_reset(s);
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        s->sysconfig = value & 0x31d;
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        break;
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    case 0x18:        /* MCSPI_IRQSTATUS */
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        if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
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            s->irqst &= ~value;
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            omap_mcspi_interrupt_update(s);
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        }
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        break;
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    case 0x1c:        /* MCSPI_IRQENABLE */
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        s->irqen = value & 0x1777f;
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        omap_mcspi_interrupt_update(s);
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        break;
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    case 0x20:        /* MCSPI_WAKEUPENABLE */
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        s->wken = value & 1;
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        break;
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    case 0x24:        /* MCSPI_SYST */
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        if (s->control & (1 << 3))                        /* SYSTEM_TEST */
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            if (value & (1 << 11)) {                        /* SSB */
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                s->irqst |= 0x1777f;
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                omap_mcspi_interrupt_update(s);
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            }
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        s->systest = value & 0xfff;
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        break;
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    case 0x28:        /* MCSPI_MODULCTRL */
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        if (value & (1 << 3))                                /* SYSTEM_TEST */
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            if (s->systest & (1 << 11)) {                /* SSB */
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                s->irqst |= 0x1777f;
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                omap_mcspi_interrupt_update(s);
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            }
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        s->control = value & 0xf;
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        break;
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    case 0x68: ch ++;
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    case 0x54: ch ++;
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    case 0x40: ch ++;
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    case 0x2c:        /* MCSPI_CHCONF */
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        if ((value ^ s->ch[ch].config) & (3 << 14))        /* DMAR | DMAW */
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            omap_mcspi_dmarequest_update(s->ch + ch);
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        if (((value >> 12) & 3) == 3)                        /* TRM */
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            fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
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        if (((value >> 7) & 0x1f) < 3)                        /* WL */
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            fprintf(stderr, "%s: invalid WL value (%i)\n",
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                            __FUNCTION__, (value >> 7) & 0x1f);
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        s->ch[ch].config = value & 0x7fffff;
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        break;
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    case 0x70: ch ++;
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    case 0x5c: ch ++;
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    case 0x48: ch ++;
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    case 0x34:        /* MCSPI_CHCTRL */
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        if (value & ~s->ch[ch].control & 1) {                /* EN */
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            s->ch[ch].control |= 1;
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            omap_mcspi_transfer_run(s, ch);
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        } else
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            s->ch[ch].control = value & 1;
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        break;
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    case 0x74: ch ++;
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    case 0x60: ch ++;
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    case 0x4c: ch ++;
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    case 0x38:        /* MCSPI_TX */
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        s->ch[ch].tx = value;
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        s->ch[ch].status &= ~(1 << 1);                        /* TXS */
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        omap_mcspi_transfer_run(s, ch);
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        break;
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    default:
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        OMAP_BAD_REG(addr);
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        return;
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    }
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}
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static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
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    omap_badwidth_read32,
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    omap_badwidth_read32,
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    omap_mcspi_read,
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};
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static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
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    omap_badwidth_write32,
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    omap_badwidth_write32,
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    omap_mcspi_write,
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};
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struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
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                qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
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{
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    int iomemtype;
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    struct omap_mcspi_s *s = (struct omap_mcspi_s *)
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            qemu_mallocz(sizeof(struct omap_mcspi_s));
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    struct omap_mcspi_ch_s *ch = s->ch;
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    s->irq = irq;
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    s->chnum = chnum;
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    while (chnum --) {
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        ch->txdrq = *drq ++;
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        ch->rxdrq = *drq ++;
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        ch ++;
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    }
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    omap_mcspi_reset(s);
329 2d08cc7c cmchao
330 2d08cc7c cmchao
    iomemtype = l4_register_io_memory(omap_mcspi_readfn,
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                    omap_mcspi_writefn, s);
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    omap_l4_attach(ta, 0, iomemtype);
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    return s;
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}
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337 2d08cc7c cmchao
void omap_mcspi_attach(struct omap_mcspi_s *s,
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                uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
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                int chipselect)
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{
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    if (chipselect < 0 || chipselect >= s->chnum)
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        hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
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    s->ch[chipselect].txrx = txrx;
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    s->ch[chipselect].opaque = opaque;
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}