root / hw / omap_intc.c @ 17786d52
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/*
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* TI OMAP interrupt controller emulation.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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* Copyright (C) 2007-2008 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "omap.h" |
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|
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/* Interrupt Handlers */
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struct omap_intr_handler_bank_s {
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uint32_t irqs; |
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uint32_t inputs; |
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uint32_t mask; |
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uint32_t fiq; |
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uint32_t sens_edge; |
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uint32_t swi; |
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unsigned char priority[32]; |
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}; |
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struct omap_intr_handler_s {
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qemu_irq *pins; |
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qemu_irq parent_intr[2];
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unsigned char nbanks; |
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int level_only;
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|
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/* state */
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uint32_t new_agr[2];
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int sir_intr[2]; |
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int autoidle;
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uint32_t mask; |
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struct omap_intr_handler_bank_s bank[];
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}; |
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|
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inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n) |
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{
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return s->pins[n];
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} |
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|
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static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) |
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{
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int i, j, sir_intr, p_intr, p, f;
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uint32_t level; |
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sir_intr = 0;
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p_intr = 255;
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/* Find the interrupt line with the highest dynamic priority.
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* Note: 0 denotes the hightest priority.
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* If all interrupts have the same priority, the default order is IRQ_N,
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* IRQ_N-1,...,IRQ_0. */
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for (j = 0; j < s->nbanks; ++j) { |
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level = s->bank[j].irqs & ~s->bank[j].mask & |
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(is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); |
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for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, |
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level >>= f) {
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p = s->bank[j].priority[i]; |
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if (p <= p_intr) {
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p_intr = p; |
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sir_intr = 32 * j + i;
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} |
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f = ffs(level >> 1);
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} |
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} |
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s->sir_intr[is_fiq] = sir_intr; |
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} |
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|
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static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) |
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{
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int i;
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uint32_t has_intr = 0;
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for (i = 0; i < s->nbanks; ++i) |
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has_intr |= s->bank[i].irqs & ~s->bank[i].mask & |
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(is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); |
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if (s->new_agr[is_fiq] & has_intr & s->mask) {
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s->new_agr[is_fiq] = 0;
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omap_inth_sir_update(s, is_fiq); |
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qemu_set_irq(s->parent_intr[is_fiq], 1);
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} |
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} |
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#define INT_FALLING_EDGE 0 |
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#define INT_LOW_LEVEL 1 |
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static void omap_set_intr(void *opaque, int irq, int req) |
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{
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struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
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uint32_t rise; |
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struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
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int n = irq & 31; |
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if (req) {
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rise = ~bank->irqs & (1 << n);
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if (~bank->sens_edge & (1 << n)) |
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rise &= ~bank->inputs; |
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bank->inputs |= (1 << n);
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if (rise) {
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bank->irqs |= rise; |
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omap_inth_update(ih, 0);
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omap_inth_update(ih, 1);
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} |
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} else {
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rise = bank->sens_edge & bank->irqs & (1 << n);
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bank->irqs &= ~rise; |
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bank->inputs &= ~(1 << n);
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} |
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} |
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/* Simplified version with no edge detection */
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static void omap_set_intr_noedge(void *opaque, int irq, int req) |
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{
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struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
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uint32_t rise; |
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struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
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int n = irq & 31; |
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if (req) {
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rise = ~bank->inputs & (1 << n);
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if (rise) {
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bank->irqs |= bank->inputs |= rise; |
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omap_inth_update(ih, 0);
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omap_inth_update(ih, 1);
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} |
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} else
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bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
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} |
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static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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int i, offset = addr;
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int bank_no = offset >> 8; |
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int line_no;
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struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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offset &= 0xff;
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switch (offset) {
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case 0x00: /* ITR */ |
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return bank->irqs;
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case 0x04: /* MIR */ |
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return bank->mask;
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case 0x10: /* SIR_IRQ_CODE */ |
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case 0x14: /* SIR_FIQ_CODE */ |
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if (bank_no != 0) |
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break;
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line_no = s->sir_intr[(offset - 0x10) >> 2]; |
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bank = &s->bank[line_no >> 5];
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i = line_no & 31;
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if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) |
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bank->irqs &= ~(1 << i);
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return line_no;
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case 0x18: /* CONTROL_REG */ |
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if (bank_no != 0) |
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break;
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return 0; |
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|
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case 0x1c: /* ILR0 */ |
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case 0x20: /* ILR1 */ |
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case 0x24: /* ILR2 */ |
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case 0x28: /* ILR3 */ |
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case 0x2c: /* ILR4 */ |
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case 0x30: /* ILR5 */ |
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case 0x34: /* ILR6 */ |
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case 0x38: /* ILR7 */ |
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case 0x3c: /* ILR8 */ |
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case 0x40: /* ILR9 */ |
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case 0x44: /* ILR10 */ |
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case 0x48: /* ILR11 */ |
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case 0x4c: /* ILR12 */ |
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case 0x50: /* ILR13 */ |
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case 0x54: /* ILR14 */ |
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case 0x58: /* ILR15 */ |
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case 0x5c: /* ILR16 */ |
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case 0x60: /* ILR17 */ |
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case 0x64: /* ILR18 */ |
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case 0x68: /* ILR19 */ |
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case 0x6c: /* ILR20 */ |
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case 0x70: /* ILR21 */ |
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case 0x74: /* ILR22 */ |
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case 0x78: /* ILR23 */ |
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case 0x7c: /* ILR24 */ |
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case 0x80: /* ILR25 */ |
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case 0x84: /* ILR26 */ |
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case 0x88: /* ILR27 */ |
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case 0x8c: /* ILR28 */ |
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case 0x90: /* ILR29 */ |
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case 0x94: /* ILR30 */ |
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case 0x98: /* ILR31 */ |
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i = (offset - 0x1c) >> 2; |
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return (bank->priority[i] << 2) | |
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(((bank->sens_edge >> i) & 1) << 1) | |
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((bank->fiq >> i) & 1);
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case 0x9c: /* ISR */ |
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return 0x00000000; |
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|
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} |
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OMAP_BAD_REG(addr); |
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return 0; |
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} |
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|
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static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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int i, offset = addr;
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int bank_no = offset >> 8; |
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struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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offset &= 0xff;
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switch (offset) {
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case 0x00: /* ITR */ |
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/* Important: ignore the clearing if the IRQ is level-triggered and
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the input bit is 1 */
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bank->irqs &= value | (bank->inputs & bank->sens_edge); |
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return;
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case 0x04: /* MIR */ |
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bank->mask = value; |
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omap_inth_update(s, 0);
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omap_inth_update(s, 1);
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return;
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|
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case 0x10: /* SIR_IRQ_CODE */ |
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case 0x14: /* SIR_FIQ_CODE */ |
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OMAP_RO_REG(addr); |
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break;
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|
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case 0x18: /* CONTROL_REG */ |
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if (bank_no != 0) |
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break;
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if (value & 2) { |
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qemu_set_irq(s->parent_intr[1], 0); |
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s->new_agr[1] = ~0; |
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omap_inth_update(s, 1);
|
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} |
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if (value & 1) { |
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qemu_set_irq(s->parent_intr[0], 0); |
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s->new_agr[0] = ~0; |
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omap_inth_update(s, 0);
|
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} |
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return;
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|
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case 0x1c: /* ILR0 */ |
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case 0x20: /* ILR1 */ |
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case 0x24: /* ILR2 */ |
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case 0x28: /* ILR3 */ |
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case 0x2c: /* ILR4 */ |
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case 0x30: /* ILR5 */ |
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case 0x34: /* ILR6 */ |
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case 0x38: /* ILR7 */ |
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case 0x3c: /* ILR8 */ |
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case 0x40: /* ILR9 */ |
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case 0x44: /* ILR10 */ |
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case 0x48: /* ILR11 */ |
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case 0x4c: /* ILR12 */ |
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case 0x50: /* ILR13 */ |
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case 0x54: /* ILR14 */ |
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case 0x58: /* ILR15 */ |
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case 0x5c: /* ILR16 */ |
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case 0x60: /* ILR17 */ |
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case 0x64: /* ILR18 */ |
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case 0x68: /* ILR19 */ |
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case 0x6c: /* ILR20 */ |
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case 0x70: /* ILR21 */ |
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case 0x74: /* ILR22 */ |
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case 0x78: /* ILR23 */ |
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case 0x7c: /* ILR24 */ |
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case 0x80: /* ILR25 */ |
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case 0x84: /* ILR26 */ |
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case 0x88: /* ILR27 */ |
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case 0x8c: /* ILR28 */ |
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case 0x90: /* ILR29 */ |
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case 0x94: /* ILR30 */ |
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case 0x98: /* ILR31 */ |
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i = (offset - 0x1c) >> 2; |
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bank->priority[i] = (value >> 2) & 0x1f; |
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bank->sens_edge &= ~(1 << i);
|
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bank->sens_edge |= ((value >> 1) & 1) << i; |
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bank->fiq &= ~(1 << i);
|
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bank->fiq |= (value & 1) << i;
|
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return;
|
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|
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case 0x9c: /* ISR */ |
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for (i = 0; i < 32; i ++) |
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if (value & (1 << i)) { |
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omap_set_intr(s, 32 * bank_no + i, 1); |
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return;
|
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} |
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return;
|
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} |
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OMAP_BAD_REG(addr); |
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} |
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|
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static CPUReadMemoryFunc * const omap_inth_readfn[] = { |
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omap_badwidth_read32, |
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omap_badwidth_read32, |
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omap_inth_read, |
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}; |
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|
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static CPUWriteMemoryFunc * const omap_inth_writefn[] = { |
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omap_inth_write, |
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omap_inth_write, |
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omap_inth_write, |
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}; |
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|
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void omap_inth_reset(struct omap_intr_handler_s *s) |
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{
|
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int i;
|
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|
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for (i = 0; i < s->nbanks; ++i){ |
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s->bank[i].irqs = 0x00000000;
|
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s->bank[i].mask = 0xffffffff;
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s->bank[i].sens_edge = 0x00000000;
|
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s->bank[i].fiq = 0x00000000;
|
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s->bank[i].inputs = 0x00000000;
|
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s->bank[i].swi = 0x00000000;
|
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memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); |
| 339 |
|
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if (s->level_only)
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s->bank[i].sens_edge = 0xffffffff;
|
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} |
| 343 |
|
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s->new_agr[0] = ~0; |
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s->new_agr[1] = ~0; |
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s->sir_intr[0] = 0; |
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s->sir_intr[1] = 0; |
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s->autoidle = 0;
|
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s->mask = ~0;
|
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|
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qemu_set_irq(s->parent_intr[0], 0); |
| 352 |
qemu_set_irq(s->parent_intr[1], 0); |
| 353 |
} |
| 354 |
|
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
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unsigned long size, unsigned char nbanks, qemu_irq **pins, |
| 357 |
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) |
| 358 |
{
|
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int iomemtype;
|
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
| 361 |
qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
| 362 |
sizeof(struct omap_intr_handler_bank_s) * nbanks); |
| 363 |
|
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s->parent_intr[0] = parent_irq;
|
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s->parent_intr[1] = parent_fiq;
|
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s->nbanks = nbanks; |
| 367 |
s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
|
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if (pins)
|
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*pins = s->pins; |
| 370 |
|
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omap_inth_reset(s); |
| 372 |
|
| 373 |
iomemtype = cpu_register_io_memory(omap_inth_readfn, |
| 374 |
omap_inth_writefn, s); |
| 375 |
cpu_register_physical_memory(base, size, iomemtype); |
| 376 |
|
| 377 |
return s;
|
| 378 |
} |
| 379 |
|
| 380 |
static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) |
| 381 |
{
|
| 382 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 383 |
int offset = addr;
|
| 384 |
int bank_no, line_no;
|
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struct omap_intr_handler_bank_s *bank = NULL; |
| 386 |
|
| 387 |
if ((offset & 0xf80) == 0x80) { |
| 388 |
bank_no = (offset & 0x60) >> 5; |
| 389 |
if (bank_no < s->nbanks) {
|
| 390 |
offset &= ~0x60;
|
| 391 |
bank = &s->bank[bank_no]; |
| 392 |
} |
| 393 |
} |
| 394 |
|
| 395 |
switch (offset) {
|
| 396 |
case 0x00: /* INTC_REVISION */ |
| 397 |
return 0x21; |
| 398 |
|
| 399 |
case 0x10: /* INTC_SYSCONFIG */ |
| 400 |
return (s->autoidle >> 2) & 1; |
| 401 |
|
| 402 |
case 0x14: /* INTC_SYSSTATUS */ |
| 403 |
return 1; /* RESETDONE */ |
| 404 |
|
| 405 |
case 0x40: /* INTC_SIR_IRQ */ |
| 406 |
return s->sir_intr[0]; |
| 407 |
|
| 408 |
case 0x44: /* INTC_SIR_FIQ */ |
| 409 |
return s->sir_intr[1]; |
| 410 |
|
| 411 |
case 0x48: /* INTC_CONTROL */ |
| 412 |
return (!s->mask) << 2; /* GLOBALMASK */ |
| 413 |
|
| 414 |
case 0x4c: /* INTC_PROTECTION */ |
| 415 |
return 0; |
| 416 |
|
| 417 |
case 0x50: /* INTC_IDLE */ |
| 418 |
return s->autoidle & 3; |
| 419 |
|
| 420 |
/* Per-bank registers */
|
| 421 |
case 0x80: /* INTC_ITR */ |
| 422 |
return bank->inputs;
|
| 423 |
|
| 424 |
case 0x84: /* INTC_MIR */ |
| 425 |
return bank->mask;
|
| 426 |
|
| 427 |
case 0x88: /* INTC_MIR_CLEAR */ |
| 428 |
case 0x8c: /* INTC_MIR_SET */ |
| 429 |
return 0; |
| 430 |
|
| 431 |
case 0x90: /* INTC_ISR_SET */ |
| 432 |
return bank->swi;
|
| 433 |
|
| 434 |
case 0x94: /* INTC_ISR_CLEAR */ |
| 435 |
return 0; |
| 436 |
|
| 437 |
case 0x98: /* INTC_PENDING_IRQ */ |
| 438 |
return bank->irqs & ~bank->mask & ~bank->fiq;
|
| 439 |
|
| 440 |
case 0x9c: /* INTC_PENDING_FIQ */ |
| 441 |
return bank->irqs & ~bank->mask & bank->fiq;
|
| 442 |
|
| 443 |
/* Per-line registers */
|
| 444 |
case 0x100 ... 0x300: /* INTC_ILR */ |
| 445 |
bank_no = (offset - 0x100) >> 7; |
| 446 |
if (bank_no > s->nbanks)
|
| 447 |
break;
|
| 448 |
bank = &s->bank[bank_no]; |
| 449 |
line_no = (offset & 0x7f) >> 2; |
| 450 |
return (bank->priority[line_no] << 2) | |
| 451 |
((bank->fiq >> line_no) & 1);
|
| 452 |
} |
| 453 |
OMAP_BAD_REG(addr); |
| 454 |
return 0; |
| 455 |
} |
| 456 |
|
| 457 |
static void omap2_inth_write(void *opaque, target_phys_addr_t addr, |
| 458 |
uint32_t value) |
| 459 |
{
|
| 460 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 461 |
int offset = addr;
|
| 462 |
int bank_no, line_no;
|
| 463 |
struct omap_intr_handler_bank_s *bank = NULL; |
| 464 |
|
| 465 |
if ((offset & 0xf80) == 0x80) { |
| 466 |
bank_no = (offset & 0x60) >> 5; |
| 467 |
if (bank_no < s->nbanks) {
|
| 468 |
offset &= ~0x60;
|
| 469 |
bank = &s->bank[bank_no]; |
| 470 |
} |
| 471 |
} |
| 472 |
|
| 473 |
switch (offset) {
|
| 474 |
case 0x10: /* INTC_SYSCONFIG */ |
| 475 |
s->autoidle &= 4;
|
| 476 |
s->autoidle |= (value & 1) << 2; |
| 477 |
if (value & 2) /* SOFTRESET */ |
| 478 |
omap_inth_reset(s); |
| 479 |
return;
|
| 480 |
|
| 481 |
case 0x48: /* INTC_CONTROL */ |
| 482 |
s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ |
| 483 |
if (value & 2) { /* NEWFIQAGR */ |
| 484 |
qemu_set_irq(s->parent_intr[1], 0); |
| 485 |
s->new_agr[1] = ~0; |
| 486 |
omap_inth_update(s, 1);
|
| 487 |
} |
| 488 |
if (value & 1) { /* NEWIRQAGR */ |
| 489 |
qemu_set_irq(s->parent_intr[0], 0); |
| 490 |
s->new_agr[0] = ~0; |
| 491 |
omap_inth_update(s, 0);
|
| 492 |
} |
| 493 |
return;
|
| 494 |
|
| 495 |
case 0x4c: /* INTC_PROTECTION */ |
| 496 |
/* TODO: Make a bitmap (or sizeof(char)map) of access privileges
|
| 497 |
* for every register, see Chapter 3 and 4 for privileged mode. */
|
| 498 |
if (value & 1) |
| 499 |
fprintf(stderr, "%s: protection mode enable attempt\n",
|
| 500 |
__FUNCTION__); |
| 501 |
return;
|
| 502 |
|
| 503 |
case 0x50: /* INTC_IDLE */ |
| 504 |
s->autoidle &= ~3;
|
| 505 |
s->autoidle |= value & 3;
|
| 506 |
return;
|
| 507 |
|
| 508 |
/* Per-bank registers */
|
| 509 |
case 0x84: /* INTC_MIR */ |
| 510 |
bank->mask = value; |
| 511 |
omap_inth_update(s, 0);
|
| 512 |
omap_inth_update(s, 1);
|
| 513 |
return;
|
| 514 |
|
| 515 |
case 0x88: /* INTC_MIR_CLEAR */ |
| 516 |
bank->mask &= ~value; |
| 517 |
omap_inth_update(s, 0);
|
| 518 |
omap_inth_update(s, 1);
|
| 519 |
return;
|
| 520 |
|
| 521 |
case 0x8c: /* INTC_MIR_SET */ |
| 522 |
bank->mask |= value; |
| 523 |
return;
|
| 524 |
|
| 525 |
case 0x90: /* INTC_ISR_SET */ |
| 526 |
bank->irqs |= bank->swi |= value; |
| 527 |
omap_inth_update(s, 0);
|
| 528 |
omap_inth_update(s, 1);
|
| 529 |
return;
|
| 530 |
|
| 531 |
case 0x94: /* INTC_ISR_CLEAR */ |
| 532 |
bank->swi &= ~value; |
| 533 |
bank->irqs = bank->swi & bank->inputs; |
| 534 |
return;
|
| 535 |
|
| 536 |
/* Per-line registers */
|
| 537 |
case 0x100 ... 0x300: /* INTC_ILR */ |
| 538 |
bank_no = (offset - 0x100) >> 7; |
| 539 |
if (bank_no > s->nbanks)
|
| 540 |
break;
|
| 541 |
bank = &s->bank[bank_no]; |
| 542 |
line_no = (offset & 0x7f) >> 2; |
| 543 |
bank->priority[line_no] = (value >> 2) & 0x3f; |
| 544 |
bank->fiq &= ~(1 << line_no);
|
| 545 |
bank->fiq |= (value & 1) << line_no;
|
| 546 |
return;
|
| 547 |
|
| 548 |
case 0x00: /* INTC_REVISION */ |
| 549 |
case 0x14: /* INTC_SYSSTATUS */ |
| 550 |
case 0x40: /* INTC_SIR_IRQ */ |
| 551 |
case 0x44: /* INTC_SIR_FIQ */ |
| 552 |
case 0x80: /* INTC_ITR */ |
| 553 |
case 0x98: /* INTC_PENDING_IRQ */ |
| 554 |
case 0x9c: /* INTC_PENDING_FIQ */ |
| 555 |
OMAP_RO_REG(addr); |
| 556 |
return;
|
| 557 |
} |
| 558 |
OMAP_BAD_REG(addr); |
| 559 |
} |
| 560 |
|
| 561 |
static CPUReadMemoryFunc * const omap2_inth_readfn[] = { |
| 562 |
omap_badwidth_read32, |
| 563 |
omap_badwidth_read32, |
| 564 |
omap2_inth_read, |
| 565 |
}; |
| 566 |
|
| 567 |
static CPUWriteMemoryFunc * const omap2_inth_writefn[] = { |
| 568 |
omap2_inth_write, |
| 569 |
omap2_inth_write, |
| 570 |
omap2_inth_write, |
| 571 |
}; |
| 572 |
|
| 573 |
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
|
| 574 |
int size, int nbanks, qemu_irq **pins, |
| 575 |
qemu_irq parent_irq, qemu_irq parent_fiq, |
| 576 |
omap_clk fclk, omap_clk iclk) |
| 577 |
{
|
| 578 |
int iomemtype;
|
| 579 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
| 580 |
qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
| 581 |
sizeof(struct omap_intr_handler_bank_s) * nbanks); |
| 582 |
|
| 583 |
s->parent_intr[0] = parent_irq;
|
| 584 |
s->parent_intr[1] = parent_fiq;
|
| 585 |
s->nbanks = nbanks; |
| 586 |
s->level_only = 1;
|
| 587 |
s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
|
| 588 |
if (pins)
|
| 589 |
*pins = s->pins; |
| 590 |
|
| 591 |
omap_inth_reset(s); |
| 592 |
|
| 593 |
iomemtype = cpu_register_io_memory(omap2_inth_readfn, |
| 594 |
omap2_inth_writefn, s); |
| 595 |
cpu_register_physical_memory(base, size, iomemtype); |
| 596 |
|
| 597 |
return s;
|
| 598 |
} |