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/*
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* OneNAND flash memories emulation.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h" |
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#include "flash.h" |
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#include "irq.h" |
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#include "blockdev.h" |
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11 |
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6) |
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typedef struct { |
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uint32_t id; |
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int shift;
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target_phys_addr_t base; |
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qemu_irq intr; |
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qemu_irq rdy; |
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BlockDriverState *bdrv; |
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BlockDriverState *bdrv_cur; |
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uint8_t *image; |
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uint8_t *otp; |
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uint8_t *current; |
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ram_addr_t ram; |
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uint8_t *boot[2];
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uint8_t *data[2][2]; |
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int iomemtype;
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int cycle;
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int otpmode;
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uint16_t addr[8];
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uint16_t unladdr[8];
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int bufaddr;
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int count;
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uint16_t command; |
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uint16_t config[2];
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uint16_t status; |
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uint16_t intstatus; |
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uint16_t wpstatus; |
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ECCState ecc; |
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int density_mask;
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int secs;
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int secs_cur;
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int blocks;
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uint8_t *blockwp; |
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} OneNANDState; |
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enum {
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ONEN_BUF_BLOCK = 0,
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ONEN_BUF_BLOCK2 = 1,
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ONEN_BUF_DEST_BLOCK = 2,
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ONEN_BUF_DEST_PAGE = 3,
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ONEN_BUF_PAGE = 7,
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}; |
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enum {
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ONEN_ERR_CMD = 1 << 10, |
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ONEN_ERR_ERASE = 1 << 11, |
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ONEN_ERR_PROG = 1 << 12, |
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ONEN_ERR_LOAD = 1 << 13, |
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}; |
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enum {
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ONEN_INT_RESET = 1 << 4, |
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ONEN_INT_ERASE = 1 << 5, |
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ONEN_INT_PROG = 1 << 6, |
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ONEN_INT_LOAD = 1 << 7, |
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ONEN_INT = 1 << 15, |
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}; |
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enum {
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ONEN_LOCK_LOCKTIGHTEN = 1 << 0, |
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ONEN_LOCK_LOCKED = 1 << 1, |
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ONEN_LOCK_UNLOCKED = 1 << 2, |
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}; |
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|
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void onenand_base_update(void *opaque, target_phys_addr_t new) |
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{ |
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OneNANDState *s = (OneNANDState *) opaque; |
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s->base = new; |
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/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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* write boot commands. Also take note of the BWPS bit. */
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cpu_register_physical_memory(s->base + (0x0000 << s->shift),
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0x0200 << s->shift, s->iomemtype);
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cpu_register_physical_memory(s->base + (0x0200 << s->shift),
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0xbe00 << s->shift,
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(s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
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if (s->iomemtype)
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cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
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0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift)); |
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} |
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void onenand_base_unmap(void *opaque) |
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{ |
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OneNANDState *s = (OneNANDState *) opaque; |
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cpu_register_physical_memory(s->base, |
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0x10000 << s->shift, IO_MEM_UNASSIGNED);
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} |
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static void onenand_intr_update(OneNANDState *s) |
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{ |
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qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
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} |
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/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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static void onenand_reset(OneNANDState *s, int cold) |
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{ |
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memset(&s->addr, 0, sizeof(s->addr)); |
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s->command = 0;
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s->count = 1;
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s->bufaddr = 0;
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s->config[0] = 0x40c0; |
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s->config[1] = 0x0000; |
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onenand_intr_update(s); |
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qemu_irq_raise(s->rdy); |
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s->status = 0x0000;
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s->intstatus = cold ? 0x8080 : 0x8010; |
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s->unladdr[0] = 0; |
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s->unladdr[1] = 0; |
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s->wpstatus = 0x0002;
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s->cycle = 0;
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s->otpmode = 0;
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s->bdrv_cur = s->bdrv; |
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s->current = s->image; |
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s->secs_cur = s->secs; |
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if (cold) {
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/* Lock the whole flash */
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memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); |
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if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0) |
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hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
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} |
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} |
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static inline int onenand_load_main(OneNANDState *s, int sec, int secn, |
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void *dest)
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{ |
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if (s->bdrv_cur)
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return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(dest, s->current + (sec << 9), secn << 9); |
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return 0; |
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} |
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static inline int onenand_prog_main(OneNANDState *s, int sec, int secn, |
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void *src)
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{ |
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if (s->bdrv_cur)
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return bdrv_write(s->bdrv_cur, sec, src, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (sec << 9), src, secn << 9); |
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return 0; |
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} |
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static inline int onenand_load_spare(OneNANDState *s, int sec, int secn, |
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void *dest)
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{ |
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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else
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memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
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return 0; |
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} |
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static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn, |
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void *src)
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{ |
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(buf + ((sec & 31) << 4), src, secn << 4); |
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return bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0; |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (s->secs_cur << 9) + (sec << 4), src, secn << 4); |
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return 0; |
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} |
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static inline int onenand_erase(OneNANDState *s, int sec, int num) |
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{ |
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/* TODO: optimise */
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uint8_t buf[512];
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memset(buf, 0xff, sizeof(buf)); |
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for (; num > 0; num --, sec ++) { |
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if (onenand_prog_main(s, sec, 1, buf)) |
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return 1; |
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if (onenand_prog_spare(s, sec, 1, buf)) |
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return 1; |
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} |
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return 0; |
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} |
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static void onenand_command(OneNANDState *s, int cmd) |
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{ |
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \ |
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9)); |
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ |
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buf += (s->bufaddr & 3) << 9; |
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ |
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buf += (s->bufaddr & 3) << 4; |
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switch (cmd) {
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case 0x00: /* Load single/multiple sector data unit into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_M() |
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if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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#if 0
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SETBUF_S()
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x13: /* Load single/multiple spare sector into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_S() |
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x80: /* Program single/multiple sector data unit from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_M() |
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if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
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#if 0
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SETBUF_S()
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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#endif
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|
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
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case 0x1a: /* Program single/multiple spare area sector from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
312 |
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SETBUF_S() |
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
316 |
|
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
322 |
break;
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case 0x1b: /* Copy-back program */ |
324 |
SETBUF_S() |
325 |
|
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
327 |
if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
329 |
|
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SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) |
331 |
if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
333 |
|
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/* TODO: spare areas */
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|
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
337 |
break;
|
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|
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case 0x23: /* Unlock NAND array block(s) */ |
340 |
s->intstatus |= ONEN_INT; |
341 |
|
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/* XXX the previous (?) area should be locked automatically */
|
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
344 |
if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD; |
346 |
break;
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347 |
} |
348 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
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break;
|
350 |
|
351 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
352 |
} |
353 |
break;
|
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case 0x27: /* Unlock All NAND array blocks */ |
355 |
s->intstatus |= ONEN_INT; |
356 |
|
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for (b = 0; b < s->blocks; b ++) { |
358 |
if (b >= s->blocks) {
|
359 |
s->status |= ONEN_ERR_CMD; |
360 |
break;
|
361 |
} |
362 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
363 |
break;
|
364 |
|
365 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
366 |
} |
367 |
break;
|
368 |
|
369 |
case 0x2a: /* Lock NAND array block(s) */ |
370 |
s->intstatus |= ONEN_INT; |
371 |
|
372 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
373 |
if (b >= s->blocks) {
|
374 |
s->status |= ONEN_ERR_CMD; |
375 |
break;
|
376 |
} |
377 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
378 |
break;
|
379 |
|
380 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; |
381 |
} |
382 |
break;
|
383 |
case 0x2c: /* Lock-tight NAND array block(s) */ |
384 |
s->intstatus |= ONEN_INT; |
385 |
|
386 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
387 |
if (b >= s->blocks) {
|
388 |
s->status |= ONEN_ERR_CMD; |
389 |
break;
|
390 |
} |
391 |
if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
392 |
continue;
|
393 |
|
394 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; |
395 |
} |
396 |
break;
|
397 |
|
398 |
case 0x71: /* Erase-Verify-Read */ |
399 |
s->intstatus |= ONEN_INT; |
400 |
break;
|
401 |
case 0x95: /* Multi-block erase */ |
402 |
qemu_irq_pulse(s->intr); |
403 |
/* Fall through. */
|
404 |
case 0x94: /* Block erase */ |
405 |
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
406 |
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) |
407 |
<< (BLOCK_SHIFT - 9);
|
408 |
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) |
409 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; |
410 |
|
411 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
412 |
break;
|
413 |
case 0xb0: /* Erase suspend */ |
414 |
break;
|
415 |
case 0x30: /* Erase resume */ |
416 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
417 |
break;
|
418 |
|
419 |
case 0xf0: /* Reset NAND Flash core */ |
420 |
onenand_reset(s, 0);
|
421 |
break;
|
422 |
case 0xf3: /* Reset OneNAND */ |
423 |
onenand_reset(s, 0);
|
424 |
break;
|
425 |
|
426 |
case 0x65: /* OTP Access */ |
427 |
s->intstatus |= ONEN_INT; |
428 |
s->bdrv_cur = NULL;
|
429 |
s->current = s->otp; |
430 |
s->secs_cur = 1 << (BLOCK_SHIFT - 9); |
431 |
s->addr[ONEN_BUF_BLOCK] = 0;
|
432 |
s->otpmode = 1;
|
433 |
break;
|
434 |
|
435 |
default:
|
436 |
s->status |= ONEN_ERR_CMD; |
437 |
s->intstatus |= ONEN_INT; |
438 |
fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
439 |
__FUNCTION__, cmd); |
440 |
} |
441 |
|
442 |
onenand_intr_update(s); |
443 |
} |
444 |
|
445 |
static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) |
446 |
{ |
447 |
OneNANDState *s = (OneNANDState *) opaque; |
448 |
int offset = addr >> s->shift;
|
449 |
|
450 |
switch (offset) {
|
451 |
case 0x0000 ... 0xc000: |
452 |
return lduw_le_p(s->boot[0] + addr); |
453 |
|
454 |
case 0xf000: /* Manufacturer ID */ |
455 |
return (s->id >> 16) & 0xff; |
456 |
case 0xf001: /* Device ID */ |
457 |
return (s->id >> 8) & 0xff; |
458 |
/* TODO: get the following values from a real chip! */
|
459 |
case 0xf002: /* Version ID */ |
460 |
return (s->id >> 0) & 0xff; |
461 |
case 0xf003: /* Data Buffer size */ |
462 |
return 1 << PAGE_SHIFT; |
463 |
case 0xf004: /* Boot Buffer size */ |
464 |
return 0x200; |
465 |
case 0xf005: /* Amount of buffers */ |
466 |
return 1 | (2 << 8); |
467 |
case 0xf006: /* Technology */ |
468 |
return 0; |
469 |
|
470 |
case 0xf100 ... 0xf107: /* Start addresses */ |
471 |
return s->addr[offset - 0xf100]; |
472 |
|
473 |
case 0xf200: /* Start buffer */ |
474 |
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
475 |
|
476 |
case 0xf220: /* Command */ |
477 |
return s->command;
|
478 |
case 0xf221: /* System Configuration 1 */ |
479 |
return s->config[0] & 0xffe0; |
480 |
case 0xf222: /* System Configuration 2 */ |
481 |
return s->config[1]; |
482 |
|
483 |
case 0xf240: /* Controller Status */ |
484 |
return s->status;
|
485 |
case 0xf241: /* Interrupt */ |
486 |
return s->intstatus;
|
487 |
case 0xf24c: /* Unlock Start Block Address */ |
488 |
return s->unladdr[0]; |
489 |
case 0xf24d: /* Unlock End Block Address */ |
490 |
return s->unladdr[1]; |
491 |
case 0xf24e: /* Write Protection Status */ |
492 |
return s->wpstatus;
|
493 |
|
494 |
case 0xff00: /* ECC Status */ |
495 |
return 0x00; |
496 |
case 0xff01: /* ECC Result of main area data */ |
497 |
case 0xff02: /* ECC Result of spare area data */ |
498 |
case 0xff03: /* ECC Result of main area data */ |
499 |
case 0xff04: /* ECC Result of spare area data */ |
500 |
hw_error("%s: imeplement ECC\n", __FUNCTION__);
|
501 |
return 0x0000; |
502 |
} |
503 |
|
504 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
505 |
__FUNCTION__, offset); |
506 |
return 0; |
507 |
} |
508 |
|
509 |
static void onenand_write(void *opaque, target_phys_addr_t addr, |
510 |
uint32_t value) |
511 |
{ |
512 |
OneNANDState *s = (OneNANDState *) opaque; |
513 |
int offset = addr >> s->shift;
|
514 |
int sec;
|
515 |
|
516 |
switch (offset) {
|
517 |
case 0x0000 ... 0x01ff: |
518 |
case 0x8000 ... 0x800f: |
519 |
if (s->cycle) {
|
520 |
s->cycle = 0;
|
521 |
|
522 |
if (value == 0x0000) { |
523 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
524 |
onenand_load_main(s, sec, |
525 |
1 << (PAGE_SHIFT - 9), s->data[0][0]); |
526 |
s->addr[ONEN_BUF_PAGE] += 4;
|
527 |
s->addr[ONEN_BUF_PAGE] &= 0xff;
|
528 |
} |
529 |
break;
|
530 |
} |
531 |
|
532 |
switch (value) {
|
533 |
case 0x00f0: /* Reset OneNAND */ |
534 |
onenand_reset(s, 0);
|
535 |
break;
|
536 |
|
537 |
case 0x00e0: /* Load Data into Buffer */ |
538 |
s->cycle = 1;
|
539 |
break;
|
540 |
|
541 |
case 0x0090: /* Read Identification Data */ |
542 |
memset(s->boot[0], 0, 3 << s->shift); |
543 |
s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff; |
544 |
s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff; |
545 |
s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
546 |
break;
|
547 |
|
548 |
default:
|
549 |
fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
|
550 |
__FUNCTION__, value); |
551 |
} |
552 |
break;
|
553 |
|
554 |
case 0xf100 ... 0xf107: /* Start addresses */ |
555 |
s->addr[offset - 0xf100] = value;
|
556 |
break;
|
557 |
|
558 |
case 0xf200: /* Start buffer */ |
559 |
s->bufaddr = (value >> 8) & 0xf; |
560 |
if (PAGE_SHIFT == 11) |
561 |
s->count = (value & 3) ?: 4; |
562 |
else if (PAGE_SHIFT == 10) |
563 |
s->count = (value & 1) ?: 2; |
564 |
break;
|
565 |
|
566 |
case 0xf220: /* Command */ |
567 |
if (s->intstatus & (1 << 15)) |
568 |
break;
|
569 |
s->command = value; |
570 |
onenand_command(s, s->command); |
571 |
break;
|
572 |
case 0xf221: /* System Configuration 1 */ |
573 |
s->config[0] = value;
|
574 |
onenand_intr_update(s); |
575 |
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); |
576 |
break;
|
577 |
case 0xf222: /* System Configuration 2 */ |
578 |
s->config[1] = value;
|
579 |
break;
|
580 |
|
581 |
case 0xf241: /* Interrupt */ |
582 |
s->intstatus &= value; |
583 |
if ((1 << 15) & ~s->intstatus) |
584 |
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | |
585 |
ONEN_ERR_PROG | ONEN_ERR_LOAD); |
586 |
onenand_intr_update(s); |
587 |
break;
|
588 |
case 0xf24c: /* Unlock Start Block Address */ |
589 |
s->unladdr[0] = value & (s->blocks - 1); |
590 |
/* For some reason we have to set the end address to by default
|
591 |
* be same as start because the software forgets to write anything
|
592 |
* in there. */
|
593 |
s->unladdr[1] = value & (s->blocks - 1); |
594 |
break;
|
595 |
case 0xf24d: /* Unlock End Block Address */ |
596 |
s->unladdr[1] = value & (s->blocks - 1); |
597 |
break;
|
598 |
|
599 |
default:
|
600 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
601 |
__FUNCTION__, offset); |
602 |
} |
603 |
} |
604 |
|
605 |
static CPUReadMemoryFunc * const onenand_readfn[] = { |
606 |
onenand_read, /* TODO */
|
607 |
onenand_read, |
608 |
onenand_read, |
609 |
}; |
610 |
|
611 |
static CPUWriteMemoryFunc * const onenand_writefn[] = { |
612 |
onenand_write, /* TODO */
|
613 |
onenand_write, |
614 |
onenand_write, |
615 |
}; |
616 |
|
617 |
void *onenand_init(uint32_t id, int regshift, qemu_irq irq) |
618 |
{ |
619 |
OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
|
620 |
DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); |
621 |
uint32_t size = 1 << (24 + ((id >> 12) & 7)); |
622 |
void *ram;
|
623 |
|
624 |
s->shift = regshift; |
625 |
s->intr = irq; |
626 |
s->rdy = NULL;
|
627 |
s->id = id; |
628 |
s->blocks = size >> BLOCK_SHIFT; |
629 |
s->secs = size >> 9;
|
630 |
s->blockwp = qemu_malloc(s->blocks); |
631 |
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; |
632 |
s->iomemtype = cpu_register_io_memory(onenand_readfn, |
633 |
onenand_writefn, s); |
634 |
if (!dinfo)
|
635 |
s->image = memset(qemu_malloc(size + (size >> 5)),
|
636 |
0xff, size + (size >> 5)); |
637 |
else
|
638 |
s->bdrv = dinfo->bdrv; |
639 |
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), |
640 |
0xff, (64 + 2) << PAGE_SHIFT); |
641 |
s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift); |
642 |
ram = qemu_get_ram_ptr(s->ram); |
643 |
s->boot[0] = ram + (0x0000 << s->shift); |
644 |
s->boot[1] = ram + (0x8000 << s->shift); |
645 |
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); |
646 |
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); |
647 |
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); |
648 |
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); |
649 |
|
650 |
onenand_reset(s, 1);
|
651 |
|
652 |
return s;
|
653 |
} |
654 |
|
655 |
void *onenand_raw_otp(void *opaque) |
656 |
{ |
657 |
OneNANDState *s = (OneNANDState *) opaque; |
658 |
|
659 |
return s->otp;
|
660 |
} |