Revision 18b21a2f
b/target-ppc/cpu.h | ||
---|---|---|
561 | 561 |
/* XER */ |
562 | 562 |
target_ulong xer; |
563 | 563 |
/* Reservation address */ |
564 |
target_ulong reserve; |
|
564 |
target_ulong reserve_addr; |
|
565 |
/* Reservation value */ |
|
566 |
target_ulong reserve_val; |
|
565 | 567 |
|
566 | 568 |
/* Those ones are used in supervisor mode only */ |
567 | 569 |
/* machine state register */ |
b/target-ppc/helper.c | ||
---|---|---|
2805 | 2805 |
env->msr |= (1ULL << MSR_SF); |
2806 | 2806 |
#endif |
2807 | 2807 |
hreg_compute_hflags(env); |
2808 |
env->reserve = (target_ulong)-1ULL; |
|
2808 |
env->reserve_addr = (target_ulong)-1ULL;
|
|
2809 | 2809 |
/* Be sure no exception or interrupt is pending */ |
2810 | 2810 |
env->pending_interrupts = 0; |
2811 | 2811 |
env->exception_index = POWERPC_EXCP_NONE; |
b/target-ppc/machine.c | ||
---|---|---|
20 | 20 |
for (i = 0; i < 8; i++) |
21 | 21 |
qemu_put_be32s(f, &env->crf[i]); |
22 | 22 |
qemu_put_betls(f, &env->xer); |
23 |
qemu_put_betls(f, &env->reserve); |
|
23 |
qemu_put_betls(f, &env->reserve_addr);
|
|
24 | 24 |
qemu_put_betls(f, &env->msr); |
25 | 25 |
for (i = 0; i < 4; i++) |
26 | 26 |
qemu_put_betls(f, &env->tgpr[i]); |
... | ... | |
107 | 107 |
for (i = 0; i < 8; i++) |
108 | 108 |
qemu_get_be32s(f, &env->crf[i]); |
109 | 109 |
qemu_get_betls(f, &env->xer); |
110 |
qemu_get_betls(f, &env->reserve); |
|
110 |
qemu_get_betls(f, &env->reserve_addr);
|
|
111 | 111 |
qemu_get_betls(f, &env->msr); |
112 | 112 |
for (i = 0; i < 4; i++) |
113 | 113 |
qemu_get_betls(f, &env->tgpr[i]); |
b/target-ppc/op_helper.c | ||
---|---|---|
329 | 329 |
for (i = 0 ; i < dcache_line_size ; i += 4) { |
330 | 330 |
stl(addr + i , 0); |
331 | 331 |
} |
332 |
if (env->reserve == addr) |
|
333 |
env->reserve = (target_ulong)-1ULL; |
|
332 |
if (env->reserve_addr == addr)
|
|
333 |
env->reserve_addr = (target_ulong)-1ULL;
|
|
334 | 334 |
} |
335 | 335 |
|
336 | 336 |
void helper_dcbz(target_ulong addr) |
b/target-ppc/translate.c | ||
---|---|---|
158 | 158 |
offsetof(CPUState, xer), "xer"); |
159 | 159 |
|
160 | 160 |
cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
161 |
offsetof(CPUState, reserve), "reserve"); |
|
161 |
offsetof(CPUState, reserve_addr), |
|
162 |
"reserve_addr"); |
|
162 | 163 |
|
163 | 164 |
cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
164 | 165 |
offsetof(CPUState, fpscr), "fpscr"); |
... | ... | |
3006 | 3007 |
static void gen_lwarx(DisasContext *ctx) |
3007 | 3008 |
{ |
3008 | 3009 |
TCGv t0; |
3010 |
TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
|
3009 | 3011 |
gen_set_access_type(ctx, ACCESS_RES); |
3010 | 3012 |
t0 = tcg_temp_local_new(); |
3011 | 3013 |
gen_addr_reg_index(ctx, t0); |
3012 | 3014 |
gen_check_align(ctx, t0, 0x03); |
3013 |
gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
|
|
3015 |
gen_qemu_ld32u(ctx, gpr, t0);
|
|
3014 | 3016 |
tcg_gen_mov_tl(cpu_reserve, t0); |
3017 |
tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
|
3015 | 3018 |
tcg_temp_free(t0); |
3016 | 3019 |
} |
3017 | 3020 |
|
... | ... | |
3041 | 3044 |
static void gen_ldarx(DisasContext *ctx) |
3042 | 3045 |
{ |
3043 | 3046 |
TCGv t0; |
3047 |
TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
|
3044 | 3048 |
gen_set_access_type(ctx, ACCESS_RES); |
3045 | 3049 |
t0 = tcg_temp_local_new(); |
3046 | 3050 |
gen_addr_reg_index(ctx, t0); |
3047 | 3051 |
gen_check_align(ctx, t0, 0x07); |
3048 |
gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
|
|
3052 |
gen_qemu_ld64(ctx, gpr, t0);
|
|
3049 | 3053 |
tcg_gen_mov_tl(cpu_reserve, t0); |
3054 |
tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
|
3050 | 3055 |
tcg_temp_free(t0); |
3051 | 3056 |
} |
3052 | 3057 |
|
... | ... | |
8834 | 8839 |
a = 'E'; |
8835 | 8840 |
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
8836 | 8841 |
} |
8837 |
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); |
|
8842 |
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve_addr);
|
|
8838 | 8843 |
for (i = 0; i < 32; i++) { |
8839 | 8844 |
if ((i & (RFPL - 1)) == 0) |
8840 | 8845 |
cpu_fprintf(f, "FPR%02d", i); |
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