56 |
56 |
struct tm current_tm;
|
57 |
57 |
qemu_irq irq;
|
58 |
58 |
target_phys_addr_t base;
|
|
59 |
int it_shift;
|
59 |
60 |
/* periodic timer */
|
60 |
61 |
QEMUTimer *periodic_timer;
|
61 |
62 |
int64_t next_periodic_time;
|
... | ... | |
492 |
493 |
{
|
493 |
494 |
RTCState *s = opaque;
|
494 |
495 |
|
495 |
|
return cmos_ioport_read(s, addr - s->base) & 0xFF;
|
|
496 |
return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
|
496 |
497 |
}
|
497 |
498 |
|
498 |
499 |
void cmos_mm_writeb (void *opaque,
|
... | ... | |
500 |
501 |
{
|
501 |
502 |
RTCState *s = opaque;
|
502 |
503 |
|
503 |
|
cmos_ioport_write(s, addr - s->base, value & 0xFF);
|
|
504 |
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
|
504 |
505 |
}
|
505 |
506 |
|
506 |
507 |
uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
|
507 |
508 |
{
|
508 |
509 |
RTCState *s = opaque;
|
|
510 |
uint32_t val;
|
509 |
511 |
|
510 |
|
return cmos_ioport_read(s, addr - s->base) & 0xFFFF;
|
|
512 |
val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
|
|
513 |
#ifdef TARGET_WORDS_BIGENDIAN
|
|
514 |
val = bswap16(val);
|
|
515 |
#endif
|
|
516 |
return val;
|
511 |
517 |
}
|
512 |
518 |
|
513 |
519 |
void cmos_mm_writew (void *opaque,
|
514 |
520 |
target_phys_addr_t addr, uint32_t value)
|
515 |
521 |
{
|
516 |
522 |
RTCState *s = opaque;
|
517 |
|
|
518 |
|
cmos_ioport_write(s, addr - s->base, value & 0xFFFF);
|
|
523 |
#ifdef TARGET_WORDS_BIGENDIAN
|
|
524 |
value = bswap16(value);
|
|
525 |
#endif
|
|
526 |
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
|
519 |
527 |
}
|
520 |
528 |
|
521 |
529 |
uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
|
522 |
530 |
{
|
523 |
531 |
RTCState *s = opaque;
|
|
532 |
uint32_t val;
|
524 |
533 |
|
525 |
|
return cmos_ioport_read(s, addr - s->base);
|
|
534 |
val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
|
|
535 |
#ifdef TARGET_WORDS_BIGENDIAN
|
|
536 |
val = bswap32(val);
|
|
537 |
#endif
|
|
538 |
return val;
|
526 |
539 |
}
|
527 |
540 |
|
528 |
541 |
void cmos_mm_writel (void *opaque,
|
529 |
542 |
target_phys_addr_t addr, uint32_t value)
|
530 |
543 |
{
|
531 |
544 |
RTCState *s = opaque;
|
532 |
|
|
533 |
|
cmos_ioport_write(s, addr - s->base, value);
|
|
545 |
#ifdef TARGET_WORDS_BIGENDIAN
|
|
546 |
value = bswap32(value);
|
|
547 |
#endif
|
|
548 |
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
|
534 |
549 |
}
|
535 |
550 |
|
536 |
551 |
static CPUReadMemoryFunc *rtc_mm_read[] = {
|
... | ... | |
545 |
560 |
&cmos_mm_writel,
|
546 |
561 |
};
|
547 |
562 |
|
548 |
|
RTCState *rtc_mm_init(target_phys_addr_t base, qemu_irq irq)
|
|
563 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
|
549 |
564 |
{
|
550 |
565 |
RTCState *s;
|
551 |
566 |
int io_memory;
|
... | ... | |
574 |
589 |
qemu_mod_timer(s->second_timer2, s->next_second_time);
|
575 |
590 |
|
576 |
591 |
io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
|
577 |
|
cpu_register_physical_memory(base, 2, io_memory);
|
|
592 |
cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
578 |
593 |
|
579 |
594 |
register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
|
580 |
595 |
return s;
|