root / hw / sh_pci.c @ 18e08a55
History | View | Annotate | Download (5.7 kB)
1 |
/*
|
---|---|
2 |
* SuperH on-chip PCIC emulation.
|
3 |
*
|
4 |
* Copyright (c) 2008 Takashi YOSHII
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "hw.h" |
25 |
#include "sh.h" |
26 |
#include "pci.h" |
27 |
#include "sh_pci.h" |
28 |
#include "bswap.h" |
29 |
|
30 |
typedef struct { |
31 |
PCIBus *bus; |
32 |
PCIDevice *dev; |
33 |
uint32_t par; |
34 |
uint32_t mbr; |
35 |
uint32_t iobr; |
36 |
} SHPCIC; |
37 |
|
38 |
static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) |
39 |
{ |
40 |
SHPCIC *pcic = p; |
41 |
switch(addr) {
|
42 |
case 0 ... 0xfc: |
43 |
cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); |
44 |
break;
|
45 |
case 0x1c0: |
46 |
pcic->par = val; |
47 |
break;
|
48 |
case 0x1c4: |
49 |
pcic->mbr = val; |
50 |
break;
|
51 |
case 0x1c8: |
52 |
pcic->iobr = val; |
53 |
break;
|
54 |
case 0x220: |
55 |
pci_data_write(pcic->bus, pcic->par, val, 4);
|
56 |
break;
|
57 |
} |
58 |
} |
59 |
|
60 |
static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) |
61 |
{ |
62 |
SHPCIC *pcic = p; |
63 |
switch(addr) {
|
64 |
case 0 ... 0xfc: |
65 |
return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
|
66 |
case 0x1c0: |
67 |
return pcic->par;
|
68 |
case 0x220: |
69 |
return pci_data_read(pcic->bus, pcic->par, 4); |
70 |
} |
71 |
return 0; |
72 |
} |
73 |
|
74 |
static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr, |
75 |
uint32_t val, int size)
|
76 |
{ |
77 |
pci_data_write(pcic->bus, addr + pcic->mbr, val, size); |
78 |
} |
79 |
|
80 |
static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
|
81 |
int size)
|
82 |
{ |
83 |
return pci_data_read(pcic->bus, addr + pcic->mbr, size);
|
84 |
} |
85 |
|
86 |
static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val) |
87 |
{ |
88 |
sh_pci_data_write(p, addr, val, 1);
|
89 |
} |
90 |
|
91 |
static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val) |
92 |
{ |
93 |
sh_pci_data_write(p, addr, val, 2);
|
94 |
} |
95 |
|
96 |
static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val) |
97 |
{ |
98 |
sh_pci_data_write(p, addr, val, 4);
|
99 |
} |
100 |
|
101 |
static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr) |
102 |
{ |
103 |
return sh_pci_mem_read(p, addr, 1); |
104 |
} |
105 |
|
106 |
static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr) |
107 |
{ |
108 |
return sh_pci_mem_read(p, addr, 2); |
109 |
} |
110 |
|
111 |
static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr) |
112 |
{ |
113 |
return sh_pci_mem_read(p, addr, 4); |
114 |
} |
115 |
|
116 |
static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr) |
117 |
{ |
118 |
return addr + pcic->iobr;
|
119 |
} |
120 |
|
121 |
static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val) |
122 |
{ |
123 |
cpu_outb(sh_pci_addr2port(p, addr), val); |
124 |
} |
125 |
|
126 |
static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val) |
127 |
{ |
128 |
cpu_outw(sh_pci_addr2port(p, addr), val); |
129 |
} |
130 |
|
131 |
static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val) |
132 |
{ |
133 |
cpu_outl(sh_pci_addr2port(p, addr), val); |
134 |
} |
135 |
|
136 |
static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr) |
137 |
{ |
138 |
return cpu_inb(sh_pci_addr2port(p, addr));
|
139 |
} |
140 |
|
141 |
static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr) |
142 |
{ |
143 |
return cpu_inw(sh_pci_addr2port(p, addr));
|
144 |
} |
145 |
|
146 |
static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr) |
147 |
{ |
148 |
return cpu_inl(sh_pci_addr2port(p, addr));
|
149 |
} |
150 |
|
151 |
typedef struct { |
152 |
CPUReadMemoryFunc * const r[3]; |
153 |
CPUWriteMemoryFunc * const w[3]; |
154 |
} MemOp; |
155 |
|
156 |
static MemOp sh_pci_reg = {
|
157 |
{ NULL, NULL, sh_pci_reg_read }, |
158 |
{ NULL, NULL, sh_pci_reg_write }, |
159 |
}; |
160 |
|
161 |
static MemOp sh_pci_mem = {
|
162 |
{ sh_pci_readb, sh_pci_readw, sh_pci_readl }, |
163 |
{ sh_pci_writeb, sh_pci_writew, sh_pci_writel }, |
164 |
}; |
165 |
|
166 |
static MemOp sh_pci_iop = {
|
167 |
{ sh_pci_inb, sh_pci_inw, sh_pci_inl }, |
168 |
{ sh_pci_outb, sh_pci_outw, sh_pci_outl }, |
169 |
}; |
170 |
|
171 |
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
172 |
void *opaque, int devfn_min, int nirq) |
173 |
{ |
174 |
SHPCIC *p; |
175 |
int mem, reg, iop;
|
176 |
|
177 |
p = qemu_mallocz(sizeof(SHPCIC));
|
178 |
p->bus = pci_register_bus(NULL, "pci", |
179 |
set_irq, map_irq, opaque, devfn_min, nirq); |
180 |
|
181 |
p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), |
182 |
-1, NULL, NULL); |
183 |
reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p); |
184 |
iop = cpu_register_io_memory(sh_pci_iop.r, sh_pci_iop.w, p); |
185 |
mem = cpu_register_io_memory(sh_pci_mem.r, sh_pci_mem.w, p); |
186 |
cpu_register_physical_memory(0x1e200000, 0x224, reg); |
187 |
cpu_register_physical_memory(0x1e240000, 0x40000, iop); |
188 |
cpu_register_physical_memory(0x1d000000, 0x1000000, mem); |
189 |
cpu_register_physical_memory(0xfe200000, 0x224, reg); |
190 |
cpu_register_physical_memory(0xfe240000, 0x40000, iop); |
191 |
cpu_register_physical_memory(0xfd000000, 0x1000000, mem); |
192 |
|
193 |
pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI); |
194 |
pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R); |
195 |
p->dev->config[0x04] = 0x80; |
196 |
p->dev->config[0x05] = 0x00; |
197 |
p->dev->config[0x06] = 0x90; |
198 |
p->dev->config[0x07] = 0x02; |
199 |
|
200 |
return p->bus;
|
201 |
} |