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1
/*
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 * QEMU GT64120 PCI host
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 *
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 * Copyright (c) 2006,2007 Aurelien Jarno
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h"
29

    
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//#define DEBUG
31

    
32
#ifdef DEBUG
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#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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#define GT_REGS                        (0x1000 >> 2)
39

    
40
/* CPU Configuration */
41
#define GT_CPU                    (0x000 >> 2)
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#define GT_MULTI                    (0x120 >> 2)
43

    
44
/* CPU Address Decode */
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#define GT_SCS10LD                    (0x008 >> 2)
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#define GT_SCS10HD                    (0x010 >> 2)
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#define GT_SCS32LD                    (0x018 >> 2)
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#define GT_SCS32HD                    (0x020 >> 2)
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#define GT_CS20LD                    (0x028 >> 2)
50
#define GT_CS20HD                    (0x030 >> 2)
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#define GT_CS3BOOTLD            (0x038 >> 2)
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#define GT_CS3BOOTHD            (0x040 >> 2)
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#define GT_PCI0IOLD                    (0x048 >> 2)
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#define GT_PCI0IOHD                    (0x050 >> 2)
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#define GT_PCI0M0LD                    (0x058 >> 2)
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#define GT_PCI0M0HD                    (0x060 >> 2)
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#define GT_PCI0M1LD                    (0x080 >> 2)
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#define GT_PCI0M1HD                    (0x088 >> 2)
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#define GT_PCI1IOLD                    (0x090 >> 2)
60
#define GT_PCI1IOHD                    (0x098 >> 2)
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#define GT_PCI1M0LD                    (0x0a0 >> 2)
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#define GT_PCI1M0HD                    (0x0a8 >> 2)
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#define GT_PCI1M1LD                    (0x0b0 >> 2)
64
#define GT_PCI1M1HD                    (0x0b8 >> 2)
65
#define GT_ISD                    (0x068 >> 2)
66

    
67
#define GT_SCS10AR                    (0x0d0 >> 2)
68
#define GT_SCS32AR                    (0x0d8 >> 2)
69
#define GT_CS20R                    (0x0e0 >> 2)
70
#define GT_CS3BOOTR                    (0x0e8 >> 2)
71

    
72
#define GT_PCI0IOREMAP            (0x0f0 >> 2)
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#define GT_PCI0M0REMAP            (0x0f8 >> 2)
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#define GT_PCI0M1REMAP            (0x100 >> 2)
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#define GT_PCI1IOREMAP            (0x108 >> 2)
76
#define GT_PCI1M0REMAP            (0x110 >> 2)
77
#define GT_PCI1M1REMAP            (0x118 >> 2)
78

    
79
/* CPU Error Report */
80
#define GT_CPUERR_ADDRLO            (0x070 >> 2)
81
#define GT_CPUERR_ADDRHI            (0x078 >> 2)
82
#define GT_CPUERR_DATALO            (0x128 >> 2)                /* GT-64120A only  */
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#define GT_CPUERR_DATAHI            (0x130 >> 2)                /* GT-64120A only  */
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#define GT_CPUERR_PARITY            (0x138 >> 2)                /* GT-64120A only  */
85

    
86
/* CPU Sync Barrier */
87
#define GT_PCI0SYNC                    (0x0c0 >> 2)
88
#define GT_PCI1SYNC                    (0x0c8 >> 2)
89

    
90
/* SDRAM and Device Address Decode */
91
#define GT_SCS0LD                    (0x400 >> 2)
92
#define GT_SCS0HD                    (0x404 >> 2)
93
#define GT_SCS1LD                    (0x408 >> 2)
94
#define GT_SCS1HD                    (0x40c >> 2)
95
#define GT_SCS2LD                    (0x410 >> 2)
96
#define GT_SCS2HD                    (0x414 >> 2)
97
#define GT_SCS3LD                    (0x418 >> 2)
98
#define GT_SCS3HD                    (0x41c >> 2)
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#define GT_CS0LD                    (0x420 >> 2)
100
#define GT_CS0HD                    (0x424 >> 2)
101
#define GT_CS1LD                    (0x428 >> 2)
102
#define GT_CS1HD                    (0x42c >> 2)
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#define GT_CS2LD                    (0x430 >> 2)
104
#define GT_CS2HD                    (0x434 >> 2)
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#define GT_CS3LD                    (0x438 >> 2)
106
#define GT_CS3HD                    (0x43c >> 2)
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#define GT_BOOTLD                    (0x440 >> 2)
108
#define GT_BOOTHD                    (0x444 >> 2)
109
#define GT_ADERR                    (0x470 >> 2)
110

    
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/* SDRAM Configuration */
112
#define GT_SDRAM_CFG            (0x448 >> 2)
113
#define GT_SDRAM_OPMODE            (0x474 >> 2)
114
#define GT_SDRAM_BM                    (0x478 >> 2)
115
#define GT_SDRAM_ADDRDECODE            (0x47c >> 2)
116

    
117
/* SDRAM Parameters */
118
#define GT_SDRAM_B0                    (0x44c >> 2)
119
#define GT_SDRAM_B1                    (0x450 >> 2)
120
#define GT_SDRAM_B2                    (0x454 >> 2)
121
#define GT_SDRAM_B3                    (0x458 >> 2)
122

    
123
/* Device Parameters */
124
#define GT_DEV_B0                    (0x45c >> 2)
125
#define GT_DEV_B1                    (0x460 >> 2)
126
#define GT_DEV_B2                    (0x464 >> 2)
127
#define GT_DEV_B3                    (0x468 >> 2)
128
#define GT_DEV_BOOT                    (0x46c >> 2)
129

    
130
/* ECC */
131
#define GT_ECC_ERRDATALO        (0x480 >> 2)                /* GT-64120A only  */
132
#define GT_ECC_ERRDATAHI        (0x484 >> 2)                /* GT-64120A only  */
133
#define GT_ECC_MEM                (0x488 >> 2)                /* GT-64120A only  */
134
#define GT_ECC_CALC                (0x48c >> 2)                /* GT-64120A only  */
135
#define GT_ECC_ERRADDR                (0x490 >> 2)                /* GT-64120A only  */
136

    
137
/* DMA Record */
138
#define GT_DMA0_CNT                    (0x800 >> 2)
139
#define GT_DMA1_CNT                    (0x804 >> 2)
140
#define GT_DMA2_CNT                    (0x808 >> 2)
141
#define GT_DMA3_CNT                    (0x80c >> 2)
142
#define GT_DMA0_SA                    (0x810 >> 2)
143
#define GT_DMA1_SA                    (0x814 >> 2)
144
#define GT_DMA2_SA                    (0x818 >> 2)
145
#define GT_DMA3_SA                    (0x81c >> 2)
146
#define GT_DMA0_DA                    (0x820 >> 2)
147
#define GT_DMA1_DA                    (0x824 >> 2)
148
#define GT_DMA2_DA                    (0x828 >> 2)
149
#define GT_DMA3_DA                    (0x82c >> 2)
150
#define GT_DMA0_NEXT            (0x830 >> 2)
151
#define GT_DMA1_NEXT            (0x834 >> 2)
152
#define GT_DMA2_NEXT            (0x838 >> 2)
153
#define GT_DMA3_NEXT            (0x83c >> 2)
154
#define GT_DMA0_CUR                    (0x870 >> 2)
155
#define GT_DMA1_CUR                    (0x874 >> 2)
156
#define GT_DMA2_CUR                    (0x878 >> 2)
157
#define GT_DMA3_CUR                    (0x87c >> 2)
158

    
159
/* DMA Channel Control */
160
#define GT_DMA0_CTRL            (0x840 >> 2)
161
#define GT_DMA1_CTRL            (0x844 >> 2)
162
#define GT_DMA2_CTRL            (0x848 >> 2)
163
#define GT_DMA3_CTRL            (0x84c >> 2)
164

    
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/* DMA Arbiter */
166
#define GT_DMA_ARB                    (0x860 >> 2)
167

    
168
/* Timer/Counter */
169
#define GT_TC0                    (0x850 >> 2)
170
#define GT_TC1                    (0x854 >> 2)
171
#define GT_TC2                    (0x858 >> 2)
172
#define GT_TC3                    (0x85c >> 2)
173
#define GT_TC_CONTROL            (0x864 >> 2)
174

    
175
/* PCI Internal */
176
#define GT_PCI0_CMD                    (0xc00 >> 2)
177
#define GT_PCI0_TOR                    (0xc04 >> 2)
178
#define GT_PCI0_BS_SCS10            (0xc08 >> 2)
179
#define GT_PCI0_BS_SCS32            (0xc0c >> 2)
180
#define GT_PCI0_BS_CS20            (0xc10 >> 2)
181
#define GT_PCI0_BS_CS3BT            (0xc14 >> 2)
182
#define GT_PCI1_IACK            (0xc30 >> 2)
183
#define GT_PCI0_IACK            (0xc34 >> 2)
184
#define GT_PCI0_BARE            (0xc3c >> 2)
185
#define GT_PCI0_PREFMBR            (0xc40 >> 2)
186
#define GT_PCI0_SCS10_BAR            (0xc48 >> 2)
187
#define GT_PCI0_SCS32_BAR            (0xc4c >> 2)
188
#define GT_PCI0_CS20_BAR            (0xc50 >> 2)
189
#define GT_PCI0_CS3BT_BAR            (0xc54 >> 2)
190
#define GT_PCI0_SSCS10_BAR            (0xc58 >> 2)
191
#define GT_PCI0_SSCS32_BAR            (0xc5c >> 2)
192
#define GT_PCI0_SCS3BT_BAR            (0xc64 >> 2)
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#define GT_PCI1_CMD                    (0xc80 >> 2)
194
#define GT_PCI1_TOR                    (0xc84 >> 2)
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#define GT_PCI1_BS_SCS10            (0xc88 >> 2)
196
#define GT_PCI1_BS_SCS32            (0xc8c >> 2)
197
#define GT_PCI1_BS_CS20            (0xc90 >> 2)
198
#define GT_PCI1_BS_CS3BT            (0xc94 >> 2)
199
#define GT_PCI1_BARE            (0xcbc >> 2)
200
#define GT_PCI1_PREFMBR            (0xcc0 >> 2)
201
#define GT_PCI1_SCS10_BAR            (0xcc8 >> 2)
202
#define GT_PCI1_SCS32_BAR            (0xccc >> 2)
203
#define GT_PCI1_CS20_BAR            (0xcd0 >> 2)
204
#define GT_PCI1_CS3BT_BAR            (0xcd4 >> 2)
205
#define GT_PCI1_SSCS10_BAR            (0xcd8 >> 2)
206
#define GT_PCI1_SSCS32_BAR            (0xcdc >> 2)
207
#define GT_PCI1_SCS3BT_BAR            (0xce4 >> 2)
208
#define GT_PCI1_CFGADDR            (0xcf0 >> 2)
209
#define GT_PCI1_CFGDATA            (0xcf4 >> 2)
210
#define GT_PCI0_CFGADDR            (0xcf8 >> 2)
211
#define GT_PCI0_CFGDATA            (0xcfc >> 2)
212

    
213
/* Interrupts */
214
#define GT_INTRCAUSE            (0xc18 >> 2)
215
#define GT_INTRMASK                    (0xc1c >> 2)
216
#define GT_PCI0_ICMASK            (0xc24 >> 2)
217
#define GT_PCI0_SERR0MASK            (0xc28 >> 2)
218
#define GT_CPU_INTSEL            (0xc70 >> 2)
219
#define GT_PCI0_INTSEL            (0xc74 >> 2)
220
#define GT_HINTRCAUSE            (0xc98 >> 2)
221
#define GT_HINTRMASK            (0xc9c >> 2)
222
#define GT_PCI0_HICMASK            (0xca4 >> 2)
223
#define GT_PCI1_SERR1MASK            (0xca8 >> 2)
224

    
225

    
226
typedef PCIHostState GT64120PCIState;
227

    
228
#define PCI_MAPPING_ENTRY(regname)            \
229
    target_phys_addr_t regname ##_start;      \
230
    target_phys_addr_t regname ##_length;     \
231
    int regname ##_handle
232

    
233
typedef struct GT64120State {
234
    GT64120PCIState *pci;
235
    uint32_t regs[GT_REGS];
236
    PCI_MAPPING_ENTRY(PCI0IO);
237
    PCI_MAPPING_ENTRY(ISD);
238
} GT64120State;
239

    
240
/* Adjust range to avoid touching space which isn't mappable via PCI */
241
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
242
                                    0x1fc00000 - 0x1fd00000  */
243
static void check_reserved_space (target_phys_addr_t *start,
244
                                  target_phys_addr_t *length)
245
{
246
    target_phys_addr_t begin = *start;
247
    target_phys_addr_t end = *start + *length;
248

    
249
    if (end >= 0x1e000000LL && end < 0x1f100000LL)
250
        end = 0x1e000000LL;
251
    if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
252
        begin = 0x1f100000LL;
253
    if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
254
        end = 0x1fc00000LL;
255
    if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
256
        begin = 0x1fd00000LL;
257
    /* XXX: This is broken when a reserved range splits the requested range */
258
    if (end >= 0x1f100000LL && begin < 0x1e000000LL)
259
        end = 0x1e000000LL;
260
    if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
261
        end = 0x1fc00000LL;
262

    
263
    *start = begin;
264
    *length = end - begin;
265
}
266

    
267
static void gt64120_isd_mapping(GT64120State *s)
268
{
269
    target_phys_addr_t start = s->regs[GT_ISD] << 21;
270
    target_phys_addr_t length = 0x1000;
271

    
272
    if (s->ISD_length)
273
        cpu_register_physical_memory(s->ISD_start, s->ISD_length,
274
                                     IO_MEM_UNASSIGNED);
275
    check_reserved_space(&start, &length);
276
    length = 0x1000;
277
    /* Map new address */
278
    dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
279
            length, start, s->ISD_handle);
280
    s->ISD_start = start;
281
    s->ISD_length = length;
282
    cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
283
}
284

    
285
static void gt64120_pci_mapping(GT64120State *s)
286
{
287
    /* Update IO mapping */
288
    if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
289
    {
290
      /* Unmap old IO address */
291
      if (s->PCI0IO_length)
292
      {
293
        cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
294
      }
295
      /* Map new IO address */
296
      s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
297
      s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
298
      isa_mem_base = s->PCI0IO_start;
299
      isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
300
    }
301
}
302

    
303
static void gt64120_writel (void *opaque, target_phys_addr_t addr,
304
                            uint32_t val)
305
{
306
    GT64120State *s = opaque;
307
    uint32_t saddr;
308

    
309
    if (!(s->regs[GT_PCI0_CMD] & 1))
310
        val = bswap32(val);
311

    
312
    saddr = (addr & 0xfff) >> 2;
313
    switch (saddr) {
314

    
315
    /* CPU Configuration */
316
    case GT_CPU:
317
        s->regs[GT_CPU] = val;
318
        break;
319
    case GT_MULTI:
320
        /* Read-only register as only one GT64xxx is present on the CPU bus */
321
        break;
322

    
323
    /* CPU Address Decode */
324
    case GT_PCI0IOLD:
325
        s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
326
        s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
327
        gt64120_pci_mapping(s);
328
        break;
329
    case GT_PCI0M0LD:
330
        s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
331
        s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
332
        break;
333
    case GT_PCI0M1LD:
334
        s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
335
        s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
336
        break;
337
    case GT_PCI1IOLD:
338
        s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
339
        s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
340
        break;
341
    case GT_PCI1M0LD:
342
        s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
343
        s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
344
        break;
345
    case GT_PCI1M1LD:
346
        s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
347
        s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
348
        break;
349
    case GT_PCI0IOHD:
350
        s->regs[saddr] = val & 0x0000007f;
351
        gt64120_pci_mapping(s);
352
        break;
353
    case GT_PCI0M0HD:
354
    case GT_PCI0M1HD:
355
    case GT_PCI1IOHD:
356
    case GT_PCI1M0HD:
357
    case GT_PCI1M1HD:
358
        s->regs[saddr] = val & 0x0000007f;
359
        break;
360
    case GT_ISD:
361
        s->regs[saddr] = val & 0x00007fff;
362
        gt64120_isd_mapping(s);
363
        break;
364

    
365
    case GT_PCI0IOREMAP:
366
    case GT_PCI0M0REMAP:
367
    case GT_PCI0M1REMAP:
368
    case GT_PCI1IOREMAP:
369
    case GT_PCI1M0REMAP:
370
    case GT_PCI1M1REMAP:
371
        s->regs[saddr] = val & 0x000007ff;
372
        break;
373

    
374
    /* CPU Error Report */
375
    case GT_CPUERR_ADDRLO:
376
    case GT_CPUERR_ADDRHI:
377
    case GT_CPUERR_DATALO:
378
    case GT_CPUERR_DATAHI:
379
    case GT_CPUERR_PARITY:
380
        /* Read-only registers, do nothing */
381
        break;
382

    
383
    /* CPU Sync Barrier */
384
    case GT_PCI0SYNC:
385
    case GT_PCI1SYNC:
386
        /* Read-only registers, do nothing */
387
        break;
388

    
389
    /* SDRAM and Device Address Decode */
390
    case GT_SCS0LD:
391
    case GT_SCS0HD:
392
    case GT_SCS1LD:
393
    case GT_SCS1HD:
394
    case GT_SCS2LD:
395
    case GT_SCS2HD:
396
    case GT_SCS3LD:
397
    case GT_SCS3HD:
398
    case GT_CS0LD:
399
    case GT_CS0HD:
400
    case GT_CS1LD:
401
    case GT_CS1HD:
402
    case GT_CS2LD:
403
    case GT_CS2HD:
404
    case GT_CS3LD:
405
    case GT_CS3HD:
406
    case GT_BOOTLD:
407
    case GT_BOOTHD:
408
    case GT_ADERR:
409
    /* SDRAM Configuration */
410
    case GT_SDRAM_CFG:
411
    case GT_SDRAM_OPMODE:
412
    case GT_SDRAM_BM:
413
    case GT_SDRAM_ADDRDECODE:
414
        /* Accept and ignore SDRAM interleave configuration */
415
        s->regs[saddr] = val;
416
        break;
417

    
418
    /* Device Parameters */
419
    case GT_DEV_B0:
420
    case GT_DEV_B1:
421
    case GT_DEV_B2:
422
    case GT_DEV_B3:
423
    case GT_DEV_BOOT:
424
        /* Not implemented */
425
        dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
426
        break;
427

    
428
    /* ECC */
429
    case GT_ECC_ERRDATALO:
430
    case GT_ECC_ERRDATAHI:
431
    case GT_ECC_MEM:
432
    case GT_ECC_CALC:
433
    case GT_ECC_ERRADDR:
434
        /* Read-only registers, do nothing */
435
        break;
436

    
437
    /* DMA Record */
438
    case GT_DMA0_CNT:
439
    case GT_DMA1_CNT:
440
    case GT_DMA2_CNT:
441
    case GT_DMA3_CNT:
442
    case GT_DMA0_SA:
443
    case GT_DMA1_SA:
444
    case GT_DMA2_SA:
445
    case GT_DMA3_SA:
446
    case GT_DMA0_DA:
447
    case GT_DMA1_DA:
448
    case GT_DMA2_DA:
449
    case GT_DMA3_DA:
450
    case GT_DMA0_NEXT:
451
    case GT_DMA1_NEXT:
452
    case GT_DMA2_NEXT:
453
    case GT_DMA3_NEXT:
454
    case GT_DMA0_CUR:
455
    case GT_DMA1_CUR:
456
    case GT_DMA2_CUR:
457
    case GT_DMA3_CUR:
458
        /* Not implemented */
459
        dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
460
        break;
461

    
462
    /* DMA Channel Control */
463
    case GT_DMA0_CTRL:
464
    case GT_DMA1_CTRL:
465
    case GT_DMA2_CTRL:
466
    case GT_DMA3_CTRL:
467
        /* Not implemented */
468
        dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
469
        break;
470

    
471
    /* DMA Arbiter */
472
    case GT_DMA_ARB:
473
        /* Not implemented */
474
        dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
475
        break;
476

    
477
    /* Timer/Counter */
478
    case GT_TC0:
479
    case GT_TC1:
480
    case GT_TC2:
481
    case GT_TC3:
482
    case GT_TC_CONTROL:
483
        /* Not implemented */
484
        dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
485
        break;
486

    
487
    /* PCI Internal */
488
    case GT_PCI0_CMD:
489
    case GT_PCI1_CMD:
490
        s->regs[saddr] = val & 0x0401fc0f;
491
        break;
492
    case GT_PCI0_TOR:
493
    case GT_PCI0_BS_SCS10:
494
    case GT_PCI0_BS_SCS32:
495
    case GT_PCI0_BS_CS20:
496
    case GT_PCI0_BS_CS3BT:
497
    case GT_PCI1_IACK:
498
    case GT_PCI0_IACK:
499
    case GT_PCI0_BARE:
500
    case GT_PCI0_PREFMBR:
501
    case GT_PCI0_SCS10_BAR:
502
    case GT_PCI0_SCS32_BAR:
503
    case GT_PCI0_CS20_BAR:
504
    case GT_PCI0_CS3BT_BAR:
505
    case GT_PCI0_SSCS10_BAR:
506
    case GT_PCI0_SSCS32_BAR:
507
    case GT_PCI0_SCS3BT_BAR:
508
    case GT_PCI1_TOR:
509
    case GT_PCI1_BS_SCS10:
510
    case GT_PCI1_BS_SCS32:
511
    case GT_PCI1_BS_CS20:
512
    case GT_PCI1_BS_CS3BT:
513
    case GT_PCI1_BARE:
514
    case GT_PCI1_PREFMBR:
515
    case GT_PCI1_SCS10_BAR:
516
    case GT_PCI1_SCS32_BAR:
517
    case GT_PCI1_CS20_BAR:
518
    case GT_PCI1_CS3BT_BAR:
519
    case GT_PCI1_SSCS10_BAR:
520
    case GT_PCI1_SSCS32_BAR:
521
    case GT_PCI1_SCS3BT_BAR:
522
    case GT_PCI1_CFGADDR:
523
    case GT_PCI1_CFGDATA:
524
        /* not implemented */
525
        break;
526
    case GT_PCI0_CFGADDR:
527
        s->pci->config_reg = val & 0x80fffffc;
528
        break;
529
    case GT_PCI0_CFGDATA:
530
        pci_host_data_writel(s->pci, 0, val);
531
        break;
532

    
533
    /* Interrupts */
534
    case GT_INTRCAUSE:
535
        /* not really implemented */
536
        s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
537
        s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
538
        dprintf("INTRCAUSE %x\n", val);
539
        break;
540
    case GT_INTRMASK:
541
        s->regs[saddr] = val & 0x3c3ffffe;
542
        dprintf("INTRMASK %x\n", val);
543
        break;
544
    case GT_PCI0_ICMASK:
545
        s->regs[saddr] = val & 0x03fffffe;
546
        dprintf("ICMASK %x\n", val);
547
        break;
548
    case GT_PCI0_SERR0MASK:
549
        s->regs[saddr] = val & 0x0000003f;
550
        dprintf("SERR0MASK %x\n", val);
551
        break;
552

    
553
    /* Reserved when only PCI_0 is configured. */
554
    case GT_HINTRCAUSE:
555
    case GT_CPU_INTSEL:
556
    case GT_PCI0_INTSEL:
557
    case GT_HINTRMASK:
558
    case GT_PCI0_HICMASK:
559
    case GT_PCI1_SERR1MASK:
560
        /* not implemented */
561
        break;
562

    
563
    /* SDRAM Parameters */
564
    case GT_SDRAM_B0:
565
    case GT_SDRAM_B1:
566
    case GT_SDRAM_B2:
567
    case GT_SDRAM_B3:
568
        /* We don't simulate electrical parameters of the SDRAM.
569
           Accept, but ignore the values. */
570
        s->regs[saddr] = val;
571
        break;
572

    
573
    default:
574
        dprintf ("Bad register offset 0x%x\n", (int)addr);
575
        break;
576
    }
577
}
578

    
579
static uint32_t gt64120_readl (void *opaque,
580
                               target_phys_addr_t addr)
581
{
582
    GT64120State *s = opaque;
583
    uint32_t val;
584
    uint32_t saddr;
585

    
586
    saddr = (addr & 0xfff) >> 2;
587
    switch (saddr) {
588

    
589
    /* CPU Configuration */
590
    case GT_MULTI:
591
        /* Only one GT64xxx is present on the CPU bus, return
592
           the initial value */
593
        val = s->regs[saddr];
594
        break;
595

    
596
    /* CPU Error Report */
597
    case GT_CPUERR_ADDRLO:
598
    case GT_CPUERR_ADDRHI:
599
    case GT_CPUERR_DATALO:
600
    case GT_CPUERR_DATAHI:
601
    case GT_CPUERR_PARITY:
602
        /* Emulated memory has no error, always return the initial
603
           values */
604
        val = s->regs[saddr];
605
        break;
606

    
607
    /* CPU Sync Barrier */
608
    case GT_PCI0SYNC:
609
    case GT_PCI1SYNC:
610
        /* Reading those register should empty all FIFO on the PCI
611
           bus, which are not emulated. The return value should be
612
           a random value that should be ignored. */
613
        val = 0xc000ffee;
614
        break;
615

    
616
    /* ECC */
617
    case GT_ECC_ERRDATALO:
618
    case GT_ECC_ERRDATAHI:
619
    case GT_ECC_MEM:
620
    case GT_ECC_CALC:
621
    case GT_ECC_ERRADDR:
622
        /* Emulated memory has no error, always return the initial
623
           values */
624
        val = s->regs[saddr];
625
        break;
626

    
627
    case GT_CPU:
628
    case GT_SCS10LD:
629
    case GT_SCS10HD:
630
    case GT_SCS32LD:
631
    case GT_SCS32HD:
632
    case GT_CS20LD:
633
    case GT_CS20HD:
634
    case GT_CS3BOOTLD:
635
    case GT_CS3BOOTHD:
636
    case GT_SCS10AR:
637
    case GT_SCS32AR:
638
    case GT_CS20R:
639
    case GT_CS3BOOTR:
640
    case GT_PCI0IOLD:
641
    case GT_PCI0M0LD:
642
    case GT_PCI0M1LD:
643
    case GT_PCI1IOLD:
644
    case GT_PCI1M0LD:
645
    case GT_PCI1M1LD:
646
    case GT_PCI0IOHD:
647
    case GT_PCI0M0HD:
648
    case GT_PCI0M1HD:
649
    case GT_PCI1IOHD:
650
    case GT_PCI1M0HD:
651
    case GT_PCI1M1HD:
652
    case GT_PCI0IOREMAP:
653
    case GT_PCI0M0REMAP:
654
    case GT_PCI0M1REMAP:
655
    case GT_PCI1IOREMAP:
656
    case GT_PCI1M0REMAP:
657
    case GT_PCI1M1REMAP:
658
    case GT_ISD:
659
        val = s->regs[saddr];
660
        break;
661
    case GT_PCI0_IACK:
662
        /* Read the IRQ number */
663
        val = pic_read_irq(isa_pic);
664
        break;
665

    
666
    /* SDRAM and Device Address Decode */
667
    case GT_SCS0LD:
668
    case GT_SCS0HD:
669
    case GT_SCS1LD:
670
    case GT_SCS1HD:
671
    case GT_SCS2LD:
672
    case GT_SCS2HD:
673
    case GT_SCS3LD:
674
    case GT_SCS3HD:
675
    case GT_CS0LD:
676
    case GT_CS0HD:
677
    case GT_CS1LD:
678
    case GT_CS1HD:
679
    case GT_CS2LD:
680
    case GT_CS2HD:
681
    case GT_CS3LD:
682
    case GT_CS3HD:
683
    case GT_BOOTLD:
684
    case GT_BOOTHD:
685
    case GT_ADERR:
686
        val = s->regs[saddr];
687
        break;
688

    
689
    /* SDRAM Configuration */
690
    case GT_SDRAM_CFG:
691
    case GT_SDRAM_OPMODE:
692
    case GT_SDRAM_BM:
693
    case GT_SDRAM_ADDRDECODE:
694
        val = s->regs[saddr];
695
        break;
696

    
697
    /* SDRAM Parameters */
698
    case GT_SDRAM_B0:
699
    case GT_SDRAM_B1:
700
    case GT_SDRAM_B2:
701
    case GT_SDRAM_B3:
702
        /* We don't simulate electrical parameters of the SDRAM.
703
           Just return the last written value. */
704
        val = s->regs[saddr];
705
        break;
706

    
707
    /* Device Parameters */
708
    case GT_DEV_B0:
709
    case GT_DEV_B1:
710
    case GT_DEV_B2:
711
    case GT_DEV_B3:
712
    case GT_DEV_BOOT:
713
        val = s->regs[saddr];
714
        break;
715

    
716
    /* DMA Record */
717
    case GT_DMA0_CNT:
718
    case GT_DMA1_CNT:
719
    case GT_DMA2_CNT:
720
    case GT_DMA3_CNT:
721
    case GT_DMA0_SA:
722
    case GT_DMA1_SA:
723
    case GT_DMA2_SA:
724
    case GT_DMA3_SA:
725
    case GT_DMA0_DA:
726
    case GT_DMA1_DA:
727
    case GT_DMA2_DA:
728
    case GT_DMA3_DA:
729
    case GT_DMA0_NEXT:
730
    case GT_DMA1_NEXT:
731
    case GT_DMA2_NEXT:
732
    case GT_DMA3_NEXT:
733
    case GT_DMA0_CUR:
734
    case GT_DMA1_CUR:
735
    case GT_DMA2_CUR:
736
    case GT_DMA3_CUR:
737
        val = s->regs[saddr];
738
        break;
739

    
740
    /* DMA Channel Control */
741
    case GT_DMA0_CTRL:
742
    case GT_DMA1_CTRL:
743
    case GT_DMA2_CTRL:
744
    case GT_DMA3_CTRL:
745
        val = s->regs[saddr];
746
        break;
747

    
748
    /* DMA Arbiter */
749
    case GT_DMA_ARB:
750
        val = s->regs[saddr];
751
        break;
752

    
753
    /* Timer/Counter */
754
    case GT_TC0:
755
    case GT_TC1:
756
    case GT_TC2:
757
    case GT_TC3:
758
    case GT_TC_CONTROL:
759
        val = s->regs[saddr];
760
        break;
761

    
762
    /* PCI Internal */
763
    case GT_PCI0_CFGADDR:
764
        val = s->pci->config_reg;
765
        break;
766
    case GT_PCI0_CFGDATA:
767
        val = pci_host_data_readl(s->pci, 0);
768
        break;
769

    
770
    case GT_PCI0_CMD:
771
    case GT_PCI0_TOR:
772
    case GT_PCI0_BS_SCS10:
773
    case GT_PCI0_BS_SCS32:
774
    case GT_PCI0_BS_CS20:
775
    case GT_PCI0_BS_CS3BT:
776
    case GT_PCI1_IACK:
777
    case GT_PCI0_BARE:
778
    case GT_PCI0_PREFMBR:
779
    case GT_PCI0_SCS10_BAR:
780
    case GT_PCI0_SCS32_BAR:
781
    case GT_PCI0_CS20_BAR:
782
    case GT_PCI0_CS3BT_BAR:
783
    case GT_PCI0_SSCS10_BAR:
784
    case GT_PCI0_SSCS32_BAR:
785
    case GT_PCI0_SCS3BT_BAR:
786
    case GT_PCI1_CMD:
787
    case GT_PCI1_TOR:
788
    case GT_PCI1_BS_SCS10:
789
    case GT_PCI1_BS_SCS32:
790
    case GT_PCI1_BS_CS20:
791
    case GT_PCI1_BS_CS3BT:
792
    case GT_PCI1_BARE:
793
    case GT_PCI1_PREFMBR:
794
    case GT_PCI1_SCS10_BAR:
795
    case GT_PCI1_SCS32_BAR:
796
    case GT_PCI1_CS20_BAR:
797
    case GT_PCI1_CS3BT_BAR:
798
    case GT_PCI1_SSCS10_BAR:
799
    case GT_PCI1_SSCS32_BAR:
800
    case GT_PCI1_SCS3BT_BAR:
801
    case GT_PCI1_CFGADDR:
802
    case GT_PCI1_CFGDATA:
803
        val = s->regs[saddr];
804
        break;
805

    
806
    /* Interrupts */
807
    case GT_INTRCAUSE:
808
        val = s->regs[saddr];
809
        dprintf("INTRCAUSE %x\n", val);
810
        break;
811
    case GT_INTRMASK:
812
        val = s->regs[saddr];
813
        dprintf("INTRMASK %x\n", val);
814
        break;
815
    case GT_PCI0_ICMASK:
816
        val = s->regs[saddr];
817
        dprintf("ICMASK %x\n", val);
818
        break;
819
    case GT_PCI0_SERR0MASK:
820
        val = s->regs[saddr];
821
        dprintf("SERR0MASK %x\n", val);
822
        break;
823

    
824
    /* Reserved when only PCI_0 is configured. */
825
    case GT_HINTRCAUSE:
826
    case GT_CPU_INTSEL:
827
    case GT_PCI0_INTSEL:
828
    case GT_HINTRMASK:
829
    case GT_PCI0_HICMASK:
830
    case GT_PCI1_SERR1MASK:
831
        val = s->regs[saddr];
832
        break;
833

    
834
    default:
835
        val = s->regs[saddr];
836
        dprintf ("Bad register offset 0x%x\n", (int)addr);
837
        break;
838
    }
839

    
840
    if (!(s->regs[GT_PCI0_CMD] & 1))
841
        val = bswap32(val);
842

    
843
    return val;
844
}
845

    
846
static CPUWriteMemoryFunc *gt64120_write[] = {
847
    &gt64120_writel,
848
    &gt64120_writel,
849
    &gt64120_writel,
850
};
851

    
852
static CPUReadMemoryFunc *gt64120_read[] = {
853
    &gt64120_readl,
854
    &gt64120_readl,
855
    &gt64120_readl,
856
};
857

    
858
static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
859
{
860
    int slot;
861

    
862
    slot = (pci_dev->devfn >> 3);
863

    
864
    switch (slot) {
865
      /* PIIX4 USB */
866
      case 10:
867
        return 3;
868
      /* AMD 79C973 Ethernet */
869
      case 11:
870
        return 1;
871
      /* Crystal 4281 Sound */
872
      case 12:
873
        return 2;
874
      /* PCI slot 1 to 4 */
875
      case 18 ... 21:
876
        return ((slot - 18) + irq_num) & 0x03;
877
      /* Unknown device, don't do any translation */
878
      default:
879
        return irq_num;
880
    }
881
}
882

    
883
extern PCIDevice *piix4_dev;
884
static int pci_irq_levels[4];
885

    
886
static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
887
{
888
    int i, pic_irq, pic_level;
889

    
890
    pci_irq_levels[irq_num] = level;
891

    
892
    /* now we change the pic irq level according to the piix irq mappings */
893
    /* XXX: optimize */
894
    pic_irq = piix4_dev->config[0x60 + irq_num];
895
    if (pic_irq < 16) {
896
        /* The pic level is the logical OR of all the PCI irqs mapped
897
           to it */
898
        pic_level = 0;
899
        for (i = 0; i < 4; i++) {
900
            if (pic_irq == piix4_dev->config[0x60 + i])
901
                pic_level |= pci_irq_levels[i];
902
        }
903
        qemu_set_irq(pic[pic_irq], pic_level);
904
    }
905
}
906

    
907

    
908
void gt64120_reset(void *opaque)
909
{
910
    GT64120State *s = opaque;
911

    
912
    /* FIXME: Malta specific hw assumptions ahead */
913

    
914
    /* CPU Configuration */
915
#ifdef TARGET_WORDS_BIGENDIAN
916
    s->regs[GT_CPU]           = 0x00000000;
917
#else
918
    s->regs[GT_CPU]           = 0x00001000;
919
#endif
920
    s->regs[GT_MULTI]         = 0x00000003;
921

    
922
    /* CPU Address decode */
923
    s->regs[GT_SCS10LD]       = 0x00000000;
924
    s->regs[GT_SCS10HD]       = 0x00000007;
925
    s->regs[GT_SCS32LD]       = 0x00000008;
926
    s->regs[GT_SCS32HD]       = 0x0000000f;
927
    s->regs[GT_CS20LD]        = 0x000000e0;
928
    s->regs[GT_CS20HD]        = 0x00000070;
929
    s->regs[GT_CS3BOOTLD]     = 0x000000f8;
930
    s->regs[GT_CS3BOOTHD]     = 0x0000007f;
931

    
932
    s->regs[GT_PCI0IOLD]      = 0x00000080;
933
    s->regs[GT_PCI0IOHD]      = 0x0000000f;
934
    s->regs[GT_PCI0M0LD]      = 0x00000090;
935
    s->regs[GT_PCI0M0HD]      = 0x0000001f;
936
    s->regs[GT_ISD]           = 0x000000a0;
937
    s->regs[GT_PCI0M1LD]      = 0x00000790;
938
    s->regs[GT_PCI0M1HD]      = 0x0000001f;
939
    s->regs[GT_PCI1IOLD]      = 0x00000100;
940
    s->regs[GT_PCI1IOHD]      = 0x0000000f;
941
    s->regs[GT_PCI1M0LD]      = 0x00000110;
942
    s->regs[GT_PCI1M0HD]      = 0x0000001f;
943
    s->regs[GT_PCI1M1LD]      = 0x00000120;
944
    s->regs[GT_PCI1M1HD]      = 0x0000002f;
945

    
946
    s->regs[GT_SCS10AR]       = 0x00000000;
947
    s->regs[GT_SCS32AR]       = 0x00000008;
948
    s->regs[GT_CS20R]         = 0x000000e0;
949
    s->regs[GT_CS3BOOTR]      = 0x000000f8;
950

    
951
    s->regs[GT_PCI0IOREMAP]   = 0x00000080;
952
    s->regs[GT_PCI0M0REMAP]   = 0x00000090;
953
    s->regs[GT_PCI0M1REMAP]   = 0x00000790;
954
    s->regs[GT_PCI1IOREMAP]   = 0x00000100;
955
    s->regs[GT_PCI1M0REMAP]   = 0x00000110;
956
    s->regs[GT_PCI1M1REMAP]   = 0x00000120;
957

    
958
    /* CPU Error Report */
959
    s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
960
    s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
961
    s->regs[GT_CPUERR_DATALO] = 0xffffffff;
962
    s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
963
    s->regs[GT_CPUERR_PARITY] = 0x000000ff;
964

    
965
    /* CPU Sync Barrier */
966
    s->regs[GT_PCI0SYNC]      = 0x00000000;
967
    s->regs[GT_PCI1SYNC]      = 0x00000000;
968

    
969
    /* SDRAM and Device Address Decode */
970
    s->regs[GT_SCS0LD]        = 0x00000000;
971
    s->regs[GT_SCS0HD]        = 0x00000007;
972
    s->regs[GT_SCS1LD]        = 0x00000008;
973
    s->regs[GT_SCS1HD]        = 0x0000000f;
974
    s->regs[GT_SCS2LD]        = 0x00000010;
975
    s->regs[GT_SCS2HD]        = 0x00000017;
976
    s->regs[GT_SCS3LD]        = 0x00000018;
977
    s->regs[GT_SCS3HD]        = 0x0000001f;
978
    s->regs[GT_CS0LD]         = 0x000000c0;
979
    s->regs[GT_CS0HD]         = 0x000000c7;
980
    s->regs[GT_CS1LD]         = 0x000000c8;
981
    s->regs[GT_CS1HD]         = 0x000000cf;
982
    s->regs[GT_CS2LD]         = 0x000000d0;
983
    s->regs[GT_CS2HD]         = 0x000000df;
984
    s->regs[GT_CS3LD]         = 0x000000f0;
985
    s->regs[GT_CS3HD]         = 0x000000fb;
986
    s->regs[GT_BOOTLD]        = 0x000000fc;
987
    s->regs[GT_BOOTHD]        = 0x000000ff;
988
    s->regs[GT_ADERR]         = 0xffffffff;
989

    
990
    /* SDRAM Configuration */
991
    s->regs[GT_SDRAM_CFG]     = 0x00000200;
992
    s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
993
    s->regs[GT_SDRAM_BM]      = 0x00000007;
994
    s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
995

    
996
    /* SDRAM Parameters */
997
    s->regs[GT_SDRAM_B0]      = 0x00000005;
998
    s->regs[GT_SDRAM_B1]      = 0x00000005;
999
    s->regs[GT_SDRAM_B2]      = 0x00000005;
1000
    s->regs[GT_SDRAM_B3]      = 0x00000005;
1001

    
1002
    /* ECC */
1003
    s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1004
    s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1005
    s->regs[GT_ECC_MEM]       = 0x00000000;
1006
    s->regs[GT_ECC_CALC]      = 0x00000000;
1007
    s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1008

    
1009
    /* Device Parameters */
1010
    s->regs[GT_DEV_B0]        = 0x386fffff;
1011
    s->regs[GT_DEV_B1]        = 0x386fffff;
1012
    s->regs[GT_DEV_B2]        = 0x386fffff;
1013
    s->regs[GT_DEV_B3]        = 0x386fffff;
1014
    s->regs[GT_DEV_BOOT]      = 0x146fffff;
1015

    
1016
    /* DMA registers are all zeroed at reset */
1017

    
1018
    /* Timer/Counter */
1019
    s->regs[GT_TC0]           = 0xffffffff;
1020
    s->regs[GT_TC1]           = 0x00ffffff;
1021
    s->regs[GT_TC2]           = 0x00ffffff;
1022
    s->regs[GT_TC3]           = 0x00ffffff;
1023
    s->regs[GT_TC_CONTROL]    = 0x00000000;
1024

    
1025
    /* PCI Internal */
1026
#ifdef TARGET_WORDS_BIGENDIAN
1027
    s->regs[GT_PCI0_CMD]      = 0x00000000;
1028
#else
1029
    s->regs[GT_PCI0_CMD]      = 0x00010001;
1030
#endif
1031
    s->regs[GT_PCI0_TOR]      = 0x0000070f;
1032
    s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1033
    s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1034
    s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1035
    s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1036
    s->regs[GT_PCI1_IACK]     = 0x00000000;
1037
    s->regs[GT_PCI0_IACK]     = 0x00000000;
1038
    s->regs[GT_PCI0_BARE]     = 0x0000000f;
1039
    s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1040
    s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1041
    s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1042
    s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1043
    s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1044
    s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1045
    s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1046
    s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1047
#ifdef TARGET_WORDS_BIGENDIAN
1048
    s->regs[GT_PCI1_CMD]      = 0x00000000;
1049
#else
1050
    s->regs[GT_PCI1_CMD]      = 0x00010001;
1051
#endif
1052
    s->regs[GT_PCI1_TOR]      = 0x0000070f;
1053
    s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1054
    s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1055
    s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1056
    s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1057
    s->regs[GT_PCI1_BARE]     = 0x0000000f;
1058
    s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1059
    s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1060
    s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1061
    s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1062
    s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1063
    s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1064
    s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1065
    s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1066
    s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1067
    s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1068
    s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1069
    s->regs[GT_PCI0_CFGDATA]  = 0x00000000;
1070

    
1071
    /* Interrupt registers are all zeroed at reset */
1072

    
1073
    gt64120_isd_mapping(s);
1074
    gt64120_pci_mapping(s);
1075
}
1076

    
1077
static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
1078
{
1079
    return pci_default_read_config(d, address, len);
1080
}
1081

    
1082
static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
1083
                                 int len)
1084
{
1085
    pci_default_write_config(d, address, val, len);
1086
}
1087

    
1088
static void gt64120_save(QEMUFile* f, void *opaque)
1089
{
1090
    PCIDevice *d = opaque;
1091
    pci_device_save(d, f);
1092
}
1093

    
1094
static int gt64120_load(QEMUFile* f, void *opaque, int version_id)
1095
{
1096
    PCIDevice *d = opaque;
1097
    int ret;
1098

    
1099
    if (version_id != 1)
1100
        return -EINVAL;
1101
    ret = pci_device_load(d, f);
1102
    if (ret < 0)
1103
        return ret;
1104
    return 0;
1105
}
1106

    
1107
PCIBus *pci_gt64120_init(qemu_irq *pic)
1108
{
1109
    GT64120State *s;
1110
    PCIDevice *d;
1111

    
1112
    s = qemu_mallocz(sizeof(GT64120State));
1113
    s->pci = qemu_mallocz(sizeof(GT64120PCIState));
1114

    
1115
    s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
1116
                                   pic, 144, 4);
1117
    s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);
1118
    d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
1119
                            0, gt64120_read_config, gt64120_write_config);
1120

    
1121
    /* FIXME: Malta specific hw assumptions ahead */
1122

    
1123
    d->config[0x00] = 0xab; /* vendor_id */
1124
    d->config[0x01] = 0x11;
1125
    d->config[0x02] = 0x20; /* device_id */
1126
    d->config[0x03] = 0x46;
1127

    
1128
    d->config[0x04] = 0x00;
1129
    d->config[0x05] = 0x00;
1130
    d->config[0x06] = 0x80;
1131
    d->config[0x07] = 0x02;
1132

    
1133
    d->config[0x08] = 0x10;
1134
    d->config[0x09] = 0x00;
1135
    d->config[0x0A] = 0x00;
1136
    d->config[0x0B] = 0x06;
1137

    
1138
    d->config[0x10] = 0x08;
1139
    d->config[0x14] = 0x08;
1140
    d->config[0x17] = 0x01;
1141
    d->config[0x1B] = 0x1c;
1142
    d->config[0x1F] = 0x1f;
1143
    d->config[0x23] = 0x14;
1144
    d->config[0x24] = 0x01;
1145
    d->config[0x27] = 0x14;
1146
    d->config[0x3D] = 0x01;
1147

    
1148
    gt64120_reset(s);
1149

    
1150
    register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
1151

    
1152
    return s->pci->bus;
1153
}