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1 | 2c0262af | bellard | /*
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2 | 5fafdf24 | ths | * i386 execution defines
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 7d3505c5 | bellard | #include "config.h" |
21 | 2c0262af | bellard | #include "dyngen-exec.h" |
22 | 2c0262af | bellard | |
23 | 14ce26e7 | bellard | /* XXX: factorize this mess */
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24 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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25 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 64 |
26 | 14ce26e7 | bellard | #else
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27 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 32 |
28 | 14ce26e7 | bellard | #endif
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29 | 14ce26e7 | bellard | |
30 | d785e6be | bellard | #include "cpu-defs.h" |
31 | d785e6be | bellard | |
32 | 0d1a29f9 | bellard | /* at least 4 register variables are defined */
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33 | 2c0262af | bellard | register struct CPUX86State *env asm(AREG0); |
34 | 14ce26e7 | bellard | |
35 | edea5f01 | bellard | #ifndef CPU_NO_GLOBAL_REGS
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36 | edea5f01 | bellard | |
37 | d785e6be | bellard | #if TARGET_LONG_BITS > HOST_LONG_BITS
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38 | d785e6be | bellard | |
39 | d785e6be | bellard | /* no registers can be used */
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40 | d785e6be | bellard | #define T0 (env->t0)
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41 | d785e6be | bellard | #define T1 (env->t1)
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42 | d785e6be | bellard | #define T2 (env->t2)
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43 | 14ce26e7 | bellard | |
44 | d785e6be | bellard | #else
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45 | d785e6be | bellard | |
46 | d785e6be | bellard | /* XXX: use unsigned long instead of target_ulong - better code will
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47 | d785e6be | bellard | be generated for 64 bit CPUs */
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48 | d785e6be | bellard | register target_ulong T0 asm(AREG1); |
49 | d785e6be | bellard | register target_ulong T1 asm(AREG2); |
50 | d785e6be | bellard | register target_ulong T2 asm(AREG3); |
51 | 2c0262af | bellard | |
52 | d785e6be | bellard | #endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */ |
53 | 14ce26e7 | bellard | |
54 | edea5f01 | bellard | #endif /* ! CPU_NO_GLOBAL_REGS */ |
55 | edea5f01 | bellard | |
56 | 14ce26e7 | bellard | #define A0 T2
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57 | 14ce26e7 | bellard | |
58 | 2c0262af | bellard | extern FILE *logfile;
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59 | 2c0262af | bellard | extern int loglevel; |
60 | 2c0262af | bellard | |
61 | 2c0262af | bellard | #ifndef reg_EAX
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62 | 2c0262af | bellard | #define EAX (env->regs[R_EAX])
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63 | 2c0262af | bellard | #endif
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64 | 2c0262af | bellard | #ifndef reg_ECX
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65 | 2c0262af | bellard | #define ECX (env->regs[R_ECX])
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66 | 2c0262af | bellard | #endif
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67 | 2c0262af | bellard | #ifndef reg_EDX
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68 | 2c0262af | bellard | #define EDX (env->regs[R_EDX])
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69 | 2c0262af | bellard | #endif
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70 | 2c0262af | bellard | #ifndef reg_EBX
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71 | 2c0262af | bellard | #define EBX (env->regs[R_EBX])
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72 | 2c0262af | bellard | #endif
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73 | 2c0262af | bellard | #ifndef reg_ESP
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74 | 2c0262af | bellard | #define ESP (env->regs[R_ESP])
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75 | 2c0262af | bellard | #endif
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76 | 2c0262af | bellard | #ifndef reg_EBP
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77 | 2c0262af | bellard | #define EBP (env->regs[R_EBP])
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78 | 2c0262af | bellard | #endif
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79 | 2c0262af | bellard | #ifndef reg_ESI
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80 | 2c0262af | bellard | #define ESI (env->regs[R_ESI])
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81 | 2c0262af | bellard | #endif
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82 | 2c0262af | bellard | #ifndef reg_EDI
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83 | 2c0262af | bellard | #define EDI (env->regs[R_EDI])
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84 | 2c0262af | bellard | #endif
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85 | 2c0262af | bellard | #define EIP (env->eip)
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86 | 2c0262af | bellard | #define DF (env->df)
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87 | 2c0262af | bellard | |
88 | 2c0262af | bellard | #define CC_SRC (env->cc_src)
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89 | 2c0262af | bellard | #define CC_DST (env->cc_dst)
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90 | 2c0262af | bellard | #define CC_OP (env->cc_op)
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91 | 2c0262af | bellard | |
92 | 2c0262af | bellard | /* float macros */
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93 | 2c0262af | bellard | #define FT0 (env->ft0)
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94 | 664e0f19 | bellard | #define ST0 (env->fpregs[env->fpstt].d)
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95 | 664e0f19 | bellard | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) |
96 | 2c0262af | bellard | #define ST1 ST(1) |
97 | 2c0262af | bellard | |
98 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
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99 | 2c0262af | bellard | #define FP_CONVERT (env->fp_convert)
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100 | 2c0262af | bellard | #endif
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101 | 2c0262af | bellard | |
102 | 2c0262af | bellard | #include "cpu.h" |
103 | 2c0262af | bellard | #include "exec-all.h" |
104 | 2c0262af | bellard | |
105 | 2c0262af | bellard | typedef struct CCTable { |
106 | 2c0262af | bellard | int (*compute_all)(void); /* return all the flags */ |
107 | 2c0262af | bellard | int (*compute_c)(void); /* return the C flag */ |
108 | 2c0262af | bellard | } CCTable; |
109 | 2c0262af | bellard | |
110 | 2c0262af | bellard | extern CCTable cc_table[];
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111 | 2c0262af | bellard | |
112 | 8e682019 | bellard | void load_seg(int seg_reg, int selector); |
113 | 08cea4ee | bellard | void helper_ljmp_protected_T0_T1(int next_eip); |
114 | 2c0262af | bellard | void helper_lcall_real_T0_T1(int shift, int next_eip); |
115 | 2c0262af | bellard | void helper_lcall_protected_T0_T1(int shift, int next_eip); |
116 | 2c0262af | bellard | void helper_iret_real(int shift); |
117 | 08cea4ee | bellard | void helper_iret_protected(int shift, int next_eip); |
118 | 2c0262af | bellard | void helper_lret_protected(int shift, int addend); |
119 | 2c0262af | bellard | void helper_lldt_T0(void); |
120 | 2c0262af | bellard | void helper_ltr_T0(void); |
121 | 2c0262af | bellard | void helper_movl_crN_T0(int reg); |
122 | 2c0262af | bellard | void helper_movl_drN_T0(int reg); |
123 | 8f091a59 | bellard | void helper_invlpg(target_ulong addr);
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124 | 1ac157da | bellard | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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125 | 14ce26e7 | bellard | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
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126 | 1ac157da | bellard | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
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127 | 8f091a59 | bellard | void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr);
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128 | 5fafdf24 | ths | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
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129 | 6ebbf390 | j_mayer | int is_write, int mmu_idx, int is_softmmu); |
130 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
131 | 61382a50 | bellard | void *retaddr);
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132 | 2c0262af | bellard | void __hidden cpu_lock(void); |
133 | 2c0262af | bellard | void __hidden cpu_unlock(void); |
134 | 5fafdf24 | ths | void do_interrupt(int intno, int is_int, int error_code, |
135 | 14ce26e7 | bellard | target_ulong next_eip, int is_hw);
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136 | 5fafdf24 | ths | void do_interrupt_user(int intno, int is_int, int error_code, |
137 | 14ce26e7 | bellard | target_ulong next_eip); |
138 | 5fafdf24 | ths | void raise_interrupt(int intno, int is_int, int error_code, |
139 | a8ede8ba | bellard | int next_eip_addend);
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140 | 2c0262af | bellard | void raise_exception_err(int exception_index, int error_code); |
141 | 2c0262af | bellard | void raise_exception(int exception_index); |
142 | 3b21e03e | bellard | void do_smm_enter(void); |
143 | 2c0262af | bellard | void __hidden cpu_loop_exit(void); |
144 | 2c0262af | bellard | |
145 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0(void); |
146 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags(void); |
147 | 57fec1fe | bellard | |
148 | 57fec1fe | bellard | #include "helper.h" |
149 | 57fec1fe | bellard | |
150 | 14ce26e7 | bellard | void helper_mulq_EAX_T0(void); |
151 | 14ce26e7 | bellard | void helper_imulq_EAX_T0(void); |
152 | 14ce26e7 | bellard | void helper_imulq_T0_T1(void); |
153 | 14ce26e7 | bellard | void helper_divq_EAX_T0(void); |
154 | 14ce26e7 | bellard | void helper_idivq_EAX_T0(void); |
155 | 68cae3d8 | bellard | void helper_bswapq_T0(void); |
156 | 2c0262af | bellard | void helper_cmpxchg8b(void); |
157 | 88fe8a41 | ths | void helper_single_step(void); |
158 | 2c0262af | bellard | void helper_cpuid(void); |
159 | 61a8c4ec | bellard | void helper_enter_level(int level, int data32); |
160 | 8f091a59 | bellard | void helper_enter64_level(int level, int data64); |
161 | 023fe10d | bellard | void helper_sysenter(void); |
162 | 023fe10d | bellard | void helper_sysexit(void); |
163 | 06c2f506 | bellard | void helper_syscall(int next_eip_addend); |
164 | 14ce26e7 | bellard | void helper_sysret(int dflag); |
165 | 2c0262af | bellard | void helper_rdtsc(void); |
166 | df01e0fc | balrog | void helper_rdpmc(void); |
167 | 2c0262af | bellard | void helper_rdmsr(void); |
168 | 2c0262af | bellard | void helper_wrmsr(void); |
169 | 2c0262af | bellard | void helper_lsl(void); |
170 | 2c0262af | bellard | void helper_lar(void); |
171 | 3ab493de | bellard | void helper_verr(void); |
172 | 3ab493de | bellard | void helper_verw(void); |
173 | 3b21e03e | bellard | void helper_rsm(void); |
174 | 2c0262af | bellard | |
175 | 3e25f951 | bellard | void check_iob_T0(void); |
176 | 3e25f951 | bellard | void check_iow_T0(void); |
177 | 3e25f951 | bellard | void check_iol_T0(void); |
178 | 3e25f951 | bellard | void check_iob_DX(void); |
179 | 3e25f951 | bellard | void check_iow_DX(void); |
180 | 3e25f951 | bellard | void check_iol_DX(void); |
181 | 3e25f951 | bellard | |
182 | 9951bf39 | bellard | #if !defined(CONFIG_USER_ONLY)
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183 | 9951bf39 | bellard | |
184 | a9049a07 | bellard | #include "softmmu_exec.h" |
185 | 9951bf39 | bellard | |
186 | 14ce26e7 | bellard | static inline double ldfq(target_ulong ptr) |
187 | 9951bf39 | bellard | { |
188 | 9951bf39 | bellard | union {
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189 | 9951bf39 | bellard | double d;
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190 | 9951bf39 | bellard | uint64_t i; |
191 | 9951bf39 | bellard | } u; |
192 | 9951bf39 | bellard | u.i = ldq(ptr); |
193 | 9951bf39 | bellard | return u.d;
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194 | 9951bf39 | bellard | } |
195 | 9951bf39 | bellard | |
196 | 14ce26e7 | bellard | static inline void stfq(target_ulong ptr, double v) |
197 | 9951bf39 | bellard | { |
198 | 9951bf39 | bellard | union {
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199 | 9951bf39 | bellard | double d;
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200 | 9951bf39 | bellard | uint64_t i; |
201 | 9951bf39 | bellard | } u; |
202 | 9951bf39 | bellard | u.d = v; |
203 | 9951bf39 | bellard | stq(ptr, u.i); |
204 | 9951bf39 | bellard | } |
205 | 9951bf39 | bellard | |
206 | 14ce26e7 | bellard | static inline float ldfl(target_ulong ptr) |
207 | 9951bf39 | bellard | { |
208 | 9951bf39 | bellard | union {
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209 | 9951bf39 | bellard | float f;
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210 | 9951bf39 | bellard | uint32_t i; |
211 | 9951bf39 | bellard | } u; |
212 | 9951bf39 | bellard | u.i = ldl(ptr); |
213 | 9951bf39 | bellard | return u.f;
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214 | 9951bf39 | bellard | } |
215 | 9951bf39 | bellard | |
216 | 14ce26e7 | bellard | static inline void stfl(target_ulong ptr, float v) |
217 | 9951bf39 | bellard | { |
218 | 9951bf39 | bellard | union {
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219 | 9951bf39 | bellard | float f;
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220 | 9951bf39 | bellard | uint32_t i; |
221 | 9951bf39 | bellard | } u; |
222 | 9951bf39 | bellard | u.f = v; |
223 | 9951bf39 | bellard | stl(ptr, u.i); |
224 | 9951bf39 | bellard | } |
225 | 9951bf39 | bellard | |
226 | 9951bf39 | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
227 | 9951bf39 | bellard | |
228 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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229 | 2c0262af | bellard | /* use long double functions */
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230 | 7a0e1f41 | bellard | #define floatx_to_int32 floatx80_to_int32
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231 | 7a0e1f41 | bellard | #define floatx_to_int64 floatx80_to_int64
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232 | 465e9838 | bellard | #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
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233 | 465e9838 | bellard | #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
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234 | 19e6c4b8 | bellard | #define int32_to_floatx int32_to_floatx80
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235 | 19e6c4b8 | bellard | #define int64_to_floatx int64_to_floatx80
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236 | 19e6c4b8 | bellard | #define float32_to_floatx float32_to_floatx80
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237 | 19e6c4b8 | bellard | #define float64_to_floatx float64_to_floatx80
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238 | 19e6c4b8 | bellard | #define floatx_to_float32 floatx80_to_float32
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239 | 19e6c4b8 | bellard | #define floatx_to_float64 floatx80_to_float64
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240 | 7a0e1f41 | bellard | #define floatx_abs floatx80_abs
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241 | 7a0e1f41 | bellard | #define floatx_chs floatx80_chs
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242 | 7a0e1f41 | bellard | #define floatx_round_to_int floatx80_round_to_int
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243 | 8422b113 | bellard | #define floatx_compare floatx80_compare
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244 | 8422b113 | bellard | #define floatx_compare_quiet floatx80_compare_quiet
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245 | 2c0262af | bellard | #define sin sinl
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246 | 2c0262af | bellard | #define cos cosl
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247 | 2c0262af | bellard | #define sqrt sqrtl
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248 | 2c0262af | bellard | #define pow powl
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249 | 2c0262af | bellard | #define log logl
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250 | 2c0262af | bellard | #define tan tanl
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251 | 2c0262af | bellard | #define atan2 atan2l
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252 | 2c0262af | bellard | #define floor floorl
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253 | 2c0262af | bellard | #define ceil ceill
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254 | 57e4c06e | bellard | #define ldexp ldexpl
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255 | 7d3505c5 | bellard | #else
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256 | 7a0e1f41 | bellard | #define floatx_to_int32 float64_to_int32
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257 | 7a0e1f41 | bellard | #define floatx_to_int64 float64_to_int64
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258 | 465e9838 | bellard | #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
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259 | 465e9838 | bellard | #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
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260 | 19e6c4b8 | bellard | #define int32_to_floatx int32_to_float64
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261 | 19e6c4b8 | bellard | #define int64_to_floatx int64_to_float64
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262 | 19e6c4b8 | bellard | #define float32_to_floatx float32_to_float64
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263 | 19e6c4b8 | bellard | #define float64_to_floatx(x, e) (x)
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264 | 19e6c4b8 | bellard | #define floatx_to_float32 float64_to_float32
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265 | 19e6c4b8 | bellard | #define floatx_to_float64(x, e) (x)
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266 | 7a0e1f41 | bellard | #define floatx_abs float64_abs
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267 | 7a0e1f41 | bellard | #define floatx_chs float64_chs
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268 | 7a0e1f41 | bellard | #define floatx_round_to_int float64_round_to_int
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269 | 8422b113 | bellard | #define floatx_compare float64_compare
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270 | 8422b113 | bellard | #define floatx_compare_quiet float64_compare_quiet
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271 | 7d3505c5 | bellard | #endif
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272 | 7a0e1f41 | bellard | |
273 | 2c0262af | bellard | extern CPU86_LDouble sin(CPU86_LDouble x);
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274 | 2c0262af | bellard | extern CPU86_LDouble cos(CPU86_LDouble x);
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275 | 2c0262af | bellard | extern CPU86_LDouble sqrt(CPU86_LDouble x);
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276 | 2c0262af | bellard | extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
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277 | 2c0262af | bellard | extern CPU86_LDouble log(CPU86_LDouble x);
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278 | 2c0262af | bellard | extern CPU86_LDouble tan(CPU86_LDouble x);
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279 | 2c0262af | bellard | extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
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280 | 2c0262af | bellard | extern CPU86_LDouble floor(CPU86_LDouble x);
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281 | 2c0262af | bellard | extern CPU86_LDouble ceil(CPU86_LDouble x);
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282 | 2c0262af | bellard | |
283 | 2c0262af | bellard | #define RC_MASK 0xc00 |
284 | 2c0262af | bellard | #define RC_NEAR 0x000 |
285 | 2c0262af | bellard | #define RC_DOWN 0x400 |
286 | 2c0262af | bellard | #define RC_UP 0x800 |
287 | 2c0262af | bellard | #define RC_CHOP 0xc00 |
288 | 2c0262af | bellard | |
289 | 2c0262af | bellard | #define MAXTAN 9223372036854775808.0 |
290 | 2c0262af | bellard | |
291 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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292 | 2c0262af | bellard | |
293 | 2c0262af | bellard | /* only for x86 */
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294 | 2c0262af | bellard | typedef union { |
295 | 2c0262af | bellard | long double d; |
296 | 2c0262af | bellard | struct {
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297 | 2c0262af | bellard | unsigned long long lower; |
298 | 2c0262af | bellard | unsigned short upper; |
299 | 2c0262af | bellard | } l; |
300 | 2c0262af | bellard | } CPU86_LDoubleU; |
301 | 2c0262af | bellard | |
302 | 2c0262af | bellard | /* the following deal with x86 long double-precision numbers */
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303 | 2c0262af | bellard | #define MAXEXPD 0x7fff |
304 | 2c0262af | bellard | #define EXPBIAS 16383 |
305 | 2c0262af | bellard | #define EXPD(fp) (fp.l.upper & 0x7fff) |
306 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x8000) |
307 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower)
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308 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS |
309 | 2c0262af | bellard | |
310 | 2c0262af | bellard | #else
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311 | 2c0262af | bellard | |
312 | 2c0262af | bellard | /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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313 | 2c0262af | bellard | typedef union { |
314 | 2c0262af | bellard | double d;
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315 | 2c0262af | bellard | #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
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316 | 2c0262af | bellard | struct {
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317 | 2c0262af | bellard | uint32_t lower; |
318 | 2c0262af | bellard | int32_t upper; |
319 | 2c0262af | bellard | } l; |
320 | 2c0262af | bellard | #else
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321 | 2c0262af | bellard | struct {
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322 | 2c0262af | bellard | int32_t upper; |
323 | 2c0262af | bellard | uint32_t lower; |
324 | 2c0262af | bellard | } l; |
325 | 2c0262af | bellard | #endif
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326 | 2c0262af | bellard | #ifndef __arm__
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327 | 2c0262af | bellard | int64_t ll; |
328 | 2c0262af | bellard | #endif
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329 | 2c0262af | bellard | } CPU86_LDoubleU; |
330 | 2c0262af | bellard | |
331 | 2c0262af | bellard | /* the following deal with IEEE double-precision numbers */
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332 | 2c0262af | bellard | #define MAXEXPD 0x7ff |
333 | 2c0262af | bellard | #define EXPBIAS 1023 |
334 | 2c0262af | bellard | #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF) |
335 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x80000000) |
336 | 2c0262af | bellard | #ifdef __arm__
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337 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32)) |
338 | 2c0262af | bellard | #else
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339 | 2c0262af | bellard | #define MANTD(fp) (fp.ll & ((1LL << 52) - 1)) |
340 | 2c0262af | bellard | #endif
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341 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20) |
342 | 2c0262af | bellard | #endif
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343 | 2c0262af | bellard | |
344 | 2c0262af | bellard | static inline void fpush(void) |
345 | 2c0262af | bellard | { |
346 | 2c0262af | bellard | env->fpstt = (env->fpstt - 1) & 7; |
347 | 2c0262af | bellard | env->fptags[env->fpstt] = 0; /* validate stack entry */ |
348 | 2c0262af | bellard | } |
349 | 2c0262af | bellard | |
350 | 2c0262af | bellard | static inline void fpop(void) |
351 | 2c0262af | bellard | { |
352 | 2c0262af | bellard | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ |
353 | 2c0262af | bellard | env->fpstt = (env->fpstt + 1) & 7; |
354 | 2c0262af | bellard | } |
355 | 2c0262af | bellard | |
356 | 2c0262af | bellard | #ifndef USE_X86LDOUBLE
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357 | 14ce26e7 | bellard | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
358 | 2c0262af | bellard | { |
359 | 2c0262af | bellard | CPU86_LDoubleU temp; |
360 | 2c0262af | bellard | int upper, e;
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361 | 2c0262af | bellard | uint64_t ll; |
362 | 2c0262af | bellard | |
363 | 2c0262af | bellard | /* mantissa */
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364 | 2c0262af | bellard | upper = lduw(ptr + 8);
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365 | 2c0262af | bellard | /* XXX: handle overflow ? */
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366 | 2c0262af | bellard | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */ |
367 | 2c0262af | bellard | e |= (upper >> 4) & 0x800; /* sign */ |
368 | 2c0262af | bellard | ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1); |
369 | 2c0262af | bellard | #ifdef __arm__
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370 | 2c0262af | bellard | temp.l.upper = (e << 20) | (ll >> 32); |
371 | 2c0262af | bellard | temp.l.lower = ll; |
372 | 2c0262af | bellard | #else
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373 | 2c0262af | bellard | temp.ll = ll | ((uint64_t)e << 52);
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374 | 2c0262af | bellard | #endif
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375 | 2c0262af | bellard | return temp.d;
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376 | 2c0262af | bellard | } |
377 | 2c0262af | bellard | |
378 | 664e0f19 | bellard | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
379 | 2c0262af | bellard | { |
380 | 2c0262af | bellard | CPU86_LDoubleU temp; |
381 | 2c0262af | bellard | int e;
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382 | 2c0262af | bellard | |
383 | 2c0262af | bellard | temp.d = f; |
384 | 2c0262af | bellard | /* mantissa */
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385 | 2c0262af | bellard | stq(ptr, (MANTD(temp) << 11) | (1LL << 63)); |
386 | 2c0262af | bellard | /* exponent + sign */
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387 | 2c0262af | bellard | e = EXPD(temp) - EXPBIAS + 16383;
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388 | 2c0262af | bellard | e |= SIGND(temp) >> 16;
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389 | 2c0262af | bellard | stw(ptr + 8, e);
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390 | 2c0262af | bellard | } |
391 | 9951bf39 | bellard | #else
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392 | 9951bf39 | bellard | |
393 | 9951bf39 | bellard | /* we use memory access macros */
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394 | 9951bf39 | bellard | |
395 | 14ce26e7 | bellard | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
396 | 9951bf39 | bellard | { |
397 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
398 | 9951bf39 | bellard | |
399 | 9951bf39 | bellard | temp.l.lower = ldq(ptr); |
400 | 9951bf39 | bellard | temp.l.upper = lduw(ptr + 8);
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401 | 9951bf39 | bellard | return temp.d;
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402 | 9951bf39 | bellard | } |
403 | 9951bf39 | bellard | |
404 | 14ce26e7 | bellard | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
405 | 9951bf39 | bellard | { |
406 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
407 | 3b46e624 | ths | |
408 | 9951bf39 | bellard | temp.d = f; |
409 | 9951bf39 | bellard | stq(ptr, temp.l.lower); |
410 | 9951bf39 | bellard | stw(ptr + 8, temp.l.upper);
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411 | 9951bf39 | bellard | } |
412 | 9951bf39 | bellard | |
413 | 9951bf39 | bellard | #endif /* USE_X86LDOUBLE */ |
414 | 2c0262af | bellard | |
415 | 2ee73ac3 | bellard | #define FPUS_IE (1 << 0) |
416 | 2ee73ac3 | bellard | #define FPUS_DE (1 << 1) |
417 | 2ee73ac3 | bellard | #define FPUS_ZE (1 << 2) |
418 | 2ee73ac3 | bellard | #define FPUS_OE (1 << 3) |
419 | 2ee73ac3 | bellard | #define FPUS_UE (1 << 4) |
420 | 2ee73ac3 | bellard | #define FPUS_PE (1 << 5) |
421 | 2ee73ac3 | bellard | #define FPUS_SF (1 << 6) |
422 | 2ee73ac3 | bellard | #define FPUS_SE (1 << 7) |
423 | 2ee73ac3 | bellard | #define FPUS_B (1 << 15) |
424 | 2ee73ac3 | bellard | |
425 | 2ee73ac3 | bellard | #define FPUC_EM 0x3f |
426 | 2ee73ac3 | bellard | |
427 | 83fb7adf | bellard | extern const CPU86_LDouble f15rk[7]; |
428 | 2c0262af | bellard | |
429 | 2ee73ac3 | bellard | void fpu_raise_exception(void); |
430 | 03857e31 | bellard | void restore_native_fp_state(CPUState *env);
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431 | 03857e31 | bellard | void save_native_fp_state(CPUState *env);
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432 | 664e0f19 | bellard | float approx_rsqrt(float a); |
433 | 664e0f19 | bellard | float approx_rcp(float a); |
434 | 7a0e1f41 | bellard | void update_fp_status(void); |
435 | 3d7374c5 | bellard | void helper_hlt(void); |
436 | 3d7374c5 | bellard | void helper_monitor(void); |
437 | 3d7374c5 | bellard | void helper_mwait(void); |
438 | 0573fbfc | ths | void helper_vmrun(target_ulong addr);
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439 | 0573fbfc | ths | void helper_vmmcall(void); |
440 | 0573fbfc | ths | void helper_vmload(target_ulong addr);
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441 | 0573fbfc | ths | void helper_vmsave(target_ulong addr);
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442 | 0573fbfc | ths | void helper_stgi(void); |
443 | 0573fbfc | ths | void helper_clgi(void); |
444 | 0573fbfc | ths | void helper_skinit(void); |
445 | 0573fbfc | ths | void helper_invlpga(void); |
446 | 0573fbfc | ths | void vmexit(uint64_t exit_code, uint64_t exit_info_1);
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447 | 2c0262af | bellard | |
448 | 83fb7adf | bellard | extern const uint8_t parity_table[256]; |
449 | 83fb7adf | bellard | extern const uint8_t rclw_table[32]; |
450 | 83fb7adf | bellard | extern const uint8_t rclb_table[32]; |
451 | 2c0262af | bellard | |
452 | 2c0262af | bellard | static inline uint32_t compute_eflags(void) |
453 | 2c0262af | bellard | { |
454 | 2c0262af | bellard | return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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455 | 2c0262af | bellard | } |
456 | 2c0262af | bellard | |
457 | 2c0262af | bellard | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
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458 | 2c0262af | bellard | static inline void load_eflags(int eflags, int update_mask) |
459 | 2c0262af | bellard | { |
460 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
461 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1)); |
462 | 5fafdf24 | ths | env->eflags = (env->eflags & ~update_mask) | |
463 | 2c0262af | bellard | (eflags & update_mask); |
464 | 2c0262af | bellard | } |
465 | 2c0262af | bellard | |
466 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
467 | 0d1a29f9 | bellard | { |
468 | 0d1a29f9 | bellard | #ifdef reg_EAX
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469 | 0d1a29f9 | bellard | EAX = env->regs[R_EAX]; |
470 | 0d1a29f9 | bellard | #endif
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471 | 0d1a29f9 | bellard | #ifdef reg_ECX
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472 | 0d1a29f9 | bellard | ECX = env->regs[R_ECX]; |
473 | 0d1a29f9 | bellard | #endif
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474 | 0d1a29f9 | bellard | #ifdef reg_EDX
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475 | 0d1a29f9 | bellard | EDX = env->regs[R_EDX]; |
476 | 0d1a29f9 | bellard | #endif
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477 | 0d1a29f9 | bellard | #ifdef reg_EBX
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478 | 0d1a29f9 | bellard | EBX = env->regs[R_EBX]; |
479 | 0d1a29f9 | bellard | #endif
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480 | 0d1a29f9 | bellard | #ifdef reg_ESP
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481 | 0d1a29f9 | bellard | ESP = env->regs[R_ESP]; |
482 | 0d1a29f9 | bellard | #endif
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483 | 0d1a29f9 | bellard | #ifdef reg_EBP
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484 | 0d1a29f9 | bellard | EBP = env->regs[R_EBP]; |
485 | 0d1a29f9 | bellard | #endif
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486 | 0d1a29f9 | bellard | #ifdef reg_ESI
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487 | 0d1a29f9 | bellard | ESI = env->regs[R_ESI]; |
488 | 0d1a29f9 | bellard | #endif
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489 | 0d1a29f9 | bellard | #ifdef reg_EDI
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490 | 0d1a29f9 | bellard | EDI = env->regs[R_EDI]; |
491 | 0d1a29f9 | bellard | #endif
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492 | 0d1a29f9 | bellard | } |
493 | 0d1a29f9 | bellard | |
494 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
495 | 0d1a29f9 | bellard | { |
496 | 0d1a29f9 | bellard | #ifdef reg_EAX
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497 | 0d1a29f9 | bellard | env->regs[R_EAX] = EAX; |
498 | 0d1a29f9 | bellard | #endif
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499 | 0d1a29f9 | bellard | #ifdef reg_ECX
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500 | 0d1a29f9 | bellard | env->regs[R_ECX] = ECX; |
501 | 0d1a29f9 | bellard | #endif
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502 | 0d1a29f9 | bellard | #ifdef reg_EDX
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503 | 0d1a29f9 | bellard | env->regs[R_EDX] = EDX; |
504 | 0d1a29f9 | bellard | #endif
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505 | 0d1a29f9 | bellard | #ifdef reg_EBX
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506 | 0d1a29f9 | bellard | env->regs[R_EBX] = EBX; |
507 | 0d1a29f9 | bellard | #endif
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508 | 0d1a29f9 | bellard | #ifdef reg_ESP
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509 | 0d1a29f9 | bellard | env->regs[R_ESP] = ESP; |
510 | 0d1a29f9 | bellard | #endif
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511 | 0d1a29f9 | bellard | #ifdef reg_EBP
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512 | 0d1a29f9 | bellard | env->regs[R_EBP] = EBP; |
513 | 0d1a29f9 | bellard | #endif
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514 | 0d1a29f9 | bellard | #ifdef reg_ESI
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515 | 0d1a29f9 | bellard | env->regs[R_ESI] = ESI; |
516 | 0d1a29f9 | bellard | #endif
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517 | 0d1a29f9 | bellard | #ifdef reg_EDI
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518 | 0d1a29f9 | bellard | env->regs[R_EDI] = EDI; |
519 | 0d1a29f9 | bellard | #endif
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520 | 0d1a29f9 | bellard | } |
521 | bfed01fc | ths | |
522 | bfed01fc | ths | static inline int cpu_halted(CPUState *env) { |
523 | bfed01fc | ths | /* handle exit of HALTED state */
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524 | d0bdf2a2 | ths | if (!(env->hflags & HF_HALTED_MASK))
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525 | bfed01fc | ths | return 0; |
526 | bfed01fc | ths | /* disable halt condition */
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527 | 474ea849 | aurel32 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
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528 | 474ea849 | aurel32 | (env->eflags & IF_MASK)) || |
529 | 474ea849 | aurel32 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { |
530 | bfed01fc | ths | env->hflags &= ~HF_HALTED_MASK; |
531 | bfed01fc | ths | return 0; |
532 | bfed01fc | ths | } |
533 | bfed01fc | ths | return EXCP_HALTED;
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534 | bfed01fc | ths | } |