root / target-sparc / machine.c @ 1a14026e
History | View | Annotate | Download (2.6 kB)
1 | 8dd3dca3 | aurel32 | #include "hw/hw.h" |
---|---|---|---|
2 | 8dd3dca3 | aurel32 | #include "hw/boards.h" |
3 | 8dd3dca3 | aurel32 | |
4 | 8dd3dca3 | aurel32 | #include "exec-all.h" |
5 | 8dd3dca3 | aurel32 | |
6 | 8dd3dca3 | aurel32 | void register_machines(void) |
7 | 8dd3dca3 | aurel32 | { |
8 | 8dd3dca3 | aurel32 | #ifdef TARGET_SPARC64
|
9 | 8dd3dca3 | aurel32 | qemu_register_machine(&sun4u_machine); |
10 | 8dd3dca3 | aurel32 | #else
|
11 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss5_machine); |
12 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss10_machine); |
13 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss600mp_machine); |
14 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss20_machine); |
15 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss2_machine); |
16 | 8dd3dca3 | aurel32 | qemu_register_machine(&voyager_machine); |
17 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss_lx_machine); |
18 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss4_machine); |
19 | 8dd3dca3 | aurel32 | qemu_register_machine(&scls_machine); |
20 | 8dd3dca3 | aurel32 | qemu_register_machine(&sbook_machine); |
21 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss1000_machine); |
22 | 8dd3dca3 | aurel32 | qemu_register_machine(&ss2000_machine); |
23 | 8dd3dca3 | aurel32 | #endif
|
24 | 8dd3dca3 | aurel32 | } |
25 | 8dd3dca3 | aurel32 | |
26 | 8dd3dca3 | aurel32 | void cpu_save(QEMUFile *f, void *opaque) |
27 | 8dd3dca3 | aurel32 | { |
28 | 8dd3dca3 | aurel32 | CPUState *env = opaque; |
29 | 8dd3dca3 | aurel32 | int i;
|
30 | 8dd3dca3 | aurel32 | uint32_t tmp; |
31 | 8dd3dca3 | aurel32 | |
32 | 8dd3dca3 | aurel32 | for(i = 0; i < 8; i++) |
33 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->gregs[i]); |
34 | 1a14026e | blueswir1 | qemu_put_be32s(f, &env->nwindows); |
35 | 1a14026e | blueswir1 | for(i = 0; i < env->nwindows * 16; i++) |
36 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->regbase[i]); |
37 | 8dd3dca3 | aurel32 | |
38 | 8dd3dca3 | aurel32 | /* FPU */
|
39 | 8dd3dca3 | aurel32 | for(i = 0; i < TARGET_FPREGS; i++) { |
40 | 8dd3dca3 | aurel32 | union {
|
41 | 8dd3dca3 | aurel32 | float32 f; |
42 | 8dd3dca3 | aurel32 | uint32_t i; |
43 | 8dd3dca3 | aurel32 | } u; |
44 | 8dd3dca3 | aurel32 | u.f = env->fpr[i]; |
45 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.i); |
46 | 8dd3dca3 | aurel32 | } |
47 | 8dd3dca3 | aurel32 | |
48 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->pc); |
49 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->npc); |
50 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->y); |
51 | 8dd3dca3 | aurel32 | tmp = GET_PSR(env); |
52 | 8dd3dca3 | aurel32 | qemu_put_be32(f, tmp); |
53 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->fsr); |
54 | 8dd3dca3 | aurel32 | qemu_put_betls(f, &env->tbr); |
55 | 8dd3dca3 | aurel32 | #ifndef TARGET_SPARC64
|
56 | 8dd3dca3 | aurel32 | qemu_put_be32s(f, &env->wim); |
57 | 8dd3dca3 | aurel32 | /* MMU */
|
58 | 8dd3dca3 | aurel32 | for(i = 0; i < 16; i++) |
59 | 8dd3dca3 | aurel32 | qemu_put_be32s(f, &env->mmuregs[i]); |
60 | 8dd3dca3 | aurel32 | #endif
|
61 | 8dd3dca3 | aurel32 | } |
62 | 8dd3dca3 | aurel32 | |
63 | 8dd3dca3 | aurel32 | int cpu_load(QEMUFile *f, void *opaque, int version_id) |
64 | 8dd3dca3 | aurel32 | { |
65 | 8dd3dca3 | aurel32 | CPUState *env = opaque; |
66 | 8dd3dca3 | aurel32 | int i;
|
67 | 8dd3dca3 | aurel32 | uint32_t tmp; |
68 | 8dd3dca3 | aurel32 | |
69 | 1a14026e | blueswir1 | if (version_id != 4) |
70 | 1a14026e | blueswir1 | return -EINVAL;
|
71 | 8dd3dca3 | aurel32 | for(i = 0; i < 8; i++) |
72 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->gregs[i]); |
73 | 1a14026e | blueswir1 | qemu_get_be32s(f, &env->nwindows); |
74 | 1a14026e | blueswir1 | for(i = 0; i < env->nwindows * 16; i++) |
75 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->regbase[i]); |
76 | 8dd3dca3 | aurel32 | |
77 | 8dd3dca3 | aurel32 | /* FPU */
|
78 | 8dd3dca3 | aurel32 | for(i = 0; i < TARGET_FPREGS; i++) { |
79 | 8dd3dca3 | aurel32 | union {
|
80 | 8dd3dca3 | aurel32 | float32 f; |
81 | 8dd3dca3 | aurel32 | uint32_t i; |
82 | 8dd3dca3 | aurel32 | } u; |
83 | 8dd3dca3 | aurel32 | u.i = qemu_get_be32(f); |
84 | 8dd3dca3 | aurel32 | env->fpr[i] = u.f; |
85 | 8dd3dca3 | aurel32 | } |
86 | 8dd3dca3 | aurel32 | |
87 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->pc); |
88 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->npc); |
89 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->y); |
90 | 8dd3dca3 | aurel32 | tmp = qemu_get_be32(f); |
91 | 8dd3dca3 | aurel32 | env->cwp = 0; /* needed to ensure that the wrapping registers are |
92 | 8dd3dca3 | aurel32 | correctly updated */
|
93 | 8dd3dca3 | aurel32 | PUT_PSR(env, tmp); |
94 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->fsr); |
95 | 8dd3dca3 | aurel32 | qemu_get_betls(f, &env->tbr); |
96 | 8dd3dca3 | aurel32 | #ifndef TARGET_SPARC64
|
97 | 8dd3dca3 | aurel32 | qemu_get_be32s(f, &env->wim); |
98 | 8dd3dca3 | aurel32 | /* MMU */
|
99 | 8dd3dca3 | aurel32 | for(i = 0; i < 16; i++) |
100 | 8dd3dca3 | aurel32 | qemu_get_be32s(f, &env->mmuregs[i]); |
101 | 8dd3dca3 | aurel32 | #endif
|
102 | 8dd3dca3 | aurel32 | tlb_flush(env, 1);
|
103 | 8dd3dca3 | aurel32 | return 0; |
104 | 8dd3dca3 | aurel32 | } |
105 | 8dd3dca3 | aurel32 |