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1	7a3f1944	bellard	/*
2	7a3f1944	bellard	SPARC translation
3	7a3f1944	bellard
4	7a3f1944	bellard	Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5	3475187d	bellard	Copyright (C) 2003-2005 Fabrice Bellard
6	7a3f1944	bellard
7	7a3f1944	bellard	This library is free software; you can redistribute it and/or
8	7a3f1944	bellard	modify it under the terms of the GNU Lesser General Public
9	7a3f1944	bellard	License as published by the Free Software Foundation; either
10	7a3f1944	bellard	version 2 of the License, or (at your option) any later version.
11	7a3f1944	bellard
12	7a3f1944	bellard	This library is distributed in the hope that it will be useful,
13	7a3f1944	bellard	but WITHOUT ANY WARRANTY; without even the implied warranty of
14	7a3f1944	bellard	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15	7a3f1944	bellard	Lesser General Public License for more details.
16	7a3f1944	bellard
17	7a3f1944	bellard	You should have received a copy of the GNU Lesser General Public
18	7a3f1944	bellard	License along with this library; if not, write to the Free Software
19	7a3f1944	bellard	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20	7a3f1944	bellard	*/
21	7a3f1944	bellard
22	7a3f1944	bellard	#include <stdarg.h>
23	7a3f1944	bellard	#include <stdlib.h>
24	7a3f1944	bellard	#include <stdio.h>
25	7a3f1944	bellard	#include <string.h>
26	7a3f1944	bellard	#include <inttypes.h>
27	7a3f1944	bellard
28	7a3f1944	bellard	#include "cpu.h"
29	7a3f1944	bellard	#include "exec-all.h"
30	7a3f1944	bellard	#include "disas.h"
31	1a2fb1c0	blueswir1	#include "helper.h"
32	57fec1fe	bellard	#include "tcg-op.h"
33	7a3f1944	bellard
34	7a3f1944	bellard	#define DEBUG_DISAS
35	7a3f1944	bellard
36	72cbca10	bellard	#define DYNAMIC_PC 1 /* dynamic pc value */
37	72cbca10	bellard	#define JUMP_PC 2 /* dynamic pc value which takes only two values
38	72cbca10	bellard	according to jump_pc[T2] */
39	72cbca10	bellard
40	1a2fb1c0	blueswir1	/* global register indexes */
41	77f193da	blueswir1	static TCGv cpu_env, cpu_T[2], cpu_regwptr;
42	77f193da	blueswir1	static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43	48d5c82b	blueswir1	static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
44	6ae20372	blueswir1	static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
45	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
46	dc99a3f2	blueswir1	static TCGv cpu_xcc;
47	dc99a3f2	blueswir1	#endif
48	1a2fb1c0	blueswir1	/* local register indexes (only used inside old micro ops) */
49	8911f501	blueswir1	static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50	1a2fb1c0	blueswir1
51	7a3f1944	bellard	typedef struct DisasContext {
52	0f8a249a	blueswir1	target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
53	0f8a249a	blueswir1	target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
54	72cbca10	bellard	target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
55	cf495bcf	bellard	int is_br;
56	e8af50a3	bellard	int mem_idx;
57	a80dde08	bellard	int fpu_enabled;
58	cf495bcf	bellard	struct TranslationBlock *tb;
59	64a88d5d	blueswir1	uint32_t features;
60	7a3f1944	bellard	} DisasContext;
61	7a3f1944	bellard
62	3475187d	bellard	// This function uses non-native bit order
63	7a3f1944	bellard	#define GET_FIELD(X, FROM, TO) \
64	7a3f1944	bellard	((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
65	7a3f1944	bellard
66	3475187d	bellard	// This function uses the order in the manuals, i.e. bit 0 is 2^0
67	3475187d	bellard	#define GET_FIELD_SP(X, FROM, TO) \
68	3475187d	bellard	GET_FIELD(X, 31 - (TO), 31 - (FROM))
69	3475187d	bellard
70	3475187d	bellard	#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
71	46d38ba8	blueswir1	#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
72	3475187d	bellard
73	3475187d	bellard	#ifdef TARGET_SPARC64
74	19f329ad	blueswir1	#define FFPREG(r) (r)
75	0387d928	blueswir1	#define DFPREG(r) (((r & 1) << 5) \| (r & 0x1e))
76	1f587329	blueswir1	#define QFPREG(r) (((r & 1) << 5) \| (r & 0x1c))
77	3475187d	bellard	#else
78	19f329ad	blueswir1	#define FFPREG(r) (r)
79	c185970a	blueswir1	#define DFPREG(r) (r & 0x1e)
80	1f587329	blueswir1	#define QFPREG(r) (r & 0x1c)
81	3475187d	bellard	#endif
82	3475187d	bellard
83	3475187d	bellard	static int sign_extend(int x, int len)
84	3475187d	bellard	{
85	3475187d	bellard	len = 32 - len;
86	3475187d	bellard	return (x << len) >> len;
87	3475187d	bellard	}
88	3475187d	bellard
89	7a3f1944	bellard	#define IS_IMM (insn & (1<<13))
90	7a3f1944	bellard
91	ff07ec83	blueswir1	/* floating point registers moves */
92	ff07ec83	blueswir1	static void gen_op_load_fpr_FT0(unsigned int src)
93	ff07ec83	blueswir1	{
94	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
95	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
96	3475187d	bellard	}
97	ff07ec83	blueswir1
98	ff07ec83	blueswir1	static void gen_op_load_fpr_FT1(unsigned int src)
99	ff07ec83	blueswir1	{
100	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
101	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
102	e8af50a3	bellard	}
103	e8af50a3	bellard
104	ff07ec83	blueswir1	static void gen_op_store_FT0_fpr(unsigned int dst)
105	ff07ec83	blueswir1	{
106	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
107	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
108	ff07ec83	blueswir1	}
109	ff07ec83	blueswir1
110	ff07ec83	blueswir1	static void gen_op_load_fpr_DT0(unsigned int src)
111	ff07ec83	blueswir1	{
112	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
113	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
114	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
115	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
116	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
117	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
118	ff07ec83	blueswir1	}
119	ff07ec83	blueswir1
120	ff07ec83	blueswir1	static void gen_op_load_fpr_DT1(unsigned int src)
121	ff07ec83	blueswir1	{
122	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
123	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
124	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
125	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
126	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
128	ff07ec83	blueswir1	}
129	ff07ec83	blueswir1
130	ff07ec83	blueswir1	static void gen_op_store_DT0_fpr(unsigned int dst)
131	ff07ec83	blueswir1	{
132	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
133	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
134	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
135	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
137	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
138	ff07ec83	blueswir1	}
139	ff07ec83	blueswir1
140	ff07ec83	blueswir1	static void gen_op_load_fpr_QT0(unsigned int src)
141	ff07ec83	blueswir1	{
142	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
143	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
144	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
145	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
146	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
147	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
148	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
149	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
151	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
152	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
154	ff07ec83	blueswir1	}
155	ff07ec83	blueswir1
156	ff07ec83	blueswir1	static void gen_op_load_fpr_QT1(unsigned int src)
157	ff07ec83	blueswir1	{
158	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
159	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
160	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
161	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
162	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
163	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
164	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
165	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
167	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
168	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
170	ff07ec83	blueswir1	}
171	ff07ec83	blueswir1
172	ff07ec83	blueswir1	static void gen_op_store_QT0_fpr(unsigned int dst)
173	ff07ec83	blueswir1	{
174	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
175	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
176	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
177	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
179	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
180	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
182	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
183	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
185	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
186	ff07ec83	blueswir1	}
187	1f587329	blueswir1
188	81ad8ba2	blueswir1	/* moves */
189	81ad8ba2	blueswir1	#ifdef CONFIG_USER_ONLY
190	3475187d	bellard	#define supervisor(dc) 0
191	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
192	e9ebed4d	blueswir1	#define hypervisor(dc) 0
193	81ad8ba2	blueswir1	#endif
194	3475187d	bellard	#else
195	6f27aba6	blueswir1	#define supervisor(dc) (dc->mem_idx >= 1)
196	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
197	81ad8ba2	blueswir1	#define hypervisor(dc) (dc->mem_idx == 2)
198	6f27aba6	blueswir1	#else
199	3475187d	bellard	#endif
200	81ad8ba2	blueswir1	#endif
201	81ad8ba2	blueswir1
202	1a2fb1c0	blueswir1	#ifdef TARGET_ABI32
203	8911f501	blueswir1	#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
204	1a2fb1c0	blueswir1	#else
205	1a2fb1c0	blueswir1	#define ABI32_MASK(addr)
206	1a2fb1c0	blueswir1	#endif
207	3391c818	blueswir1
208	1a2fb1c0	blueswir1	static inline void gen_movl_reg_TN(int reg, TCGv tn)
209	81ad8ba2	blueswir1	{
210	1a2fb1c0	blueswir1	if (reg == 0)
211	1a2fb1c0	blueswir1	tcg_gen_movi_tl(tn, 0);
212	1a2fb1c0	blueswir1	else if (reg < 8)
213	f5069b26	blueswir1	tcg_gen_mov_tl(tn, cpu_gregs[reg]);
214	1a2fb1c0	blueswir1	else {
215	1a2fb1c0	blueswir1	tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
216	81ad8ba2	blueswir1	}
217	81ad8ba2	blueswir1	}
218	81ad8ba2	blueswir1
219	1a2fb1c0	blueswir1	static inline void gen_movl_TN_reg(int reg, TCGv tn)
220	81ad8ba2	blueswir1	{
221	1a2fb1c0	blueswir1	if (reg == 0)
222	1a2fb1c0	blueswir1	return;
223	1a2fb1c0	blueswir1	else if (reg < 8)
224	f5069b26	blueswir1	tcg_gen_mov_tl(cpu_gregs[reg], tn);
225	1a2fb1c0	blueswir1	else {
226	1a2fb1c0	blueswir1	tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
227	81ad8ba2	blueswir1	}
228	81ad8ba2	blueswir1	}
229	81ad8ba2	blueswir1
230	5fafdf24	ths	static inline void gen_goto_tb(DisasContext *s, int tb_num,
231	6e256c93	bellard	target_ulong pc, target_ulong npc)
232	6e256c93	bellard	{
233	6e256c93	bellard	TranslationBlock *tb;
234	6e256c93	bellard
235	6e256c93	bellard	tb = s->tb;
236	6e256c93	bellard	if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
237	6e256c93	bellard	(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
238	6e256c93	bellard	/* jump to same page: we can use a direct jump */
239	57fec1fe	bellard	tcg_gen_goto_tb(tb_num);
240	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
241	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
242	57fec1fe	bellard	tcg_gen_exit_tb((long)tb + tb_num);
243	6e256c93	bellard	} else {
244	6e256c93	bellard	/* jump to another page: currently not optimized */
245	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
246	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
247	57fec1fe	bellard	tcg_gen_exit_tb(0);
248	6e256c93	bellard	}
249	6e256c93	bellard	}
250	6e256c93	bellard
251	19f329ad	blueswir1	// XXX suboptimal
252	19f329ad	blueswir1	static inline void gen_mov_reg_N(TCGv reg, TCGv src)
253	19f329ad	blueswir1	{
254	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
255	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
256	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
257	19f329ad	blueswir1	}
258	19f329ad	blueswir1
259	19f329ad	blueswir1	static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
260	19f329ad	blueswir1	{
261	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
262	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
263	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
264	19f329ad	blueswir1	}
265	19f329ad	blueswir1
266	19f329ad	blueswir1	static inline void gen_mov_reg_V(TCGv reg, TCGv src)
267	19f329ad	blueswir1	{
268	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
269	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
270	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
271	19f329ad	blueswir1	}
272	19f329ad	blueswir1
273	19f329ad	blueswir1	static inline void gen_mov_reg_C(TCGv reg, TCGv src)
274	19f329ad	blueswir1	{
275	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
276	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
277	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
278	19f329ad	blueswir1	}
279	19f329ad	blueswir1
280	ce5b3c3d	blueswir1	static inline void gen_cc_clear_icc(void)
281	dc99a3f2	blueswir1	{
282	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_psr, 0);
283	ce5b3c3d	blueswir1	}
284	ce5b3c3d	blueswir1
285	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
286	ce5b3c3d	blueswir1	static inline void gen_cc_clear_xcc(void)
287	ce5b3c3d	blueswir1	{
288	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_xcc, 0);
289	dc99a3f2	blueswir1	}
290	ce5b3c3d	blueswir1	#endif
291	dc99a3f2	blueswir1
292	dc99a3f2	blueswir1	/* old op:
293	dc99a3f2	blueswir1	if (!T0)
294	dc99a3f2	blueswir1	env->psr \|= PSR_ZERO;
295	dc99a3f2	blueswir1	if ((int32_t) T0 < 0)
296	dc99a3f2	blueswir1	env->psr \|= PSR_NEG;
297	dc99a3f2	blueswir1	*/
298	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_icc(TCGv dst)
299	dc99a3f2	blueswir1	{
300	8911f501	blueswir1	TCGv r_temp;
301	dc99a3f2	blueswir1	int l1, l2;
302	dc99a3f2	blueswir1
303	dc99a3f2	blueswir1	l1 = gen_new_label();
304	dc99a3f2	blueswir1	l2 = gen_new_label();
305	8911f501	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
306	8911f501	blueswir1	tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
307	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
308	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
309	dc99a3f2	blueswir1	gen_set_label(l1);
310	bdf46ea2	blueswir1	tcg_gen_ext_i32_tl(r_temp, dst);
311	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
312	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
313	dc99a3f2	blueswir1	gen_set_label(l2);
314	2ea815ca	blueswir1	tcg_temp_free(r_temp);
315	ce5b3c3d	blueswir1	}
316	ce5b3c3d	blueswir1
317	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
318	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_xcc(TCGv dst)
319	ce5b3c3d	blueswir1	{
320	ce5b3c3d	blueswir1	int l1, l2;
321	ce5b3c3d	blueswir1
322	ce5b3c3d	blueswir1	l1 = gen_new_label();
323	ce5b3c3d	blueswir1	l2 = gen_new_label();
324	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
325	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
326	ce5b3c3d	blueswir1	gen_set_label(l1);
327	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
328	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
329	ce5b3c3d	blueswir1	gen_set_label(l2);
330	dc99a3f2	blueswir1	}
331	ce5b3c3d	blueswir1	#endif
332	dc99a3f2	blueswir1
333	dc99a3f2	blueswir1	/* old op:
334	dc99a3f2	blueswir1	if (T0 < src1)
335	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
336	dc99a3f2	blueswir1	*/
337	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
338	dc99a3f2	blueswir1	{
339	8911f501	blueswir1	TCGv r_temp;
340	dc99a3f2	blueswir1	int l1;
341	dc99a3f2	blueswir1
342	dc99a3f2	blueswir1	l1 = gen_new_label();
343	8911f501	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
344	8911f501	blueswir1	tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
345	8911f501	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
346	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
347	dc99a3f2	blueswir1	gen_set_label(l1);
348	2ea815ca	blueswir1	tcg_temp_free(r_temp);
349	ce5b3c3d	blueswir1	}
350	ce5b3c3d	blueswir1
351	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
352	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
353	ce5b3c3d	blueswir1	{
354	ce5b3c3d	blueswir1	int l1;
355	dc99a3f2	blueswir1
356	ce5b3c3d	blueswir1	l1 = gen_new_label();
357	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
358	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
359	ce5b3c3d	blueswir1	gen_set_label(l1);
360	dc99a3f2	blueswir1	}
361	ce5b3c3d	blueswir1	#endif
362	dc99a3f2	blueswir1
363	dc99a3f2	blueswir1	/* old op:
364	dc99a3f2	blueswir1	if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
365	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
366	dc99a3f2	blueswir1	*/
367	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
368	dc99a3f2	blueswir1	{
369	0425bee5	blueswir1	TCGv r_temp;
370	dc99a3f2	blueswir1
371	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
372	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
373	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
374	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
375	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
376	0425bee5	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
377	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
378	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
379	2ea815ca	blueswir1	tcg_temp_free(r_temp);
380	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
381	ce5b3c3d	blueswir1	}
382	ce5b3c3d	blueswir1
383	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
384	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
385	ce5b3c3d	blueswir1	{
386	ce5b3c3d	blueswir1	TCGv r_temp;
387	ce5b3c3d	blueswir1
388	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
389	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
390	ce5b3c3d	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
391	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
392	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
393	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
394	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
395	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
396	2ea815ca	blueswir1	tcg_temp_free(r_temp);
397	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
398	dc99a3f2	blueswir1	}
399	ce5b3c3d	blueswir1	#endif
400	dc99a3f2	blueswir1
401	dc99a3f2	blueswir1	static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
402	dc99a3f2	blueswir1	{
403	2ea815ca	blueswir1	TCGv r_temp, r_const;
404	dc99a3f2	blueswir1	int l1;
405	dc99a3f2	blueswir1
406	dc99a3f2	blueswir1	l1 = gen_new_label();
407	dc99a3f2	blueswir1
408	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
409	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
410	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
411	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
412	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
413	0425bee5	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
414	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
415	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
416	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
417	2ea815ca	blueswir1	tcg_temp_free(r_const);
418	dc99a3f2	blueswir1	gen_set_label(l1);
419	2ea815ca	blueswir1	tcg_temp_free(r_temp);
420	dc99a3f2	blueswir1	}
421	dc99a3f2	blueswir1
422	dc99a3f2	blueswir1	static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
423	dc99a3f2	blueswir1	{
424	dc99a3f2	blueswir1	int l1;
425	dc99a3f2	blueswir1
426	dc99a3f2	blueswir1	l1 = gen_new_label();
427	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
428	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
429	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
430	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
431	dc99a3f2	blueswir1	gen_set_label(l1);
432	dc99a3f2	blueswir1	}
433	dc99a3f2	blueswir1
434	dc99a3f2	blueswir1	static inline void gen_tag_tv(TCGv src1, TCGv src2)
435	dc99a3f2	blueswir1	{
436	dc99a3f2	blueswir1	int l1;
437	2ea815ca	blueswir1	TCGv r_const;
438	dc99a3f2	blueswir1
439	dc99a3f2	blueswir1	l1 = gen_new_label();
440	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
441	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
442	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
443	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
444	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
445	2ea815ca	blueswir1	tcg_temp_free(r_const);
446	dc99a3f2	blueswir1	gen_set_label(l1);
447	dc99a3f2	blueswir1	}
448	dc99a3f2	blueswir1
449	4af984a7	blueswir1	static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
450	dc99a3f2	blueswir1	{
451	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
452	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
453	4af984a7	blueswir1	tcg_gen_add_tl(dst, src1, src2);
454	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
455	ce5b3c3d	blueswir1	gen_cc_clear_icc();
456	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
457	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
458	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
459	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
460	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
461	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
462	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
463	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
464	ce5b3c3d	blueswir1	#endif
465	dc99a3f2	blueswir1	}
466	dc99a3f2	blueswir1
467	4af984a7	blueswir1	static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
468	dc99a3f2	blueswir1	{
469	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
470	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
471	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
472	4af984a7	blueswir1	tcg_gen_add_tl(dst, src1, cpu_tmp0);
473	ce5b3c3d	blueswir1	gen_cc_clear_icc();
474	4af984a7	blueswir1	gen_cc_C_add_icc(dst, cpu_cc_src);
475	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
476	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
477	4af984a7	blueswir1	gen_cc_C_add_xcc(dst, cpu_cc_src);
478	ce5b3c3d	blueswir1	#endif
479	6f551262	blueswir1	tcg_gen_add_tl(dst, dst, cpu_cc_src2);
480	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
481	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
482	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
483	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
484	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
485	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
486	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
487	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
488	ce5b3c3d	blueswir1	#endif
489	dc99a3f2	blueswir1	}
490	dc99a3f2	blueswir1
491	4af984a7	blueswir1	static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
492	dc99a3f2	blueswir1	{
493	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
494	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
495	4af984a7	blueswir1	tcg_gen_add_tl(dst, src1, src2);
496	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
497	ce5b3c3d	blueswir1	gen_cc_clear_icc();
498	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
499	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
500	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
501	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
502	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
503	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
504	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
505	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
506	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
507	ce5b3c3d	blueswir1	#endif
508	dc99a3f2	blueswir1	}
509	dc99a3f2	blueswir1
510	4af984a7	blueswir1	static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
511	dc99a3f2	blueswir1	{
512	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
513	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
514	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
515	4af984a7	blueswir1	tcg_gen_add_tl(dst, src1, src2);
516	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
517	6f551262	blueswir1	gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
518	ce5b3c3d	blueswir1	gen_cc_clear_icc();
519	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
520	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
521	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
522	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
523	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
524	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
525	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
526	ce5b3c3d	blueswir1	#endif
527	dc99a3f2	blueswir1	}
528	dc99a3f2	blueswir1
529	dc99a3f2	blueswir1	/* old op:
530	dc99a3f2	blueswir1	if (src1 < T1)
531	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
532	dc99a3f2	blueswir1	*/
533	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
534	dc99a3f2	blueswir1	{
535	8911f501	blueswir1	TCGv r_temp1, r_temp2;
536	dc99a3f2	blueswir1	int l1;
537	dc99a3f2	blueswir1
538	dc99a3f2	blueswir1	l1 = gen_new_label();
539	8911f501	blueswir1	r_temp1 = tcg_temp_new(TCG_TYPE_TL);
540	8911f501	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_TL);
541	8911f501	blueswir1	tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
542	8911f501	blueswir1	tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
543	8911f501	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
544	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
545	dc99a3f2	blueswir1	gen_set_label(l1);
546	2ea815ca	blueswir1	tcg_temp_free(r_temp1);
547	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
548	ce5b3c3d	blueswir1	}
549	ce5b3c3d	blueswir1
550	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
551	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
552	ce5b3c3d	blueswir1	{
553	ce5b3c3d	blueswir1	int l1;
554	dc99a3f2	blueswir1
555	ce5b3c3d	blueswir1	l1 = gen_new_label();
556	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
557	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
558	ce5b3c3d	blueswir1	gen_set_label(l1);
559	dc99a3f2	blueswir1	}
560	ce5b3c3d	blueswir1	#endif
561	dc99a3f2	blueswir1
562	dc99a3f2	blueswir1	/* old op:
563	dc99a3f2	blueswir1	if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
564	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
565	dc99a3f2	blueswir1	*/
566	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
567	dc99a3f2	blueswir1	{
568	0425bee5	blueswir1	TCGv r_temp;
569	dc99a3f2	blueswir1
570	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
571	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
572	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
573	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
574	0425bee5	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
575	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
576	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
577	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
578	2ea815ca	blueswir1	tcg_temp_free(r_temp);
579	ce5b3c3d	blueswir1	}
580	ce5b3c3d	blueswir1
581	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
582	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
583	ce5b3c3d	blueswir1	{
584	ce5b3c3d	blueswir1	TCGv r_temp;
585	ce5b3c3d	blueswir1
586	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
587	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
588	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
591	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
592	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
594	2ea815ca	blueswir1	tcg_temp_free(r_temp);
595	dc99a3f2	blueswir1	}
596	ce5b3c3d	blueswir1	#endif
597	dc99a3f2	blueswir1
598	dc99a3f2	blueswir1	static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
599	dc99a3f2	blueswir1	{
600	2ea815ca	blueswir1	TCGv r_temp, r_const;
601	dc99a3f2	blueswir1	int l1;
602	dc99a3f2	blueswir1
603	dc99a3f2	blueswir1	l1 = gen_new_label();
604	dc99a3f2	blueswir1
605	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
606	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
607	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
608	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
609	0425bee5	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
610	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
611	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
612	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
613	2ea815ca	blueswir1	tcg_temp_free(r_const);
614	dc99a3f2	blueswir1	gen_set_label(l1);
615	2ea815ca	blueswir1	tcg_temp_free(r_temp);
616	dc99a3f2	blueswir1	}
617	dc99a3f2	blueswir1
618	4af984a7	blueswir1	static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
619	dc99a3f2	blueswir1	{
620	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
621	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
622	4af984a7	blueswir1	tcg_gen_sub_tl(dst, src1, src2);
623	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
624	ce5b3c3d	blueswir1	gen_cc_clear_icc();
625	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
626	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
627	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
628	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
629	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
630	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
631	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
632	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
633	ce5b3c3d	blueswir1	#endif
634	dc99a3f2	blueswir1	}
635	dc99a3f2	blueswir1
636	4af984a7	blueswir1	static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
637	dc99a3f2	blueswir1	{
638	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
639	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
640	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
641	4af984a7	blueswir1	tcg_gen_sub_tl(dst, src1, cpu_tmp0);
642	ce5b3c3d	blueswir1	gen_cc_clear_icc();
643	4af984a7	blueswir1	gen_cc_C_sub_icc(dst, cpu_cc_src);
644	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
645	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
646	4af984a7	blueswir1	gen_cc_C_sub_xcc(dst, cpu_cc_src);
647	ce5b3c3d	blueswir1	#endif
648	6f551262	blueswir1	tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
649	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
650	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
651	ba28189b	blueswir1	gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
652	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
653	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
654	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
655	ba28189b	blueswir1	gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
656	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
657	ce5b3c3d	blueswir1	#endif
658	dc99a3f2	blueswir1	}
659	dc99a3f2	blueswir1
660	4af984a7	blueswir1	static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
661	dc99a3f2	blueswir1	{
662	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
663	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
664	4af984a7	blueswir1	tcg_gen_sub_tl(dst, src1, src2);
665	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
666	ce5b3c3d	blueswir1	gen_cc_clear_icc();
667	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
668	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
669	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
670	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
671	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
672	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
673	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
674	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
675	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
676	ce5b3c3d	blueswir1	#endif
677	dc99a3f2	blueswir1	}
678	dc99a3f2	blueswir1
679	4af984a7	blueswir1	static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
680	dc99a3f2	blueswir1	{
681	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
682	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
683	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
684	4af984a7	blueswir1	tcg_gen_sub_tl(dst, src1, src2);
685	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
686	6f551262	blueswir1	gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
687	ce5b3c3d	blueswir1	gen_cc_clear_icc();
688	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
689	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
690	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
691	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
692	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
693	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
694	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
695	ce5b3c3d	blueswir1	#endif
696	dc99a3f2	blueswir1	}
697	dc99a3f2	blueswir1
698	4af984a7	blueswir1	static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
699	d9bdab86	blueswir1	{
700	7127fe84	blueswir1	TCGv r_temp, r_temp2;
701	6f551262	blueswir1	int l1;
702	d9bdab86	blueswir1
703	d9bdab86	blueswir1	l1 = gen_new_label();
704	d9bdab86	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
705	7127fe84	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I32);
706	d9bdab86	blueswir1
707	d9bdab86	blueswir1	/* old op:
708	d9bdab86	blueswir1	if (!(env->y & 1))
709	d9bdab86	blueswir1	T1 = 0;
710	d9bdab86	blueswir1	*/
711	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
712	7127fe84	blueswir1	tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
713	7127fe84	blueswir1	tcg_gen_trunc_tl_i32(r_temp2, r_temp);
714	7127fe84	blueswir1	tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
715	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
716	cb63669a	pbrook	tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
717	d9bdab86	blueswir1	tcg_gen_movi_tl(cpu_cc_src2, 0);
718	6f551262	blueswir1	gen_set_label(l1);
719	d9bdab86	blueswir1
720	d9bdab86	blueswir1	// b2 = T0 & 1;
721	d9bdab86	blueswir1	// env->y = (b2 << 31) \| (env->y >> 1);
722	6f551262	blueswir1	tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
723	7127fe84	blueswir1	tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
724	7127fe84	blueswir1	tcg_gen_shli_i32(r_temp2, r_temp2, 31);
725	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
726	8911f501	blueswir1	tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
727	7127fe84	blueswir1	tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
728	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
729	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
730	d9bdab86	blueswir1
731	d9bdab86	blueswir1	// b1 = N ^ V;
732	d9bdab86	blueswir1	gen_mov_reg_N(cpu_tmp0, cpu_psr);
733	d9bdab86	blueswir1	gen_mov_reg_V(r_temp, cpu_psr);
734	d9bdab86	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
735	2ea815ca	blueswir1	tcg_temp_free(r_temp);
736	d9bdab86	blueswir1
737	d9bdab86	blueswir1	// T0 = (b1 << 31) \| (T0 >> 1);
738	d9bdab86	blueswir1	// src1 = T0;
739	d9bdab86	blueswir1	tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
740	6f551262	blueswir1	tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
741	d9bdab86	blueswir1	tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
742	d9bdab86	blueswir1
743	d9bdab86	blueswir1	/* do addition and update flags */
744	4af984a7	blueswir1	tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
745	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
746	d9bdab86	blueswir1
747	ce5b3c3d	blueswir1	gen_cc_clear_icc();
748	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
749	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
750	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
751	d9bdab86	blueswir1	}
752	d9bdab86	blueswir1
753	4af984a7	blueswir1	static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
754	8879d139	blueswir1	{
755	8879d139	blueswir1	TCGv r_temp, r_temp2;
756	8879d139	blueswir1
757	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
758	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
759	8879d139	blueswir1
760	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp, src2);
761	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp2, src1);
762	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
763	8879d139	blueswir1
764	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
765	8879d139	blueswir1	tcg_gen_trunc_i64_i32(r_temp, r_temp);
766	8879d139	blueswir1	tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
767	2ea815ca	blueswir1	tcg_temp_free(r_temp);
768	8879d139	blueswir1	#ifdef TARGET_SPARC64
769	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
770	8879d139	blueswir1	#else
771	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
772	8879d139	blueswir1	#endif
773	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
774	8879d139	blueswir1	}
775	8879d139	blueswir1
776	4af984a7	blueswir1	static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
777	8879d139	blueswir1	{
778	8879d139	blueswir1	TCGv r_temp, r_temp2;
779	8879d139	blueswir1
780	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
781	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
782	8879d139	blueswir1
783	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp, src2);
784	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp2, src1);
785	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
786	8879d139	blueswir1
787	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
788	8879d139	blueswir1	tcg_gen_trunc_i64_i32(r_temp, r_temp);
789	8879d139	blueswir1	tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
790	2ea815ca	blueswir1	tcg_temp_free(r_temp);
791	8879d139	blueswir1	#ifdef TARGET_SPARC64
792	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
793	8879d139	blueswir1	#else
794	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
795	8879d139	blueswir1	#endif
796	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
797	8879d139	blueswir1	}
798	8879d139	blueswir1
799	1a7b60e7	blueswir1	#ifdef TARGET_SPARC64
800	8911f501	blueswir1	static inline void gen_trap_ifdivzero_tl(TCGv divisor)
801	1a7b60e7	blueswir1	{
802	2ea815ca	blueswir1	TCGv r_const;
803	1a7b60e7	blueswir1	int l1;
804	1a7b60e7	blueswir1
805	1a7b60e7	blueswir1	l1 = gen_new_label();
806	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
807	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_DIV_ZERO);
808	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
809	2ea815ca	blueswir1	tcg_temp_free(r_const);
810	1a7b60e7	blueswir1	gen_set_label(l1);
811	1a7b60e7	blueswir1	}
812	1a7b60e7	blueswir1
813	4af984a7	blueswir1	static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
814	1a7b60e7	blueswir1	{
815	1a7b60e7	blueswir1	int l1, l2;
816	1a7b60e7	blueswir1
817	1a7b60e7	blueswir1	l1 = gen_new_label();
818	1a7b60e7	blueswir1	l2 = gen_new_label();
819	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
820	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
821	4af984a7	blueswir1	gen_trap_ifdivzero_tl(src2);
822	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
823	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
824	4af984a7	blueswir1	tcg_gen_movi_i64(dst, INT64_MIN);
825	06b3e1b3	blueswir1	tcg_gen_br(l2);
826	1a7b60e7	blueswir1	gen_set_label(l1);
827	6f551262	blueswir1	tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
828	1a7b60e7	blueswir1	gen_set_label(l2);
829	1a7b60e7	blueswir1	}
830	1a7b60e7	blueswir1	#endif
831	1a7b60e7	blueswir1
832	4af984a7	blueswir1	static inline void gen_op_div_cc(TCGv dst)
833	dc99a3f2	blueswir1	{
834	dc99a3f2	blueswir1	int l1;
835	dc99a3f2	blueswir1
836	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
837	ce5b3c3d	blueswir1	gen_cc_clear_icc();
838	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
839	dc99a3f2	blueswir1	l1 = gen_new_label();
840	3b89f26c	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
841	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
842	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
843	dc99a3f2	blueswir1	gen_set_label(l1);
844	dc99a3f2	blueswir1	}
845	dc99a3f2	blueswir1
846	4af984a7	blueswir1	static inline void gen_op_logic_cc(TCGv dst)
847	dc99a3f2	blueswir1	{
848	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
849	ba28189b	blueswir1
850	ce5b3c3d	blueswir1	gen_cc_clear_icc();
851	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
852	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
853	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
854	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
855	ce5b3c3d	blueswir1	#endif
856	dc99a3f2	blueswir1	}
857	dc99a3f2	blueswir1
858	19f329ad	blueswir1	// 1
859	19f329ad	blueswir1	static inline void gen_op_eval_ba(TCGv dst)
860	19f329ad	blueswir1	{
861	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 1);
862	19f329ad	blueswir1	}
863	19f329ad	blueswir1
864	19f329ad	blueswir1	// Z
865	19f329ad	blueswir1	static inline void gen_op_eval_be(TCGv dst, TCGv src)
866	19f329ad	blueswir1	{
867	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
868	19f329ad	blueswir1	}
869	19f329ad	blueswir1
870	19f329ad	blueswir1	// Z \| (N ^ V)
871	19f329ad	blueswir1	static inline void gen_op_eval_ble(TCGv dst, TCGv src)
872	19f329ad	blueswir1	{
873	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
874	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
875	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
876	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
877	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
878	19f329ad	blueswir1	}
879	19f329ad	blueswir1
880	19f329ad	blueswir1	// N ^ V
881	19f329ad	blueswir1	static inline void gen_op_eval_bl(TCGv dst, TCGv src)
882	19f329ad	blueswir1	{
883	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
884	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
885	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
886	19f329ad	blueswir1	}
887	19f329ad	blueswir1
888	19f329ad	blueswir1	// C \| Z
889	19f329ad	blueswir1	static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
890	19f329ad	blueswir1	{
891	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
892	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
893	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
894	19f329ad	blueswir1	}
895	19f329ad	blueswir1
896	19f329ad	blueswir1	// C
897	19f329ad	blueswir1	static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
898	19f329ad	blueswir1	{
899	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
900	19f329ad	blueswir1	}
901	19f329ad	blueswir1
902	19f329ad	blueswir1	// V
903	19f329ad	blueswir1	static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
904	19f329ad	blueswir1	{
905	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
906	19f329ad	blueswir1	}
907	19f329ad	blueswir1
908	19f329ad	blueswir1	// 0
909	19f329ad	blueswir1	static inline void gen_op_eval_bn(TCGv dst)
910	19f329ad	blueswir1	{
911	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 0);
912	19f329ad	blueswir1	}
913	19f329ad	blueswir1
914	19f329ad	blueswir1	// N
915	19f329ad	blueswir1	static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
916	19f329ad	blueswir1	{
917	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
918	19f329ad	blueswir1	}
919	19f329ad	blueswir1
920	19f329ad	blueswir1	// !Z
921	19f329ad	blueswir1	static inline void gen_op_eval_bne(TCGv dst, TCGv src)
922	19f329ad	blueswir1	{
923	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
924	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
925	19f329ad	blueswir1	}
926	19f329ad	blueswir1
927	19f329ad	blueswir1	// !(Z \| (N ^ V))
928	19f329ad	blueswir1	static inline void gen_op_eval_bg(TCGv dst, TCGv src)
929	19f329ad	blueswir1	{
930	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
931	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
932	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
933	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
934	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
935	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
936	19f329ad	blueswir1	}
937	19f329ad	blueswir1
938	19f329ad	blueswir1	// !(N ^ V)
939	19f329ad	blueswir1	static inline void gen_op_eval_bge(TCGv dst, TCGv src)
940	19f329ad	blueswir1	{
941	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
942	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
943	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
944	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
945	19f329ad	blueswir1	}
946	19f329ad	blueswir1
947	19f329ad	blueswir1	// !(C \| Z)
948	19f329ad	blueswir1	static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
949	19f329ad	blueswir1	{
950	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
951	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
952	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
953	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
954	19f329ad	blueswir1	}
955	19f329ad	blueswir1
956	19f329ad	blueswir1	// !C
957	19f329ad	blueswir1	static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
958	19f329ad	blueswir1	{
959	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
960	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
961	19f329ad	blueswir1	}
962	19f329ad	blueswir1
963	19f329ad	blueswir1	// !N
964	19f329ad	blueswir1	static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
965	19f329ad	blueswir1	{
966	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
967	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
968	19f329ad	blueswir1	}
969	19f329ad	blueswir1
970	19f329ad	blueswir1	// !V
971	19f329ad	blueswir1	static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
972	19f329ad	blueswir1	{
973	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
974	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
975	19f329ad	blueswir1	}
976	19f329ad	blueswir1
977	19f329ad	blueswir1	/*
978	19f329ad	blueswir1	FPSR bit field FCC1 \| FCC0:
979	19f329ad	blueswir1	0 =
980	19f329ad	blueswir1	1 <
981	19f329ad	blueswir1	2 >
982	19f329ad	blueswir1	3 unordered
983	19f329ad	blueswir1	*/
984	19f329ad	blueswir1	static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
985	19f329ad	blueswir1	unsigned int fcc_offset)
986	19f329ad	blueswir1	{
987	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
988	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
989	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
990	19f329ad	blueswir1	}
991	19f329ad	blueswir1
992	19f329ad	blueswir1	static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
993	19f329ad	blueswir1	unsigned int fcc_offset)
994	19f329ad	blueswir1	{
995	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
996	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
997	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
998	19f329ad	blueswir1	}
999	19f329ad	blueswir1
1000	19f329ad	blueswir1	// !0: FCC0 \| FCC1
1001	19f329ad	blueswir1	static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1002	19f329ad	blueswir1	unsigned int fcc_offset)
1003	19f329ad	blueswir1	{
1004	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1005	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1006	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1007	19f329ad	blueswir1	}
1008	19f329ad	blueswir1
1009	19f329ad	blueswir1	// 1 or 2: FCC0 ^ FCC1
1010	19f329ad	blueswir1	static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1011	19f329ad	blueswir1	unsigned int fcc_offset)
1012	19f329ad	blueswir1	{
1013	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1014	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1015	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1016	19f329ad	blueswir1	}
1017	19f329ad	blueswir1
1018	19f329ad	blueswir1	// 1 or 3: FCC0
1019	19f329ad	blueswir1	static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1020	19f329ad	blueswir1	unsigned int fcc_offset)
1021	19f329ad	blueswir1	{
1022	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1023	19f329ad	blueswir1	}
1024	19f329ad	blueswir1
1025	19f329ad	blueswir1	// 1: FCC0 & !FCC1
1026	19f329ad	blueswir1	static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1027	19f329ad	blueswir1	unsigned int fcc_offset)
1028	19f329ad	blueswir1	{
1029	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1030	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1031	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1032	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1033	19f329ad	blueswir1	}
1034	19f329ad	blueswir1
1035	19f329ad	blueswir1	// 2 or 3: FCC1
1036	19f329ad	blueswir1	static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1037	19f329ad	blueswir1	unsigned int fcc_offset)
1038	19f329ad	blueswir1	{
1039	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1040	19f329ad	blueswir1	}
1041	19f329ad	blueswir1
1042	19f329ad	blueswir1	// 2: !FCC0 & FCC1
1043	19f329ad	blueswir1	static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1044	19f329ad	blueswir1	unsigned int fcc_offset)
1045	19f329ad	blueswir1	{
1046	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1047	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1048	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1049	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1050	19f329ad	blueswir1	}
1051	19f329ad	blueswir1
1052	19f329ad	blueswir1	// 3: FCC0 & FCC1
1053	19f329ad	blueswir1	static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1054	19f329ad	blueswir1	unsigned int fcc_offset)
1055	19f329ad	blueswir1	{
1056	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1057	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1058	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1059	19f329ad	blueswir1	}
1060	19f329ad	blueswir1
1061	19f329ad	blueswir1	// 0: !(FCC0 \| FCC1)
1062	19f329ad	blueswir1	static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1063	19f329ad	blueswir1	unsigned int fcc_offset)
1064	19f329ad	blueswir1	{
1065	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1066	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1067	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1068	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1069	19f329ad	blueswir1	}
1070	19f329ad	blueswir1
1071	19f329ad	blueswir1	// 0 or 3: !(FCC0 ^ FCC1)
1072	19f329ad	blueswir1	static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1073	19f329ad	blueswir1	unsigned int fcc_offset)
1074	19f329ad	blueswir1	{
1075	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1076	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1077	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1078	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1079	19f329ad	blueswir1	}
1080	19f329ad	blueswir1
1081	19f329ad	blueswir1	// 0 or 2: !FCC0
1082	19f329ad	blueswir1	static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1083	19f329ad	blueswir1	unsigned int fcc_offset)
1084	19f329ad	blueswir1	{
1085	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1086	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1087	19f329ad	blueswir1	}
1088	19f329ad	blueswir1
1089	19f329ad	blueswir1	// !1: !(FCC0 & !FCC1)
1090	19f329ad	blueswir1	static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1091	19f329ad	blueswir1	unsigned int fcc_offset)
1092	19f329ad	blueswir1	{
1093	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1094	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1095	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1096	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1097	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1098	19f329ad	blueswir1	}
1099	19f329ad	blueswir1
1100	19f329ad	blueswir1	// 0 or 1: !FCC1
1101	19f329ad	blueswir1	static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1102	19f329ad	blueswir1	unsigned int fcc_offset)
1103	19f329ad	blueswir1	{
1104	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1105	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1106	19f329ad	blueswir1	}
1107	19f329ad	blueswir1
1108	19f329ad	blueswir1	// !2: !(!FCC0 & FCC1)
1109	19f329ad	blueswir1	static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1110	19f329ad	blueswir1	unsigned int fcc_offset)
1111	19f329ad	blueswir1	{
1112	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1113	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1114	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1115	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1116	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1117	19f329ad	blueswir1	}
1118	19f329ad	blueswir1
1119	19f329ad	blueswir1	// !3: !(FCC0 & FCC1)
1120	19f329ad	blueswir1	static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1121	19f329ad	blueswir1	unsigned int fcc_offset)
1122	19f329ad	blueswir1	{
1123	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1124	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1125	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1126	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1127	19f329ad	blueswir1	}
1128	19f329ad	blueswir1
1129	46525e1f	blueswir1	static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1130	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1131	83469015	bellard	{
1132	83469015	bellard	int l1;
1133	83469015	bellard
1134	83469015	bellard	l1 = gen_new_label();
1135	83469015	bellard
1136	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1137	83469015	bellard
1138	6e256c93	bellard	gen_goto_tb(dc, 0, pc1, pc1 + 4);
1139	83469015	bellard
1140	83469015	bellard	gen_set_label(l1);
1141	6e256c93	bellard	gen_goto_tb(dc, 1, pc2, pc2 + 4);
1142	83469015	bellard	}
1143	83469015	bellard
1144	46525e1f	blueswir1	static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1145	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1146	83469015	bellard	{
1147	83469015	bellard	int l1;
1148	83469015	bellard
1149	83469015	bellard	l1 = gen_new_label();
1150	83469015	bellard
1151	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1152	83469015	bellard
1153	6e256c93	bellard	gen_goto_tb(dc, 0, pc2, pc1);
1154	83469015	bellard
1155	83469015	bellard	gen_set_label(l1);
1156	6e256c93	bellard	gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1157	83469015	bellard	}
1158	83469015	bellard
1159	19f329ad	blueswir1	static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1160	19f329ad	blueswir1	TCGv r_cond)
1161	83469015	bellard	{
1162	83469015	bellard	int l1, l2;
1163	83469015	bellard
1164	83469015	bellard	l1 = gen_new_label();
1165	83469015	bellard	l2 = gen_new_label();
1166	19f329ad	blueswir1
1167	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1168	83469015	bellard
1169	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc1);
1170	06b3e1b3	blueswir1	tcg_gen_br(l2);
1171	83469015	bellard
1172	83469015	bellard	gen_set_label(l1);
1173	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc2);
1174	83469015	bellard	gen_set_label(l2);
1175	83469015	bellard	}
1176	83469015	bellard
1177	4af984a7	blueswir1	/* call this function before using the condition register as it may
1178	4af984a7	blueswir1	have been set for a jump */
1179	4af984a7	blueswir1	static inline void flush_cond(DisasContext *dc, TCGv cond)
1180	83469015	bellard	{
1181	83469015	bellard	if (dc->npc == JUMP_PC) {
1182	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1183	83469015	bellard	dc->npc = DYNAMIC_PC;
1184	83469015	bellard	}
1185	83469015	bellard	}
1186	83469015	bellard
1187	4af984a7	blueswir1	static inline void save_npc(DisasContext *dc, TCGv cond)
1188	72cbca10	bellard	{
1189	72cbca10	bellard	if (dc->npc == JUMP_PC) {
1190	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1191	72cbca10	bellard	dc->npc = DYNAMIC_PC;
1192	72cbca10	bellard	} else if (dc->npc != DYNAMIC_PC) {
1193	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, dc->npc);
1194	72cbca10	bellard	}
1195	72cbca10	bellard	}
1196	72cbca10	bellard
1197	4af984a7	blueswir1	static inline void save_state(DisasContext *dc, TCGv cond)
1198	72cbca10	bellard	{
1199	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
1200	4af984a7	blueswir1	save_npc(dc, cond);
1201	72cbca10	bellard	}
1202	72cbca10	bellard
1203	4af984a7	blueswir1	static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1204	0bee699e	bellard	{
1205	0bee699e	bellard	if (dc->npc == JUMP_PC) {
1206	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1207	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1208	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1209	0bee699e	bellard	} else if (dc->npc == DYNAMIC_PC) {
1210	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1211	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1212	0bee699e	bellard	} else {
1213	0bee699e	bellard	dc->pc = dc->npc;
1214	0bee699e	bellard	}
1215	0bee699e	bellard	}
1216	0bee699e	bellard
1217	38bc628b	blueswir1	static inline void gen_op_next_insn(void)
1218	38bc628b	blueswir1	{
1219	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1220	48d5c82b	blueswir1	tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1221	38bc628b	blueswir1	}
1222	38bc628b	blueswir1
1223	19f329ad	blueswir1	static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1224	19f329ad	blueswir1	{
1225	19f329ad	blueswir1	TCGv r_src;
1226	3475187d	bellard
1227	3475187d	bellard	#ifdef TARGET_SPARC64
1228	19f329ad	blueswir1	if (cc)
1229	dc99a3f2	blueswir1	r_src = cpu_xcc;
1230	19f329ad	blueswir1	else
1231	dc99a3f2	blueswir1	r_src = cpu_psr;
1232	3475187d	bellard	#else
1233	dc99a3f2	blueswir1	r_src = cpu_psr;
1234	3475187d	bellard	#endif
1235	19f329ad	blueswir1	switch (cond) {
1236	19f329ad	blueswir1	case 0x0:
1237	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1238	19f329ad	blueswir1	break;
1239	19f329ad	blueswir1	case 0x1:
1240	19f329ad	blueswir1	gen_op_eval_be(r_dst, r_src);
1241	19f329ad	blueswir1	break;
1242	19f329ad	blueswir1	case 0x2:
1243	19f329ad	blueswir1	gen_op_eval_ble(r_dst, r_src);
1244	19f329ad	blueswir1	break;
1245	19f329ad	blueswir1	case 0x3:
1246	19f329ad	blueswir1	gen_op_eval_bl(r_dst, r_src);
1247	19f329ad	blueswir1	break;
1248	19f329ad	blueswir1	case 0x4:
1249	19f329ad	blueswir1	gen_op_eval_bleu(r_dst, r_src);
1250	19f329ad	blueswir1	break;
1251	19f329ad	blueswir1	case 0x5:
1252	19f329ad	blueswir1	gen_op_eval_bcs(r_dst, r_src);
1253	19f329ad	blueswir1	break;
1254	19f329ad	blueswir1	case 0x6:
1255	19f329ad	blueswir1	gen_op_eval_bneg(r_dst, r_src);
1256	19f329ad	blueswir1	break;
1257	19f329ad	blueswir1	case 0x7:
1258	19f329ad	blueswir1	gen_op_eval_bvs(r_dst, r_src);
1259	19f329ad	blueswir1	break;
1260	19f329ad	blueswir1	case 0x8:
1261	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1262	19f329ad	blueswir1	break;
1263	19f329ad	blueswir1	case 0x9:
1264	19f329ad	blueswir1	gen_op_eval_bne(r_dst, r_src);
1265	19f329ad	blueswir1	break;
1266	19f329ad	blueswir1	case 0xa:
1267	19f329ad	blueswir1	gen_op_eval_bg(r_dst, r_src);
1268	19f329ad	blueswir1	break;
1269	19f329ad	blueswir1	case 0xb:
1270	19f329ad	blueswir1	gen_op_eval_bge(r_dst, r_src);
1271	19f329ad	blueswir1	break;
1272	19f329ad	blueswir1	case 0xc:
1273	19f329ad	blueswir1	gen_op_eval_bgu(r_dst, r_src);
1274	19f329ad	blueswir1	break;
1275	19f329ad	blueswir1	case 0xd:
1276	19f329ad	blueswir1	gen_op_eval_bcc(r_dst, r_src);
1277	19f329ad	blueswir1	break;
1278	19f329ad	blueswir1	case 0xe:
1279	19f329ad	blueswir1	gen_op_eval_bpos(r_dst, r_src);
1280	19f329ad	blueswir1	break;
1281	19f329ad	blueswir1	case 0xf:
1282	19f329ad	blueswir1	gen_op_eval_bvc(r_dst, r_src);
1283	19f329ad	blueswir1	break;
1284	19f329ad	blueswir1	}
1285	19f329ad	blueswir1	}
1286	7a3f1944	bellard
1287	19f329ad	blueswir1	static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1288	e8af50a3	bellard	{
1289	19f329ad	blueswir1	unsigned int offset;
1290	19f329ad	blueswir1
1291	19f329ad	blueswir1	switch (cc) {
1292	19f329ad	blueswir1	default:
1293	19f329ad	blueswir1	case 0x0:
1294	19f329ad	blueswir1	offset = 0;
1295	19f329ad	blueswir1	break;
1296	19f329ad	blueswir1	case 0x1:
1297	19f329ad	blueswir1	offset = 32 - 10;
1298	19f329ad	blueswir1	break;
1299	19f329ad	blueswir1	case 0x2:
1300	19f329ad	blueswir1	offset = 34 - 10;
1301	19f329ad	blueswir1	break;
1302	19f329ad	blueswir1	case 0x3:
1303	19f329ad	blueswir1	offset = 36 - 10;
1304	19f329ad	blueswir1	break;
1305	19f329ad	blueswir1	}
1306	19f329ad	blueswir1
1307	19f329ad	blueswir1	switch (cond) {
1308	19f329ad	blueswir1	case 0x0:
1309	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1310	19f329ad	blueswir1	break;
1311	19f329ad	blueswir1	case 0x1:
1312	87e92502	blueswir1	gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1313	19f329ad	blueswir1	break;
1314	19f329ad	blueswir1	case 0x2:
1315	87e92502	blueswir1	gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1316	19f329ad	blueswir1	break;
1317	19f329ad	blueswir1	case 0x3:
1318	87e92502	blueswir1	gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1319	19f329ad	blueswir1	break;
1320	19f329ad	blueswir1	case 0x4:
1321	87e92502	blueswir1	gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1322	19f329ad	blueswir1	break;
1323	19f329ad	blueswir1	case 0x5:
1324	87e92502	blueswir1	gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1325	19f329ad	blueswir1	break;
1326	19f329ad	blueswir1	case 0x6:
1327	87e92502	blueswir1	gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1328	19f329ad	blueswir1	break;
1329	19f329ad	blueswir1	case 0x7:
1330	87e92502	blueswir1	gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1331	19f329ad	blueswir1	break;
1332	19f329ad	blueswir1	case 0x8:
1333	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1334	19f329ad	blueswir1	break;
1335	19f329ad	blueswir1	case 0x9:
1336	87e92502	blueswir1	gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1337	19f329ad	blueswir1	break;
1338	19f329ad	blueswir1	case 0xa:
1339	87e92502	blueswir1	gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1340	19f329ad	blueswir1	break;
1341	19f329ad	blueswir1	case 0xb:
1342	87e92502	blueswir1	gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1343	19f329ad	blueswir1	break;
1344	19f329ad	blueswir1	case 0xc:
1345	87e92502	blueswir1	gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1346	19f329ad	blueswir1	break;
1347	19f329ad	blueswir1	case 0xd:
1348	87e92502	blueswir1	gen_op_eval_fble(r_dst, cpu_fsr, offset);
1349	19f329ad	blueswir1	break;
1350	19f329ad	blueswir1	case 0xe:
1351	87e92502	blueswir1	gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1352	19f329ad	blueswir1	break;
1353	19f329ad	blueswir1	case 0xf:
1354	87e92502	blueswir1	gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1355	19f329ad	blueswir1	break;
1356	19f329ad	blueswir1	}
1357	e8af50a3	bellard	}
1358	00f219bf	blueswir1
1359	19f329ad	blueswir1	#ifdef TARGET_SPARC64
1360	00f219bf	blueswir1	// Inverted logic
1361	00f219bf	blueswir1	static const int gen_tcg_cond_reg[8] = {
1362	00f219bf	blueswir1	-1,
1363	00f219bf	blueswir1	TCG_COND_NE,
1364	00f219bf	blueswir1	TCG_COND_GT,
1365	00f219bf	blueswir1	TCG_COND_GE,
1366	00f219bf	blueswir1	-1,
1367	00f219bf	blueswir1	TCG_COND_EQ,
1368	00f219bf	blueswir1	TCG_COND_LE,
1369	00f219bf	blueswir1	TCG_COND_LT,
1370	00f219bf	blueswir1	};
1371	19f329ad	blueswir1
1372	4af984a7	blueswir1	static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1373	19f329ad	blueswir1	{
1374	19f329ad	blueswir1	int l1;
1375	19f329ad	blueswir1
1376	19f329ad	blueswir1	l1 = gen_new_label();
1377	0425bee5	blueswir1	tcg_gen_movi_tl(r_dst, 0);
1378	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1379	19f329ad	blueswir1	tcg_gen_movi_tl(r_dst, 1);
1380	19f329ad	blueswir1	gen_set_label(l1);
1381	19f329ad	blueswir1	}
1382	3475187d	bellard	#endif
1383	cf495bcf	bellard
1384	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1385	4af984a7	blueswir1	static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1386	4af984a7	blueswir1	TCGv r_cond)
1387	7a3f1944	bellard	{
1388	cf495bcf	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1389	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1390	5fafdf24	ths
1391	cf495bcf	bellard	if (cond == 0x0) {
1392	0f8a249a	blueswir1	/* unconditional not taken */
1393	0f8a249a	blueswir1	if (a) {
1394	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1395	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1396	0f8a249a	blueswir1	} else {
1397	0f8a249a	blueswir1	dc->pc = dc->npc;
1398	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1399	0f8a249a	blueswir1	}
1400	cf495bcf	bellard	} else if (cond == 0x8) {
1401	0f8a249a	blueswir1	/* unconditional taken */
1402	0f8a249a	blueswir1	if (a) {
1403	0f8a249a	blueswir1	dc->pc = target;
1404	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1405	0f8a249a	blueswir1	} else {
1406	0f8a249a	blueswir1	dc->pc = dc->npc;
1407	0f8a249a	blueswir1	dc->npc = target;
1408	0f8a249a	blueswir1	}
1409	cf495bcf	bellard	} else {
1410	4af984a7	blueswir1	flush_cond(dc, r_cond);
1411	4af984a7	blueswir1	gen_cond(r_cond, cc, cond);
1412	0f8a249a	blueswir1	if (a) {
1413	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1414	cf495bcf	bellard	dc->is_br = 1;
1415	0f8a249a	blueswir1	} else {
1416	cf495bcf	bellard	dc->pc = dc->npc;
1417	72cbca10	bellard	dc->jump_pc[0] = target;
1418	72cbca10	bellard	dc->jump_pc[1] = dc->npc + 4;
1419	72cbca10	bellard	dc->npc = JUMP_PC;
1420	0f8a249a	blueswir1	}
1421	cf495bcf	bellard	}
1422	7a3f1944	bellard	}
1423	7a3f1944	bellard
1424	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1425	4af984a7	blueswir1	static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1426	4af984a7	blueswir1	TCGv r_cond)
1427	e8af50a3	bellard	{
1428	e8af50a3	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1429	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1430	af7bf89b	bellard
1431	e8af50a3	bellard	if (cond == 0x0) {
1432	0f8a249a	blueswir1	/* unconditional not taken */
1433	0f8a249a	blueswir1	if (a) {
1434	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1435	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1436	0f8a249a	blueswir1	} else {
1437	0f8a249a	blueswir1	dc->pc = dc->npc;
1438	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1439	0f8a249a	blueswir1	}
1440	e8af50a3	bellard	} else if (cond == 0x8) {
1441	0f8a249a	blueswir1	/* unconditional taken */
1442	0f8a249a	blueswir1	if (a) {
1443	0f8a249a	blueswir1	dc->pc = target;
1444	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1445	0f8a249a	blueswir1	} else {
1446	0f8a249a	blueswir1	dc->pc = dc->npc;
1447	0f8a249a	blueswir1	dc->npc = target;
1448	0f8a249a	blueswir1	}
1449	e8af50a3	bellard	} else {
1450	4af984a7	blueswir1	flush_cond(dc, r_cond);
1451	4af984a7	blueswir1	gen_fcond(r_cond, cc, cond);
1452	0f8a249a	blueswir1	if (a) {
1453	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1454	e8af50a3	bellard	dc->is_br = 1;
1455	0f8a249a	blueswir1	} else {
1456	e8af50a3	bellard	dc->pc = dc->npc;
1457	e8af50a3	bellard	dc->jump_pc[0] = target;
1458	e8af50a3	bellard	dc->jump_pc[1] = dc->npc + 4;
1459	e8af50a3	bellard	dc->npc = JUMP_PC;
1460	0f8a249a	blueswir1	}
1461	e8af50a3	bellard	}
1462	e8af50a3	bellard	}
1463	e8af50a3	bellard
1464	3475187d	bellard	#ifdef TARGET_SPARC64
1465	3475187d	bellard	/* XXX: potentially incorrect if dynamic npc */
1466	4af984a7	blueswir1	static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1467	4af984a7	blueswir1	TCGv r_cond, TCGv r_reg)
1468	7a3f1944	bellard	{
1469	3475187d	bellard	unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1470	3475187d	bellard	target_ulong target = dc->pc + offset;
1471	3475187d	bellard
1472	4af984a7	blueswir1	flush_cond(dc, r_cond);
1473	4af984a7	blueswir1	gen_cond_reg(r_cond, cond, r_reg);
1474	3475187d	bellard	if (a) {
1475	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1476	0f8a249a	blueswir1	dc->is_br = 1;
1477	3475187d	bellard	} else {
1478	0f8a249a	blueswir1	dc->pc = dc->npc;
1479	0f8a249a	blueswir1	dc->jump_pc[0] = target;
1480	0f8a249a	blueswir1	dc->jump_pc[1] = dc->npc + 4;
1481	0f8a249a	blueswir1	dc->npc = JUMP_PC;
1482	3475187d	bellard	}
1483	7a3f1944	bellard	}
1484	7a3f1944	bellard
1485	3475187d	bellard	static GenOpFunc * const gen_fcmps[4] = {
1486	7e8c2b6c	blueswir1	helper_fcmps,
1487	7e8c2b6c	blueswir1	helper_fcmps_fcc1,
1488	7e8c2b6c	blueswir1	helper_fcmps_fcc2,
1489	7e8c2b6c	blueswir1	helper_fcmps_fcc3,
1490	3475187d	bellard	};
1491	3475187d	bellard
1492	3475187d	bellard	static GenOpFunc * const gen_fcmpd[4] = {
1493	7e8c2b6c	blueswir1	helper_fcmpd,
1494	7e8c2b6c	blueswir1	helper_fcmpd_fcc1,
1495	7e8c2b6c	blueswir1	helper_fcmpd_fcc2,
1496	7e8c2b6c	blueswir1	helper_fcmpd_fcc3,
1497	3475187d	bellard	};
1498	417454b0	blueswir1
1499	1f587329	blueswir1	static GenOpFunc * const gen_fcmpq[4] = {
1500	7e8c2b6c	blueswir1	helper_fcmpq,
1501	7e8c2b6c	blueswir1	helper_fcmpq_fcc1,
1502	7e8c2b6c	blueswir1	helper_fcmpq_fcc2,
1503	7e8c2b6c	blueswir1	helper_fcmpq_fcc3,
1504	1f587329	blueswir1	};
1505	1f587329	blueswir1
1506	417454b0	blueswir1	static GenOpFunc * const gen_fcmpes[4] = {
1507	7e8c2b6c	blueswir1	helper_fcmpes,
1508	7e8c2b6c	blueswir1	helper_fcmpes_fcc1,
1509	7e8c2b6c	blueswir1	helper_fcmpes_fcc2,
1510	7e8c2b6c	blueswir1	helper_fcmpes_fcc3,
1511	417454b0	blueswir1	};
1512	417454b0	blueswir1
1513	417454b0	blueswir1	static GenOpFunc * const gen_fcmped[4] = {
1514	7e8c2b6c	blueswir1	helper_fcmped,
1515	7e8c2b6c	blueswir1	helper_fcmped_fcc1,
1516	7e8c2b6c	blueswir1	helper_fcmped_fcc2,
1517	7e8c2b6c	blueswir1	helper_fcmped_fcc3,
1518	417454b0	blueswir1	};
1519	417454b0	blueswir1
1520	1f587329	blueswir1	static GenOpFunc * const gen_fcmpeq[4] = {
1521	7e8c2b6c	blueswir1	helper_fcmpeq,
1522	7e8c2b6c	blueswir1	helper_fcmpeq_fcc1,
1523	7e8c2b6c	blueswir1	helper_fcmpeq_fcc2,
1524	7e8c2b6c	blueswir1	helper_fcmpeq_fcc3,
1525	1f587329	blueswir1	};
1526	7e8c2b6c	blueswir1
1527	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1528	7e8c2b6c	blueswir1	{
1529	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmps[fccno]);
1530	7e8c2b6c	blueswir1	}
1531	7e8c2b6c	blueswir1
1532	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1533	7e8c2b6c	blueswir1	{
1534	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1535	7e8c2b6c	blueswir1	}
1536	7e8c2b6c	blueswir1
1537	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1538	7e8c2b6c	blueswir1	{
1539	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1540	7e8c2b6c	blueswir1	}
1541	7e8c2b6c	blueswir1
1542	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1543	7e8c2b6c	blueswir1	{
1544	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1545	7e8c2b6c	blueswir1	}
1546	7e8c2b6c	blueswir1
1547	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1548	7e8c2b6c	blueswir1	{
1549	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmped[fccno]);
1550	7e8c2b6c	blueswir1	}
1551	7e8c2b6c	blueswir1
1552	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1553	7e8c2b6c	blueswir1	{
1554	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1555	7e8c2b6c	blueswir1	}
1556	7e8c2b6c	blueswir1
1557	7e8c2b6c	blueswir1	#else
1558	7e8c2b6c	blueswir1
1559	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1560	7e8c2b6c	blueswir1	{
1561	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmps);
1562	7e8c2b6c	blueswir1	}
1563	7e8c2b6c	blueswir1
1564	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1565	7e8c2b6c	blueswir1	{
1566	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpd);
1567	7e8c2b6c	blueswir1	}
1568	7e8c2b6c	blueswir1
1569	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1570	7e8c2b6c	blueswir1	{
1571	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpq);
1572	7e8c2b6c	blueswir1	}
1573	7e8c2b6c	blueswir1
1574	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1575	7e8c2b6c	blueswir1	{
1576	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpes);
1577	7e8c2b6c	blueswir1	}
1578	7e8c2b6c	blueswir1
1579	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1580	7e8c2b6c	blueswir1	{
1581	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmped);
1582	7e8c2b6c	blueswir1	}
1583	7e8c2b6c	blueswir1
1584	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1585	7e8c2b6c	blueswir1	{
1586	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq);
1587	7e8c2b6c	blueswir1	}
1588	7e8c2b6c	blueswir1	#endif
1589	7e8c2b6c	blueswir1
1590	134d77a1	blueswir1	static inline void gen_op_fpexception_im(int fsr_flags)
1591	134d77a1	blueswir1	{
1592	2ea815ca	blueswir1	TCGv r_const;
1593	2ea815ca	blueswir1
1594	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1595	87e92502	blueswir1	tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1596	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_FP_EXCP);
1597	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1598	2ea815ca	blueswir1	tcg_temp_free(r_const);
1599	134d77a1	blueswir1	}
1600	134d77a1	blueswir1
1601	4af984a7	blueswir1	static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1602	a80dde08	bellard	{
1603	a80dde08	bellard	#if !defined(CONFIG_USER_ONLY)
1604	a80dde08	bellard	if (!dc->fpu_enabled) {
1605	2ea815ca	blueswir1	TCGv r_const;
1606	2ea815ca	blueswir1
1607	4af984a7	blueswir1	save_state(dc, r_cond);
1608	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NFPU_INSN);
1609	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1610	2ea815ca	blueswir1	tcg_temp_free(r_const);
1611	a80dde08	bellard	dc->is_br = 1;
1612	a80dde08	bellard	return 1;
1613	a80dde08	bellard	}
1614	a80dde08	bellard	#endif
1615	a80dde08	bellard	return 0;
1616	a80dde08	bellard	}
1617	a80dde08	bellard
1618	7e8c2b6c	blueswir1	static inline void gen_op_clear_ieee_excp_and_FTT(void)
1619	7e8c2b6c	blueswir1	{
1620	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK \| FSR_CEXC_MASK));
1621	7e8c2b6c	blueswir1	}
1622	7e8c2b6c	blueswir1
1623	7e8c2b6c	blueswir1	static inline void gen_clear_float_exceptions(void)
1624	7e8c2b6c	blueswir1	{
1625	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_clear_float_exceptions);
1626	7e8c2b6c	blueswir1	}
1627	7e8c2b6c	blueswir1
1628	1a2fb1c0	blueswir1	/* asi moves */
1629	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
1630	0425bee5	blueswir1	static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1631	1a2fb1c0	blueswir1	{
1632	1a2fb1c0	blueswir1	int asi, offset;
1633	0425bee5	blueswir1	TCGv r_asi;
1634	1a2fb1c0	blueswir1
1635	1a2fb1c0	blueswir1	if (IS_IMM) {
1636	0425bee5	blueswir1	r_asi = tcg_temp_new(TCG_TYPE_I32);
1637	1a2fb1c0	blueswir1	offset = GET_FIELD(insn, 25, 31);
1638	0425bee5	blueswir1	tcg_gen_addi_tl(r_addr, r_addr, offset);
1639	0425bee5	blueswir1	tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1640	1a2fb1c0	blueswir1	} else {
1641	1a2fb1c0	blueswir1	asi = GET_FIELD(insn, 19, 26);
1642	0425bee5	blueswir1	r_asi = tcg_const_i32(asi);
1643	1a2fb1c0	blueswir1	}
1644	0425bee5	blueswir1	return r_asi;
1645	0425bee5	blueswir1	}
1646	0425bee5	blueswir1
1647	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1648	77f193da	blueswir1	int sign)
1649	0425bee5	blueswir1	{
1650	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1651	0425bee5	blueswir1
1652	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1653	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1654	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1655	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1656	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1657	2ea815ca	blueswir1	tcg_temp_free(r_size);
1658	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1659	1a2fb1c0	blueswir1	}
1660	1a2fb1c0	blueswir1
1661	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1662	1a2fb1c0	blueswir1	{
1663	2ea815ca	blueswir1	TCGv r_asi, r_size;
1664	1a2fb1c0	blueswir1
1665	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1666	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1667	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1668	2ea815ca	blueswir1	tcg_temp_free(r_size);
1669	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1670	1a2fb1c0	blueswir1	}
1671	1a2fb1c0	blueswir1
1672	4af984a7	blueswir1	static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1673	1a2fb1c0	blueswir1	{
1674	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1675	1a2fb1c0	blueswir1
1676	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1677	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1678	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1679	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1680	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1681	2ea815ca	blueswir1	tcg_temp_free(r_size);
1682	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1683	1a2fb1c0	blueswir1	}
1684	1a2fb1c0	blueswir1
1685	4af984a7	blueswir1	static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1686	1a2fb1c0	blueswir1	{
1687	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1688	1a2fb1c0	blueswir1
1689	31741a27	blueswir1	r_asi = gen_get_asi(insn, addr);
1690	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1691	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1692	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1693	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1694	2ea815ca	blueswir1	tcg_temp_free(r_size);
1695	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1696	1a2fb1c0	blueswir1	}
1697	1a2fb1c0	blueswir1
1698	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1699	1a2fb1c0	blueswir1	{
1700	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1701	1a2fb1c0	blueswir1
1702	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1703	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1704	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1705	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1706	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1707	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1708	2ea815ca	blueswir1	tcg_temp_free(r_size);
1709	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1710	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1711	1a2fb1c0	blueswir1	}
1712	1a2fb1c0	blueswir1
1713	4af984a7	blueswir1	static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1714	1a2fb1c0	blueswir1	{
1715	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1716	1a2fb1c0	blueswir1
1717	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1718	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1719	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1720	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1721	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1722	2ea815ca	blueswir1	tcg_temp_free(r_size);
1723	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1724	4af984a7	blueswir1	tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1725	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1726	4af984a7	blueswir1	tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1727	0425bee5	blueswir1	}
1728	0425bee5	blueswir1
1729	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1730	0425bee5	blueswir1	{
1731	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1732	0425bee5	blueswir1
1733	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1734	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1735	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1736	0425bee5	blueswir1	r_temp);
1737	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1738	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1739	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1740	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1741	2ea815ca	blueswir1	tcg_temp_free(r_size);
1742	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1743	1a2fb1c0	blueswir1	}
1744	1a2fb1c0	blueswir1
1745	77f193da	blueswir1	static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1746	77f193da	blueswir1	int rd)
1747	1a2fb1c0	blueswir1	{
1748	1a2fb1c0	blueswir1	TCGv r_val1, r_asi;
1749	1a2fb1c0	blueswir1
1750	ef28fd86	blueswir1	r_val1 = tcg_temp_new(TCG_TYPE_TL);
1751	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd, r_val1);
1752	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1753	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1754	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1755	2ea815ca	blueswir1	tcg_temp_free(r_val1);
1756	1a2fb1c0	blueswir1	}
1757	1a2fb1c0	blueswir1
1758	77f193da	blueswir1	static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1759	77f193da	blueswir1	int rd)
1760	1a2fb1c0	blueswir1	{
1761	8911f501	blueswir1	TCGv r_asi;
1762	1a2fb1c0	blueswir1
1763	8911f501	blueswir1	gen_movl_reg_TN(rd, cpu_tmp64);
1764	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1765	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1766	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1767	1a2fb1c0	blueswir1	}
1768	1a2fb1c0	blueswir1
1769	1a2fb1c0	blueswir1	#elif !defined(CONFIG_USER_ONLY)
1770	1a2fb1c0	blueswir1
1771	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1772	77f193da	blueswir1	int sign)
1773	1a2fb1c0	blueswir1	{
1774	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1775	1a2fb1c0	blueswir1
1776	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1777	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1778	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1779	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1780	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1781	2ea815ca	blueswir1	tcg_temp_free(r_size);
1782	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1783	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1784	1a2fb1c0	blueswir1	}
1785	1a2fb1c0	blueswir1
1786	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1787	1a2fb1c0	blueswir1	{
1788	2ea815ca	blueswir1	TCGv r_asi, r_size;
1789	1a2fb1c0	blueswir1
1790	4af984a7	blueswir1	tcg_gen_extu_tl_i64(cpu_tmp64, src);
1791	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1792	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1793	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1794	2ea815ca	blueswir1	tcg_temp_free(r_size);
1795	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1796	1a2fb1c0	blueswir1	}
1797	1a2fb1c0	blueswir1
1798	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1799	1a2fb1c0	blueswir1	{
1800	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1801	1a2fb1c0	blueswir1
1802	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1803	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1804	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1805	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1806	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1807	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1808	2ea815ca	blueswir1	tcg_temp_free(r_size);
1809	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1810	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1811	1a2fb1c0	blueswir1	}
1812	1a2fb1c0	blueswir1
1813	4af984a7	blueswir1	static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1814	1a2fb1c0	blueswir1	{
1815	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1816	1a2fb1c0	blueswir1
1817	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1818	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1819	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1820	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1821	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1822	2ea815ca	blueswir1	tcg_temp_free(r_size);
1823	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1824	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1825	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1826	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1827	0425bee5	blueswir1	}
1828	0425bee5	blueswir1
1829	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1830	0425bee5	blueswir1	{
1831	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1832	0425bee5	blueswir1
1833	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1834	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1835	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1836	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1837	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1838	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1839	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1840	2ea815ca	blueswir1	tcg_temp_free(r_size);
1841	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1842	1a2fb1c0	blueswir1	}
1843	1a2fb1c0	blueswir1	#endif
1844	1a2fb1c0	blueswir1
1845	1a2fb1c0	blueswir1	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
1846	4af984a7	blueswir1	static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1847	1a2fb1c0	blueswir1	{
1848	2ea815ca	blueswir1	TCGv r_val, r_asi, r_size;
1849	1a2fb1c0	blueswir1
1850	4af984a7	blueswir1	gen_ld_asi(dst, addr, insn, 1, 0);
1851	1a2fb1c0	blueswir1
1852	2ea815ca	blueswir1	r_val = tcg_const_i64(0xffULL);
1853	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1854	2ea815ca	blueswir1	r_size = tcg_const_i32(1);
1855	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1856	2ea815ca	blueswir1	tcg_temp_free(r_size);
1857	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1858	2ea815ca	blueswir1	tcg_temp_free(r_val);
1859	1a2fb1c0	blueswir1	}
1860	1a2fb1c0	blueswir1	#endif
1861	1a2fb1c0	blueswir1
1862	9322a4bf	blueswir1	static inline TCGv get_src1(unsigned int insn, TCGv def)
1863	9322a4bf	blueswir1	{
1864	9322a4bf	blueswir1	TCGv r_rs1 = def;
1865	9322a4bf	blueswir1	unsigned int rs1;
1866	9322a4bf	blueswir1
1867	9322a4bf	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
1868	9322a4bf	blueswir1	if (rs1 == 0)
1869	9322a4bf	blueswir1	//r_rs1 = tcg_const_tl(0);
1870	9322a4bf	blueswir1	tcg_gen_movi_tl(def, 0);
1871	9322a4bf	blueswir1	else if (rs1 < 8)
1872	9322a4bf	blueswir1	//r_rs1 = cpu_gregs[rs1];
1873	9322a4bf	blueswir1	tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1874	9322a4bf	blueswir1	else
1875	9322a4bf	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1876	9322a4bf	blueswir1	return r_rs1;
1877	9322a4bf	blueswir1	}
1878	9322a4bf	blueswir1
1879	a49d9390	blueswir1	static inline TCGv get_src2(unsigned int insn, TCGv def)
1880	a49d9390	blueswir1	{
1881	a49d9390	blueswir1	TCGv r_rs2 = def;
1882	a49d9390	blueswir1	unsigned int rs2;
1883	a49d9390	blueswir1
1884	a49d9390	blueswir1	if (IS_IMM) { /* immediate */
1885	a49d9390	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
1886	2ea815ca	blueswir1	r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1887	a49d9390	blueswir1	} else { /* register */
1888	a49d9390	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
1889	a49d9390	blueswir1	if (rs2 == 0)
1890	2ea815ca	blueswir1	r_rs2 = tcg_const_tl(0); // XXX how to free?
1891	a49d9390	blueswir1	else if (rs2 < 8)
1892	a49d9390	blueswir1	r_rs2 = cpu_gregs[rs2];
1893	a49d9390	blueswir1	else
1894	a49d9390	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1895	a49d9390	blueswir1	}
1896	a49d9390	blueswir1	return r_rs2;
1897	a49d9390	blueswir1	}
1898	a49d9390	blueswir1
1899	64a88d5d	blueswir1	#define CHECK_IU_FEATURE(dc, FEATURE) \
1900	64a88d5d	blueswir1	if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1901	64a88d5d	blueswir1	goto illegal_insn;
1902	64a88d5d	blueswir1	#define CHECK_FPU_FEATURE(dc, FEATURE) \
1903	64a88d5d	blueswir1	if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1904	64a88d5d	blueswir1	goto nfpu_insn;
1905	64a88d5d	blueswir1
1906	0bee699e	bellard	/* before an instruction, dc->pc must be static */
1907	cf495bcf	bellard	static void disas_sparc_insn(DisasContext * dc)
1908	cf495bcf	bellard	{
1909	cf495bcf	bellard	unsigned int insn, opc, rs1, rs2, rd;
1910	7a3f1944	bellard
1911	a8c768c0	blueswir1	if (unlikely(loglevel & CPU_LOG_TB_OP))
1912	a8c768c0	blueswir1	tcg_gen_debug_insn_start(dc->pc);
1913	0fa85d43	bellard	insn = ldl_code(dc->pc);
1914	cf495bcf	bellard	opc = GET_FIELD(insn, 0, 1);
1915	7a3f1944	bellard
1916	cf495bcf	bellard	rd = GET_FIELD(insn, 2, 6);
1917	6ae20372	blueswir1
1918	6ae20372	blueswir1	cpu_dst = cpu_T[0];
1919	6ae20372	blueswir1	cpu_src1 = cpu_T[0]; // const
1920	6ae20372	blueswir1	cpu_src2 = cpu_T[1]; // const
1921	6ae20372	blueswir1
1922	6ae20372	blueswir1	// loads and stores
1923	6ae20372	blueswir1	cpu_addr = cpu_T[0];
1924	6ae20372	blueswir1	cpu_val = cpu_T[1];
1925	6ae20372	blueswir1
1926	cf495bcf	bellard	switch (opc) {
1927	0f8a249a	blueswir1	case 0: /* branches/sethi */
1928	0f8a249a	blueswir1	{
1929	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 9);
1930	0f8a249a	blueswir1	int32_t target;
1931	0f8a249a	blueswir1	switch (xop) {
1932	3475187d	bellard	#ifdef TARGET_SPARC64
1933	0f8a249a	blueswir1	case 0x1: /* V9 BPcc */
1934	0f8a249a	blueswir1	{
1935	0f8a249a	blueswir1	int cc;
1936	0f8a249a	blueswir1
1937	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1938	0f8a249a	blueswir1	target = sign_extend(target, 18);
1939	0f8a249a	blueswir1	target <<= 2;
1940	0f8a249a	blueswir1	cc = GET_FIELD_SP(insn, 20, 21);
1941	0f8a249a	blueswir1	if (cc == 0)
1942	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1943	0f8a249a	blueswir1	else if (cc == 2)
1944	6ae20372	blueswir1	do_branch(dc, target, insn, 1, cpu_cond);
1945	0f8a249a	blueswir1	else
1946	0f8a249a	blueswir1	goto illegal_insn;
1947	0f8a249a	blueswir1	goto jmp_insn;
1948	0f8a249a	blueswir1	}
1949	0f8a249a	blueswir1	case 0x3: /* V9 BPr */
1950	0f8a249a	blueswir1	{
1951	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 13) \|
1952	13846e70	bellard	(GET_FIELD_SP(insn, 20, 21) << 14);
1953	0f8a249a	blueswir1	target = sign_extend(target, 16);
1954	0f8a249a	blueswir1	target <<= 2;
1955	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
1956	6ae20372	blueswir1	do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1957	0f8a249a	blueswir1	goto jmp_insn;
1958	0f8a249a	blueswir1	}
1959	0f8a249a	blueswir1	case 0x5: /* V9 FBPcc */
1960	0f8a249a	blueswir1	{
1961	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 20, 21);
1962	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1963	a80dde08	bellard	goto jmp_insn;
1964	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1965	0f8a249a	blueswir1	target = sign_extend(target, 19);
1966	0f8a249a	blueswir1	target <<= 2;
1967	6ae20372	blueswir1	do_fbranch(dc, target, insn, cc, cpu_cond);
1968	0f8a249a	blueswir1	goto jmp_insn;
1969	0f8a249a	blueswir1	}
1970	a4d17f19	blueswir1	#else
1971	0f8a249a	blueswir1	case 0x7: /* CBN+x */
1972	0f8a249a	blueswir1	{
1973	0f8a249a	blueswir1	goto ncp_insn;
1974	0f8a249a	blueswir1	}
1975	0f8a249a	blueswir1	#endif
1976	0f8a249a	blueswir1	case 0x2: /* BN+x */
1977	0f8a249a	blueswir1	{
1978	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1979	0f8a249a	blueswir1	target = sign_extend(target, 22);
1980	0f8a249a	blueswir1	target <<= 2;
1981	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1982	0f8a249a	blueswir1	goto jmp_insn;
1983	0f8a249a	blueswir1	}
1984	0f8a249a	blueswir1	case 0x6: /* FBN+x */
1985	0f8a249a	blueswir1	{
1986	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1987	a80dde08	bellard	goto jmp_insn;
1988	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1989	0f8a249a	blueswir1	target = sign_extend(target, 22);
1990	0f8a249a	blueswir1	target <<= 2;
1991	6ae20372	blueswir1	do_fbranch(dc, target, insn, 0, cpu_cond);
1992	0f8a249a	blueswir1	goto jmp_insn;
1993	0f8a249a	blueswir1	}
1994	0f8a249a	blueswir1	case 0x4: /* SETHI */
1995	0f8a249a	blueswir1	if (rd) { // nop
1996	0f8a249a	blueswir1	uint32_t value = GET_FIELD(insn, 10, 31);
1997	2ea815ca	blueswir1	TCGv r_const;
1998	2ea815ca	blueswir1
1999	2ea815ca	blueswir1	r_const = tcg_const_tl(value << 10);
2000	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2001	2ea815ca	blueswir1	tcg_temp_free(r_const);
2002	0f8a249a	blueswir1	}
2003	0f8a249a	blueswir1	break;
2004	0f8a249a	blueswir1	case 0x0: /* UNIMPL */
2005	0f8a249a	blueswir1	default:
2006	3475187d	bellard	goto illegal_insn;
2007	0f8a249a	blueswir1	}
2008	0f8a249a	blueswir1	break;
2009	0f8a249a	blueswir1	}
2010	0f8a249a	blueswir1	break;
2011	cf495bcf	bellard	case 1:
2012	0f8a249a	blueswir1	/CALL/ {
2013	0f8a249a	blueswir1	target_long target = GET_FIELDs(insn, 2, 31) << 2;
2014	2ea815ca	blueswir1	TCGv r_const;
2015	cf495bcf	bellard
2016	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2017	2ea815ca	blueswir1	gen_movl_TN_reg(15, r_const);
2018	2ea815ca	blueswir1	tcg_temp_free(r_const);
2019	0f8a249a	blueswir1	target += dc->pc;
2020	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
2021	0f8a249a	blueswir1	dc->npc = target;
2022	0f8a249a	blueswir1	}
2023	0f8a249a	blueswir1	goto jmp_insn;
2024	0f8a249a	blueswir1	case 2: /* FPU & Logical Operations */
2025	0f8a249a	blueswir1	{
2026	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
2027	0f8a249a	blueswir1	if (xop == 0x3a) { /* generate trap */
2028	cf495bcf	bellard	int cond;
2029	3475187d	bellard
2030	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2031	0f8a249a	blueswir1	if (IS_IMM) {
2032	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 25, 31);
2033	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2034	cf495bcf	bellard	} else {
2035	cf495bcf	bellard	rs2 = GET_FIELD(insn, 27, 31);
2036	0f8a249a	blueswir1	if (rs2 != 0) {
2037	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2038	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2039	6f551262	blueswir1	} else
2040	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
2041	cf495bcf	bellard	}
2042	cf495bcf	bellard	cond = GET_FIELD(insn, 3, 6);
2043	cf495bcf	bellard	if (cond == 0x8) {
2044	6ae20372	blueswir1	save_state(dc, cpu_cond);
2045	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_trap, cpu_dst);
2046	af7bf89b	bellard	} else if (cond != 0) {
2047	748b9d8e	blueswir1	TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2048	3475187d	bellard	#ifdef TARGET_SPARC64
2049	0f8a249a	blueswir1	/* V9 icc/xcc */
2050	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
2051	748b9d8e	blueswir1
2052	6ae20372	blueswir1	save_state(dc, cpu_cond);
2053	0f8a249a	blueswir1	if (cc == 0)
2054	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2055	0f8a249a	blueswir1	else if (cc == 2)
2056	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
2057	0f8a249a	blueswir1	else
2058	0f8a249a	blueswir1	goto illegal_insn;
2059	3475187d	bellard	#else
2060	6ae20372	blueswir1	save_state(dc, cpu_cond);
2061	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2062	3475187d	bellard	#endif
2063	6ae20372	blueswir1	tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2064	2ea815ca	blueswir1	tcg_temp_free(r_cond);
2065	cf495bcf	bellard	}
2066	a80dde08	bellard	gen_op_next_insn();
2067	57fec1fe	bellard	tcg_gen_exit_tb(0);
2068	a80dde08	bellard	dc->is_br = 1;
2069	a80dde08	bellard	goto jmp_insn;
2070	cf495bcf	bellard	} else if (xop == 0x28) {
2071	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2072	cf495bcf	bellard	switch(rs1) {
2073	cf495bcf	bellard	case 0: /* rdy */
2074	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
2075	65fe7b09	blueswir1	case 0x01 ... 0x0e: /* undefined in the SPARCv8
2076	65fe7b09	blueswir1	manual, rdy on the microSPARC
2077	65fe7b09	blueswir1	II */
2078	65fe7b09	blueswir1	case 0x0f: /* stbar in the SPARCv8 manual,
2079	65fe7b09	blueswir1	rdy on the microSPARC II */
2080	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent in the
2081	65fe7b09	blueswir1	SPARCv8 manual, rdy on the
2082	65fe7b09	blueswir1	microSPARC II */
2083	65fe7b09	blueswir1	#endif
2084	77f193da	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2085	77f193da	blueswir1	offsetof(CPUSPARCState, y));
2086	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2087	cf495bcf	bellard	break;
2088	3475187d	bellard	#ifdef TARGET_SPARC64
2089	0f8a249a	blueswir1	case 0x2: /* V9 rdccr */
2090	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2091	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2092	3475187d	bellard	break;
2093	0f8a249a	blueswir1	case 0x3: /* V9 rdasi */
2094	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2095	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
2096	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2097	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2098	3475187d	bellard	break;
2099	0f8a249a	blueswir1	case 0x4: /* V9 rdtick */
2100	ccd4a219	blueswir1	{
2101	ccd4a219	blueswir1	TCGv r_tickptr;
2102	ccd4a219	blueswir1
2103	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2104	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2105	ccd4a219	blueswir1	offsetof(CPUState, tick));
2106	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2107	ccd4a219	blueswir1	r_tickptr);
2108	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2109	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2110	ccd4a219	blueswir1	}
2111	3475187d	bellard	break;
2112	0f8a249a	blueswir1	case 0x5: /* V9 rdpc */
2113	2ea815ca	blueswir1	{
2114	2ea815ca	blueswir1	TCGv r_const;
2115	2ea815ca	blueswir1
2116	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2117	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2118	2ea815ca	blueswir1	tcg_temp_free(r_const);
2119	2ea815ca	blueswir1	}
2120	0f8a249a	blueswir1	break;
2121	0f8a249a	blueswir1	case 0x6: /* V9 rdfprs */
2122	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2123	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
2124	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2125	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2126	3475187d	bellard	break;
2127	65fe7b09	blueswir1	case 0xf: /* V9 membar */
2128	65fe7b09	blueswir1	break; /* no effect */
2129	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
2130	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2131	725cb90b	bellard	goto jmp_insn;
2132	77f193da	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2133	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
2134	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2135	725cb90b	bellard	break;
2136	0f8a249a	blueswir1	case 0x17: /* Tick compare */
2137	77f193da	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2138	77f193da	blueswir1	offsetof(CPUSPARCState, tick_cmpr));
2139	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2140	83469015	bellard	break;
2141	0f8a249a	blueswir1	case 0x18: /* System tick */
2142	ccd4a219	blueswir1	{
2143	ccd4a219	blueswir1	TCGv r_tickptr;
2144	ccd4a219	blueswir1
2145	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2146	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2147	ccd4a219	blueswir1	offsetof(CPUState, stick));
2148	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2149	ccd4a219	blueswir1	r_tickptr);
2150	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2151	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2152	ccd4a219	blueswir1	}
2153	83469015	bellard	break;
2154	0f8a249a	blueswir1	case 0x19: /* System tick compare */
2155	77f193da	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2156	77f193da	blueswir1	offsetof(CPUSPARCState, stick_cmpr));
2157	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2158	83469015	bellard	break;
2159	0f8a249a	blueswir1	case 0x10: /* Performance Control */
2160	0f8a249a	blueswir1	case 0x11: /* Performance Instrumentation Counter */
2161	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
2162	0f8a249a	blueswir1	case 0x14: /* Softint set, WO */
2163	0f8a249a	blueswir1	case 0x15: /* Softint clear, WO */
2164	0f8a249a	blueswir1	case 0x16: /* Softint write */
2165	3475187d	bellard	#endif
2166	3475187d	bellard	default:
2167	cf495bcf	bellard	goto illegal_insn;
2168	cf495bcf	bellard	}
2169	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
2170	e9ebed4d	blueswir1	} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2171	3475187d	bellard	#ifndef TARGET_SPARC64
2172	0f8a249a	blueswir1	if (!supervisor(dc))
2173	0f8a249a	blueswir1	goto priv_insn;
2174	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2175	e9ebed4d	blueswir1	#else
2176	e9ebed4d	blueswir1	if (!hypervisor(dc))
2177	e9ebed4d	blueswir1	goto priv_insn;
2178	e9ebed4d	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
2179	e9ebed4d	blueswir1	switch (rs1) {
2180	e9ebed4d	blueswir1	case 0: // hpstate
2181	e9ebed4d	blueswir1	// gen_op_rdhpstate();
2182	e9ebed4d	blueswir1	break;
2183	e9ebed4d	blueswir1	case 1: // htstate
2184	e9ebed4d	blueswir1	// gen_op_rdhtstate();
2185	e9ebed4d	blueswir1	break;
2186	e9ebed4d	blueswir1	case 3: // hintp
2187	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2188	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
2189	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2190	e9ebed4d	blueswir1	break;
2191	e9ebed4d	blueswir1	case 5: // htba
2192	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2193	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
2194	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2195	e9ebed4d	blueswir1	break;
2196	e9ebed4d	blueswir1	case 6: // hver
2197	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2198	77f193da	blueswir1	offsetof(CPUSPARCState, hver));
2199	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2200	e9ebed4d	blueswir1	break;
2201	e9ebed4d	blueswir1	case 31: // hstick_cmpr
2202	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2203	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
2204	77f193da	blueswir1	offsetof(CPUSPARCState, hstick_cmpr));
2205	e9ebed4d	blueswir1	break;
2206	e9ebed4d	blueswir1	default:
2207	e9ebed4d	blueswir1	goto illegal_insn;
2208	e9ebed4d	blueswir1	}
2209	e9ebed4d	blueswir1	#endif
2210	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2211	e8af50a3	bellard	break;
2212	3475187d	bellard	} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2213	0f8a249a	blueswir1	if (!supervisor(dc))
2214	0f8a249a	blueswir1	goto priv_insn;
2215	3475187d	bellard	#ifdef TARGET_SPARC64
2216	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
2217	0f8a249a	blueswir1	switch (rs1) {
2218	0f8a249a	blueswir1	case 0: // tpc
2219	375ee38b	blueswir1	{
2220	375ee38b	blueswir1	TCGv r_tsptr;
2221	375ee38b	blueswir1
2222	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2223	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2224	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2225	6ae20372	blueswir1	tcg_gen_ld_tl(cpu_dst, r_tsptr,
2226	375ee38b	blueswir1	offsetof(trap_state, tpc));
2227	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2228	375ee38b	blueswir1	}
2229	0f8a249a	blueswir1	break;
2230	0f8a249a	blueswir1	case 1: // tnpc
2231	375ee38b	blueswir1	{
2232	375ee38b	blueswir1	TCGv r_tsptr;
2233	375ee38b	blueswir1
2234	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2235	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2236	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2237	6ae20372	blueswir1	tcg_gen_ld_tl(cpu_dst, r_tsptr,
2238	375ee38b	blueswir1	offsetof(trap_state, tnpc));
2239	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2240	375ee38b	blueswir1	}
2241	0f8a249a	blueswir1	break;
2242	0f8a249a	blueswir1	case 2: // tstate
2243	375ee38b	blueswir1	{
2244	375ee38b	blueswir1	TCGv r_tsptr;
2245	375ee38b	blueswir1
2246	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2247	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2248	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2249	6ae20372	blueswir1	tcg_gen_ld_tl(cpu_dst, r_tsptr,
2250	375ee38b	blueswir1	offsetof(trap_state, tstate));
2251	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2252	375ee38b	blueswir1	}
2253	0f8a249a	blueswir1	break;
2254	0f8a249a	blueswir1	case 3: // tt
2255	375ee38b	blueswir1	{
2256	375ee38b	blueswir1	TCGv r_tsptr;
2257	375ee38b	blueswir1
2258	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2259	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2260	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2261	6ae20372	blueswir1	tcg_gen_ld_i32(cpu_dst, r_tsptr,
2262	375ee38b	blueswir1	offsetof(trap_state, tt));
2263	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2264	375ee38b	blueswir1	}
2265	0f8a249a	blueswir1	break;
2266	0f8a249a	blueswir1	case 4: // tick
2267	ccd4a219	blueswir1	{
2268	ccd4a219	blueswir1	TCGv r_tickptr;
2269	ccd4a219	blueswir1
2270	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2271	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2272	ccd4a219	blueswir1	offsetof(CPUState, tick));
2273	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2274	ccd4a219	blueswir1	r_tickptr);
2275	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2276	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2277	ccd4a219	blueswir1	}
2278	0f8a249a	blueswir1	break;
2279	0f8a249a	blueswir1	case 5: // tba
2280	77f193da	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2281	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
2282	0f8a249a	blueswir1	break;
2283	0f8a249a	blueswir1	case 6: // pstate
2284	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2285	77f193da	blueswir1	offsetof(CPUSPARCState, pstate));
2286	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2287	0f8a249a	blueswir1	break;
2288	0f8a249a	blueswir1	case 7: // tl
2289	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2290	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
2291	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2292	0f8a249a	blueswir1	break;
2293	0f8a249a	blueswir1	case 8: // pil
2294	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295	77f193da	blueswir1	offsetof(CPUSPARCState, psrpil));
2296	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2297	0f8a249a	blueswir1	break;
2298	0f8a249a	blueswir1	case 9: // cwp
2299	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2300	0f8a249a	blueswir1	break;
2301	0f8a249a	blueswir1	case 10: // cansave
2302	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2303	77f193da	blueswir1	offsetof(CPUSPARCState, cansave));
2304	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2305	0f8a249a	blueswir1	break;
2306	0f8a249a	blueswir1	case 11: // canrestore
2307	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2308	77f193da	blueswir1	offsetof(CPUSPARCState, canrestore));
2309	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2310	0f8a249a	blueswir1	break;
2311	0f8a249a	blueswir1	case 12: // cleanwin
2312	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2313	77f193da	blueswir1	offsetof(CPUSPARCState, cleanwin));
2314	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2315	0f8a249a	blueswir1	break;
2316	0f8a249a	blueswir1	case 13: // otherwin
2317	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2318	77f193da	blueswir1	offsetof(CPUSPARCState, otherwin));
2319	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2320	0f8a249a	blueswir1	break;
2321	0f8a249a	blueswir1	case 14: // wstate
2322	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2323	77f193da	blueswir1	offsetof(CPUSPARCState, wstate));
2324	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2325	0f8a249a	blueswir1	break;
2326	e9ebed4d	blueswir1	case 16: // UA2005 gl
2327	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2328	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
2329	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2330	e9ebed4d	blueswir1	break;
2331	e9ebed4d	blueswir1	case 26: // UA2005 strand status
2332	e9ebed4d	blueswir1	if (!hypervisor(dc))
2333	e9ebed4d	blueswir1	goto priv_insn;
2334	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2335	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
2336	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2337	e9ebed4d	blueswir1	break;
2338	0f8a249a	blueswir1	case 31: // ver
2339	77f193da	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2340	77f193da	blueswir1	offsetof(CPUSPARCState, version));
2341	0f8a249a	blueswir1	break;
2342	0f8a249a	blueswir1	case 15: // fq
2343	0f8a249a	blueswir1	default:
2344	0f8a249a	blueswir1	goto illegal_insn;
2345	0f8a249a	blueswir1	}
2346	3475187d	bellard	#else
2347	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2348	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
2349	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2350	3475187d	bellard	#endif
2351	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2352	e8af50a3	bellard	break;
2353	3475187d	bellard	} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2354	3475187d	bellard	#ifdef TARGET_SPARC64
2355	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_flushw);
2356	3475187d	bellard	#else
2357	0f8a249a	blueswir1	if (!supervisor(dc))
2358	0f8a249a	blueswir1	goto priv_insn;
2359	6ae20372	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2360	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2361	3475187d	bellard	#endif
2362	e8af50a3	bellard	break;
2363	e8af50a3	bellard	#endif
2364	0f8a249a	blueswir1	} else if (xop == 0x34) { /* FPU Operations */
2365	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2366	a80dde08	bellard	goto jmp_insn;
2367	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2368	e8af50a3	bellard	rs1 = GET_FIELD(insn, 13, 17);
2369	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2370	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2371	0f8a249a	blueswir1	switch (xop) {
2372	0f8a249a	blueswir1	case 0x1: /* fmovs */
2373	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs2);
2374	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2375	0f8a249a	blueswir1	break;
2376	0f8a249a	blueswir1	case 0x5: /* fnegs */
2377	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2378	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegs);
2379	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2380	0f8a249a	blueswir1	break;
2381	0f8a249a	blueswir1	case 0x9: /* fabss */
2382	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2383	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabss);
2384	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2385	0f8a249a	blueswir1	break;
2386	0f8a249a	blueswir1	case 0x29: /* fsqrts */
2387	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2388	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2389	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2390	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrts);
2391	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2392	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2393	0f8a249a	blueswir1	break;
2394	0f8a249a	blueswir1	case 0x2a: /* fsqrtd */
2395	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2396	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2397	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2398	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtd);
2399	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2400	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2401	0f8a249a	blueswir1	break;
2402	0f8a249a	blueswir1	case 0x2b: /* fsqrtq */
2403	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2404	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2405	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2406	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtq);
2407	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2408	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2409	1f587329	blueswir1	break;
2410	0f8a249a	blueswir1	case 0x41:
2411	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2412	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2413	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2414	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fadds);
2415	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2416	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2417	0f8a249a	blueswir1	break;
2418	0f8a249a	blueswir1	case 0x42:
2419	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2420	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2421	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2422	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddd);
2423	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2424	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2425	0f8a249a	blueswir1	break;
2426	0f8a249a	blueswir1	case 0x43: /* faddq */
2427	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2428	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2429	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2430	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2431	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddq);
2432	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2433	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2434	1f587329	blueswir1	break;
2435	0f8a249a	blueswir1	case 0x45:
2436	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2437	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2438	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2439	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubs);
2440	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2441	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2442	0f8a249a	blueswir1	break;
2443	0f8a249a	blueswir1	case 0x46:
2444	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2445	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2446	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2447	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubd);
2448	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2449	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2450	0f8a249a	blueswir1	break;
2451	0f8a249a	blueswir1	case 0x47: /* fsubq */
2452	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2453	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2454	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2455	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2456	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubq);
2457	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2458	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2459	1f587329	blueswir1	break;
2460	64a88d5d	blueswir1	case 0x49: /* fmuls */
2461	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2462	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2463	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2464	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2465	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuls);
2466	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2467	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2468	0f8a249a	blueswir1	break;
2469	64a88d5d	blueswir1	case 0x4a: /* fmuld */
2470	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2471	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2472	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2473	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2474	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld);
2475	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2476	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2477	0f8a249a	blueswir1	break;
2478	0f8a249a	blueswir1	case 0x4b: /* fmulq */
2479	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2480	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2481	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2482	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2483	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2484	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmulq);
2485	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2486	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2487	1f587329	blueswir1	break;
2488	0f8a249a	blueswir1	case 0x4d:
2489	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2490	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2491	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2492	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivs);
2493	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2494	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2495	0f8a249a	blueswir1	break;
2496	0f8a249a	blueswir1	case 0x4e:
2497	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2498	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2499	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2500	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivd);
2501	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2502	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2503	0f8a249a	blueswir1	break;
2504	0f8a249a	blueswir1	case 0x4f: /* fdivq */
2505	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2506	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2507	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2508	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2509	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivq);
2510	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2511	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2512	1f587329	blueswir1	break;
2513	0f8a249a	blueswir1	case 0x69:
2514	e30b4678	blueswir1	CHECK_FPU_FEATURE(dc, FSMULD);
2515	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2516	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2517	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2518	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsmuld);
2519	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2520	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2521	0f8a249a	blueswir1	break;
2522	0f8a249a	blueswir1	case 0x6e: /* fdmulq */
2523	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2524	1f587329	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2525	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2526	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2527	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdmulq);
2528	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2529	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2530	1f587329	blueswir1	break;
2531	0f8a249a	blueswir1	case 0xc4:
2532	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2533	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2534	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitos);
2535	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2536	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2537	0f8a249a	blueswir1	break;
2538	0f8a249a	blueswir1	case 0xc6:
2539	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2540	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2541	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtos);
2542	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2543	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2544	0f8a249a	blueswir1	break;
2545	0f8a249a	blueswir1	case 0xc7: /* fqtos */
2546	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2547	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2548	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2549	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtos);
2550	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2551	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2552	1f587329	blueswir1	break;
2553	0f8a249a	blueswir1	case 0xc8:
2554	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2555	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitod);
2556	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2557	0f8a249a	blueswir1	break;
2558	0f8a249a	blueswir1	case 0xc9:
2559	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2560	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstod);
2561	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2562	0f8a249a	blueswir1	break;
2563	0f8a249a	blueswir1	case 0xcb: /* fqtod */
2564	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2565	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2566	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2567	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtod);
2568	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2569	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2570	1f587329	blueswir1	break;
2571	0f8a249a	blueswir1	case 0xcc: /* fitoq */
2572	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2573	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2574	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitoq);
2575	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2576	1f587329	blueswir1	break;
2577	0f8a249a	blueswir1	case 0xcd: /* fstoq */
2578	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2579	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2580	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoq);
2581	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2582	1f587329	blueswir1	break;
2583	0f8a249a	blueswir1	case 0xce: /* fdtoq */
2584	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2585	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2586	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoq);
2587	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2588	1f587329	blueswir1	break;
2589	0f8a249a	blueswir1	case 0xd1:
2590	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2591	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2592	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoi);
2593	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2594	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2595	0f8a249a	blueswir1	break;
2596	0f8a249a	blueswir1	case 0xd2:
2597	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2598	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2599	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoi);
2600	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2601	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2602	0f8a249a	blueswir1	break;
2603	0f8a249a	blueswir1	case 0xd3: /* fqtoi */
2604	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2605	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2606	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2607	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtoi);
2608	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2609	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2610	1f587329	blueswir1	break;
2611	3475187d	bellard	#ifdef TARGET_SPARC64
2612	0f8a249a	blueswir1	case 0x2: /* V9 fmovd */
2613	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2614	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2615	0f8a249a	blueswir1	break;
2616	1f587329	blueswir1	case 0x3: /* V9 fmovq */
2617	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2618	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2619	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2620	1f587329	blueswir1	break;
2621	0f8a249a	blueswir1	case 0x6: /* V9 fnegd */
2622	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2623	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegd);
2624	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2625	0f8a249a	blueswir1	break;
2626	1f587329	blueswir1	case 0x7: /* V9 fnegq */
2627	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2628	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2629	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegq);
2630	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2631	1f587329	blueswir1	break;
2632	0f8a249a	blueswir1	case 0xa: /* V9 fabsd */
2633	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2634	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsd);
2635	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2636	0f8a249a	blueswir1	break;
2637	1f587329	blueswir1	case 0xb: /* V9 fabsq */
2638	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2639	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2640	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsq);
2641	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2642	1f587329	blueswir1	break;
2643	0f8a249a	blueswir1	case 0x81: /* V9 fstox */
2644	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2645	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2646	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstox);
2647	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2648	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2649	0f8a249a	blueswir1	break;
2650	0f8a249a	blueswir1	case 0x82: /* V9 fdtox */
2651	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2652	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2653	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtox);
2654	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2655	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2656	0f8a249a	blueswir1	break;
2657	1f587329	blueswir1	case 0x83: /* V9 fqtox */
2658	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2659	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2660	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2661	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtox);
2662	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2663	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2664	1f587329	blueswir1	break;
2665	0f8a249a	blueswir1	case 0x84: /* V9 fxtos */
2666	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2667	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2668	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtos);
2669	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2670	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2671	0f8a249a	blueswir1	break;
2672	0f8a249a	blueswir1	case 0x88: /* V9 fxtod */
2673	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2674	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2675	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtod);
2676	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2677	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2678	0f8a249a	blueswir1	break;
2679	0f8a249a	blueswir1	case 0x8c: /* V9 fxtoq */
2680	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2681	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2682	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2683	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtoq);
2684	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2685	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2686	1f587329	blueswir1	break;
2687	1f587329	blueswir1	#endif
2688	0f8a249a	blueswir1	default:
2689	0f8a249a	blueswir1	goto illegal_insn;
2690	0f8a249a	blueswir1	}
2691	0f8a249a	blueswir1	} else if (xop == 0x35) { /* FPU Operations */
2692	3475187d	bellard	#ifdef TARGET_SPARC64
2693	0f8a249a	blueswir1	int cond;
2694	3475187d	bellard	#endif
2695	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2696	a80dde08	bellard	goto jmp_insn;
2697	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2698	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2699	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2700	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2701	3475187d	bellard	#ifdef TARGET_SPARC64
2702	0f8a249a	blueswir1	if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2703	dcf24905	blueswir1	int l1;
2704	dcf24905	blueswir1
2705	dcf24905	blueswir1	l1 = gen_new_label();
2706	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2707	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2708	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2709	cb63669a	pbrook	0, l1);
2710	19f329ad	blueswir1	gen_op_load_fpr_FT0(rs2);
2711	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2712	dcf24905	blueswir1	gen_set_label(l1);
2713	0f8a249a	blueswir1	break;
2714	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2715	dcf24905	blueswir1	int l1;
2716	dcf24905	blueswir1
2717	dcf24905	blueswir1	l1 = gen_new_label();
2718	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2719	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2720	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2721	cb63669a	pbrook	0, l1);
2722	19f329ad	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2723	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2724	dcf24905	blueswir1	gen_set_label(l1);
2725	0f8a249a	blueswir1	break;
2726	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2727	dcf24905	blueswir1	int l1;
2728	dcf24905	blueswir1
2729	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2730	dcf24905	blueswir1	l1 = gen_new_label();
2731	1f587329	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2732	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2733	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2734	cb63669a	pbrook	0, l1);
2735	19f329ad	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2736	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2737	dcf24905	blueswir1	gen_set_label(l1);
2738	1f587329	blueswir1	break;
2739	0f8a249a	blueswir1	}
2740	0f8a249a	blueswir1	#endif
2741	0f8a249a	blueswir1	switch (xop) {
2742	3475187d	bellard	#ifdef TARGET_SPARC64
2743	19f329ad	blueswir1	#define FMOVCC(size_FDQ, fcc) \
2744	19f329ad	blueswir1	{ \
2745	0425bee5	blueswir1	TCGv r_cond; \
2746	19f329ad	blueswir1	int l1; \
2747	19f329ad	blueswir1	\
2748	19f329ad	blueswir1	l1 = gen_new_label(); \
2749	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2750	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2751	19f329ad	blueswir1	gen_fcond(r_cond, fcc, cond); \
2752	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2753	cb63669a	pbrook	0, l1); \
2754	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2755	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2756	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2757	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2758	19f329ad	blueswir1	gen_set_label(l1); \
2759	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2760	19f329ad	blueswir1	}
2761	0f8a249a	blueswir1	case 0x001: /* V9 fmovscc %fcc0 */
2762	19f329ad	blueswir1	FMOVCC(F, 0);
2763	0f8a249a	blueswir1	break;
2764	0f8a249a	blueswir1	case 0x002: /* V9 fmovdcc %fcc0 */
2765	19f329ad	blueswir1	FMOVCC(D, 0);
2766	0f8a249a	blueswir1	break;
2767	0f8a249a	blueswir1	case 0x003: /* V9 fmovqcc %fcc0 */
2768	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2769	19f329ad	blueswir1	FMOVCC(Q, 0);
2770	1f587329	blueswir1	break;
2771	0f8a249a	blueswir1	case 0x041: /* V9 fmovscc %fcc1 */
2772	19f329ad	blueswir1	FMOVCC(F, 1);
2773	0f8a249a	blueswir1	break;
2774	0f8a249a	blueswir1	case 0x042: /* V9 fmovdcc %fcc1 */
2775	19f329ad	blueswir1	FMOVCC(D, 1);
2776	0f8a249a	blueswir1	break;
2777	0f8a249a	blueswir1	case 0x043: /* V9 fmovqcc %fcc1 */
2778	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2779	19f329ad	blueswir1	FMOVCC(Q, 1);
2780	1f587329	blueswir1	break;
2781	0f8a249a	blueswir1	case 0x081: /* V9 fmovscc %fcc2 */
2782	19f329ad	blueswir1	FMOVCC(F, 2);
2783	0f8a249a	blueswir1	break;
2784	0f8a249a	blueswir1	case 0x082: /* V9 fmovdcc %fcc2 */
2785	19f329ad	blueswir1	FMOVCC(D, 2);
2786	0f8a249a	blueswir1	break;
2787	0f8a249a	blueswir1	case 0x083: /* V9 fmovqcc %fcc2 */
2788	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2789	19f329ad	blueswir1	FMOVCC(Q, 2);
2790	1f587329	blueswir1	break;
2791	0f8a249a	blueswir1	case 0x0c1: /* V9 fmovscc %fcc3 */
2792	19f329ad	blueswir1	FMOVCC(F, 3);
2793	0f8a249a	blueswir1	break;
2794	0f8a249a	blueswir1	case 0x0c2: /* V9 fmovdcc %fcc3 */
2795	19f329ad	blueswir1	FMOVCC(D, 3);
2796	0f8a249a	blueswir1	break;
2797	0f8a249a	blueswir1	case 0x0c3: /* V9 fmovqcc %fcc3 */
2798	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2799	19f329ad	blueswir1	FMOVCC(Q, 3);
2800	1f587329	blueswir1	break;
2801	19f329ad	blueswir1	#undef FMOVCC
2802	19f329ad	blueswir1	#define FMOVCC(size_FDQ, icc) \
2803	19f329ad	blueswir1	{ \
2804	0425bee5	blueswir1	TCGv r_cond; \
2805	19f329ad	blueswir1	int l1; \
2806	19f329ad	blueswir1	\
2807	19f329ad	blueswir1	l1 = gen_new_label(); \
2808	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2809	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2810	19f329ad	blueswir1	gen_cond(r_cond, icc, cond); \
2811	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2812	cb63669a	pbrook	0, l1); \
2813	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2814	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2815	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2816	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2817	19f329ad	blueswir1	gen_set_label(l1); \
2818	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2819	19f329ad	blueswir1	}
2820	19f329ad	blueswir1
2821	0f8a249a	blueswir1	case 0x101: /* V9 fmovscc %icc */
2822	19f329ad	blueswir1	FMOVCC(F, 0);
2823	0f8a249a	blueswir1	break;
2824	0f8a249a	blueswir1	case 0x102: /* V9 fmovdcc %icc */
2825	19f329ad	blueswir1	FMOVCC(D, 0);
2826	0f8a249a	blueswir1	case 0x103: /* V9 fmovqcc %icc */
2827	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2828	64a88d5d	blueswir1	FMOVCC(Q, 0);
2829	1f587329	blueswir1	break;
2830	0f8a249a	blueswir1	case 0x181: /* V9 fmovscc %xcc */
2831	19f329ad	blueswir1	FMOVCC(F, 1);
2832	0f8a249a	blueswir1	break;
2833	0f8a249a	blueswir1	case 0x182: /* V9 fmovdcc %xcc */
2834	19f329ad	blueswir1	FMOVCC(D, 1);
2835	0f8a249a	blueswir1	break;
2836	0f8a249a	blueswir1	case 0x183: /* V9 fmovqcc %xcc */
2837	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2838	19f329ad	blueswir1	FMOVCC(Q, 1);
2839	1f587329	blueswir1	break;
2840	19f329ad	blueswir1	#undef FMOVCC
2841	1f587329	blueswir1	#endif
2842	1f587329	blueswir1	case 0x51: /* fcmps, V9 %fcc */
2843	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2844	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2845	7e8c2b6c	blueswir1	gen_op_fcmps(rd & 3);
2846	0f8a249a	blueswir1	break;
2847	1f587329	blueswir1	case 0x52: /* fcmpd, V9 %fcc */
2848	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2849	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2850	7e8c2b6c	blueswir1	gen_op_fcmpd(rd & 3);
2851	0f8a249a	blueswir1	break;
2852	1f587329	blueswir1	case 0x53: /* fcmpq, V9 %fcc */
2853	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2854	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2855	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2856	7e8c2b6c	blueswir1	gen_op_fcmpq(rd & 3);
2857	1f587329	blueswir1	break;
2858	0f8a249a	blueswir1	case 0x55: /* fcmpes, V9 %fcc */
2859	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2860	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2861	7e8c2b6c	blueswir1	gen_op_fcmpes(rd & 3);
2862	0f8a249a	blueswir1	break;
2863	0f8a249a	blueswir1	case 0x56: /* fcmped, V9 %fcc */
2864	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2865	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2866	7e8c2b6c	blueswir1	gen_op_fcmped(rd & 3);
2867	0f8a249a	blueswir1	break;
2868	1f587329	blueswir1	case 0x57: /* fcmpeq, V9 %fcc */
2869	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2870	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2871	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2872	7e8c2b6c	blueswir1	gen_op_fcmpeq(rd & 3);
2873	1f587329	blueswir1	break;
2874	0f8a249a	blueswir1	default:
2875	0f8a249a	blueswir1	goto illegal_insn;
2876	0f8a249a	blueswir1	}
2877	0f8a249a	blueswir1	} else if (xop == 0x2) {
2878	0f8a249a	blueswir1	// clr/mov shortcut
2879	e80cfcfc	bellard
2880	e80cfcfc	bellard	rs1 = GET_FIELD(insn, 13, 17);
2881	0f8a249a	blueswir1	if (rs1 == 0) {
2882	1a2fb1c0	blueswir1	// or %g0, x, y -> mov T0, x; mov y, T0
2883	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2884	2ea815ca	blueswir1	TCGv r_const;
2885	2ea815ca	blueswir1
2886	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2887	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
2888	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2889	2ea815ca	blueswir1	tcg_temp_free(r_const);
2890	0f8a249a	blueswir1	} else { /* register */
2891	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2892	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_dst);
2893	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2894	0f8a249a	blueswir1	}
2895	0f8a249a	blueswir1	} else {
2896	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2897	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2898	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2899	6ae20372	blueswir1	tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2900	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2901	0f8a249a	blueswir1	} else { /* register */
2902	0f8a249a	blueswir1	// or x, %g0, y -> mov T1, x; mov y, T1
2903	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2904	0f8a249a	blueswir1	if (rs2 != 0) {
2905	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2906	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2907	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2908	6f551262	blueswir1	} else
2909	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_src1);
2910	0f8a249a	blueswir1	}
2911	0f8a249a	blueswir1	}
2912	83469015	bellard	#ifdef TARGET_SPARC64
2913	0f8a249a	blueswir1	} else if (xop == 0x25) { /* sll, V9 sllx */
2914	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2915	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2916	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2917	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2918	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2919	1a2fb1c0	blueswir1	} else {
2920	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2921	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2922	1a2fb1c0	blueswir1	}
2923	0f8a249a	blueswir1	} else { /* register */
2924	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2925	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2926	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2927	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2928	6ae20372	blueswir1	tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2929	1a2fb1c0	blueswir1	} else {
2930	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2931	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2932	6ae20372	blueswir1	tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2933	1a2fb1c0	blueswir1	}
2934	83469015	bellard	}
2935	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2936	0f8a249a	blueswir1	} else if (xop == 0x26) { /* srl, V9 srlx */
2937	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2938	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2939	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2940	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2941	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2942	1a2fb1c0	blueswir1	} else {
2943	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2944	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2945	1a2fb1c0	blueswir1	}
2946	0f8a249a	blueswir1	} else { /* register */
2947	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2948	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2949	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2950	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2951	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2952	1a2fb1c0	blueswir1	} else {
2953	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2954	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2955	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2956	1a2fb1c0	blueswir1	}
2957	83469015	bellard	}
2958	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2959	0f8a249a	blueswir1	} else if (xop == 0x27) { /* sra, V9 srax */
2960	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2961	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2962	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2963	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2964	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2965	1a2fb1c0	blueswir1	} else {
2966	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2967	6ae20372	blueswir1	tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2968	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2969	1a2fb1c0	blueswir1	}
2970	0f8a249a	blueswir1	} else { /* register */
2971	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2972	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2973	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2974	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2975	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2976	1a2fb1c0	blueswir1	} else {
2977	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2978	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2979	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2980	1a2fb1c0	blueswir1	}
2981	83469015	bellard	}
2982	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2983	83469015	bellard	#endif
2984	fcc72045	blueswir1	} else if (xop < 0x36) {
2985	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2986	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
2987	cf495bcf	bellard	if (xop < 0x20) {
2988	cf495bcf	bellard	switch (xop & ~0x10) {
2989	cf495bcf	bellard	case 0x0:
2990	cf495bcf	bellard	if (xop & 0x10)
2991	6ae20372	blueswir1	gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2992	cf495bcf	bellard	else
2993	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2994	cf495bcf	bellard	break;
2995	cf495bcf	bellard	case 0x1:
2996	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2997	cf495bcf	bellard	if (xop & 0x10)
2998	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
2999	cf495bcf	bellard	break;
3000	cf495bcf	bellard	case 0x2:
3001	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3002	0f8a249a	blueswir1	if (xop & 0x10)
3003	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3004	0f8a249a	blueswir1	break;
3005	cf495bcf	bellard	case 0x3:
3006	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3007	cf495bcf	bellard	if (xop & 0x10)
3008	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3009	cf495bcf	bellard	break;
3010	cf495bcf	bellard	case 0x4:
3011	cf495bcf	bellard	if (xop & 0x10)
3012	6ae20372	blueswir1	gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3013	cf495bcf	bellard	else
3014	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3015	cf495bcf	bellard	break;
3016	cf495bcf	bellard	case 0x5:
3017	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3018	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3019	cf495bcf	bellard	if (xop & 0x10)
3020	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3021	cf495bcf	bellard	break;
3022	cf495bcf	bellard	case 0x6:
3023	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3025	cf495bcf	bellard	if (xop & 0x10)
3026	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3027	cf495bcf	bellard	break;
3028	cf495bcf	bellard	case 0x7:
3029	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3030	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3031	cf495bcf	bellard	if (xop & 0x10)
3032	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3033	cf495bcf	bellard	break;
3034	cf495bcf	bellard	case 0x8:
3035	cf495bcf	bellard	if (xop & 0x10)
3036	6ae20372	blueswir1	gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3037	38bc628b	blueswir1	else {
3038	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3039	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3040	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3041	38bc628b	blueswir1	}
3042	cf495bcf	bellard	break;
3043	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3044	0f8a249a	blueswir1	case 0x9: /* V9 mulx */
3045	6ae20372	blueswir1	tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3046	ded3ab80	pbrook	break;
3047	ded3ab80	pbrook	#endif
3048	cf495bcf	bellard	case 0xa:
3049	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3050	6ae20372	blueswir1	gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3051	cf495bcf	bellard	if (xop & 0x10)
3052	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3053	cf495bcf	bellard	break;
3054	cf495bcf	bellard	case 0xb:
3055	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3056	6ae20372	blueswir1	gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3057	cf495bcf	bellard	if (xop & 0x10)
3058	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3059	cf495bcf	bellard	break;
3060	cf495bcf	bellard	case 0xc:
3061	cf495bcf	bellard	if (xop & 0x10)
3062	6ae20372	blueswir1	gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3063	38bc628b	blueswir1	else {
3064	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3065	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3066	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3067	38bc628b	blueswir1	}
3068	cf495bcf	bellard	break;
3069	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3070	0f8a249a	blueswir1	case 0xd: /* V9 udivx */
3071	6ae20372	blueswir1	gen_trap_ifdivzero_tl(cpu_src2);
3072	6ae20372	blueswir1	tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
3073	ded3ab80	pbrook	break;
3074	ded3ab80	pbrook	#endif
3075	cf495bcf	bellard	case 0xe:
3076	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3077	77f193da	blueswir1	tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3078	77f193da	blueswir1	cpu_src2);
3079	cf495bcf	bellard	if (xop & 0x10)
3080	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3081	cf495bcf	bellard	break;
3082	cf495bcf	bellard	case 0xf:
3083	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3084	77f193da	blueswir1	tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3085	77f193da	blueswir1	cpu_src2);
3086	cf495bcf	bellard	if (xop & 0x10)
3087	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3088	cf495bcf	bellard	break;
3089	cf495bcf	bellard	default:
3090	cf495bcf	bellard	goto illegal_insn;
3091	cf495bcf	bellard	}
3092	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3093	cf495bcf	bellard	} else {
3094	cf495bcf	bellard	switch (xop) {
3095	0f8a249a	blueswir1	case 0x20: /* taddcc */
3096	6ae20372	blueswir1	gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3097	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3098	0f8a249a	blueswir1	break;
3099	0f8a249a	blueswir1	case 0x21: /* tsubcc */
3100	6ae20372	blueswir1	gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3101	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3102	0f8a249a	blueswir1	break;
3103	0f8a249a	blueswir1	case 0x22: /* taddcctv */
3104	6ae20372	blueswir1	save_state(dc, cpu_cond);
3105	6ae20372	blueswir1	gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3106	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3107	0f8a249a	blueswir1	break;
3108	0f8a249a	blueswir1	case 0x23: /* tsubcctv */
3109	6ae20372	blueswir1	save_state(dc, cpu_cond);
3110	6ae20372	blueswir1	gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3111	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3112	0f8a249a	blueswir1	break;
3113	cf495bcf	bellard	case 0x24: /* mulscc */
3114	6ae20372	blueswir1	gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3115	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3116	cf495bcf	bellard	break;
3117	83469015	bellard	#ifndef TARGET_SPARC64
3118	0f8a249a	blueswir1	case 0x25: /* sll */
3119	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3120	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3121	e35298cd	blueswir1	tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3122	e35298cd	blueswir1	} else { /* register */
3123	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3124	e35298cd	blueswir1	tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3125	e35298cd	blueswir1	}
3126	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3127	cf495bcf	bellard	break;
3128	83469015	bellard	case 0x26: /* srl */
3129	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3130	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3131	e35298cd	blueswir1	tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3132	e35298cd	blueswir1	} else { /* register */
3133	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3134	e35298cd	blueswir1	tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3135	e35298cd	blueswir1	}
3136	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3137	cf495bcf	bellard	break;
3138	83469015	bellard	case 0x27: /* sra */
3139	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3140	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3141	e35298cd	blueswir1	tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3142	e35298cd	blueswir1	} else { /* register */
3143	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3144	e35298cd	blueswir1	tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3145	e35298cd	blueswir1	}
3146	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3147	cf495bcf	bellard	break;
3148	83469015	bellard	#endif
3149	cf495bcf	bellard	case 0x30:
3150	cf495bcf	bellard	{
3151	cf495bcf	bellard	switch(rd) {
3152	3475187d	bellard	case 0: /* wry */
3153	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3154	77f193da	blueswir1	tcg_gen_st_tl(cpu_dst, cpu_env,
3155	77f193da	blueswir1	offsetof(CPUSPARCState, y));
3156	cf495bcf	bellard	break;
3157	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
3158	65fe7b09	blueswir1	case 0x01 ... 0x0f: /* undefined in the
3159	65fe7b09	blueswir1	SPARCv8 manual, nop
3160	65fe7b09	blueswir1	on the microSPARC
3161	65fe7b09	blueswir1	II */
3162	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent
3163	65fe7b09	blueswir1	in the SPARCv8
3164	65fe7b09	blueswir1	manual, nop on the
3165	65fe7b09	blueswir1	microSPARC II */
3166	65fe7b09	blueswir1	break;
3167	65fe7b09	blueswir1	#else
3168	0f8a249a	blueswir1	case 0x2: /* V9 wrccr */
3169	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3170	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3171	0f8a249a	blueswir1	break;
3172	0f8a249a	blueswir1	case 0x3: /* V9 wrasi */
3173	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3174	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3175	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3176	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
3177	0f8a249a	blueswir1	break;
3178	0f8a249a	blueswir1	case 0x6: /* V9 wrfprs */
3179	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3180	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3181	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3182	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
3183	6ae20372	blueswir1	save_state(dc, cpu_cond);
3184	3299908c	blueswir1	gen_op_next_insn();
3185	57fec1fe	bellard	tcg_gen_exit_tb(0);
3186	3299908c	blueswir1	dc->is_br = 1;
3187	0f8a249a	blueswir1	break;
3188	0f8a249a	blueswir1	case 0xf: /* V9 sir, nop if user */
3189	3475187d	bellard	#if !defined(CONFIG_USER_ONLY)
3190	0f8a249a	blueswir1	if (supervisor(dc))
3191	1a2fb1c0	blueswir1	; // XXX
3192	3475187d	bellard	#endif
3193	0f8a249a	blueswir1	break;
3194	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
3195	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3196	725cb90b	bellard	goto jmp_insn;
3197	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3198	77f193da	blueswir1	tcg_gen_st_tl(cpu_dst, cpu_env,
3199	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
3200	0f8a249a	blueswir1	break;
3201	0f8a249a	blueswir1	case 0x17: /* Tick compare */
3202	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3203	0f8a249a	blueswir1	if (!supervisor(dc))
3204	0f8a249a	blueswir1	goto illegal_insn;
3205	83469015	bellard	#endif
3206	ccd4a219	blueswir1	{
3207	ccd4a219	blueswir1	TCGv r_tickptr;
3208	ccd4a219	blueswir1
3209	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1,
3210	6ae20372	blueswir1	cpu_src2);
3211	77f193da	blueswir1	tcg_gen_st_tl(cpu_dst, cpu_env,
3212	77f193da	blueswir1	offsetof(CPUSPARCState,
3213	77f193da	blueswir1	tick_cmpr));
3214	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3215	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3216	ccd4a219	blueswir1	offsetof(CPUState, tick));
3217	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3218	6ae20372	blueswir1	r_tickptr, cpu_dst);
3219	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3220	ccd4a219	blueswir1	}
3221	0f8a249a	blueswir1	break;
3222	0f8a249a	blueswir1	case 0x18: /* System tick */
3223	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3224	0f8a249a	blueswir1	if (!supervisor(dc))
3225	0f8a249a	blueswir1	goto illegal_insn;
3226	83469015	bellard	#endif
3227	ccd4a219	blueswir1	{
3228	ccd4a219	blueswir1	TCGv r_tickptr;
3229	ccd4a219	blueswir1
3230	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1,
3231	6ae20372	blueswir1	cpu_src2);
3232	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3233	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3234	ccd4a219	blueswir1	offsetof(CPUState, stick));
3235	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3236	6ae20372	blueswir1	r_tickptr, cpu_dst);
3237	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3238	ccd4a219	blueswir1	}
3239	0f8a249a	blueswir1	break;
3240	0f8a249a	blueswir1	case 0x19: /* System tick compare */
3241	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3242	0f8a249a	blueswir1	if (!supervisor(dc))
3243	0f8a249a	blueswir1	goto illegal_insn;
3244	3475187d	bellard	#endif
3245	ccd4a219	blueswir1	{
3246	ccd4a219	blueswir1	TCGv r_tickptr;
3247	ccd4a219	blueswir1
3248	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1,
3249	6ae20372	blueswir1	cpu_src2);
3250	77f193da	blueswir1	tcg_gen_st_tl(cpu_dst, cpu_env,
3251	77f193da	blueswir1	offsetof(CPUSPARCState,
3252	77f193da	blueswir1	stick_cmpr));
3253	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3254	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3255	ccd4a219	blueswir1	offsetof(CPUState, stick));
3256	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3257	6ae20372	blueswir1	r_tickptr, cpu_dst);
3258	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3259	ccd4a219	blueswir1	}
3260	0f8a249a	blueswir1	break;
3261	83469015	bellard
3262	0f8a249a	blueswir1	case 0x10: /* Performance Control */
3263	77f193da	blueswir1	case 0x11: /* Performance Instrumentation
3264	77f193da	blueswir1	Counter */
3265	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
3266	0f8a249a	blueswir1	case 0x14: /* Softint set */
3267	0f8a249a	blueswir1	case 0x15: /* Softint clear */
3268	0f8a249a	blueswir1	case 0x16: /* Softint write */
3269	83469015	bellard	#endif
3270	3475187d	bellard	default:
3271	cf495bcf	bellard	goto illegal_insn;
3272	cf495bcf	bellard	}
3273	cf495bcf	bellard	}
3274	cf495bcf	bellard	break;
3275	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
3276	af7bf89b	bellard	case 0x31: /* wrpsr, V9 saved, restored */
3277	e8af50a3	bellard	{
3278	0f8a249a	blueswir1	if (!supervisor(dc))
3279	0f8a249a	blueswir1	goto priv_insn;
3280	3475187d	bellard	#ifdef TARGET_SPARC64
3281	0f8a249a	blueswir1	switch (rd) {
3282	0f8a249a	blueswir1	case 0:
3283	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_saved);
3284	0f8a249a	blueswir1	break;
3285	0f8a249a	blueswir1	case 1:
3286	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restored);
3287	0f8a249a	blueswir1	break;
3288	e9ebed4d	blueswir1	case 2: /* UA2005 allclean */
3289	e9ebed4d	blueswir1	case 3: /* UA2005 otherw */
3290	e9ebed4d	blueswir1	case 4: /* UA2005 normalw */
3291	e9ebed4d	blueswir1	case 5: /* UA2005 invalw */
3292	e9ebed4d	blueswir1	// XXX
3293	0f8a249a	blueswir1	default:
3294	3475187d	bellard	goto illegal_insn;
3295	3475187d	bellard	}
3296	3475187d	bellard	#else
3297	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3298	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3299	6ae20372	blueswir1	save_state(dc, cpu_cond);
3300	9e61bde5	bellard	gen_op_next_insn();
3301	57fec1fe	bellard	tcg_gen_exit_tb(0);
3302	0f8a249a	blueswir1	dc->is_br = 1;
3303	3475187d	bellard	#endif
3304	e8af50a3	bellard	}
3305	e8af50a3	bellard	break;
3306	af7bf89b	bellard	case 0x32: /* wrwim, V9 wrpr */
3307	e8af50a3	bellard	{
3308	0f8a249a	blueswir1	if (!supervisor(dc))
3309	0f8a249a	blueswir1	goto priv_insn;
3310	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3311	3475187d	bellard	#ifdef TARGET_SPARC64
3312	0f8a249a	blueswir1	switch (rd) {
3313	0f8a249a	blueswir1	case 0: // tpc
3314	375ee38b	blueswir1	{
3315	375ee38b	blueswir1	TCGv r_tsptr;
3316	375ee38b	blueswir1
3317	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3318	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3319	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3320	6ae20372	blueswir1	tcg_gen_st_tl(cpu_dst, r_tsptr,
3321	375ee38b	blueswir1	offsetof(trap_state, tpc));
3322	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3323	375ee38b	blueswir1	}
3324	0f8a249a	blueswir1	break;
3325	0f8a249a	blueswir1	case 1: // tnpc
3326	375ee38b	blueswir1	{
3327	375ee38b	blueswir1	TCGv r_tsptr;
3328	375ee38b	blueswir1
3329	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3330	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3331	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3332	6ae20372	blueswir1	tcg_gen_st_tl(cpu_dst, r_tsptr,
3333	375ee38b	blueswir1	offsetof(trap_state, tnpc));
3334	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3335	375ee38b	blueswir1	}
3336	0f8a249a	blueswir1	break;
3337	0f8a249a	blueswir1	case 2: // tstate
3338	375ee38b	blueswir1	{
3339	375ee38b	blueswir1	TCGv r_tsptr;
3340	375ee38b	blueswir1
3341	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3342	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3343	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3344	6ae20372	blueswir1	tcg_gen_st_tl(cpu_dst, r_tsptr,
3345	77f193da	blueswir1	offsetof(trap_state,
3346	77f193da	blueswir1	tstate));
3347	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3348	375ee38b	blueswir1	}
3349	0f8a249a	blueswir1	break;
3350	0f8a249a	blueswir1	case 3: // tt
3351	375ee38b	blueswir1	{
3352	375ee38b	blueswir1	TCGv r_tsptr;
3353	375ee38b	blueswir1
3354	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3355	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3356	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3357	6ae20372	blueswir1	tcg_gen_st_i32(cpu_dst, r_tsptr,
3358	375ee38b	blueswir1	offsetof(trap_state, tt));
3359	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3360	375ee38b	blueswir1	}
3361	0f8a249a	blueswir1	break;
3362	0f8a249a	blueswir1	case 4: // tick
3363	ccd4a219	blueswir1	{
3364	ccd4a219	blueswir1	TCGv r_tickptr;
3365	ccd4a219	blueswir1
3366	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3367	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3368	ccd4a219	blueswir1	offsetof(CPUState, tick));
3369	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3370	6ae20372	blueswir1	r_tickptr, cpu_dst);
3371	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3372	ccd4a219	blueswir1	}
3373	0f8a249a	blueswir1	break;
3374	0f8a249a	blueswir1	case 5: // tba
3375	77f193da	blueswir1	tcg_gen_st_tl(cpu_dst, cpu_env,
3376	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3377	0f8a249a	blueswir1	break;
3378	0f8a249a	blueswir1	case 6: // pstate
3379	6ae20372	blueswir1	save_state(dc, cpu_cond);
3380	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3381	ded3ab80	pbrook	gen_op_next_insn();
3382	57fec1fe	bellard	tcg_gen_exit_tb(0);
3383	ded3ab80	pbrook	dc->is_br = 1;
3384	0f8a249a	blueswir1	break;
3385	0f8a249a	blueswir1	case 7: // tl
3386	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3387	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3388	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
3389	0f8a249a	blueswir1	break;
3390	0f8a249a	blueswir1	case 8: // pil
3391	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3392	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3393	77f193da	blueswir1	offsetof(CPUSPARCState,
3394	77f193da	blueswir1	psrpil));
3395	0f8a249a	blueswir1	break;
3396	0f8a249a	blueswir1	case 9: // cwp
3397	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3398	0f8a249a	blueswir1	break;
3399	0f8a249a	blueswir1	case 10: // cansave
3400	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3401	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3402	77f193da	blueswir1	offsetof(CPUSPARCState,
3403	77f193da	blueswir1	cansave));
3404	0f8a249a	blueswir1	break;
3405	0f8a249a	blueswir1	case 11: // canrestore
3406	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3407	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3408	77f193da	blueswir1	offsetof(CPUSPARCState,
3409	77f193da	blueswir1	canrestore));
3410	0f8a249a	blueswir1	break;
3411	0f8a249a	blueswir1	case 12: // cleanwin
3412	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3413	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3414	77f193da	blueswir1	offsetof(CPUSPARCState,
3415	77f193da	blueswir1	cleanwin));
3416	0f8a249a	blueswir1	break;
3417	0f8a249a	blueswir1	case 13: // otherwin
3418	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3419	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3420	77f193da	blueswir1	offsetof(CPUSPARCState,
3421	77f193da	blueswir1	otherwin));
3422	0f8a249a	blueswir1	break;
3423	0f8a249a	blueswir1	case 14: // wstate
3424	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3425	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3426	77f193da	blueswir1	offsetof(CPUSPARCState,
3427	77f193da	blueswir1	wstate));
3428	0f8a249a	blueswir1	break;
3429	e9ebed4d	blueswir1	case 16: // UA2005 gl
3430	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3431	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3432	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
3433	e9ebed4d	blueswir1	break;
3434	e9ebed4d	blueswir1	case 26: // UA2005 strand status
3435	e9ebed4d	blueswir1	if (!hypervisor(dc))
3436	e9ebed4d	blueswir1	goto priv_insn;
3437	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3438	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3439	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
3440	e9ebed4d	blueswir1	break;
3441	0f8a249a	blueswir1	default:
3442	0f8a249a	blueswir1	goto illegal_insn;
3443	0f8a249a	blueswir1	}
3444	3475187d	bellard	#else
3445	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3446	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3447	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
3448	3475187d	bellard	#endif
3449	e8af50a3	bellard	}
3450	e8af50a3	bellard	break;
3451	e9ebed4d	blueswir1	case 0x33: /* wrtbr, UA2005 wrhpr */
3452	e8af50a3	bellard	{
3453	e9ebed4d	blueswir1	#ifndef TARGET_SPARC64
3454	0f8a249a	blueswir1	if (!supervisor(dc))
3455	0f8a249a	blueswir1	goto priv_insn;
3456	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3457	77f193da	blueswir1	tcg_gen_st_tl(cpu_dst, cpu_env,
3458	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3459	e9ebed4d	blueswir1	#else
3460	e9ebed4d	blueswir1	if (!hypervisor(dc))
3461	e9ebed4d	blueswir1	goto priv_insn;
3462	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3463	e9ebed4d	blueswir1	switch (rd) {
3464	e9ebed4d	blueswir1	case 0: // hpstate
3465	e9ebed4d	blueswir1	// XXX gen_op_wrhpstate();
3466	6ae20372	blueswir1	save_state(dc, cpu_cond);
3467	e9ebed4d	blueswir1	gen_op_next_insn();
3468	57fec1fe	bellard	tcg_gen_exit_tb(0);
3469	e9ebed4d	blueswir1	dc->is_br = 1;
3470	e9ebed4d	blueswir1	break;
3471	e9ebed4d	blueswir1	case 1: // htstate
3472	e9ebed4d	blueswir1	// XXX gen_op_wrhtstate();
3473	e9ebed4d	blueswir1	break;
3474	e9ebed4d	blueswir1	case 3: // hintp
3475	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3476	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3477	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
3478	e9ebed4d	blueswir1	break;
3479	e9ebed4d	blueswir1	case 5: // htba
3480	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3481	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3482	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
3483	e9ebed4d	blueswir1	break;
3484	e9ebed4d	blueswir1	case 31: // hstick_cmpr
3485	ccd4a219	blueswir1	{
3486	ccd4a219	blueswir1	TCGv r_tickptr;
3487	ccd4a219	blueswir1
3488	77f193da	blueswir1	tcg_gen_st_tl(cpu_dst, cpu_env,
3489	77f193da	blueswir1	offsetof(CPUSPARCState,
3490	77f193da	blueswir1	hstick_cmpr));
3491	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3492	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3493	ccd4a219	blueswir1	offsetof(CPUState, hstick));
3494	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3495	6ae20372	blueswir1	r_tickptr, cpu_dst);
3496	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3497	ccd4a219	blueswir1	}
3498	e9ebed4d	blueswir1	break;
3499	e9ebed4d	blueswir1	case 6: // hver readonly
3500	e9ebed4d	blueswir1	default:
3501	e9ebed4d	blueswir1	goto illegal_insn;
3502	e9ebed4d	blueswir1	}
3503	e9ebed4d	blueswir1	#endif
3504	e8af50a3	bellard	}
3505	e8af50a3	bellard	break;
3506	e8af50a3	bellard	#endif
3507	3475187d	bellard	#ifdef TARGET_SPARC64
3508	0f8a249a	blueswir1	case 0x2c: /* V9 movcc */
3509	0f8a249a	blueswir1	{
3510	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
3511	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 14, 17);
3512	748b9d8e	blueswir1	TCGv r_cond;
3513	00f219bf	blueswir1	int l1;
3514	00f219bf	blueswir1
3515	748b9d8e	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL);
3516	0f8a249a	blueswir1	if (insn & (1 << 18)) {
3517	0f8a249a	blueswir1	if (cc == 0)
3518	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
3519	0f8a249a	blueswir1	else if (cc == 2)
3520	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
3521	0f8a249a	blueswir1	else
3522	0f8a249a	blueswir1	goto illegal_insn;
3523	0f8a249a	blueswir1	} else {
3524	748b9d8e	blueswir1	gen_fcond(r_cond, cc, cond);
3525	0f8a249a	blueswir1	}
3526	00f219bf	blueswir1
3527	00f219bf	blueswir1	l1 = gen_new_label();
3528	00f219bf	blueswir1
3529	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3530	00f219bf	blueswir1	if (IS_IMM) { /* immediate */
3531	2ea815ca	blueswir1	TCGv r_const;
3532	2ea815ca	blueswir1
3533	00f219bf	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 10);
3534	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3535	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3536	2ea815ca	blueswir1	tcg_temp_free(r_const);
3537	00f219bf	blueswir1	} else {
3538	00f219bf	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3539	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3540	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3541	00f219bf	blueswir1	}
3542	00f219bf	blueswir1	gen_set_label(l1);
3543	2ea815ca	blueswir1	tcg_temp_free(r_cond);
3544	0f8a249a	blueswir1	break;
3545	0f8a249a	blueswir1	}
3546	0f8a249a	blueswir1	case 0x2d: /* V9 sdivx */
3547	6ae20372	blueswir1	gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3548	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3549	0f8a249a	blueswir1	break;
3550	0f8a249a	blueswir1	case 0x2e: /* V9 popc */
3551	0f8a249a	blueswir1	{
3552	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
3553	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_popc, cpu_dst,
3554	6ae20372	blueswir1	cpu_src2);
3555	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3556	0f8a249a	blueswir1	}
3557	0f8a249a	blueswir1	case 0x2f: /* V9 movr */
3558	0f8a249a	blueswir1	{
3559	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 10, 12);
3560	00f219bf	blueswir1	int l1;
3561	00f219bf	blueswir1
3562	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3563	00f219bf	blueswir1
3564	00f219bf	blueswir1	l1 = gen_new_label();
3565	00f219bf	blueswir1
3566	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3567	cb63669a	pbrook	cpu_src1, 0, l1);
3568	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
3569	2ea815ca	blueswir1	TCGv r_const;
3570	2ea815ca	blueswir1
3571	0f8a249a	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 9);
3572	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3573	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3574	2ea815ca	blueswir1	tcg_temp_free(r_const);
3575	00f219bf	blueswir1	} else {
3576	0f8a249a	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3577	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3578	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3579	0f8a249a	blueswir1	}
3580	00f219bf	blueswir1	gen_set_label(l1);
3581	0f8a249a	blueswir1	break;
3582	0f8a249a	blueswir1	}
3583	0f8a249a	blueswir1	#endif
3584	0f8a249a	blueswir1	default:
3585	0f8a249a	blueswir1	goto illegal_insn;
3586	0f8a249a	blueswir1	}
3587	0f8a249a	blueswir1	}
3588	3299908c	blueswir1	} else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3589	3299908c	blueswir1	#ifdef TARGET_SPARC64
3590	3299908c	blueswir1	int opf = GET_FIELD_SP(insn, 5, 13);
3591	3299908c	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
3592	3299908c	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
3593	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3594	e9ebed4d	blueswir1	goto jmp_insn;
3595	3299908c	blueswir1
3596	3299908c	blueswir1	switch (opf) {
3597	e9ebed4d	blueswir1	case 0x000: /* VIS I edge8cc */
3598	e9ebed4d	blueswir1	case 0x001: /* VIS II edge8n */
3599	e9ebed4d	blueswir1	case 0x002: /* VIS I edge8lcc */
3600	e9ebed4d	blueswir1	case 0x003: /* VIS II edge8ln */
3601	e9ebed4d	blueswir1	case 0x004: /* VIS I edge16cc */
3602	e9ebed4d	blueswir1	case 0x005: /* VIS II edge16n */
3603	e9ebed4d	blueswir1	case 0x006: /* VIS I edge16lcc */
3604	e9ebed4d	blueswir1	case 0x007: /* VIS II edge16ln */
3605	e9ebed4d	blueswir1	case 0x008: /* VIS I edge32cc */
3606	e9ebed4d	blueswir1	case 0x009: /* VIS II edge32n */
3607	e9ebed4d	blueswir1	case 0x00a: /* VIS I edge32lcc */
3608	e9ebed4d	blueswir1	case 0x00b: /* VIS II edge32ln */
3609	e9ebed4d	blueswir1	// XXX
3610	e9ebed4d	blueswir1	goto illegal_insn;
3611	e9ebed4d	blueswir1	case 0x010: /* VIS I array8 */
3612	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3613	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3614	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3615	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3616	6ae20372	blueswir1	cpu_src2);
3617	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3618	e9ebed4d	blueswir1	break;
3619	e9ebed4d	blueswir1	case 0x012: /* VIS I array16 */
3620	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3621	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3622	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3623	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3624	6ae20372	blueswir1	cpu_src2);
3625	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3626	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3627	e9ebed4d	blueswir1	break;
3628	e9ebed4d	blueswir1	case 0x014: /* VIS I array32 */
3629	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3630	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3631	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3632	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3633	6ae20372	blueswir1	cpu_src2);
3634	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3635	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3636	e9ebed4d	blueswir1	break;
3637	3299908c	blueswir1	case 0x018: /* VIS I alignaddr */
3638	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3639	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3640	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3641	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3642	6ae20372	blueswir1	cpu_src2);
3643	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3644	3299908c	blueswir1	break;
3645	e9ebed4d	blueswir1	case 0x019: /* VIS II bmask */
3646	3299908c	blueswir1	case 0x01a: /* VIS I alignaddrl */
3647	3299908c	blueswir1	// XXX
3648	e9ebed4d	blueswir1	goto illegal_insn;
3649	e9ebed4d	blueswir1	case 0x020: /* VIS I fcmple16 */
3650	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3651	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3652	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3653	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple16);
3654	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3655	e9ebed4d	blueswir1	break;
3656	e9ebed4d	blueswir1	case 0x022: /* VIS I fcmpne16 */
3657	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3658	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3659	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3660	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne16);
3661	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3662	3299908c	blueswir1	break;
3663	e9ebed4d	blueswir1	case 0x024: /* VIS I fcmple32 */
3664	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3665	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3666	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3667	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple32);
3668	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3669	e9ebed4d	blueswir1	break;
3670	e9ebed4d	blueswir1	case 0x026: /* VIS I fcmpne32 */
3671	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3672	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3673	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3674	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne32);
3675	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3676	e9ebed4d	blueswir1	break;
3677	e9ebed4d	blueswir1	case 0x028: /* VIS I fcmpgt16 */
3678	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3679	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3680	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3681	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt16);
3682	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3683	e9ebed4d	blueswir1	break;
3684	e9ebed4d	blueswir1	case 0x02a: /* VIS I fcmpeq16 */
3685	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3686	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3687	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3688	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq16);
3689	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3690	e9ebed4d	blueswir1	break;
3691	e9ebed4d	blueswir1	case 0x02c: /* VIS I fcmpgt32 */
3692	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3693	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3694	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3695	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt32);
3696	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3697	e9ebed4d	blueswir1	break;
3698	e9ebed4d	blueswir1	case 0x02e: /* VIS I fcmpeq32 */
3699	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3700	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3701	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3702	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq32);
3703	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3704	e9ebed4d	blueswir1	break;
3705	e9ebed4d	blueswir1	case 0x031: /* VIS I fmul8x16 */
3706	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3707	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3708	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3709	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16);
3710	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3711	e9ebed4d	blueswir1	break;
3712	e9ebed4d	blueswir1	case 0x033: /* VIS I fmul8x16au */
3713	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3714	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3715	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3716	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16au);
3717	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3718	e9ebed4d	blueswir1	break;
3719	e9ebed4d	blueswir1	case 0x035: /* VIS I fmul8x16al */
3720	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3721	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3722	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3723	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16al);
3724	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3725	e9ebed4d	blueswir1	break;
3726	e9ebed4d	blueswir1	case 0x036: /* VIS I fmul8sux16 */
3727	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3728	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3729	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3730	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8sux16);
3731	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3732	e9ebed4d	blueswir1	break;
3733	e9ebed4d	blueswir1	case 0x037: /* VIS I fmul8ulx16 */
3734	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3735	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3736	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3737	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8ulx16);
3738	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3739	e9ebed4d	blueswir1	break;
3740	e9ebed4d	blueswir1	case 0x038: /* VIS I fmuld8sux16 */
3741	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3742	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3743	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3744	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8sux16);
3745	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3746	e9ebed4d	blueswir1	break;
3747	e9ebed4d	blueswir1	case 0x039: /* VIS I fmuld8ulx16 */
3748	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3749	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3750	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3751	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8ulx16);
3752	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3753	e9ebed4d	blueswir1	break;
3754	e9ebed4d	blueswir1	case 0x03a: /* VIS I fpack32 */
3755	e9ebed4d	blueswir1	case 0x03b: /* VIS I fpack16 */
3756	e9ebed4d	blueswir1	case 0x03d: /* VIS I fpackfix */
3757	e9ebed4d	blueswir1	case 0x03e: /* VIS I pdist */
3758	e9ebed4d	blueswir1	// XXX
3759	e9ebed4d	blueswir1	goto illegal_insn;
3760	3299908c	blueswir1	case 0x048: /* VIS I faligndata */
3761	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3762	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3763	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3764	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faligndata);
3765	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3766	3299908c	blueswir1	break;
3767	e9ebed4d	blueswir1	case 0x04b: /* VIS I fpmerge */
3768	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3769	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3770	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3771	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpmerge);
3772	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3773	e9ebed4d	blueswir1	break;
3774	e9ebed4d	blueswir1	case 0x04c: /* VIS II bshuffle */
3775	e9ebed4d	blueswir1	// XXX
3776	e9ebed4d	blueswir1	goto illegal_insn;
3777	e9ebed4d	blueswir1	case 0x04d: /* VIS I fexpand */
3778	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3779	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3780	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3781	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fexpand);
3782	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3783	e9ebed4d	blueswir1	break;
3784	e9ebed4d	blueswir1	case 0x050: /* VIS I fpadd16 */
3785	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3786	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3787	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3788	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16);
3789	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3790	e9ebed4d	blueswir1	break;
3791	e9ebed4d	blueswir1	case 0x051: /* VIS I fpadd16s */
3792	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3793	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3794	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3795	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16s);
3796	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3797	e9ebed4d	blueswir1	break;
3798	e9ebed4d	blueswir1	case 0x052: /* VIS I fpadd32 */
3799	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3800	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3801	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3802	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3803	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3804	e9ebed4d	blueswir1	break;
3805	e9ebed4d	blueswir1	case 0x053: /* VIS I fpadd32s */
3806	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3807	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3808	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3809	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32s);
3810	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3811	e9ebed4d	blueswir1	break;
3812	e9ebed4d	blueswir1	case 0x054: /* VIS I fpsub16 */
3813	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3814	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3815	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3816	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16);
3817	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3818	e9ebed4d	blueswir1	break;
3819	e9ebed4d	blueswir1	case 0x055: /* VIS I fpsub16s */
3820	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3821	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3822	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3823	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16s);
3824	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3825	e9ebed4d	blueswir1	break;
3826	e9ebed4d	blueswir1	case 0x056: /* VIS I fpsub32 */
3827	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3828	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3829	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3830	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3831	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3832	e9ebed4d	blueswir1	break;
3833	e9ebed4d	blueswir1	case 0x057: /* VIS I fpsub32s */
3834	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3835	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3836	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3837	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub32s);
3838	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3839	e9ebed4d	blueswir1	break;
3840	3299908c	blueswir1	case 0x060: /* VIS I fzero */
3841	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3842	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_0);
3843	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3844	3299908c	blueswir1	break;
3845	3299908c	blueswir1	case 0x061: /* VIS I fzeros */
3846	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3847	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_0);
3848	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3849	3299908c	blueswir1	break;
3850	e9ebed4d	blueswir1	case 0x062: /* VIS I fnor */
3851	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3852	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3853	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3854	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnor);
3855	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3856	e9ebed4d	blueswir1	break;
3857	e9ebed4d	blueswir1	case 0x063: /* VIS I fnors */
3858	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3859	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3860	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3861	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnors);
3862	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3863	e9ebed4d	blueswir1	break;
3864	e9ebed4d	blueswir1	case 0x064: /* VIS I fandnot2 */
3865	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3866	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3867	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3868	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3869	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3870	e9ebed4d	blueswir1	break;
3871	e9ebed4d	blueswir1	case 0x065: /* VIS I fandnot2s */
3872	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3873	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3874	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
3875	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3876	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3877	e9ebed4d	blueswir1	break;
3878	e9ebed4d	blueswir1	case 0x066: /* VIS I fnot2 */
3879	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3880	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3881	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3882	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3883	e9ebed4d	blueswir1	break;
3884	e9ebed4d	blueswir1	case 0x067: /* VIS I fnot2s */
3885	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3886	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3887	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3888	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3889	e9ebed4d	blueswir1	break;
3890	e9ebed4d	blueswir1	case 0x068: /* VIS I fandnot1 */
3891	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3892	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3893	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3894	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3895	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3896	e9ebed4d	blueswir1	break;
3897	e9ebed4d	blueswir1	case 0x069: /* VIS I fandnot1s */
3898	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3899	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3900	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3901	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3902	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3903	e9ebed4d	blueswir1	break;
3904	e9ebed4d	blueswir1	case 0x06a: /* VIS I fnot1 */
3905	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3906	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3907	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3908	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3909	e9ebed4d	blueswir1	break;
3910	e9ebed4d	blueswir1	case 0x06b: /* VIS I fnot1s */
3911	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3912	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3913	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3914	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3915	e9ebed4d	blueswir1	break;
3916	e9ebed4d	blueswir1	case 0x06c: /* VIS I fxor */
3917	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3918	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3919	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3920	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxor);
3921	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3922	e9ebed4d	blueswir1	break;
3923	e9ebed4d	blueswir1	case 0x06d: /* VIS I fxors */
3924	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3925	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3926	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3927	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxors);
3928	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3929	e9ebed4d	blueswir1	break;
3930	e9ebed4d	blueswir1	case 0x06e: /* VIS I fnand */
3931	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3932	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3933	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3934	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnand);
3935	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3936	e9ebed4d	blueswir1	break;
3937	e9ebed4d	blueswir1	case 0x06f: /* VIS I fnands */
3938	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3939	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3940	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3941	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnands);
3942	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3943	e9ebed4d	blueswir1	break;
3944	e9ebed4d	blueswir1	case 0x070: /* VIS I fand */
3945	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3946	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3947	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3948	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fand);
3949	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3950	e9ebed4d	blueswir1	break;
3951	e9ebed4d	blueswir1	case 0x071: /* VIS I fands */
3952	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3953	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3954	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3955	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fands);
3956	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3957	e9ebed4d	blueswir1	break;
3958	e9ebed4d	blueswir1	case 0x072: /* VIS I fxnor */
3959	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3960	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3961	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3962	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnor);
3963	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3964	e9ebed4d	blueswir1	break;
3965	e9ebed4d	blueswir1	case 0x073: /* VIS I fxnors */
3966	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3967	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3968	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3969	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnors);
3970	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3971	e9ebed4d	blueswir1	break;
3972	3299908c	blueswir1	case 0x074: /* VIS I fsrc1 */
3973	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3974	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3975	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3976	3299908c	blueswir1	break;
3977	3299908c	blueswir1	case 0x075: /* VIS I fsrc1s */
3978	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3979	3299908c	blueswir1	gen_op_load_fpr_FT0(rs1);
3980	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3981	3299908c	blueswir1	break;
3982	e9ebed4d	blueswir1	case 0x076: /* VIS I fornot2 */
3983	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3984	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3985	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3986	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
3987	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3988	e9ebed4d	blueswir1	break;
3989	e9ebed4d	blueswir1	case 0x077: /* VIS I fornot2s */
3990	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3991	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3992	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
3993	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
3994	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3995	e9ebed4d	blueswir1	break;
3996	3299908c	blueswir1	case 0x078: /* VIS I fsrc2 */
3997	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3998	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3999	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4000	3299908c	blueswir1	break;
4001	3299908c	blueswir1	case 0x079: /* VIS I fsrc2s */
4002	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4003	3299908c	blueswir1	gen_op_load_fpr_FT0(rs2);
4004	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4005	3299908c	blueswir1	break;
4006	e9ebed4d	blueswir1	case 0x07a: /* VIS I fornot1 */
4007	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4008	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4009	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4010	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
4011	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4012	e9ebed4d	blueswir1	break;
4013	e9ebed4d	blueswir1	case 0x07b: /* VIS I fornot1s */
4014	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4015	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4016	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4017	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
4018	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4019	e9ebed4d	blueswir1	break;
4020	e9ebed4d	blueswir1	case 0x07c: /* VIS I for */
4021	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4022	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4023	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4024	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_for);
4025	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4026	e9ebed4d	blueswir1	break;
4027	e9ebed4d	blueswir1	case 0x07d: /* VIS I fors */
4028	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4029	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4030	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4031	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fors);
4032	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4033	e9ebed4d	blueswir1	break;
4034	3299908c	blueswir1	case 0x07e: /* VIS I fone */
4035	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4036	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_1);
4037	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4038	3299908c	blueswir1	break;
4039	3299908c	blueswir1	case 0x07f: /* VIS I fones */
4040	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4041	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_1);
4042	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4043	3299908c	blueswir1	break;
4044	e9ebed4d	blueswir1	case 0x080: /* VIS I shutdown */
4045	e9ebed4d	blueswir1	case 0x081: /* VIS II siam */
4046	e9ebed4d	blueswir1	// XXX
4047	e9ebed4d	blueswir1	goto illegal_insn;
4048	3299908c	blueswir1	default:
4049	3299908c	blueswir1	goto illegal_insn;
4050	3299908c	blueswir1	}
4051	3299908c	blueswir1	#else
4052	0f8a249a	blueswir1	goto ncp_insn;
4053	3299908c	blueswir1	#endif
4054	3299908c	blueswir1	} else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4055	fcc72045	blueswir1	#ifdef TARGET_SPARC64
4056	0f8a249a	blueswir1	goto illegal_insn;
4057	fcc72045	blueswir1	#else
4058	0f8a249a	blueswir1	goto ncp_insn;
4059	fcc72045	blueswir1	#endif
4060	3475187d	bellard	#ifdef TARGET_SPARC64
4061	0f8a249a	blueswir1	} else if (xop == 0x39) { /* V9 return */
4062	2ea815ca	blueswir1	TCGv r_const;
4063	2ea815ca	blueswir1
4064	6ae20372	blueswir1	save_state(dc, cpu_cond);
4065	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4066	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4067	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4068	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4069	0f8a249a	blueswir1	} else { /* register */
4070	3475187d	bellard	rs2 = GET_FIELD(insn, 27, 31);
4071	0f8a249a	blueswir1	if (rs2) {
4072	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4073	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4074	6f551262	blueswir1	} else
4075	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4076	3475187d	bellard	}
4077	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4078	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4079	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4080	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4081	2ea815ca	blueswir1	tcg_temp_free(r_const);
4082	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4083	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4084	0f8a249a	blueswir1	goto jmp_insn;
4085	3475187d	bellard	#endif
4086	0f8a249a	blueswir1	} else {
4087	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4088	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4089	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4090	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4091	0f8a249a	blueswir1	} else { /* register */
4092	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
4093	0f8a249a	blueswir1	if (rs2) {
4094	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4095	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4096	6f551262	blueswir1	} else
4097	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4098	cf495bcf	bellard	}
4099	0f8a249a	blueswir1	switch (xop) {
4100	0f8a249a	blueswir1	case 0x38: /* jmpl */
4101	0f8a249a	blueswir1	{
4102	2ea815ca	blueswir1	TCGv r_const;
4103	2ea815ca	blueswir1
4104	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
4105	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
4106	2ea815ca	blueswir1	tcg_temp_free(r_const);
4107	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4108	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4109	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4110	2ea815ca	blueswir1	r_const);
4111	2ea815ca	blueswir1	tcg_temp_free(r_const);
4112	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4113	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4114	0f8a249a	blueswir1	}
4115	0f8a249a	blueswir1	goto jmp_insn;
4116	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4117	0f8a249a	blueswir1	case 0x39: /* rett, V9 return */
4118	0f8a249a	blueswir1	{
4119	2ea815ca	blueswir1	TCGv r_const;
4120	2ea815ca	blueswir1
4121	0f8a249a	blueswir1	if (!supervisor(dc))
4122	0f8a249a	blueswir1	goto priv_insn;
4123	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4124	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4125	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4126	2ea815ca	blueswir1	r_const);
4127	2ea815ca	blueswir1	tcg_temp_free(r_const);
4128	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4129	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4130	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_rett);
4131	0f8a249a	blueswir1	}
4132	0f8a249a	blueswir1	goto jmp_insn;
4133	0f8a249a	blueswir1	#endif
4134	0f8a249a	blueswir1	case 0x3b: /* flush */
4135	64a88d5d	blueswir1	if (!((dc)->features & CPU_FEATURE_FLUSH))
4136	64a88d5d	blueswir1	goto unimp_flush;
4137	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_flush, cpu_dst);
4138	0f8a249a	blueswir1	break;
4139	0f8a249a	blueswir1	case 0x3c: /* save */
4140	6ae20372	blueswir1	save_state(dc, cpu_cond);
4141	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_save);
4142	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4143	0f8a249a	blueswir1	break;
4144	0f8a249a	blueswir1	case 0x3d: /* restore */
4145	6ae20372	blueswir1	save_state(dc, cpu_cond);
4146	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4147	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4148	0f8a249a	blueswir1	break;
4149	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4150	0f8a249a	blueswir1	case 0x3e: /* V9 done/retry */
4151	0f8a249a	blueswir1	{
4152	0f8a249a	blueswir1	switch (rd) {
4153	0f8a249a	blueswir1	case 0:
4154	0f8a249a	blueswir1	if (!supervisor(dc))
4155	0f8a249a	blueswir1	goto priv_insn;
4156	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4157	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4158	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_done);
4159	0f8a249a	blueswir1	goto jmp_insn;
4160	0f8a249a	blueswir1	case 1:
4161	0f8a249a	blueswir1	if (!supervisor(dc))
4162	0f8a249a	blueswir1	goto priv_insn;
4163	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4164	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4165	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_retry);
4166	0f8a249a	blueswir1	goto jmp_insn;
4167	0f8a249a	blueswir1	default:
4168	0f8a249a	blueswir1	goto illegal_insn;
4169	0f8a249a	blueswir1	}
4170	0f8a249a	blueswir1	}
4171	0f8a249a	blueswir1	break;
4172	0f8a249a	blueswir1	#endif
4173	0f8a249a	blueswir1	default:
4174	0f8a249a	blueswir1	goto illegal_insn;
4175	0f8a249a	blueswir1	}
4176	cf495bcf	bellard	}
4177	0f8a249a	blueswir1	break;
4178	0f8a249a	blueswir1	}
4179	0f8a249a	blueswir1	break;
4180	0f8a249a	blueswir1	case 3: /* load/store instructions */
4181	0f8a249a	blueswir1	{
4182	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
4183	9322a4bf	blueswir1
4184	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4185	81ad8ba2	blueswir1	if (xop == 0x3c \|\| xop == 0x3e)
4186	81ad8ba2	blueswir1	{
4187	81ad8ba2	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4188	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4189	81ad8ba2	blueswir1	}
4190	81ad8ba2	blueswir1	else if (IS_IMM) { /* immediate */
4191	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4192	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4193	0f8a249a	blueswir1	} else { /* register */
4194	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4195	0f8a249a	blueswir1	if (rs2 != 0) {
4196	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4197	6ae20372	blueswir1	tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4198	6f551262	blueswir1	} else
4199	6f551262	blueswir1	tcg_gen_mov_tl(cpu_addr, cpu_src1);
4200	0f8a249a	blueswir1	}
4201	2f2ecb83	blueswir1	if (xop < 4 \|\| (xop > 7 && xop < 0x14 && xop != 0x0e) \|\|
4202	2f2ecb83	blueswir1	(xop > 0x17 && xop <= 0x1d ) \|\|
4203	2f2ecb83	blueswir1	(xop > 0x2c && xop <= 0x33) \|\| xop == 0x1f \|\| xop == 0x3d) {
4204	0f8a249a	blueswir1	switch (xop) {
4205	1a2fb1c0	blueswir1	case 0x0: /* load unsigned word */
4206	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4207	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4208	0f8a249a	blueswir1	break;
4209	0f8a249a	blueswir1	case 0x1: /* load unsigned byte */
4210	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4211	6ae20372	blueswir1	tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4212	0f8a249a	blueswir1	break;
4213	0f8a249a	blueswir1	case 0x2: /* load unsigned halfword */
4214	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4215	6ae20372	blueswir1	tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4216	0f8a249a	blueswir1	break;
4217	0f8a249a	blueswir1	case 0x3: /* load double word */
4218	0f8a249a	blueswir1	if (rd & 1)
4219	d4218d99	blueswir1	goto illegal_insn;
4220	1a2fb1c0	blueswir1	else {
4221	2ea815ca	blueswir1	TCGv r_const;
4222	2ea815ca	blueswir1
4223	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4224	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4225	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4226	2ea815ca	blueswir1	r_const); // XXX remove
4227	2ea815ca	blueswir1	tcg_temp_free(r_const);
4228	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4229	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4230	32b6c812	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4231	32b6c812	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4232	32b6c812	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
4233	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4234	6ae20372	blueswir1	tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4235	6ae20372	blueswir1	tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4236	1a2fb1c0	blueswir1	}
4237	0f8a249a	blueswir1	break;
4238	0f8a249a	blueswir1	case 0x9: /* load signed byte */
4239	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4240	6ae20372	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4241	0f8a249a	blueswir1	break;
4242	0f8a249a	blueswir1	case 0xa: /* load signed halfword */
4243	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4244	6ae20372	blueswir1	tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4245	0f8a249a	blueswir1	break;
4246	0f8a249a	blueswir1	case 0xd: /* ldstub -- XXX: should be atomically */
4247	2ea815ca	blueswir1	{
4248	2ea815ca	blueswir1	TCGv r_const;
4249	2ea815ca	blueswir1
4250	2ea815ca	blueswir1	ABI32_MASK(cpu_addr);
4251	2ea815ca	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4252	2ea815ca	blueswir1	r_const = tcg_const_tl(0xff);
4253	2ea815ca	blueswir1	tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4254	2ea815ca	blueswir1	tcg_temp_free(r_const);
4255	2ea815ca	blueswir1	}
4256	0f8a249a	blueswir1	break;
4257	77f193da	blueswir1	case 0x0f: /* swap register with memory. Also
4258	77f193da	blueswir1	atomically */
4259	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4260	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4261	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4262	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4263	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4264	6ae20372	blueswir1	tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4265	0f8a249a	blueswir1	break;
4266	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4267	0f8a249a	blueswir1	case 0x10: /* load word alternate */
4268	3475187d	bellard	#ifndef TARGET_SPARC64
4269	0f8a249a	blueswir1	if (IS_IMM)
4270	0f8a249a	blueswir1	goto illegal_insn;
4271	0f8a249a	blueswir1	if (!supervisor(dc))
4272	0f8a249a	blueswir1	goto priv_insn;
4273	6ea4a6c8	blueswir1	#endif
4274	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4275	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4276	0f8a249a	blueswir1	break;
4277	0f8a249a	blueswir1	case 0x11: /* load unsigned byte alternate */
4278	3475187d	bellard	#ifndef TARGET_SPARC64
4279	0f8a249a	blueswir1	if (IS_IMM)
4280	0f8a249a	blueswir1	goto illegal_insn;
4281	0f8a249a	blueswir1	if (!supervisor(dc))
4282	0f8a249a	blueswir1	goto priv_insn;
4283	0f8a249a	blueswir1	#endif
4284	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4285	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4286	0f8a249a	blueswir1	break;
4287	0f8a249a	blueswir1	case 0x12: /* load unsigned halfword alternate */
4288	3475187d	bellard	#ifndef TARGET_SPARC64
4289	0f8a249a	blueswir1	if (IS_IMM)
4290	0f8a249a	blueswir1	goto illegal_insn;
4291	0f8a249a	blueswir1	if (!supervisor(dc))
4292	0f8a249a	blueswir1	goto priv_insn;
4293	6ea4a6c8	blueswir1	#endif
4294	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4295	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4296	0f8a249a	blueswir1	break;
4297	0f8a249a	blueswir1	case 0x13: /* load double word alternate */
4298	3475187d	bellard	#ifndef TARGET_SPARC64
4299	0f8a249a	blueswir1	if (IS_IMM)
4300	0f8a249a	blueswir1	goto illegal_insn;
4301	0f8a249a	blueswir1	if (!supervisor(dc))
4302	0f8a249a	blueswir1	goto priv_insn;
4303	3475187d	bellard	#endif
4304	0f8a249a	blueswir1	if (rd & 1)
4305	d4218d99	blueswir1	goto illegal_insn;
4306	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4307	6ae20372	blueswir1	gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4308	32b6c812	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
4309	0f8a249a	blueswir1	break;
4310	0f8a249a	blueswir1	case 0x19: /* load signed byte alternate */
4311	3475187d	bellard	#ifndef TARGET_SPARC64
4312	0f8a249a	blueswir1	if (IS_IMM)
4313	0f8a249a	blueswir1	goto illegal_insn;
4314	0f8a249a	blueswir1	if (!supervisor(dc))
4315	0f8a249a	blueswir1	goto priv_insn;
4316	0f8a249a	blueswir1	#endif
4317	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4318	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4319	0f8a249a	blueswir1	break;
4320	0f8a249a	blueswir1	case 0x1a: /* load signed halfword alternate */
4321	3475187d	bellard	#ifndef TARGET_SPARC64
4322	0f8a249a	blueswir1	if (IS_IMM)
4323	0f8a249a	blueswir1	goto illegal_insn;
4324	0f8a249a	blueswir1	if (!supervisor(dc))
4325	0f8a249a	blueswir1	goto priv_insn;
4326	6ea4a6c8	blueswir1	#endif
4327	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4328	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4329	0f8a249a	blueswir1	break;
4330	0f8a249a	blueswir1	case 0x1d: /* ldstuba -- XXX: should be atomically */
4331	3475187d	bellard	#ifndef TARGET_SPARC64
4332	0f8a249a	blueswir1	if (IS_IMM)
4333	0f8a249a	blueswir1	goto illegal_insn;
4334	0f8a249a	blueswir1	if (!supervisor(dc))
4335	0f8a249a	blueswir1	goto priv_insn;
4336	0f8a249a	blueswir1	#endif
4337	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4338	6ae20372	blueswir1	gen_ldstub_asi(cpu_val, cpu_addr, insn);
4339	0f8a249a	blueswir1	break;
4340	77f193da	blueswir1	case 0x1f: /* swap reg with alt. memory. Also
4341	77f193da	blueswir1	atomically */
4342	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4343	3475187d	bellard	#ifndef TARGET_SPARC64
4344	0f8a249a	blueswir1	if (IS_IMM)
4345	0f8a249a	blueswir1	goto illegal_insn;
4346	0f8a249a	blueswir1	if (!supervisor(dc))
4347	0f8a249a	blueswir1	goto priv_insn;
4348	6ea4a6c8	blueswir1	#endif
4349	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4350	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4351	6ae20372	blueswir1	gen_swap_asi(cpu_val, cpu_addr, insn);
4352	0f8a249a	blueswir1	break;
4353	3475187d	bellard
4354	3475187d	bellard	#ifndef TARGET_SPARC64
4355	0f8a249a	blueswir1	case 0x30: /* ldc */
4356	0f8a249a	blueswir1	case 0x31: /* ldcsr */
4357	0f8a249a	blueswir1	case 0x33: /* lddc */
4358	0f8a249a	blueswir1	goto ncp_insn;
4359	3475187d	bellard	#endif
4360	3475187d	bellard	#endif
4361	3475187d	bellard	#ifdef TARGET_SPARC64
4362	0f8a249a	blueswir1	case 0x08: /* V9 ldsw */
4363	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4364	6ae20372	blueswir1	tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4365	0f8a249a	blueswir1	break;
4366	0f8a249a	blueswir1	case 0x0b: /* V9 ldx */
4367	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4368	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4369	0f8a249a	blueswir1	break;
4370	0f8a249a	blueswir1	case 0x18: /* V9 ldswa */
4371	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4372	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4373	0f8a249a	blueswir1	break;
4374	0f8a249a	blueswir1	case 0x1b: /* V9 ldxa */
4375	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4376	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4377	0f8a249a	blueswir1	break;
4378	0f8a249a	blueswir1	case 0x2d: /* V9 prefetch, no effect */
4379	0f8a249a	blueswir1	goto skip_move;
4380	0f8a249a	blueswir1	case 0x30: /* V9 ldfa */
4381	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4382	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 4, rd);
4383	81ad8ba2	blueswir1	goto skip_move;
4384	0f8a249a	blueswir1	case 0x33: /* V9 lddfa */
4385	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4386	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4387	81ad8ba2	blueswir1	goto skip_move;
4388	0f8a249a	blueswir1	case 0x3d: /* V9 prefetcha, no effect */
4389	0f8a249a	blueswir1	goto skip_move;
4390	0f8a249a	blueswir1	case 0x32: /* V9 ldqfa */
4391	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4392	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4393	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4394	1f587329	blueswir1	goto skip_move;
4395	1f587329	blueswir1	#endif
4396	0f8a249a	blueswir1	default:
4397	0f8a249a	blueswir1	goto illegal_insn;
4398	0f8a249a	blueswir1	}
4399	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4400	3475187d	bellard	#ifdef TARGET_SPARC64
4401	0f8a249a	blueswir1	skip_move: ;
4402	3475187d	bellard	#endif
4403	0f8a249a	blueswir1	} else if (xop >= 0x20 && xop < 0x24) {
4404	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4405	a80dde08	bellard	goto jmp_insn;
4406	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4407	0f8a249a	blueswir1	switch (xop) {
4408	0f8a249a	blueswir1	case 0x20: /* load fpreg */
4409	c2bc0e38	blueswir1	ABI32_MASK(cpu_addr);
4410	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4411	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4412	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4413	0f8a249a	blueswir1	break;
4414	0f8a249a	blueswir1	case 0x21: /* load fsr */
4415	c2bc0e38	blueswir1	ABI32_MASK(cpu_addr);
4416	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4417	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4418	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4419	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_ldfsr);
4420	0f8a249a	blueswir1	break;
4421	0f8a249a	blueswir1	case 0x22: /* load quad fpreg */
4422	2ea815ca	blueswir1	{
4423	2ea815ca	blueswir1	TCGv r_const;
4424	2ea815ca	blueswir1
4425	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4426	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4427	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4428	2ea815ca	blueswir1	tcg_temp_free(r_const);
4429	2ea815ca	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
4430	2ea815ca	blueswir1	}
4431	1f587329	blueswir1	break;
4432	0f8a249a	blueswir1	case 0x23: /* load double fpreg */
4433	2ea815ca	blueswir1	{
4434	2ea815ca	blueswir1	TCGv r_const;
4435	2ea815ca	blueswir1
4436	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4437	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4438	2ea815ca	blueswir1	tcg_temp_free(r_const);
4439	2ea815ca	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4440	2ea815ca	blueswir1	}
4441	0f8a249a	blueswir1	break;
4442	0f8a249a	blueswir1	default:
4443	0f8a249a	blueswir1	goto illegal_insn;
4444	0f8a249a	blueswir1	}
4445	0f8a249a	blueswir1	} else if (xop < 8 \|\| (xop >= 0x14 && xop < 0x18) \|\| \
4446	0f8a249a	blueswir1	xop == 0xe \|\| xop == 0x1e) {
4447	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4448	0f8a249a	blueswir1	switch (xop) {
4449	1a2fb1c0	blueswir1	case 0x4: /* store word */
4450	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4451	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4452	0f8a249a	blueswir1	break;
4453	1a2fb1c0	blueswir1	case 0x5: /* store byte */
4454	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4455	6ae20372	blueswir1	tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4456	0f8a249a	blueswir1	break;
4457	1a2fb1c0	blueswir1	case 0x6: /* store halfword */
4458	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4459	6ae20372	blueswir1	tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4460	0f8a249a	blueswir1	break;
4461	1a2fb1c0	blueswir1	case 0x7: /* store double word */
4462	0f8a249a	blueswir1	if (rd & 1)
4463	d4218d99	blueswir1	goto illegal_insn;
4464	1a2fb1c0	blueswir1	else {
4465	2ea815ca	blueswir1	TCGv r_low, r_const;
4466	1a2fb1c0	blueswir1
4467	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4468	c2bc0e38	blueswir1	ABI32_MASK(cpu_addr);
4469	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4470	c2bc0e38	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4471	2ea815ca	blueswir1	r_const); // XXX remove
4472	2ea815ca	blueswir1	tcg_temp_free(r_const);
4473	8d96d209	blueswir1	r_low = tcg_temp_new(TCG_TYPE_TL);
4474	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd + 1, r_low);
4475	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4476	1a2fb1c0	blueswir1	r_low);
4477	2ea815ca	blueswir1	tcg_temp_free(r_low);
4478	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4479	7fa76c0b	blueswir1	}
4480	0f8a249a	blueswir1	break;
4481	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4482	1a2fb1c0	blueswir1	case 0x14: /* store word alternate */
4483	3475187d	bellard	#ifndef TARGET_SPARC64
4484	0f8a249a	blueswir1	if (IS_IMM)
4485	0f8a249a	blueswir1	goto illegal_insn;
4486	0f8a249a	blueswir1	if (!supervisor(dc))
4487	0f8a249a	blueswir1	goto priv_insn;
4488	3475187d	bellard	#endif
4489	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4490	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 4);
4491	d39c0b99	bellard	break;
4492	1a2fb1c0	blueswir1	case 0x15: /* store byte alternate */
4493	3475187d	bellard	#ifndef TARGET_SPARC64
4494	0f8a249a	blueswir1	if (IS_IMM)
4495	0f8a249a	blueswir1	goto illegal_insn;
4496	0f8a249a	blueswir1	if (!supervisor(dc))
4497	0f8a249a	blueswir1	goto priv_insn;
4498	3475187d	bellard	#endif
4499	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4500	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 1);
4501	d39c0b99	bellard	break;
4502	1a2fb1c0	blueswir1	case 0x16: /* store halfword alternate */
4503	3475187d	bellard	#ifndef TARGET_SPARC64
4504	0f8a249a	blueswir1	if (IS_IMM)
4505	0f8a249a	blueswir1	goto illegal_insn;
4506	0f8a249a	blueswir1	if (!supervisor(dc))
4507	0f8a249a	blueswir1	goto priv_insn;
4508	3475187d	bellard	#endif
4509	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4510	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 2);
4511	d39c0b99	bellard	break;
4512	1a2fb1c0	blueswir1	case 0x17: /* store double word alternate */
4513	3475187d	bellard	#ifndef TARGET_SPARC64
4514	0f8a249a	blueswir1	if (IS_IMM)
4515	0f8a249a	blueswir1	goto illegal_insn;
4516	0f8a249a	blueswir1	if (!supervisor(dc))
4517	0f8a249a	blueswir1	goto priv_insn;
4518	3475187d	bellard	#endif
4519	0f8a249a	blueswir1	if (rd & 1)
4520	d4218d99	blueswir1	goto illegal_insn;
4521	1a2fb1c0	blueswir1	else {
4522	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4523	6ae20372	blueswir1	gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4524	1a2fb1c0	blueswir1	}
4525	d39c0b99	bellard	break;
4526	e80cfcfc	bellard	#endif
4527	3475187d	bellard	#ifdef TARGET_SPARC64
4528	0f8a249a	blueswir1	case 0x0e: /* V9 stx */
4529	6ae20372	blueswir1	ABI32_MASK(cpu_addr);
4530	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4531	0f8a249a	blueswir1	break;
4532	0f8a249a	blueswir1	case 0x1e: /* V9 stxa */
4533	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4534	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 8);
4535	0f8a249a	blueswir1	break;
4536	3475187d	bellard	#endif
4537	0f8a249a	blueswir1	default:
4538	0f8a249a	blueswir1	goto illegal_insn;
4539	0f8a249a	blueswir1	}
4540	0f8a249a	blueswir1	} else if (xop > 0x23 && xop < 0x28) {
4541	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4542	a80dde08	bellard	goto jmp_insn;
4543	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4544	0f8a249a	blueswir1	switch (xop) {
4545	ce8536e2	blueswir1	case 0x24: /* store fpreg */
4546	c2bc0e38	blueswir1	ABI32_MASK(cpu_addr);
4547	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4548	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4549	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4550	0f8a249a	blueswir1	break;
4551	0f8a249a	blueswir1	case 0x25: /* stfsr, V9 stxfsr */
4552	c2bc0e38	blueswir1	ABI32_MASK(cpu_addr);
4553	bb5529bb	blueswir1	tcg_gen_helper_0_0(helper_stfsr);
4554	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4555	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4556	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4557	0f8a249a	blueswir1	break;
4558	1f587329	blueswir1	case 0x26:
4559	1f587329	blueswir1	#ifdef TARGET_SPARC64
4560	1f587329	blueswir1	/* V9 stqf, store quad fpreg */
4561	2ea815ca	blueswir1	{
4562	2ea815ca	blueswir1	TCGv r_const;
4563	2ea815ca	blueswir1
4564	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4565	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4566	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4567	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4568	2ea815ca	blueswir1	tcg_temp_free(r_const);
4569	2ea815ca	blueswir1	}
4570	1f587329	blueswir1	break;
4571	1f587329	blueswir1	#else /* !TARGET_SPARC64 */
4572	1f587329	blueswir1	/* stdfq, store floating point queue */
4573	1f587329	blueswir1	#if defined(CONFIG_USER_ONLY)
4574	1f587329	blueswir1	goto illegal_insn;
4575	1f587329	blueswir1	#else
4576	0f8a249a	blueswir1	if (!supervisor(dc))
4577	0f8a249a	blueswir1	goto priv_insn;
4578	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4579	0f8a249a	blueswir1	goto jmp_insn;
4580	0f8a249a	blueswir1	goto nfq_insn;
4581	0f8a249a	blueswir1	#endif
4582	1f587329	blueswir1	#endif
4583	7fa76c0b	blueswir1	case 0x27: /* store double fpreg */
4584	2ea815ca	blueswir1	{
4585	2ea815ca	blueswir1	TCGv r_const;
4586	2ea815ca	blueswir1
4587	2ea815ca	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4588	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4589	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4590	2ea815ca	blueswir1	tcg_temp_free(r_const);
4591	2ea815ca	blueswir1	}
4592	0f8a249a	blueswir1	break;
4593	0f8a249a	blueswir1	default:
4594	0f8a249a	blueswir1	goto illegal_insn;
4595	0f8a249a	blueswir1	}
4596	0f8a249a	blueswir1	} else if (xop > 0x33 && xop < 0x3f) {
4597	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4598	0f8a249a	blueswir1	switch (xop) {
4599	a4d17f19	blueswir1	#ifdef TARGET_SPARC64
4600	0f8a249a	blueswir1	case 0x34: /* V9 stfa */
4601	3391c818	blueswir1	gen_op_load_fpr_FT0(rd);
4602	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 4, rd);
4603	0f8a249a	blueswir1	break;
4604	1f587329	blueswir1	case 0x36: /* V9 stqfa */
4605	2ea815ca	blueswir1	{
4606	2ea815ca	blueswir1	TCGv r_const;
4607	2ea815ca	blueswir1
4608	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4609	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4610	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4611	2ea815ca	blueswir1	r_const);
4612	2ea815ca	blueswir1	tcg_temp_free(r_const);
4613	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4614	2ea815ca	blueswir1	gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4615	2ea815ca	blueswir1	}
4616	1f587329	blueswir1	break;
4617	0f8a249a	blueswir1	case 0x37: /* V9 stdfa */
4618	3391c818	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4619	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4620	0f8a249a	blueswir1	break;
4621	0f8a249a	blueswir1	case 0x3c: /* V9 casa */
4622	6ae20372	blueswir1	gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4623	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4624	0f8a249a	blueswir1	break;
4625	0f8a249a	blueswir1	case 0x3e: /* V9 casxa */
4626	6ae20372	blueswir1	gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4627	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4628	0f8a249a	blueswir1	break;
4629	a4d17f19	blueswir1	#else
4630	0f8a249a	blueswir1	case 0x34: /* stc */
4631	0f8a249a	blueswir1	case 0x35: /* stcsr */
4632	0f8a249a	blueswir1	case 0x36: /* stdcq */
4633	0f8a249a	blueswir1	case 0x37: /* stdc */
4634	0f8a249a	blueswir1	goto ncp_insn;
4635	0f8a249a	blueswir1	#endif
4636	0f8a249a	blueswir1	default:
4637	0f8a249a	blueswir1	goto illegal_insn;
4638	0f8a249a	blueswir1	}
4639	e8af50a3	bellard	}
4640	0f8a249a	blueswir1	else
4641	0f8a249a	blueswir1	goto illegal_insn;
4642	0f8a249a	blueswir1	}
4643	0f8a249a	blueswir1	break;
4644	cf495bcf	bellard	}
4645	cf495bcf	bellard	/* default case for non jump instructions */
4646	72cbca10	bellard	if (dc->npc == DYNAMIC_PC) {
4647	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4648	0f8a249a	blueswir1	gen_op_next_insn();
4649	72cbca10	bellard	} else if (dc->npc == JUMP_PC) {
4650	72cbca10	bellard	/* we can do a static jump */
4651	6ae20372	blueswir1	gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4652	72cbca10	bellard	dc->is_br = 1;
4653	72cbca10	bellard	} else {
4654	0f8a249a	blueswir1	dc->pc = dc->npc;
4655	0f8a249a	blueswir1	dc->npc = dc->npc + 4;
4656	cf495bcf	bellard	}
4657	e80cfcfc	bellard	jmp_insn:
4658	cf495bcf	bellard	return;
4659	cf495bcf	bellard	illegal_insn:
4660	2ea815ca	blueswir1	{
4661	2ea815ca	blueswir1	TCGv r_const;
4662	2ea815ca	blueswir1
4663	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4664	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_ILL_INSN);
4665	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4666	2ea815ca	blueswir1	tcg_temp_free(r_const);
4667	2ea815ca	blueswir1	dc->is_br = 1;
4668	2ea815ca	blueswir1	}
4669	e8af50a3	bellard	return;
4670	64a88d5d	blueswir1	unimp_flush:
4671	2ea815ca	blueswir1	{
4672	2ea815ca	blueswir1	TCGv r_const;
4673	2ea815ca	blueswir1
4674	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4675	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4676	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4677	2ea815ca	blueswir1	tcg_temp_free(r_const);
4678	2ea815ca	blueswir1	dc->is_br = 1;
4679	2ea815ca	blueswir1	}
4680	64a88d5d	blueswir1	return;
4681	e80cfcfc	bellard	#if !defined(CONFIG_USER_ONLY)
4682	e8af50a3	bellard	priv_insn:
4683	2ea815ca	blueswir1	{
4684	2ea815ca	blueswir1	TCGv r_const;
4685	2ea815ca	blueswir1
4686	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4687	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_PRIV_INSN);
4688	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4689	2ea815ca	blueswir1	tcg_temp_free(r_const);
4690	2ea815ca	blueswir1	dc->is_br = 1;
4691	2ea815ca	blueswir1	}
4692	e80cfcfc	bellard	return;
4693	64a88d5d	blueswir1	#endif
4694	e80cfcfc	bellard	nfpu_insn:
4695	6ae20372	blueswir1	save_state(dc, cpu_cond);
4696	e80cfcfc	bellard	gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4697	e80cfcfc	bellard	dc->is_br = 1;
4698	fcc72045	blueswir1	return;
4699	64a88d5d	blueswir1	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4700	9143e598	blueswir1	nfq_insn:
4701	6ae20372	blueswir1	save_state(dc, cpu_cond);
4702	9143e598	blueswir1	gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4703	9143e598	blueswir1	dc->is_br = 1;
4704	9143e598	blueswir1	return;
4705	9143e598	blueswir1	#endif
4706	fcc72045	blueswir1	#ifndef TARGET_SPARC64
4707	fcc72045	blueswir1	ncp_insn:
4708	2ea815ca	blueswir1	{
4709	2ea815ca	blueswir1	TCGv r_const;
4710	2ea815ca	blueswir1
4711	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4712	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NCP_INSN);
4713	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4714	2ea815ca	blueswir1	tcg_temp_free(r_const);
4715	2ea815ca	blueswir1	dc->is_br = 1;
4716	2ea815ca	blueswir1	}
4717	fcc72045	blueswir1	return;
4718	fcc72045	blueswir1	#endif
4719	7a3f1944	bellard	}
4720	7a3f1944	bellard
4721	cf495bcf	bellard	static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4722	0f8a249a	blueswir1	int spc, CPUSPARCState *env)
4723	7a3f1944	bellard	{
4724	72cbca10	bellard	target_ulong pc_start, last_pc;
4725	cf495bcf	bellard	uint16_t *gen_opc_end;
4726	cf495bcf	bellard	DisasContext dc1, *dc = &dc1;
4727	e8af50a3	bellard	int j, lj = -1;
4728	cf495bcf	bellard
4729	cf495bcf	bellard	memset(dc, 0, sizeof(DisasContext));
4730	cf495bcf	bellard	dc->tb = tb;
4731	72cbca10	bellard	pc_start = tb->pc;
4732	cf495bcf	bellard	dc->pc = pc_start;
4733	e80cfcfc	bellard	last_pc = dc->pc;
4734	72cbca10	bellard	dc->npc = (target_ulong) tb->cs_base;
4735	6f27aba6	blueswir1	dc->mem_idx = cpu_mmu_index(env);
4736	64a88d5d	blueswir1	dc->features = env->features;
4737	64a88d5d	blueswir1	if ((dc->features & CPU_FEATURE_FLOAT)) {
4738	64a88d5d	blueswir1	dc->fpu_enabled = cpu_fpu_enabled(env);
4739	64a88d5d	blueswir1	#if defined(CONFIG_USER_ONLY)
4740	64a88d5d	blueswir1	dc->features \|= CPU_FEATURE_FLOAT128;
4741	64a88d5d	blueswir1	#endif
4742	64a88d5d	blueswir1	} else
4743	64a88d5d	blueswir1	dc->fpu_enabled = 0;
4744	cf495bcf	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4745	cf495bcf	bellard
4746	1a2fb1c0	blueswir1	cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4747	8911f501	blueswir1	cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4748	8911f501	blueswir1	cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4749	1a2fb1c0	blueswir1
4750	cf495bcf	bellard	do {
4751	e8af50a3	bellard	if (env->nb_breakpoints > 0) {
4752	e8af50a3	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
4753	e8af50a3	bellard	if (env->breakpoints[j] == dc->pc) {
4754	0f8a249a	blueswir1	if (dc->pc != pc_start)
4755	6ae20372	blueswir1	save_state(dc, cpu_cond);
4756	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_debug);
4757	57fec1fe	bellard	tcg_gen_exit_tb(0);
4758	0f8a249a	blueswir1	dc->is_br = 1;
4759	e80cfcfc	bellard	goto exit_gen_loop;
4760	e8af50a3	bellard	}
4761	e8af50a3	bellard	}
4762	e8af50a3	bellard	}
4763	e8af50a3	bellard	if (spc) {
4764	e8af50a3	bellard	if (loglevel > 0)
4765	e8af50a3	bellard	fprintf(logfile, "Search PC...\n");
4766	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4767	e8af50a3	bellard	if (lj < j) {
4768	e8af50a3	bellard	lj++;
4769	e8af50a3	bellard	while (lj < j)
4770	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4771	e8af50a3	bellard	gen_opc_pc[lj] = dc->pc;
4772	e8af50a3	bellard	gen_opc_npc[lj] = dc->npc;
4773	e8af50a3	bellard	gen_opc_instr_start[lj] = 1;
4774	e8af50a3	bellard	}
4775	e8af50a3	bellard	}
4776	0f8a249a	blueswir1	last_pc = dc->pc;
4777	0f8a249a	blueswir1	disas_sparc_insn(dc);
4778	0f8a249a	blueswir1
4779	0f8a249a	blueswir1	if (dc->is_br)
4780	0f8a249a	blueswir1	break;
4781	0f8a249a	blueswir1	/* if the next PC is different, we abort now */
4782	0f8a249a	blueswir1	if (dc->pc != (last_pc + 4))
4783	0f8a249a	blueswir1	break;
4784	d39c0b99	bellard	/* if we reach a page boundary, we stop generation so that the
4785	d39c0b99	bellard	PC of a TT_TFAULT exception is always in the right page */
4786	d39c0b99	bellard	if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4787	d39c0b99	bellard	break;
4788	e80cfcfc	bellard	/* if single step mode, we generate only one instruction and
4789	e80cfcfc	bellard	generate an exception */
4790	e80cfcfc	bellard	if (env->singlestep_enabled) {
4791	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4792	57fec1fe	bellard	tcg_gen_exit_tb(0);
4793	e80cfcfc	bellard	break;
4794	e80cfcfc	bellard	}
4795	cf495bcf	bellard	} while ((gen_opc_ptr < gen_opc_end) &&
4796	0f8a249a	blueswir1	(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4797	e80cfcfc	bellard
4798	e80cfcfc	bellard	exit_gen_loop:
4799	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp64);
4800	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp32);
4801	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp0);
4802	72cbca10	bellard	if (!dc->is_br) {
4803	5fafdf24	ths	if (dc->pc != DYNAMIC_PC &&
4804	72cbca10	bellard	(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4805	72cbca10	bellard	/* static PC and NPC: we can use direct chaining */
4806	2f5680ee	blueswir1	gen_goto_tb(dc, 0, dc->pc, dc->npc);
4807	72cbca10	bellard	} else {
4808	72cbca10	bellard	if (dc->pc != DYNAMIC_PC)
4809	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4810	6ae20372	blueswir1	save_npc(dc, cpu_cond);
4811	57fec1fe	bellard	tcg_gen_exit_tb(0);
4812	72cbca10	bellard	}
4813	72cbca10	bellard	}
4814	cf495bcf	bellard	*gen_opc_ptr = INDEX_op_end;
4815	e8af50a3	bellard	if (spc) {
4816	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4817	e8af50a3	bellard	lj++;
4818	e8af50a3	bellard	while (lj <= j)
4819	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4820	e8af50a3	bellard	#if 0
4821	e8af50a3	bellard	if (loglevel > 0) {
4822	e8af50a3	bellard	page_dump(logfile);
4823	e8af50a3	bellard	}
4824	e8af50a3	bellard	#endif
4825	c3278b7b	bellard	gen_opc_jump_pc[0] = dc->jump_pc[0];
4826	c3278b7b	bellard	gen_opc_jump_pc[1] = dc->jump_pc[1];
4827	e8af50a3	bellard	} else {
4828	e80cfcfc	bellard	tb->size = last_pc + 4 - pc_start;
4829	e8af50a3	bellard	}
4830	7a3f1944	bellard	#ifdef DEBUG_DISAS
4831	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
4832	0f8a249a	blueswir1	fprintf(logfile, "--------------\n");
4833	0f8a249a	blueswir1	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4834	0f8a249a	blueswir1	target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4835	0f8a249a	blueswir1	fprintf(logfile, "\n");
4836	cf495bcf	bellard	}
4837	7a3f1944	bellard	#endif
4838	cf495bcf	bellard	return 0;
4839	7a3f1944	bellard	}
4840	7a3f1944	bellard
4841	cf495bcf	bellard	int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4842	7a3f1944	bellard	{
4843	e8af50a3	bellard	return gen_intermediate_code_internal(tb, 0, env);
4844	7a3f1944	bellard	}
4845	7a3f1944	bellard
4846	cf495bcf	bellard	int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4847	7a3f1944	bellard	{
4848	e8af50a3	bellard	return gen_intermediate_code_internal(tb, 1, env);
4849	7a3f1944	bellard	}
4850	7a3f1944	bellard
4851	c48fcb47	blueswir1	void gen_intermediate_code_init(CPUSPARCState *env)
4852	e80cfcfc	bellard	{
4853	f5069b26	blueswir1	unsigned int i;
4854	c48fcb47	blueswir1	static int inited;
4855	f5069b26	blueswir1	static const char * const gregnames[8] = {
4856	f5069b26	blueswir1	NULL, // g0 not used
4857	f5069b26	blueswir1	"g1",
4858	f5069b26	blueswir1	"g2",
4859	f5069b26	blueswir1	"g3",
4860	f5069b26	blueswir1	"g4",
4861	f5069b26	blueswir1	"g5",
4862	f5069b26	blueswir1	"g6",
4863	f5069b26	blueswir1	"g7",
4864	f5069b26	blueswir1	};
4865	aaed909a	bellard
4866	1a2fb1c0	blueswir1	/* init various static tables */
4867	1a2fb1c0	blueswir1	if (!inited) {
4868	1a2fb1c0	blueswir1	inited = 1;
4869	1a2fb1c0	blueswir1
4870	1a2fb1c0	blueswir1	cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4871	db4a4ea4	blueswir1	cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4872	db4a4ea4	blueswir1	offsetof(CPUState, regwptr),
4873	db4a4ea4	blueswir1	"regwptr");
4874	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
4875	dc99a3f2	blueswir1	cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4876	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, xcc),
4877	dc99a3f2	blueswir1	"xcc");
4878	1a2fb1c0	blueswir1	#endif
4879	7c60cc4b	bellard	/* XXX: T0 and T1 should be temporaries */
4880	7c60cc4b	bellard	cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4881	7c60cc4b	bellard	TCG_AREG0, offsetof(CPUState, t0), "T0");
4882	7c60cc4b	bellard	cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4883	7c60cc4b	bellard	TCG_AREG0, offsetof(CPUState, t1), "T1");
4884	7c60cc4b	bellard	cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4885	77f193da	blueswir1	TCG_AREG0, offsetof(CPUState, cond),
4886	77f193da	blueswir1	"cond");
4887	dc99a3f2	blueswir1	cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4888	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_src),
4889	dc99a3f2	blueswir1	"cc_src");
4890	d9bdab86	blueswir1	cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4891	d9bdab86	blueswir1	offsetof(CPUState, cc_src2),
4892	d9bdab86	blueswir1	"cc_src2");
4893	dc99a3f2	blueswir1	cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4894	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_dst),
4895	dc99a3f2	blueswir1	"cc_dst");
4896	dc99a3f2	blueswir1	cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4897	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, psr),
4898	dc99a3f2	blueswir1	"psr");
4899	87e92502	blueswir1	cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4900	87e92502	blueswir1	TCG_AREG0, offsetof(CPUState, fsr),
4901	87e92502	blueswir1	"fsr");
4902	48d5c82b	blueswir1	cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4903	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, pc),
4904	48d5c82b	blueswir1	"pc");
4905	48d5c82b	blueswir1	cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4906	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, npc),
4907	48d5c82b	blueswir1	"npc");
4908	f5069b26	blueswir1	for (i = 1; i < 8; i++)
4909	f5069b26	blueswir1	cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4910	f5069b26	blueswir1	offsetof(CPUState, gregs[i]),
4911	f5069b26	blueswir1	gregnames[i]);
4912	c9e03d8f	blueswir1	/* register helpers */
4913	c9e03d8f	blueswir1
4914	c9e03d8f	blueswir1	#undef DEF_HELPER
4915	c9e03d8f	blueswir1	#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4916	c9e03d8f	blueswir1	#include "helper.h"
4917	1a2fb1c0	blueswir1	}
4918	658138bc	bellard	}
4919	d2856f1a	aurel32
4920	d2856f1a	aurel32	void gen_pc_load(CPUState env, TranslationBlock tb,
4921	d2856f1a	aurel32	unsigned long searched_pc, int pc_pos, void *puc)
4922	d2856f1a	aurel32	{
4923	d2856f1a	aurel32	target_ulong npc;
4924	d2856f1a	aurel32	env->pc = gen_opc_pc[pc_pos];
4925	d2856f1a	aurel32	npc = gen_opc_npc[pc_pos];
4926	d2856f1a	aurel32	if (npc == 1) {
4927	d2856f1a	aurel32	/* dynamic NPC: already stored */
4928	d2856f1a	aurel32	} else if (npc == 2) {
4929	d2856f1a	aurel32	target_ulong t2 = (target_ulong)(unsigned long)puc;
4930	d2856f1a	aurel32	/* jump PC: use T2 and the jump targets of the translation */
4931	d2856f1a	aurel32	if (t2)
4932	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[0];
4933	d2856f1a	aurel32	else
4934	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[1];
4935	d2856f1a	aurel32	} else {
4936	d2856f1a	aurel32	env->npc = npc;
4937	d2856f1a	aurel32	}
4938	d2856f1a	aurel32	}

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