Revision 1a14026e target-sparc/cpu.h
| b/target-sparc/cpu.h | ||
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| 170 | 170 |
#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
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#define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
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/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */ |
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#define NWINDOWS 8 |
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/* 3 <= NWINDOWS <= 32. */ |
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#define MIN_NWINDOWS 3 |
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#define MAX_NWINDOWS 32 |
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#if !defined(TARGET_SPARC64) |
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#define NB_MMU_MODES 2 |
| ... | ... | |
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uint32_t mmu_cxr_mask; |
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uint32_t mmu_sfsr_mask; |
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uint32_t mmu_trcr_mask; |
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uint32_t nwindows; |
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/* NOTE: we allow 8 more registers to handle wrapping */ |
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target_ulong regbase[NWINDOWS * 16 + 8]; |
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target_ulong regbase[MAX_NWINDOWS * 16 + 8];
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CPU_COMMON |
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| ... | ... | |
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#ifndef NO_CPU_IO_DEFS |
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void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
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static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) |
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{
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if (unlikely(cwp >= env1->nwindows)) |
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cwp -= env1->nwindows; |
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return cwp; |
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} |
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static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) |
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{
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if (unlikely(cwp < 0)) |
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cwp += env1->nwindows; |
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return cwp; |
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} |
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#endif |
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#define PUT_PSR(env, val) do { int _tmp = val; \
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| ... | ... | |
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env->xcc = (_tmp >> 4) << 20; \ |
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env->psr = (_tmp & 0xf) << 20; \ |
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} while (0) |
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#define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp) |
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#define PUT_CWP64(env, val) \ |
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cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1))) |
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#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp) |
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static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) |
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{
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if (unlikely(cwp >= env1->nwindows || cwp < 0)) |
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cwp = 0; |
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cpu_set_cwp(env1, env1->nwindows - 1 - cwp); |
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} |
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#endif |
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