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#ifndef CPU_SPARC_H
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#define CPU_SPARC_H
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#include "config.h"
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#if !defined(TARGET_SPARC64)
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#define TARGET_LONG_BITS 32
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#define TARGET_FPREGS 32
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#define TARGET_PAGE_BITS 12 /* 4k */
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#else
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#define TARGET_LONG_BITS 64
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#define TARGET_FPREGS 64
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#define TARGET_PAGE_BITS 13 /* 8k */
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#endif
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#define TARGET_PHYS_ADDR_BITS 64
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#if !defined(TARGET_SPARC64)
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#define ELF_MACHINE     EM_SPARC
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#else
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#define ELF_MACHINE     EM_SPARCV9
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#endif
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/*#define EXCP_INTERRUPT 0x100*/
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/* trap definitions */
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#ifndef TARGET_SPARC64
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#define TT_TFAULT   0x01
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#define TT_ILL_INSN 0x02
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#define TT_PRIV_INSN 0x03
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#define TT_NFPU_INSN 0x04
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#define TT_WIN_OVF  0x05
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#define TT_WIN_UNF  0x06
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#define TT_UNALIGNED 0x07
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#define TT_FP_EXCP  0x08
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#define TT_DFAULT   0x09
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#define TT_TOVF     0x0a
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#define TT_EXTINT   0x10
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#define TT_CODE_ACCESS 0x21
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#define TT_UNIMP_FLUSH 0x25
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#define TT_DATA_ACCESS 0x29
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#define TT_DIV_ZERO 0x2a
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#define TT_NCP_INSN 0x24
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#define TT_TRAP     0x80
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#else
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#define TT_TFAULT   0x08
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#define TT_TMISS    0x09
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#define TT_CODE_ACCESS 0x0a
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#define TT_ILL_INSN 0x10
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#define TT_UNIMP_FLUSH TT_ILL_INSN
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#define TT_PRIV_INSN 0x11
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#define TT_NFPU_INSN 0x20
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#define TT_FP_EXCP  0x21
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#define TT_TOVF     0x23
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#define TT_CLRWIN   0x24
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#define TT_DIV_ZERO 0x28
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#define TT_DFAULT   0x30
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#define TT_DMISS    0x31
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#define TT_DATA_ACCESS 0x32
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#define TT_DPROT    0x33
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#define TT_UNALIGNED 0x34
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#define TT_PRIV_ACT 0x37
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#define TT_EXTINT   0x40
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#define TT_SPILL    0x80
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#define TT_FILL     0xc0
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#define TT_WOTHER   0x10
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#define TT_TRAP     0x100
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#endif
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#define PSR_NEG_SHIFT 23
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#define PSR_NEG   (1 << PSR_NEG_SHIFT)
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#define PSR_ZERO_SHIFT 22
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#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
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#define PSR_OVF_SHIFT 21
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#define PSR_OVF   (1 << PSR_OVF_SHIFT)
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#define PSR_CARRY_SHIFT 20
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#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
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#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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#define PSR_EF    (1<<12)
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#define PSR_PIL   0xf00
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#define PSR_S     (1<<7)
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#define PSR_PS    (1<<6)
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#define PSR_ET    (1<<5)
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#define PSR_CWP   0x1f
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/* Trap base register */
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#define TBR_BASE_MASK 0xfffff000
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#if defined(TARGET_SPARC64)
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#define PS_IG    (1<<11)
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#define PS_MG    (1<<10)
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#define PS_RMO   (1<<7)
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#define PS_RED   (1<<5)
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#define PS_PEF   (1<<4)
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#define PS_AM    (1<<3)
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#define PS_PRIV  (1<<2)
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#define PS_IE    (1<<1)
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#define PS_AG    (1<<0)
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#define FPRS_FEF (1<<2)
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#define HS_PRIV  (1<<2)
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#endif
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/* Fcc */
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#define FSR_RD1        (1<<31)
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#define FSR_RD0        (1<<30)
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#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
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#define FSR_RD_NEAREST 0
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#define FSR_RD_ZERO    FSR_RD0
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#define FSR_RD_POS     FSR_RD1
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#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
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#define FSR_NVM   (1<<27)
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#define FSR_OFM   (1<<26)
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#define FSR_UFM   (1<<25)
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#define FSR_DZM   (1<<24)
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#define FSR_NXM   (1<<23)
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#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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#define FSR_NVA   (1<<9)
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#define FSR_OFA   (1<<8)
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#define FSR_UFA   (1<<7)
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#define FSR_DZA   (1<<6)
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#define FSR_NXA   (1<<5)
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#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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#define FSR_NVC   (1<<4)
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#define FSR_OFC   (1<<3)
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#define FSR_UFC   (1<<2)
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#define FSR_DZC   (1<<1)
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#define FSR_NXC   (1<<0)
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#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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#define FSR_FTT2   (1<<16)
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#define FSR_FTT1   (1<<15)
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#define FSR_FTT0   (1<<14)
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#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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#define FSR_FTT_IEEE_EXCP (1 << 14)
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#define FSR_FTT_UNIMPFPOP (3 << 14)
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#define FSR_FTT_SEQ_ERROR (4 << 14)
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#define FSR_FTT_INVAL_FPR (6 << 14)
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#define FSR_FCC1_SHIFT 11
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#define FSR_FCC1  (1 << FSR_FCC1_SHIFT)
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#define FSR_FCC0_SHIFT 10
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#define FSR_FCC0  (1 << FSR_FCC0_SHIFT)
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/* MMU */
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#define MMU_E     (1<<0)
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#define MMU_NF    (1<<1)
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#define PTE_ENTRYTYPE_MASK 3
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#define PTE_ACCESS_MASK    0x1c
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#define PTE_ACCESS_SHIFT   2
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#define PTE_PPN_SHIFT      7
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#define PTE_ADDR_MASK      0xffffff00
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#define PG_ACCESSED_BIT 5
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#define PG_MODIFIED_BIT 6
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#define PG_CACHE_BIT    7
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
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#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
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/* 3 <= NWINDOWS <= 32. */
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#define MIN_NWINDOWS 3
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#define MAX_NWINDOWS 32
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#if !defined(TARGET_SPARC64)
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#define NB_MMU_MODES 2
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#else
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#define NB_MMU_MODES 3
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typedef struct trap_state {
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    uint64_t tpc;
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    uint64_t tnpc;
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    uint64_t tstate;
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    uint32_t tt;
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} trap_state;
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#endif
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typedef struct CPUSPARCState {
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    target_ulong gregs[8]; /* general registers */
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    target_ulong *regwptr; /* pointer to current register window */
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    target_ulong pc;       /* program counter */
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    target_ulong npc;      /* next program counter */
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    target_ulong y;        /* multiply/divide register */
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    /* emulator internal flags handling */
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    target_ulong cc_src, cc_src2;
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    target_ulong cc_dst;
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    target_ulong t0, t1; /* temporaries live across basic blocks */
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    target_ulong cond; /* conditional branch result (XXX: save it in a
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                          temporary register when possible) */
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    uint32_t psr;      /* processor state register */
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    target_ulong fsr;      /* FPU state register */
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    float32 fpr[TARGET_FPREGS];  /* floating point registers */
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    uint32_t cwp;      /* index of current register window (extracted
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                          from PSR) */
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    uint32_t wim;      /* window invalid mask */
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    target_ulong tbr;  /* trap base register */
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    int      psrs;     /* supervisor mode (extracted from PSR) */
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    int      psrps;    /* previous supervisor mode */
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    int      psret;    /* enable traps */
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    uint32_t psrpil;   /* interrupt blocking level */
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    uint32_t pil_in;   /* incoming interrupt level bitmap */
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    int      psref;    /* enable fpu */
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    target_ulong version;
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    int user_mode_only;
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    int interrupt_index;
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    int interrupt_request;
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    uint32_t mmu_bm;
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    uint32_t mmu_ctpr_mask;
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    uint32_t mmu_cxr_mask;
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    uint32_t mmu_sfsr_mask;
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    uint32_t mmu_trcr_mask;
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    uint32_t nwindows;
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    /* NOTE: we allow 8 more registers to handle wrapping */
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    target_ulong regbase[MAX_NWINDOWS * 16 + 8];
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    CPU_COMMON
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    /* MMU regs */
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#if defined(TARGET_SPARC64)
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    uint64_t lsu;
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#define DMMU_E 0x8
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#define IMMU_E 0x4
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    uint64_t immuregs[16];
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    uint64_t dmmuregs[16];
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    uint64_t itlb_tag[64];
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    uint64_t itlb_tte[64];
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    uint64_t dtlb_tag[64];
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    uint64_t dtlb_tte[64];
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#else
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    uint32_t mmuregs[32];
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    uint64_t mxccdata[4];
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    uint64_t mxccregs[8];
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    uint64_t prom_addr;
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#endif
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    /* temporary float registers */
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    float32 ft0, ft1;
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    float64 dt0, dt1;
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    float128 qt0, qt1;
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    float_status fp_status;
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#if defined(TARGET_SPARC64)
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#define MAXTL 4
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    trap_state *tsptr;
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    trap_state ts[MAXTL];
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    uint32_t xcc;               /* Extended integer condition codes */
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    uint32_t asi;
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    uint32_t pstate;
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    uint32_t tl;
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    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
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    uint64_t agregs[8]; /* alternate general registers */
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    uint64_t bgregs[8]; /* backup for normal global registers */
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    uint64_t igregs[8]; /* interrupt general registers */
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    uint64_t mgregs[8]; /* mmu general registers */
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    uint64_t fprs;
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    uint64_t tick_cmpr, stick_cmpr;
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    void *tick, *stick;
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    uint64_t gsr;
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    uint32_t gl; // UA2005
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    /* UA 2005 hyperprivileged registers */
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    uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
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    void *hstick; // UA 2005
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#endif
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    uint32_t features;
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} CPUSPARCState;
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#define CPU_FEATURE_FLOAT    (1 << 0)
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#define CPU_FEATURE_FLOAT128 (1 << 1)
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#define CPU_FEATURE_SWAP     (1 << 2)
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#define CPU_FEATURE_MUL      (1 << 3)
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#define CPU_FEATURE_DIV      (1 << 4)
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#define CPU_FEATURE_FLUSH    (1 << 5)
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#define CPU_FEATURE_FSQRT    (1 << 6)
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#define CPU_FEATURE_FMUL     (1 << 7)
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#define CPU_FEATURE_VIS1     (1 << 8)
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#define CPU_FEATURE_VIS2     (1 << 9)
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#define CPU_FEATURE_FSMULD   (1 << 10)
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#ifndef TARGET_SPARC64
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#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
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                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
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                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
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                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
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#else
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#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
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                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
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                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
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                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
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                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
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#endif
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#if defined(TARGET_SPARC64)
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#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
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        env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);  \
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    } while (0)
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#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
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#define PUT_FSR64(env, val) do { uint64_t _tmp = val;   \
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        env->fsr = _tmp & 0x3fcfc1c3ffULL;              \
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    } while (0)
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#else
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#define GET_FSR32(env) (env->fsr)
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
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        env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000);       \
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    } while (0)
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#endif
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CPUSPARCState *cpu_sparc_init(const char *cpu_model);
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void gen_intermediate_code_init(CPUSPARCState *env);
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int cpu_sparc_exec(CPUSPARCState *s);
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void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
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                                                 ...));
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
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#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
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                      (env->psref? PSR_EF : 0) |                        \
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                      (env->psrpil << 8) |                              \
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                      (env->psrs? PSR_S : 0) |                          \
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                      (env->psrps? PSR_PS : 0) |                        \
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                      (env->psret? PSR_ET : 0) | env->cwp)
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#ifndef NO_CPU_IO_DEFS
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void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
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static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
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{
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    if (unlikely(cwp >= env1->nwindows))
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        cwp -= env1->nwindows;
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    return cwp;
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}
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static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
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{
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    if (unlikely(cwp < 0))
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        cwp += env1->nwindows;
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    return cwp;
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}
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#endif
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#define PUT_PSR(env, val) do { int _tmp = val;                          \
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        env->psr = _tmp & PSR_ICC;                                      \
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        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
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        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
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        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
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        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
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        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
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        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
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    } while (0)
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#ifdef TARGET_SPARC64
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#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
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#define PUT_CCR(env, val) do { int _tmp = val;                          \
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        env->xcc = (_tmp >> 4) << 20;                                   \
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        env->psr = (_tmp & 0xf) << 20;                                  \
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    } while (0)
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#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
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static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
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{
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    if (unlikely(cwp >= env1->nwindows || cwp < 0))
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        cwp = 0;
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    cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
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}
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#endif
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int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
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void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
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                          int is_asi);
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void cpu_check_irqs(CPUSPARCState *env);
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#define CPUState CPUSPARCState
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#define cpu_init cpu_sparc_init
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#define cpu_exec cpu_sparc_exec
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#define cpu_gen_code cpu_sparc_gen_code
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#define cpu_signal_handler cpu_sparc_signal_handler
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#define cpu_list sparc_cpu_list
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel
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#ifdef TARGET_SPARC64
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#define MMU_MODE2_SUFFIX _hypv
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#endif
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#define MMU_USER_IDX   0
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#define MMU_KERNEL_IDX 1
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#define MMU_HYPV_IDX   2
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static inline int cpu_mmu_index(CPUState *env1)
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{
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#if defined(CONFIG_USER_ONLY)
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    return MMU_USER_IDX;
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#elif !defined(TARGET_SPARC64)
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    return env1->psrs;
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#else
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    if (!env1->psrs)
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        return MMU_USER_IDX;
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    else if ((env1->hpstate & HS_PRIV) == 0)
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        return MMU_KERNEL_IDX;
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    else
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        return MMU_HYPV_IDX;
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#endif
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}
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static inline int cpu_fpu_enabled(CPUState *env1)
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{
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#if defined(CONFIG_USER_ONLY)
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    return 1;
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#elif !defined(TARGET_SPARC64)
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    return env1->psref;
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#else
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    return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
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#endif
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}
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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{
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    if (newsp)
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        env->regwptr[22] = newsp;
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    env->regwptr[0] = 0;
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    /* FIXME: Do we also need to clear CF?  */
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    /* XXXXX */
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    printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
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}
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#endif
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#include "cpu-all.h"
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#endif