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1
/*
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   SPARC translation
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4
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   Copyright (C) 2003-2005 Fabrice Bellard
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   This library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "helper.h"
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#include "tcg-op.h"
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34
#define DEBUG_DISAS
35

    
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#define DYNAMIC_PC  1 /* dynamic pc value */
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#define JUMP_PC     2 /* dynamic pc value which takes only two values
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                         according to jump_pc[T2] */
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40
/* global register indexes */
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static TCGv cpu_env, cpu_T[2], cpu_regwptr;
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static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
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static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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#ifdef TARGET_SPARC64
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static TCGv cpu_xcc;
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#endif
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/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50

    
51
typedef struct DisasContext {
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    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
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    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
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    int is_br;
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    int mem_idx;
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    int fpu_enabled;
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    struct TranslationBlock *tb;
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    uint32_t features;
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} DisasContext;
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62
// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
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  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
65

    
66
// This function uses the order in the manuals, i.e. bit 0 is 2^0
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#define GET_FIELD_SP(X, FROM, TO) \
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    GET_FIELD(X, 31 - (TO), 31 - (FROM))
69

    
70
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
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73
#ifdef TARGET_SPARC64
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#define FFPREG(r) (r)
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#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
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#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
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#else
78
#define FFPREG(r) (r)
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#define DFPREG(r) (r & 0x1e)
80
#define QFPREG(r) (r & 0x1c)
81
#endif
82

    
83
static int sign_extend(int x, int len)
84
{
85
    len = 32 - len;
86
    return (x << len) >> len;
87
}
88

    
89
#define IS_IMM (insn & (1<<13))
90

    
91
/* floating point registers moves */
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static void gen_op_load_fpr_FT0(unsigned int src)
93
{
94
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
95
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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}
97

    
98
static void gen_op_load_fpr_FT1(unsigned int src)
99
{
100
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
102
}
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104
static void gen_op_store_FT0_fpr(unsigned int dst)
105
{
106
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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}
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static void gen_op_load_fpr_DT0(unsigned int src)
111
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
114
                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.lower));
118
}
119

    
120
static void gen_op_load_fpr_DT1(unsigned int src)
121
{
122
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
123
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127
                   offsetof(CPU_DoubleU, l.lower));
128
}
129

    
130
static void gen_op_store_DT0_fpr(unsigned int dst)
131
{
132
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
133
                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136
                   offsetof(CPU_DoubleU, l.lower));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
138
}
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140
static void gen_op_load_fpr_QT0(unsigned int src)
141
{
142
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
143
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
144
                   offsetof(CPU_QuadU, l.upmost));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
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                   offsetof(CPU_QuadU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150
                   offsetof(CPU_QuadU, l.lower));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
152
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153
                   offsetof(CPU_QuadU, l.lowest));
154
}
155

    
156
static void gen_op_load_fpr_QT1(unsigned int src)
157
{
158
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
159
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upmost));
161
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
162
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upper));
164
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
165
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166
                   offsetof(CPU_QuadU, l.lower));
167
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
168
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169
                   offsetof(CPU_QuadU, l.lowest));
170
}
171

    
172
static void gen_op_store_QT0_fpr(unsigned int dst)
173
{
174
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
175
                   offsetof(CPU_QuadU, l.upmost));
176
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
177
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178
                   offsetof(CPU_QuadU, l.upper));
179
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
180
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181
                   offsetof(CPU_QuadU, l.lower));
182
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
183
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184
                   offsetof(CPU_QuadU, l.lowest));
185
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
186
}
187

    
188
/* moves */
189
#ifdef CONFIG_USER_ONLY
190
#define supervisor(dc) 0
191
#ifdef TARGET_SPARC64
192
#define hypervisor(dc) 0
193
#endif
194
#else
195
#define supervisor(dc) (dc->mem_idx >= 1)
196
#ifdef TARGET_SPARC64
197
#define hypervisor(dc) (dc->mem_idx == 2)
198
#else
199
#endif
200
#endif
201

    
202
#ifdef TARGET_ABI32
203
#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
204
#else
205
#define ABI32_MASK(addr)
206
#endif
207

    
208
static inline void gen_movl_reg_TN(int reg, TCGv tn)
209
{
210
    if (reg == 0)
211
        tcg_gen_movi_tl(tn, 0);
212
    else if (reg < 8)
213
        tcg_gen_mov_tl(tn, cpu_gregs[reg]);
214
    else {
215
        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
216
    }
217
}
218

    
219
static inline void gen_movl_TN_reg(int reg, TCGv tn)
220
{
221
    if (reg == 0)
222
        return;
223
    else if (reg < 8)
224
        tcg_gen_mov_tl(cpu_gregs[reg], tn);
225
    else {
226
        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
227
    }
228
}
229

    
230
static inline void gen_goto_tb(DisasContext *s, int tb_num,
231
                               target_ulong pc, target_ulong npc)
232
{
233
    TranslationBlock *tb;
234

    
235
    tb = s->tb;
236
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
237
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
238
        /* jump to same page: we can use a direct jump */
239
        tcg_gen_goto_tb(tb_num);
240
        tcg_gen_movi_tl(cpu_pc, pc);
241
        tcg_gen_movi_tl(cpu_npc, npc);
242
        tcg_gen_exit_tb((long)tb + tb_num);
243
    } else {
244
        /* jump to another page: currently not optimized */
245
        tcg_gen_movi_tl(cpu_pc, pc);
246
        tcg_gen_movi_tl(cpu_npc, npc);
247
        tcg_gen_exit_tb(0);
248
    }
249
}
250

    
251
// XXX suboptimal
252
static inline void gen_mov_reg_N(TCGv reg, TCGv src)
253
{
254
    tcg_gen_extu_i32_tl(reg, src);
255
    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
256
    tcg_gen_andi_tl(reg, reg, 0x1);
257
}
258

    
259
static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
260
{
261
    tcg_gen_extu_i32_tl(reg, src);
262
    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
263
    tcg_gen_andi_tl(reg, reg, 0x1);
264
}
265

    
266
static inline void gen_mov_reg_V(TCGv reg, TCGv src)
267
{
268
    tcg_gen_extu_i32_tl(reg, src);
269
    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
270
    tcg_gen_andi_tl(reg, reg, 0x1);
271
}
272

    
273
static inline void gen_mov_reg_C(TCGv reg, TCGv src)
274
{
275
    tcg_gen_extu_i32_tl(reg, src);
276
    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
277
    tcg_gen_andi_tl(reg, reg, 0x1);
278
}
279

    
280
static inline void gen_cc_clear_icc(void)
281
{
282
    tcg_gen_movi_i32(cpu_psr, 0);
283
}
284

    
285
#ifdef TARGET_SPARC64
286
static inline void gen_cc_clear_xcc(void)
287
{
288
    tcg_gen_movi_i32(cpu_xcc, 0);
289
}
290
#endif
291

    
292
/* old op:
293
    if (!T0)
294
        env->psr |= PSR_ZERO;
295
    if ((int32_t) T0 < 0)
296
        env->psr |= PSR_NEG;
297
*/
298
static inline void gen_cc_NZ_icc(TCGv dst)
299
{
300
    TCGv r_temp;
301
    int l1, l2;
302

    
303
    l1 = gen_new_label();
304
    l2 = gen_new_label();
305
    r_temp = tcg_temp_new(TCG_TYPE_TL);
306
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
307
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
308
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
309
    gen_set_label(l1);
310
    tcg_gen_ext_i32_tl(r_temp, dst);
311
    tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
312
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
313
    gen_set_label(l2);
314
    tcg_temp_free(r_temp);
315
}
316

    
317
#ifdef TARGET_SPARC64
318
static inline void gen_cc_NZ_xcc(TCGv dst)
319
{
320
    int l1, l2;
321

    
322
    l1 = gen_new_label();
323
    l2 = gen_new_label();
324
    tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
325
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
326
    gen_set_label(l1);
327
    tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
328
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
329
    gen_set_label(l2);
330
}
331
#endif
332

    
333
/* old op:
334
    if (T0 < src1)
335
        env->psr |= PSR_CARRY;
336
*/
337
static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
338
{
339
    TCGv r_temp;
340
    int l1;
341

    
342
    l1 = gen_new_label();
343
    r_temp = tcg_temp_new(TCG_TYPE_TL);
344
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
345
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
346
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
347
    gen_set_label(l1);
348
    tcg_temp_free(r_temp);
349
}
350

    
351
#ifdef TARGET_SPARC64
352
static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
353
{
354
    int l1;
355

    
356
    l1 = gen_new_label();
357
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
358
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
359
    gen_set_label(l1);
360
}
361
#endif
362

    
363
/* old op:
364
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
365
        env->psr |= PSR_OVF;
366
*/
367
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
368
{
369
    TCGv r_temp;
370

    
371
    r_temp = tcg_temp_new(TCG_TYPE_TL);
372
    tcg_gen_xor_tl(r_temp, src1, src2);
373
    tcg_gen_xori_tl(r_temp, r_temp, -1);
374
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
375
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
376
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
377
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
378
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
379
    tcg_temp_free(r_temp);
380
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
381
}
382

    
383
#ifdef TARGET_SPARC64
384
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
385
{
386
    TCGv r_temp;
387

    
388
    r_temp = tcg_temp_new(TCG_TYPE_TL);
389
    tcg_gen_xor_tl(r_temp, src1, src2);
390
    tcg_gen_xori_tl(r_temp, r_temp, -1);
391
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
392
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
393
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
394
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
395
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
396
    tcg_temp_free(r_temp);
397
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
398
}
399
#endif
400

    
401
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
402
{
403
    TCGv r_temp, r_const;
404
    int l1;
405

    
406
    l1 = gen_new_label();
407

    
408
    r_temp = tcg_temp_new(TCG_TYPE_TL);
409
    tcg_gen_xor_tl(r_temp, src1, src2);
410
    tcg_gen_xori_tl(r_temp, r_temp, -1);
411
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
412
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
413
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
414
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
415
    r_const = tcg_const_i32(TT_TOVF);
416
    tcg_gen_helper_0_1(raise_exception, r_const);
417
    tcg_temp_free(r_const);
418
    gen_set_label(l1);
419
    tcg_temp_free(r_temp);
420
}
421

    
422
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
423
{
424
    int l1;
425

    
426
    l1 = gen_new_label();
427
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
428
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
429
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
430
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
431
    gen_set_label(l1);
432
}
433

    
434
static inline void gen_tag_tv(TCGv src1, TCGv src2)
435
{
436
    int l1;
437
    TCGv r_const;
438

    
439
    l1 = gen_new_label();
440
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
441
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
442
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
443
    r_const = tcg_const_i32(TT_TOVF);
444
    tcg_gen_helper_0_1(raise_exception, r_const);
445
    tcg_temp_free(r_const);
446
    gen_set_label(l1);
447
}
448

    
449
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
450
{
451
    tcg_gen_mov_tl(cpu_cc_src, src1);
452
    tcg_gen_mov_tl(cpu_cc_src2, src2);
453
    tcg_gen_add_tl(dst, src1, src2);
454
    tcg_gen_mov_tl(cpu_cc_dst, dst);
455
    gen_cc_clear_icc();
456
    gen_cc_NZ_icc(cpu_cc_dst);
457
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
458
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
459
#ifdef TARGET_SPARC64
460
    gen_cc_clear_xcc();
461
    gen_cc_NZ_xcc(cpu_cc_dst);
462
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
463
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
464
#endif
465
}
466

    
467
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
468
{
469
    tcg_gen_mov_tl(cpu_cc_src, src1);
470
    tcg_gen_mov_tl(cpu_cc_src2, src2);
471
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
472
    tcg_gen_add_tl(dst, src1, cpu_tmp0);
473
    gen_cc_clear_icc();
474
    gen_cc_C_add_icc(dst, cpu_cc_src);
475
#ifdef TARGET_SPARC64
476
    gen_cc_clear_xcc();
477
    gen_cc_C_add_xcc(dst, cpu_cc_src);
478
#endif
479
    tcg_gen_add_tl(dst, dst, cpu_cc_src2);
480
    tcg_gen_mov_tl(cpu_cc_dst, dst);
481
    gen_cc_NZ_icc(cpu_cc_dst);
482
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
483
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
484
#ifdef TARGET_SPARC64
485
    gen_cc_NZ_xcc(cpu_cc_dst);
486
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
487
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
488
#endif
489
}
490

    
491
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
492
{
493
    tcg_gen_mov_tl(cpu_cc_src, src1);
494
    tcg_gen_mov_tl(cpu_cc_src2, src2);
495
    tcg_gen_add_tl(dst, src1, src2);
496
    tcg_gen_mov_tl(cpu_cc_dst, dst);
497
    gen_cc_clear_icc();
498
    gen_cc_NZ_icc(cpu_cc_dst);
499
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
500
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
501
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
502
#ifdef TARGET_SPARC64
503
    gen_cc_clear_xcc();
504
    gen_cc_NZ_xcc(cpu_cc_dst);
505
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
506
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
507
#endif
508
}
509

    
510
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
511
{
512
    tcg_gen_mov_tl(cpu_cc_src, src1);
513
    tcg_gen_mov_tl(cpu_cc_src2, src2);
514
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
515
    tcg_gen_add_tl(dst, src1, src2);
516
    tcg_gen_mov_tl(cpu_cc_dst, dst);
517
    gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
518
    gen_cc_clear_icc();
519
    gen_cc_NZ_icc(cpu_cc_dst);
520
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
521
#ifdef TARGET_SPARC64
522
    gen_cc_clear_xcc();
523
    gen_cc_NZ_xcc(cpu_cc_dst);
524
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
525
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
526
#endif
527
}
528

    
529
/* old op:
530
    if (src1 < T1)
531
        env->psr |= PSR_CARRY;
532
*/
533
static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
534
{
535
    TCGv r_temp1, r_temp2;
536
    int l1;
537

    
538
    l1 = gen_new_label();
539
    r_temp1 = tcg_temp_new(TCG_TYPE_TL);
540
    r_temp2 = tcg_temp_new(TCG_TYPE_TL);
541
    tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
542
    tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
543
    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
544
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
545
    gen_set_label(l1);
546
    tcg_temp_free(r_temp1);
547
    tcg_temp_free(r_temp2);
548
}
549

    
550
#ifdef TARGET_SPARC64
551
static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
552
{
553
    int l1;
554

    
555
    l1 = gen_new_label();
556
    tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
557
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
558
    gen_set_label(l1);
559
}
560
#endif
561

    
562
/* old op:
563
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
564
        env->psr |= PSR_OVF;
565
*/
566
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
567
{
568
    TCGv r_temp;
569

    
570
    r_temp = tcg_temp_new(TCG_TYPE_TL);
571
    tcg_gen_xor_tl(r_temp, src1, src2);
572
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
573
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
574
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
575
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
576
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
577
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
578
    tcg_temp_free(r_temp);
579
}
580

    
581
#ifdef TARGET_SPARC64
582
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
583
{
584
    TCGv r_temp;
585

    
586
    r_temp = tcg_temp_new(TCG_TYPE_TL);
587
    tcg_gen_xor_tl(r_temp, src1, src2);
588
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
591
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
592
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
594
    tcg_temp_free(r_temp);
595
}
596
#endif
597

    
598
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
599
{
600
    TCGv r_temp, r_const;
601
    int l1;
602

    
603
    l1 = gen_new_label();
604

    
605
    r_temp = tcg_temp_new(TCG_TYPE_TL);
606
    tcg_gen_xor_tl(r_temp, src1, src2);
607
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
608
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
609
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
610
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
611
    r_const = tcg_const_i32(TT_TOVF);
612
    tcg_gen_helper_0_1(raise_exception, r_const);
613
    tcg_temp_free(r_const);
614
    gen_set_label(l1);
615
    tcg_temp_free(r_temp);
616
}
617

    
618
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
619
{
620
    tcg_gen_mov_tl(cpu_cc_src, src1);
621
    tcg_gen_mov_tl(cpu_cc_src2, src2);
622
    tcg_gen_sub_tl(dst, src1, src2);
623
    tcg_gen_mov_tl(cpu_cc_dst, dst);
624
    gen_cc_clear_icc();
625
    gen_cc_NZ_icc(cpu_cc_dst);
626
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
627
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
628
#ifdef TARGET_SPARC64
629
    gen_cc_clear_xcc();
630
    gen_cc_NZ_xcc(cpu_cc_dst);
631
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
632
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
633
#endif
634
}
635

    
636
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
637
{
638
    tcg_gen_mov_tl(cpu_cc_src, src1);
639
    tcg_gen_mov_tl(cpu_cc_src2, src2);
640
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
641
    tcg_gen_sub_tl(dst, src1, cpu_tmp0);
642
    gen_cc_clear_icc();
643
    gen_cc_C_sub_icc(dst, cpu_cc_src);
644
#ifdef TARGET_SPARC64
645
    gen_cc_clear_xcc();
646
    gen_cc_C_sub_xcc(dst, cpu_cc_src);
647
#endif
648
    tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
649
    tcg_gen_mov_tl(cpu_cc_dst, dst);
650
    gen_cc_NZ_icc(cpu_cc_dst);
651
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
652
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
653
#ifdef TARGET_SPARC64
654
    gen_cc_NZ_xcc(cpu_cc_dst);
655
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
656
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
657
#endif
658
}
659

    
660
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
661
{
662
    tcg_gen_mov_tl(cpu_cc_src, src1);
663
    tcg_gen_mov_tl(cpu_cc_src2, src2);
664
    tcg_gen_sub_tl(dst, src1, src2);
665
    tcg_gen_mov_tl(cpu_cc_dst, dst);
666
    gen_cc_clear_icc();
667
    gen_cc_NZ_icc(cpu_cc_dst);
668
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
669
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
670
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
671
#ifdef TARGET_SPARC64
672
    gen_cc_clear_xcc();
673
    gen_cc_NZ_xcc(cpu_cc_dst);
674
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
675
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
676
#endif
677
}
678

    
679
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
680
{
681
    tcg_gen_mov_tl(cpu_cc_src, src1);
682
    tcg_gen_mov_tl(cpu_cc_src2, src2);
683
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
684
    tcg_gen_sub_tl(dst, src1, src2);
685
    tcg_gen_mov_tl(cpu_cc_dst, dst);
686
    gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
687
    gen_cc_clear_icc();
688
    gen_cc_NZ_icc(cpu_cc_dst);
689
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
690
#ifdef TARGET_SPARC64
691
    gen_cc_clear_xcc();
692
    gen_cc_NZ_xcc(cpu_cc_dst);
693
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
694
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
695
#endif
696
}
697

    
698
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
699
{
700
    TCGv r_temp, r_temp2;
701
    int l1;
702

    
703
    l1 = gen_new_label();
704
    r_temp = tcg_temp_new(TCG_TYPE_TL);
705
    r_temp2 = tcg_temp_new(TCG_TYPE_I32);
706

    
707
    /* old op:
708
    if (!(env->y & 1))
709
        T1 = 0;
710
    */
711
    tcg_gen_mov_tl(cpu_cc_src, src1);
712
    tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
713
    tcg_gen_trunc_tl_i32(r_temp2, r_temp);
714
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
715
    tcg_gen_mov_tl(cpu_cc_src2, src2);
716
    tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
717
    tcg_gen_movi_tl(cpu_cc_src2, 0);
718
    gen_set_label(l1);
719

    
720
    // b2 = T0 & 1;
721
    // env->y = (b2 << 31) | (env->y >> 1);
722
    tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
723
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
724
    tcg_gen_shli_i32(r_temp2, r_temp2, 31);
725
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
726
    tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
727
    tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
728
    tcg_temp_free(r_temp2);
729
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
730

    
731
    // b1 = N ^ V;
732
    gen_mov_reg_N(cpu_tmp0, cpu_psr);
733
    gen_mov_reg_V(r_temp, cpu_psr);
734
    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
735
    tcg_temp_free(r_temp);
736

    
737
    // T0 = (b1 << 31) | (T0 >> 1);
738
    // src1 = T0;
739
    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
740
    tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
741
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
742

    
743
    /* do addition and update flags */
744
    tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
745
    tcg_gen_mov_tl(cpu_cc_dst, dst);
746

    
747
    gen_cc_clear_icc();
748
    gen_cc_NZ_icc(cpu_cc_dst);
749
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
750
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
751
}
752

    
753
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
754
{
755
    TCGv r_temp, r_temp2;
756

    
757
    r_temp = tcg_temp_new(TCG_TYPE_I64);
758
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
759

    
760
    tcg_gen_extu_tl_i64(r_temp, src2);
761
    tcg_gen_extu_tl_i64(r_temp2, src1);
762
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
763

    
764
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
765
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
766
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
767
    tcg_temp_free(r_temp);
768
#ifdef TARGET_SPARC64
769
    tcg_gen_mov_i64(dst, r_temp2);
770
#else
771
    tcg_gen_trunc_i64_tl(dst, r_temp2);
772
#endif
773
    tcg_temp_free(r_temp2);
774
}
775

    
776
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
777
{
778
    TCGv r_temp, r_temp2;
779

    
780
    r_temp = tcg_temp_new(TCG_TYPE_I64);
781
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
782

    
783
    tcg_gen_ext_tl_i64(r_temp, src2);
784
    tcg_gen_ext_tl_i64(r_temp2, src1);
785
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
786

    
787
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
788
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
789
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
790
    tcg_temp_free(r_temp);
791
#ifdef TARGET_SPARC64
792
    tcg_gen_mov_i64(dst, r_temp2);
793
#else
794
    tcg_gen_trunc_i64_tl(dst, r_temp2);
795
#endif
796
    tcg_temp_free(r_temp2);
797
}
798

    
799
#ifdef TARGET_SPARC64
800
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
801
{
802
    TCGv r_const;
803
    int l1;
804

    
805
    l1 = gen_new_label();
806
    tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
807
    r_const = tcg_const_i32(TT_DIV_ZERO);
808
    tcg_gen_helper_0_1(raise_exception, r_const);
809
    tcg_temp_free(r_const);
810
    gen_set_label(l1);
811
}
812

    
813
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
814
{
815
    int l1, l2;
816

    
817
    l1 = gen_new_label();
818
    l2 = gen_new_label();
819
    tcg_gen_mov_tl(cpu_cc_src, src1);
820
    tcg_gen_mov_tl(cpu_cc_src2, src2);
821
    gen_trap_ifdivzero_tl(src2);
822
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
823
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
824
    tcg_gen_movi_i64(dst, INT64_MIN);
825
    tcg_gen_br(l2);
826
    gen_set_label(l1);
827
    tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
828
    gen_set_label(l2);
829
}
830
#endif
831

    
832
static inline void gen_op_div_cc(TCGv dst)
833
{
834
    int l1;
835

    
836
    tcg_gen_mov_tl(cpu_cc_dst, dst);
837
    gen_cc_clear_icc();
838
    gen_cc_NZ_icc(cpu_cc_dst);
839
    l1 = gen_new_label();
840
    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
841
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
842
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
843
    gen_set_label(l1);
844
}
845

    
846
static inline void gen_op_logic_cc(TCGv dst)
847
{
848
    tcg_gen_mov_tl(cpu_cc_dst, dst);
849

    
850
    gen_cc_clear_icc();
851
    gen_cc_NZ_icc(cpu_cc_dst);
852
#ifdef TARGET_SPARC64
853
    gen_cc_clear_xcc();
854
    gen_cc_NZ_xcc(cpu_cc_dst);
855
#endif
856
}
857

    
858
// 1
859
static inline void gen_op_eval_ba(TCGv dst)
860
{
861
    tcg_gen_movi_tl(dst, 1);
862
}
863

    
864
// Z
865
static inline void gen_op_eval_be(TCGv dst, TCGv src)
866
{
867
    gen_mov_reg_Z(dst, src);
868
}
869

    
870
// Z | (N ^ V)
871
static inline void gen_op_eval_ble(TCGv dst, TCGv src)
872
{
873
    gen_mov_reg_N(cpu_tmp0, src);
874
    gen_mov_reg_V(dst, src);
875
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
876
    gen_mov_reg_Z(cpu_tmp0, src);
877
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
878
}
879

    
880
// N ^ V
881
static inline void gen_op_eval_bl(TCGv dst, TCGv src)
882
{
883
    gen_mov_reg_V(cpu_tmp0, src);
884
    gen_mov_reg_N(dst, src);
885
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
886
}
887

    
888
// C | Z
889
static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
890
{
891
    gen_mov_reg_Z(cpu_tmp0, src);
892
    gen_mov_reg_C(dst, src);
893
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
894
}
895

    
896
// C
897
static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
898
{
899
    gen_mov_reg_C(dst, src);
900
}
901

    
902
// V
903
static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
904
{
905
    gen_mov_reg_V(dst, src);
906
}
907

    
908
// 0
909
static inline void gen_op_eval_bn(TCGv dst)
910
{
911
    tcg_gen_movi_tl(dst, 0);
912
}
913

    
914
// N
915
static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
916
{
917
    gen_mov_reg_N(dst, src);
918
}
919

    
920
// !Z
921
static inline void gen_op_eval_bne(TCGv dst, TCGv src)
922
{
923
    gen_mov_reg_Z(dst, src);
924
    tcg_gen_xori_tl(dst, dst, 0x1);
925
}
926

    
927
// !(Z | (N ^ V))
928
static inline void gen_op_eval_bg(TCGv dst, TCGv src)
929
{
930
    gen_mov_reg_N(cpu_tmp0, src);
931
    gen_mov_reg_V(dst, src);
932
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
933
    gen_mov_reg_Z(cpu_tmp0, src);
934
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
935
    tcg_gen_xori_tl(dst, dst, 0x1);
936
}
937

    
938
// !(N ^ V)
939
static inline void gen_op_eval_bge(TCGv dst, TCGv src)
940
{
941
    gen_mov_reg_V(cpu_tmp0, src);
942
    gen_mov_reg_N(dst, src);
943
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
944
    tcg_gen_xori_tl(dst, dst, 0x1);
945
}
946

    
947
// !(C | Z)
948
static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
949
{
950
    gen_mov_reg_Z(cpu_tmp0, src);
951
    gen_mov_reg_C(dst, src);
952
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
953
    tcg_gen_xori_tl(dst, dst, 0x1);
954
}
955

    
956
// !C
957
static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
958
{
959
    gen_mov_reg_C(dst, src);
960
    tcg_gen_xori_tl(dst, dst, 0x1);
961
}
962

    
963
// !N
964
static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
965
{
966
    gen_mov_reg_N(dst, src);
967
    tcg_gen_xori_tl(dst, dst, 0x1);
968
}
969

    
970
// !V
971
static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
972
{
973
    gen_mov_reg_V(dst, src);
974
    tcg_gen_xori_tl(dst, dst, 0x1);
975
}
976

    
977
/*
978
  FPSR bit field FCC1 | FCC0:
979
   0 =
980
   1 <
981
   2 >
982
   3 unordered
983
*/
984
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
985
                                    unsigned int fcc_offset)
986
{
987
    tcg_gen_extu_i32_tl(reg, src);
988
    tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
989
    tcg_gen_andi_tl(reg, reg, 0x1);
990
}
991

    
992
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
993
                                    unsigned int fcc_offset)
994
{
995
    tcg_gen_extu_i32_tl(reg, src);
996
    tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
997
    tcg_gen_andi_tl(reg, reg, 0x1);
998
}
999

    
1000
// !0: FCC0 | FCC1
1001
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1002
                                    unsigned int fcc_offset)
1003
{
1004
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1005
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1006
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1007
}
1008

    
1009
// 1 or 2: FCC0 ^ FCC1
1010
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1011
                                    unsigned int fcc_offset)
1012
{
1013
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1014
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1015
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1016
}
1017

    
1018
// 1 or 3: FCC0
1019
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1020
                                    unsigned int fcc_offset)
1021
{
1022
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1023
}
1024

    
1025
// 1: FCC0 & !FCC1
1026
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1027
                                    unsigned int fcc_offset)
1028
{
1029
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1030
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1031
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1032
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1033
}
1034

    
1035
// 2 or 3: FCC1
1036
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1037
                                    unsigned int fcc_offset)
1038
{
1039
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1040
}
1041

    
1042
// 2: !FCC0 & FCC1
1043
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1044
                                    unsigned int fcc_offset)
1045
{
1046
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1047
    tcg_gen_xori_tl(dst, dst, 0x1);
1048
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1049
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1050
}
1051

    
1052
// 3: FCC0 & FCC1
1053
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1054
                                    unsigned int fcc_offset)
1055
{
1056
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1057
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1058
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1059
}
1060

    
1061
// 0: !(FCC0 | FCC1)
1062
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1063
                                    unsigned int fcc_offset)
1064
{
1065
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1066
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1067
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1068
    tcg_gen_xori_tl(dst, dst, 0x1);
1069
}
1070

    
1071
// 0 or 3: !(FCC0 ^ FCC1)
1072
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1073
                                    unsigned int fcc_offset)
1074
{
1075
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1076
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1077
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1078
    tcg_gen_xori_tl(dst, dst, 0x1);
1079
}
1080

    
1081
// 0 or 2: !FCC0
1082
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1083
                                    unsigned int fcc_offset)
1084
{
1085
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1086
    tcg_gen_xori_tl(dst, dst, 0x1);
1087
}
1088

    
1089
// !1: !(FCC0 & !FCC1)
1090
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1091
                                    unsigned int fcc_offset)
1092
{
1093
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1094
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1095
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1096
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1097
    tcg_gen_xori_tl(dst, dst, 0x1);
1098
}
1099

    
1100
// 0 or 1: !FCC1
1101
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1102
                                    unsigned int fcc_offset)
1103
{
1104
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1105
    tcg_gen_xori_tl(dst, dst, 0x1);
1106
}
1107

    
1108
// !2: !(!FCC0 & FCC1)
1109
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1110
                                    unsigned int fcc_offset)
1111
{
1112
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1113
    tcg_gen_xori_tl(dst, dst, 0x1);
1114
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1115
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1116
    tcg_gen_xori_tl(dst, dst, 0x1);
1117
}
1118

    
1119
// !3: !(FCC0 & FCC1)
1120
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1121
                                    unsigned int fcc_offset)
1122
{
1123
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1124
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1125
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1126
    tcg_gen_xori_tl(dst, dst, 0x1);
1127
}
1128

    
1129
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1130
                               target_ulong pc2, TCGv r_cond)
1131
{
1132
    int l1;
1133

    
1134
    l1 = gen_new_label();
1135

    
1136
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1137

    
1138
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
1139

    
1140
    gen_set_label(l1);
1141
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
1142
}
1143

    
1144
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1145
                                target_ulong pc2, TCGv r_cond)
1146
{
1147
    int l1;
1148

    
1149
    l1 = gen_new_label();
1150

    
1151
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1152

    
1153
    gen_goto_tb(dc, 0, pc2, pc1);
1154

    
1155
    gen_set_label(l1);
1156
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1157
}
1158

    
1159
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1160
                                      TCGv r_cond)
1161
{
1162
    int l1, l2;
1163

    
1164
    l1 = gen_new_label();
1165
    l2 = gen_new_label();
1166

    
1167
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1168

    
1169
    tcg_gen_movi_tl(cpu_npc, npc1);
1170
    tcg_gen_br(l2);
1171

    
1172
    gen_set_label(l1);
1173
    tcg_gen_movi_tl(cpu_npc, npc2);
1174
    gen_set_label(l2);
1175
}
1176

    
1177
/* call this function before using the condition register as it may
1178
   have been set for a jump */
1179
static inline void flush_cond(DisasContext *dc, TCGv cond)
1180
{
1181
    if (dc->npc == JUMP_PC) {
1182
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1183
        dc->npc = DYNAMIC_PC;
1184
    }
1185
}
1186

    
1187
static inline void save_npc(DisasContext *dc, TCGv cond)
1188
{
1189
    if (dc->npc == JUMP_PC) {
1190
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1191
        dc->npc = DYNAMIC_PC;
1192
    } else if (dc->npc != DYNAMIC_PC) {
1193
        tcg_gen_movi_tl(cpu_npc, dc->npc);
1194
    }
1195
}
1196

    
1197
static inline void save_state(DisasContext *dc, TCGv cond)
1198
{
1199
    tcg_gen_movi_tl(cpu_pc, dc->pc);
1200
    save_npc(dc, cond);
1201
}
1202

    
1203
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1204
{
1205
    if (dc->npc == JUMP_PC) {
1206
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1207
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1208
        dc->pc = DYNAMIC_PC;
1209
    } else if (dc->npc == DYNAMIC_PC) {
1210
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1211
        dc->pc = DYNAMIC_PC;
1212
    } else {
1213
        dc->pc = dc->npc;
1214
    }
1215
}
1216

    
1217
static inline void gen_op_next_insn(void)
1218
{
1219
    tcg_gen_mov_tl(cpu_pc, cpu_npc);
1220
    tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1221
}
1222

    
1223
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1224
{
1225
    TCGv r_src;
1226

    
1227
#ifdef TARGET_SPARC64
1228
    if (cc)
1229
        r_src = cpu_xcc;
1230
    else
1231
        r_src = cpu_psr;
1232
#else
1233
    r_src = cpu_psr;
1234
#endif
1235
    switch (cond) {
1236
    case 0x0:
1237
        gen_op_eval_bn(r_dst);
1238
        break;
1239
    case 0x1:
1240
        gen_op_eval_be(r_dst, r_src);
1241
        break;
1242
    case 0x2:
1243
        gen_op_eval_ble(r_dst, r_src);
1244
        break;
1245
    case 0x3:
1246
        gen_op_eval_bl(r_dst, r_src);
1247
        break;
1248
    case 0x4:
1249
        gen_op_eval_bleu(r_dst, r_src);
1250
        break;
1251
    case 0x5:
1252
        gen_op_eval_bcs(r_dst, r_src);
1253
        break;
1254
    case 0x6:
1255
        gen_op_eval_bneg(r_dst, r_src);
1256
        break;
1257
    case 0x7:
1258
        gen_op_eval_bvs(r_dst, r_src);
1259
        break;
1260
    case 0x8:
1261
        gen_op_eval_ba(r_dst);
1262
        break;
1263
    case 0x9:
1264
        gen_op_eval_bne(r_dst, r_src);
1265
        break;
1266
    case 0xa:
1267
        gen_op_eval_bg(r_dst, r_src);
1268
        break;
1269
    case 0xb:
1270
        gen_op_eval_bge(r_dst, r_src);
1271
        break;
1272
    case 0xc:
1273
        gen_op_eval_bgu(r_dst, r_src);
1274
        break;
1275
    case 0xd:
1276
        gen_op_eval_bcc(r_dst, r_src);
1277
        break;
1278
    case 0xe:
1279
        gen_op_eval_bpos(r_dst, r_src);
1280
        break;
1281
    case 0xf:
1282
        gen_op_eval_bvc(r_dst, r_src);
1283
        break;
1284
    }
1285
}
1286

    
1287
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1288
{
1289
    unsigned int offset;
1290

    
1291
    switch (cc) {
1292
    default:
1293
    case 0x0:
1294
        offset = 0;
1295
        break;
1296
    case 0x1:
1297
        offset = 32 - 10;
1298
        break;
1299
    case 0x2:
1300
        offset = 34 - 10;
1301
        break;
1302
    case 0x3:
1303
        offset = 36 - 10;
1304
        break;
1305
    }
1306

    
1307
    switch (cond) {
1308
    case 0x0:
1309
        gen_op_eval_bn(r_dst);
1310
        break;
1311
    case 0x1:
1312
        gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1313
        break;
1314
    case 0x2:
1315
        gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1316
        break;
1317
    case 0x3:
1318
        gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1319
        break;
1320
    case 0x4:
1321
        gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1322
        break;
1323
    case 0x5:
1324
        gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1325
        break;
1326
    case 0x6:
1327
        gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1328
        break;
1329
    case 0x7:
1330
        gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1331
        break;
1332
    case 0x8:
1333
        gen_op_eval_ba(r_dst);
1334
        break;
1335
    case 0x9:
1336
        gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1337
        break;
1338
    case 0xa:
1339
        gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1340
        break;
1341
    case 0xb:
1342
        gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1343
        break;
1344
    case 0xc:
1345
        gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1346
        break;
1347
    case 0xd:
1348
        gen_op_eval_fble(r_dst, cpu_fsr, offset);
1349
        break;
1350
    case 0xe:
1351
        gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1352
        break;
1353
    case 0xf:
1354
        gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1355
        break;
1356
    }
1357
}
1358

    
1359
#ifdef TARGET_SPARC64
1360
// Inverted logic
1361
static const int gen_tcg_cond_reg[8] = {
1362
    -1,
1363
    TCG_COND_NE,
1364
    TCG_COND_GT,
1365
    TCG_COND_GE,
1366
    -1,
1367
    TCG_COND_EQ,
1368
    TCG_COND_LE,
1369
    TCG_COND_LT,
1370
};
1371

    
1372
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1373
{
1374
    int l1;
1375

    
1376
    l1 = gen_new_label();
1377
    tcg_gen_movi_tl(r_dst, 0);
1378
    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1379
    tcg_gen_movi_tl(r_dst, 1);
1380
    gen_set_label(l1);
1381
}
1382
#endif
1383

    
1384
/* XXX: potentially incorrect if dynamic npc */
1385
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1386
                      TCGv r_cond)
1387
{
1388
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1389
    target_ulong target = dc->pc + offset;
1390

    
1391
    if (cond == 0x0) {
1392
        /* unconditional not taken */
1393
        if (a) {
1394
            dc->pc = dc->npc + 4;
1395
            dc->npc = dc->pc + 4;
1396
        } else {
1397
            dc->pc = dc->npc;
1398
            dc->npc = dc->pc + 4;
1399
        }
1400
    } else if (cond == 0x8) {
1401
        /* unconditional taken */
1402
        if (a) {
1403
            dc->pc = target;
1404
            dc->npc = dc->pc + 4;
1405
        } else {
1406
            dc->pc = dc->npc;
1407
            dc->npc = target;
1408
        }
1409
    } else {
1410
        flush_cond(dc, r_cond);
1411
        gen_cond(r_cond, cc, cond);
1412
        if (a) {
1413
            gen_branch_a(dc, target, dc->npc, r_cond);
1414
            dc->is_br = 1;
1415
        } else {
1416
            dc->pc = dc->npc;
1417
            dc->jump_pc[0] = target;
1418
            dc->jump_pc[1] = dc->npc + 4;
1419
            dc->npc = JUMP_PC;
1420
        }
1421
    }
1422
}
1423

    
1424
/* XXX: potentially incorrect if dynamic npc */
1425
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1426
                      TCGv r_cond)
1427
{
1428
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1429
    target_ulong target = dc->pc + offset;
1430

    
1431
    if (cond == 0x0) {
1432
        /* unconditional not taken */
1433
        if (a) {
1434
            dc->pc = dc->npc + 4;
1435
            dc->npc = dc->pc + 4;
1436
        } else {
1437
            dc->pc = dc->npc;
1438
            dc->npc = dc->pc + 4;
1439
        }
1440
    } else if (cond == 0x8) {
1441
        /* unconditional taken */
1442
        if (a) {
1443
            dc->pc = target;
1444
            dc->npc = dc->pc + 4;
1445
        } else {
1446
            dc->pc = dc->npc;
1447
            dc->npc = target;
1448
        }
1449
    } else {
1450
        flush_cond(dc, r_cond);
1451
        gen_fcond(r_cond, cc, cond);
1452
        if (a) {
1453
            gen_branch_a(dc, target, dc->npc, r_cond);
1454
            dc->is_br = 1;
1455
        } else {
1456
            dc->pc = dc->npc;
1457
            dc->jump_pc[0] = target;
1458
            dc->jump_pc[1] = dc->npc + 4;
1459
            dc->npc = JUMP_PC;
1460
        }
1461
    }
1462
}
1463

    
1464
#ifdef TARGET_SPARC64
1465
/* XXX: potentially incorrect if dynamic npc */
1466
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1467
                          TCGv r_cond, TCGv r_reg)
1468
{
1469
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1470
    target_ulong target = dc->pc + offset;
1471

    
1472
    flush_cond(dc, r_cond);
1473
    gen_cond_reg(r_cond, cond, r_reg);
1474
    if (a) {
1475
        gen_branch_a(dc, target, dc->npc, r_cond);
1476
        dc->is_br = 1;
1477
    } else {
1478
        dc->pc = dc->npc;
1479
        dc->jump_pc[0] = target;
1480
        dc->jump_pc[1] = dc->npc + 4;
1481
        dc->npc = JUMP_PC;
1482
    }
1483
}
1484

    
1485
static GenOpFunc * const gen_fcmps[4] = {
1486
    helper_fcmps,
1487
    helper_fcmps_fcc1,
1488
    helper_fcmps_fcc2,
1489
    helper_fcmps_fcc3,
1490
};
1491

    
1492
static GenOpFunc * const gen_fcmpd[4] = {
1493
    helper_fcmpd,
1494
    helper_fcmpd_fcc1,
1495
    helper_fcmpd_fcc2,
1496
    helper_fcmpd_fcc3,
1497
};
1498

    
1499
static GenOpFunc * const gen_fcmpq[4] = {
1500
    helper_fcmpq,
1501
    helper_fcmpq_fcc1,
1502
    helper_fcmpq_fcc2,
1503
    helper_fcmpq_fcc3,
1504
};
1505

    
1506
static GenOpFunc * const gen_fcmpes[4] = {
1507
    helper_fcmpes,
1508
    helper_fcmpes_fcc1,
1509
    helper_fcmpes_fcc2,
1510
    helper_fcmpes_fcc3,
1511
};
1512

    
1513
static GenOpFunc * const gen_fcmped[4] = {
1514
    helper_fcmped,
1515
    helper_fcmped_fcc1,
1516
    helper_fcmped_fcc2,
1517
    helper_fcmped_fcc3,
1518
};
1519

    
1520
static GenOpFunc * const gen_fcmpeq[4] = {
1521
    helper_fcmpeq,
1522
    helper_fcmpeq_fcc1,
1523
    helper_fcmpeq_fcc2,
1524
    helper_fcmpeq_fcc3,
1525
};
1526

    
1527
static inline void gen_op_fcmps(int fccno)
1528
{
1529
    tcg_gen_helper_0_0(gen_fcmps[fccno]);
1530
}
1531

    
1532
static inline void gen_op_fcmpd(int fccno)
1533
{
1534
    tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1535
}
1536

    
1537
static inline void gen_op_fcmpq(int fccno)
1538
{
1539
    tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1540
}
1541

    
1542
static inline void gen_op_fcmpes(int fccno)
1543
{
1544
    tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1545
}
1546

    
1547
static inline void gen_op_fcmped(int fccno)
1548
{
1549
    tcg_gen_helper_0_0(gen_fcmped[fccno]);
1550
}
1551

    
1552
static inline void gen_op_fcmpeq(int fccno)
1553
{
1554
    tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1555
}
1556

    
1557
#else
1558

    
1559
static inline void gen_op_fcmps(int fccno)
1560
{
1561
    tcg_gen_helper_0_0(helper_fcmps);
1562
}
1563

    
1564
static inline void gen_op_fcmpd(int fccno)
1565
{
1566
    tcg_gen_helper_0_0(helper_fcmpd);
1567
}
1568

    
1569
static inline void gen_op_fcmpq(int fccno)
1570
{
1571
    tcg_gen_helper_0_0(helper_fcmpq);
1572
}
1573

    
1574
static inline void gen_op_fcmpes(int fccno)
1575
{
1576
    tcg_gen_helper_0_0(helper_fcmpes);
1577
}
1578

    
1579
static inline void gen_op_fcmped(int fccno)
1580
{
1581
    tcg_gen_helper_0_0(helper_fcmped);
1582
}
1583

    
1584
static inline void gen_op_fcmpeq(int fccno)
1585
{
1586
    tcg_gen_helper_0_0(helper_fcmpeq);
1587
}
1588
#endif
1589

    
1590
static inline void gen_op_fpexception_im(int fsr_flags)
1591
{
1592
    TCGv r_const;
1593

    
1594
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1595
    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1596
    r_const = tcg_const_i32(TT_FP_EXCP);
1597
    tcg_gen_helper_0_1(raise_exception, r_const);
1598
    tcg_temp_free(r_const);
1599
}
1600

    
1601
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1602
{
1603
#if !defined(CONFIG_USER_ONLY)
1604
    if (!dc->fpu_enabled) {
1605
        TCGv r_const;
1606

    
1607
        save_state(dc, r_cond);
1608
        r_const = tcg_const_i32(TT_NFPU_INSN);
1609
        tcg_gen_helper_0_1(raise_exception, r_const);
1610
        tcg_temp_free(r_const);
1611
        dc->is_br = 1;
1612
        return 1;
1613
    }
1614
#endif
1615
    return 0;
1616
}
1617

    
1618
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1619
{
1620
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1621
}
1622

    
1623
static inline void gen_clear_float_exceptions(void)
1624
{
1625
    tcg_gen_helper_0_0(helper_clear_float_exceptions);
1626
}
1627

    
1628
/* asi moves */
1629
#ifdef TARGET_SPARC64
1630
static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1631
{
1632
    int asi, offset;
1633
    TCGv r_asi;
1634

    
1635
    if (IS_IMM) {
1636
        r_asi = tcg_temp_new(TCG_TYPE_I32);
1637
        offset = GET_FIELD(insn, 25, 31);
1638
        tcg_gen_addi_tl(r_addr, r_addr, offset);
1639
        tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1640
    } else {
1641
        asi = GET_FIELD(insn, 19, 26);
1642
        r_asi = tcg_const_i32(asi);
1643
    }
1644
    return r_asi;
1645
}
1646

    
1647
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1648
                              int sign)
1649
{
1650
    TCGv r_asi, r_size, r_sign;
1651

    
1652
    r_asi = gen_get_asi(insn, addr);
1653
    r_size = tcg_const_i32(size);
1654
    r_sign = tcg_const_i32(sign);
1655
    tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1656
    tcg_temp_free(r_sign);
1657
    tcg_temp_free(r_size);
1658
    tcg_temp_free(r_asi);
1659
}
1660

    
1661
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1662
{
1663
    TCGv r_asi, r_size;
1664

    
1665
    r_asi = gen_get_asi(insn, addr);
1666
    r_size = tcg_const_i32(size);
1667
    tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1668
    tcg_temp_free(r_size);
1669
    tcg_temp_free(r_asi);
1670
}
1671

    
1672
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1673
{
1674
    TCGv r_asi, r_size, r_rd;
1675

    
1676
    r_asi = gen_get_asi(insn, addr);
1677
    r_size = tcg_const_i32(size);
1678
    r_rd = tcg_const_i32(rd);
1679
    tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1680
    tcg_temp_free(r_rd);
1681
    tcg_temp_free(r_size);
1682
    tcg_temp_free(r_asi);
1683
}
1684

    
1685
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1686
{
1687
    TCGv r_asi, r_size, r_rd;
1688

    
1689
    r_asi = gen_get_asi(insn, addr);
1690
    r_size = tcg_const_i32(size);
1691
    r_rd = tcg_const_i32(rd);
1692
    tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1693
    tcg_temp_free(r_rd);
1694
    tcg_temp_free(r_size);
1695
    tcg_temp_free(r_asi);
1696
}
1697

    
1698
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1699
{
1700
    TCGv r_asi, r_size, r_sign;
1701

    
1702
    r_asi = gen_get_asi(insn, addr);
1703
    r_size = tcg_const_i32(4);
1704
    r_sign = tcg_const_i32(0);
1705
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1706
    tcg_temp_free(r_sign);
1707
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1708
    tcg_temp_free(r_size);
1709
    tcg_temp_free(r_asi);
1710
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1711
}
1712

    
1713
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1714
{
1715
    TCGv r_asi, r_size, r_sign;
1716

    
1717
    r_asi = gen_get_asi(insn, addr);
1718
    r_size = tcg_const_i32(8);
1719
    r_sign = tcg_const_i32(0);
1720
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1721
    tcg_temp_free(r_sign);
1722
    tcg_temp_free(r_size);
1723
    tcg_temp_free(r_asi);
1724
    tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1725
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1726
    tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1727
}
1728

    
1729
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1730
{
1731
    TCGv r_temp, r_asi, r_size;
1732

    
1733
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1734
    gen_movl_reg_TN(rd + 1, r_temp);
1735
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1736
                       r_temp);
1737
    tcg_temp_free(r_temp);
1738
    r_asi = gen_get_asi(insn, addr);
1739
    r_size = tcg_const_i32(8);
1740
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1741
    tcg_temp_free(r_size);
1742
    tcg_temp_free(r_asi);
1743
}
1744

    
1745
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1746
                               int rd)
1747
{
1748
    TCGv r_val1, r_asi;
1749

    
1750
    r_val1 = tcg_temp_new(TCG_TYPE_TL);
1751
    gen_movl_reg_TN(rd, r_val1);
1752
    r_asi = gen_get_asi(insn, addr);
1753
    tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1754
    tcg_temp_free(r_asi);
1755
    tcg_temp_free(r_val1);
1756
}
1757

    
1758
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1759
                                int rd)
1760
{
1761
    TCGv r_asi;
1762

    
1763
    gen_movl_reg_TN(rd, cpu_tmp64);
1764
    r_asi = gen_get_asi(insn, addr);
1765
    tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1766
    tcg_temp_free(r_asi);
1767
}
1768

    
1769
#elif !defined(CONFIG_USER_ONLY)
1770

    
1771
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1772
                              int sign)
1773
{
1774
    TCGv r_asi, r_size, r_sign;
1775

    
1776
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1777
    r_size = tcg_const_i32(size);
1778
    r_sign = tcg_const_i32(sign);
1779
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1780
    tcg_temp_free(r_sign);
1781
    tcg_temp_free(r_size);
1782
    tcg_temp_free(r_asi);
1783
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1784
}
1785

    
1786
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1787
{
1788
    TCGv r_asi, r_size;
1789

    
1790
    tcg_gen_extu_tl_i64(cpu_tmp64, src);
1791
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1792
    r_size = tcg_const_i32(size);
1793
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1794
    tcg_temp_free(r_size);
1795
    tcg_temp_free(r_asi);
1796
}
1797

    
1798
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1799
{
1800
    TCGv r_asi, r_size, r_sign;
1801

    
1802
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1803
    r_size = tcg_const_i32(4);
1804
    r_sign = tcg_const_i32(0);
1805
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1806
    tcg_temp_free(r_sign);
1807
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1808
    tcg_temp_free(r_size);
1809
    tcg_temp_free(r_asi);
1810
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1811
}
1812

    
1813
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1814
{
1815
    TCGv r_asi, r_size, r_sign;
1816

    
1817
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1818
    r_size = tcg_const_i32(8);
1819
    r_sign = tcg_const_i32(0);
1820
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1821
    tcg_temp_free(r_sign);
1822
    tcg_temp_free(r_size);
1823
    tcg_temp_free(r_asi);
1824
    tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1825
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1826
    tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1827
}
1828

    
1829
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1830
{
1831
    TCGv r_temp, r_asi, r_size;
1832

    
1833
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1834
    gen_movl_reg_TN(rd + 1, r_temp);
1835
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1836
    tcg_temp_free(r_temp);
1837
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1838
    r_size = tcg_const_i32(8);
1839
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1840
    tcg_temp_free(r_size);
1841
    tcg_temp_free(r_asi);
1842
}
1843
#endif
1844

    
1845
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1846
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1847
{
1848
    TCGv r_val, r_asi, r_size;
1849

    
1850
    gen_ld_asi(dst, addr, insn, 1, 0);
1851

    
1852
    r_val = tcg_const_i64(0xffULL);
1853
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1854
    r_size = tcg_const_i32(1);
1855
    tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1856
    tcg_temp_free(r_size);
1857
    tcg_temp_free(r_asi);
1858
    tcg_temp_free(r_val);
1859
}
1860
#endif
1861

    
1862
static inline TCGv get_src1(unsigned int insn, TCGv def)
1863
{
1864
    TCGv r_rs1 = def;
1865
    unsigned int rs1;
1866

    
1867
    rs1 = GET_FIELD(insn, 13, 17);
1868
    if (rs1 == 0)
1869
        //r_rs1 = tcg_const_tl(0);
1870
        tcg_gen_movi_tl(def, 0);
1871
    else if (rs1 < 8)
1872
        //r_rs1 = cpu_gregs[rs1];
1873
        tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1874
    else
1875
        tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1876
    return r_rs1;
1877
}
1878

    
1879
static inline TCGv get_src2(unsigned int insn, TCGv def)
1880
{
1881
    TCGv r_rs2 = def;
1882
    unsigned int rs2;
1883

    
1884
    if (IS_IMM) { /* immediate */
1885
        rs2 = GET_FIELDs(insn, 19, 31);
1886
        r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1887
    } else { /* register */
1888
        rs2 = GET_FIELD(insn, 27, 31);
1889
        if (rs2 == 0)
1890
            r_rs2 = tcg_const_tl(0); // XXX how to free?
1891
        else if (rs2 < 8)
1892
            r_rs2 = cpu_gregs[rs2];
1893
        else
1894
            tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1895
    }
1896
    return r_rs2;
1897
}
1898

    
1899
#define CHECK_IU_FEATURE(dc, FEATURE)                      \
1900
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1901
        goto illegal_insn;
1902
#define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1903
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1904
        goto nfpu_insn;
1905

    
1906
/* before an instruction, dc->pc must be static */
1907
static void disas_sparc_insn(DisasContext * dc)
1908
{
1909
    unsigned int insn, opc, rs1, rs2, rd;
1910

    
1911
    if (unlikely(loglevel & CPU_LOG_TB_OP))
1912
        tcg_gen_debug_insn_start(dc->pc);
1913
    insn = ldl_code(dc->pc);
1914
    opc = GET_FIELD(insn, 0, 1);
1915

    
1916
    rd = GET_FIELD(insn, 2, 6);
1917

    
1918
    cpu_dst = cpu_T[0];
1919
    cpu_src1 = cpu_T[0]; // const
1920
    cpu_src2 = cpu_T[1]; // const
1921

    
1922
    // loads and stores
1923
    cpu_addr = cpu_T[0];
1924
    cpu_val = cpu_T[1];
1925

    
1926
    switch (opc) {
1927
    case 0:                     /* branches/sethi */
1928
        {
1929
            unsigned int xop = GET_FIELD(insn, 7, 9);
1930
            int32_t target;
1931
            switch (xop) {
1932
#ifdef TARGET_SPARC64
1933
            case 0x1:           /* V9 BPcc */
1934
                {
1935
                    int cc;
1936

    
1937
                    target = GET_FIELD_SP(insn, 0, 18);
1938
                    target = sign_extend(target, 18);
1939
                    target <<= 2;
1940
                    cc = GET_FIELD_SP(insn, 20, 21);
1941
                    if (cc == 0)
1942
                        do_branch(dc, target, insn, 0, cpu_cond);
1943
                    else if (cc == 2)
1944
                        do_branch(dc, target, insn, 1, cpu_cond);
1945
                    else
1946
                        goto illegal_insn;
1947
                    goto jmp_insn;
1948
                }
1949
            case 0x3:           /* V9 BPr */
1950
                {
1951
                    target = GET_FIELD_SP(insn, 0, 13) |
1952
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1953
                    target = sign_extend(target, 16);
1954
                    target <<= 2;
1955
                    cpu_src1 = get_src1(insn, cpu_src1);
1956
                    do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1957
                    goto jmp_insn;
1958
                }
1959
            case 0x5:           /* V9 FBPcc */
1960
                {
1961
                    int cc = GET_FIELD_SP(insn, 20, 21);
1962
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1963
                        goto jmp_insn;
1964
                    target = GET_FIELD_SP(insn, 0, 18);
1965
                    target = sign_extend(target, 19);
1966
                    target <<= 2;
1967
                    do_fbranch(dc, target, insn, cc, cpu_cond);
1968
                    goto jmp_insn;
1969
                }
1970
#else
1971
            case 0x7:           /* CBN+x */
1972
                {
1973
                    goto ncp_insn;
1974
                }
1975
#endif
1976
            case 0x2:           /* BN+x */
1977
                {
1978
                    target = GET_FIELD(insn, 10, 31);
1979
                    target = sign_extend(target, 22);
1980
                    target <<= 2;
1981
                    do_branch(dc, target, insn, 0, cpu_cond);
1982
                    goto jmp_insn;
1983
                }
1984
            case 0x6:           /* FBN+x */
1985
                {
1986
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1987
                        goto jmp_insn;
1988
                    target = GET_FIELD(insn, 10, 31);
1989
                    target = sign_extend(target, 22);
1990
                    target <<= 2;
1991
                    do_fbranch(dc, target, insn, 0, cpu_cond);
1992
                    goto jmp_insn;
1993
                }
1994
            case 0x4:           /* SETHI */
1995
                if (rd) { // nop
1996
                    uint32_t value = GET_FIELD(insn, 10, 31);
1997
                    TCGv r_const;
1998

    
1999
                    r_const = tcg_const_tl(value << 10);
2000
                    gen_movl_TN_reg(rd, r_const);
2001
                    tcg_temp_free(r_const);
2002
                }
2003
                break;
2004
            case 0x0:           /* UNIMPL */
2005
            default:
2006
                goto illegal_insn;
2007
            }
2008
            break;
2009
        }
2010
        break;
2011
    case 1:
2012
        /*CALL*/ {
2013
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
2014
            TCGv r_const;
2015

    
2016
            r_const = tcg_const_tl(dc->pc);
2017
            gen_movl_TN_reg(15, r_const);
2018
            tcg_temp_free(r_const);
2019
            target += dc->pc;
2020
            gen_mov_pc_npc(dc, cpu_cond);
2021
            dc->npc = target;
2022
        }
2023
        goto jmp_insn;
2024
    case 2:                     /* FPU & Logical Operations */
2025
        {
2026
            unsigned int xop = GET_FIELD(insn, 7, 12);
2027
            if (xop == 0x3a) {  /* generate trap */
2028
                int cond;
2029

    
2030
                cpu_src1 = get_src1(insn, cpu_src1);
2031
                if (IS_IMM) {
2032
                    rs2 = GET_FIELD(insn, 25, 31);
2033
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2034
                } else {
2035
                    rs2 = GET_FIELD(insn, 27, 31);
2036
                    if (rs2 != 0) {
2037
                        gen_movl_reg_TN(rs2, cpu_src2);
2038
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2039
                    } else
2040
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
2041
                }
2042
                cond = GET_FIELD(insn, 3, 6);
2043
                if (cond == 0x8) {
2044
                    save_state(dc, cpu_cond);
2045
                    tcg_gen_helper_0_1(helper_trap, cpu_dst);
2046
                } else if (cond != 0) {
2047
                    TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2048
#ifdef TARGET_SPARC64
2049
                    /* V9 icc/xcc */
2050
                    int cc = GET_FIELD_SP(insn, 11, 12);
2051

    
2052
                    save_state(dc, cpu_cond);
2053
                    if (cc == 0)
2054
                        gen_cond(r_cond, 0, cond);
2055
                    else if (cc == 2)
2056
                        gen_cond(r_cond, 1, cond);
2057
                    else
2058
                        goto illegal_insn;
2059
#else
2060
                    save_state(dc, cpu_cond);
2061
                    gen_cond(r_cond, 0, cond);
2062
#endif
2063
                    tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2064
                    tcg_temp_free(r_cond);
2065
                }
2066
                gen_op_next_insn();
2067
                tcg_gen_exit_tb(0);
2068
                dc->is_br = 1;
2069
                goto jmp_insn;
2070
            } else if (xop == 0x28) {
2071
                rs1 = GET_FIELD(insn, 13, 17);
2072
                switch(rs1) {
2073
                case 0: /* rdy */
2074
#ifndef TARGET_SPARC64
2075
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
2076
                                       manual, rdy on the microSPARC
2077
                                       II */
2078
                case 0x0f:          /* stbar in the SPARCv8 manual,
2079
                                       rdy on the microSPARC II */
2080
                case 0x10 ... 0x1f: /* implementation-dependent in the
2081
                                       SPARCv8 manual, rdy on the
2082
                                       microSPARC II */
2083
#endif
2084
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2085
                                  offsetof(CPUSPARCState, y));
2086
                    gen_movl_TN_reg(rd, cpu_dst);
2087
                    break;
2088
#ifdef TARGET_SPARC64
2089
                case 0x2: /* V9 rdccr */
2090
                    tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2091
                    gen_movl_TN_reg(rd, cpu_dst);
2092
                    break;
2093
                case 0x3: /* V9 rdasi */
2094
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2095
                                   offsetof(CPUSPARCState, asi));
2096
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2097
                    gen_movl_TN_reg(rd, cpu_dst);
2098
                    break;
2099
                case 0x4: /* V9 rdtick */
2100
                    {
2101
                        TCGv r_tickptr;
2102

    
2103
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2104
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2105
                                       offsetof(CPUState, tick));
2106
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2107
                                           r_tickptr);
2108
                        tcg_temp_free(r_tickptr);
2109
                        gen_movl_TN_reg(rd, cpu_dst);
2110
                    }
2111
                    break;
2112
                case 0x5: /* V9 rdpc */
2113
                    {
2114
                        TCGv r_const;
2115

    
2116
                        r_const = tcg_const_tl(dc->pc);
2117
                        gen_movl_TN_reg(rd, r_const);
2118
                        tcg_temp_free(r_const);
2119
                    }
2120
                    break;
2121
                case 0x6: /* V9 rdfprs */
2122
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2123
                                   offsetof(CPUSPARCState, fprs));
2124
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2125
                    gen_movl_TN_reg(rd, cpu_dst);
2126
                    break;
2127
                case 0xf: /* V9 membar */
2128
                    break; /* no effect */
2129
                case 0x13: /* Graphics Status */
2130
                    if (gen_trap_ifnofpu(dc, cpu_cond))
2131
                        goto jmp_insn;
2132
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2133
                                  offsetof(CPUSPARCState, gsr));
2134
                    gen_movl_TN_reg(rd, cpu_dst);
2135
                    break;
2136
                case 0x17: /* Tick compare */
2137
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2138
                                  offsetof(CPUSPARCState, tick_cmpr));
2139
                    gen_movl_TN_reg(rd, cpu_dst);
2140
                    break;
2141
                case 0x18: /* System tick */
2142
                    {
2143
                        TCGv r_tickptr;
2144

    
2145
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2146
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2147
                                       offsetof(CPUState, stick));
2148
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2149
                                           r_tickptr);
2150
                        tcg_temp_free(r_tickptr);
2151
                        gen_movl_TN_reg(rd, cpu_dst);
2152
                    }
2153
                    break;
2154
                case 0x19: /* System tick compare */
2155
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2156
                                  offsetof(CPUSPARCState, stick_cmpr));
2157
                    gen_movl_TN_reg(rd, cpu_dst);
2158
                    break;
2159
                case 0x10: /* Performance Control */
2160
                case 0x11: /* Performance Instrumentation Counter */
2161
                case 0x12: /* Dispatch Control */
2162
                case 0x14: /* Softint set, WO */
2163
                case 0x15: /* Softint clear, WO */
2164
                case 0x16: /* Softint write */
2165
#endif
2166
                default:
2167
                    goto illegal_insn;
2168
                }
2169
#if !defined(CONFIG_USER_ONLY)
2170
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2171
#ifndef TARGET_SPARC64
2172
                if (!supervisor(dc))
2173
                    goto priv_insn;
2174
                tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2175
#else
2176
                if (!hypervisor(dc))
2177
                    goto priv_insn;
2178
                rs1 = GET_FIELD(insn, 13, 17);
2179
                switch (rs1) {
2180
                case 0: // hpstate
2181
                    // gen_op_rdhpstate();
2182
                    break;
2183
                case 1: // htstate
2184
                    // gen_op_rdhtstate();
2185
                    break;
2186
                case 3: // hintp
2187
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2188
                                   offsetof(CPUSPARCState, hintp));
2189
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2190
                    break;
2191
                case 5: // htba
2192
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2193
                                   offsetof(CPUSPARCState, htba));
2194
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2195
                    break;
2196
                case 6: // hver
2197
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2198
                                   offsetof(CPUSPARCState, hver));
2199
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2200
                    break;
2201
                case 31: // hstick_cmpr
2202
                    tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2203
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
2204
                                   offsetof(CPUSPARCState, hstick_cmpr));
2205
                    break;
2206
                default:
2207
                    goto illegal_insn;
2208
                }
2209
#endif
2210
                gen_movl_TN_reg(rd, cpu_dst);
2211
                break;
2212
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2213
                if (!supervisor(dc))
2214
                    goto priv_insn;
2215
#ifdef TARGET_SPARC64
2216
                rs1 = GET_FIELD(insn, 13, 17);
2217
                switch (rs1) {
2218
                case 0: // tpc
2219
                    {
2220
                        TCGv r_tsptr;
2221

    
2222
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2223
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2224
                                       offsetof(CPUState, tsptr));
2225
                        tcg_gen_ld_tl(cpu_dst, r_tsptr,
2226
                                      offsetof(trap_state, tpc));
2227
                        tcg_temp_free(r_tsptr);
2228
                    }
2229
                    break;
2230
                case 1: // tnpc
2231
                    {
2232
                        TCGv r_tsptr;
2233

    
2234
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2235
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2236
                                       offsetof(CPUState, tsptr));
2237
                        tcg_gen_ld_tl(cpu_dst, r_tsptr,
2238
                                      offsetof(trap_state, tnpc));
2239
                        tcg_temp_free(r_tsptr);
2240
                    }
2241
                    break;
2242
                case 2: // tstate
2243
                    {
2244
                        TCGv r_tsptr;
2245

    
2246
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2247
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2248
                                       offsetof(CPUState, tsptr));
2249
                        tcg_gen_ld_tl(cpu_dst, r_tsptr,
2250
                                      offsetof(trap_state, tstate));
2251
                        tcg_temp_free(r_tsptr);
2252
                    }
2253
                    break;
2254
                case 3: // tt
2255
                    {
2256
                        TCGv r_tsptr;
2257

    
2258
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2259
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2260
                                       offsetof(CPUState, tsptr));
2261
                        tcg_gen_ld_i32(cpu_dst, r_tsptr,
2262
                                       offsetof(trap_state, tt));
2263
                        tcg_temp_free(r_tsptr);
2264
                    }
2265
                    break;
2266
                case 4: // tick
2267
                    {
2268
                        TCGv r_tickptr;
2269

    
2270
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2271
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2272
                                       offsetof(CPUState, tick));
2273
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2274
                                           r_tickptr);
2275
                        gen_movl_TN_reg(rd, cpu_dst);
2276
                        tcg_temp_free(r_tickptr);
2277
                    }
2278
                    break;
2279
                case 5: // tba
2280
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2281
                                  offsetof(CPUSPARCState, tbr));
2282
                    break;
2283
                case 6: // pstate
2284
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2285
                                   offsetof(CPUSPARCState, pstate));
2286
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2287
                    break;
2288
                case 7: // tl
2289
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2290
                                   offsetof(CPUSPARCState, tl));
2291
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2292
                    break;
2293
                case 8: // pil
2294
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295
                                   offsetof(CPUSPARCState, psrpil));
2296
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2297
                    break;
2298
                case 9: // cwp
2299
                    tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2300
                    break;
2301
                case 10: // cansave
2302
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2303
                                   offsetof(CPUSPARCState, cansave));
2304
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2305
                    break;
2306
                case 11: // canrestore
2307
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2308
                                   offsetof(CPUSPARCState, canrestore));
2309
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2310
                    break;
2311
                case 12: // cleanwin
2312
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2313
                                   offsetof(CPUSPARCState, cleanwin));
2314
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2315
                    break;
2316
                case 13: // otherwin
2317
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2318
                                   offsetof(CPUSPARCState, otherwin));
2319
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2320
                    break;
2321
                case 14: // wstate
2322
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2323
                                   offsetof(CPUSPARCState, wstate));
2324
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2325
                    break;
2326
                case 16: // UA2005 gl
2327
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2328
                                   offsetof(CPUSPARCState, gl));
2329
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2330
                    break;
2331
                case 26: // UA2005 strand status
2332
                    if (!hypervisor(dc))
2333
                        goto priv_insn;
2334
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2335
                                   offsetof(CPUSPARCState, ssr));
2336
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2337
                    break;
2338
                case 31: // ver
2339
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2340
                                  offsetof(CPUSPARCState, version));
2341
                    break;
2342
                case 15: // fq
2343
                default:
2344
                    goto illegal_insn;
2345
                }
2346
#else
2347
                tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2348
                               offsetof(CPUSPARCState, wim));
2349
                tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2350
#endif
2351
                gen_movl_TN_reg(rd, cpu_dst);
2352
                break;
2353
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2354
#ifdef TARGET_SPARC64
2355
                tcg_gen_helper_0_0(helper_flushw);
2356
#else
2357
                if (!supervisor(dc))
2358
                    goto priv_insn;
2359
                tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2360
                gen_movl_TN_reg(rd, cpu_dst);
2361
#endif
2362
                break;
2363
#endif
2364
            } else if (xop == 0x34) {   /* FPU Operations */
2365
                if (gen_trap_ifnofpu(dc, cpu_cond))
2366
                    goto jmp_insn;
2367
                gen_op_clear_ieee_excp_and_FTT();
2368
                rs1 = GET_FIELD(insn, 13, 17);
2369
                rs2 = GET_FIELD(insn, 27, 31);
2370
                xop = GET_FIELD(insn, 18, 26);
2371
                switch (xop) {
2372
                    case 0x1: /* fmovs */
2373
                        gen_op_load_fpr_FT0(rs2);
2374
                        gen_op_store_FT0_fpr(rd);
2375
                        break;
2376
                    case 0x5: /* fnegs */
2377
                        gen_op_load_fpr_FT1(rs2);
2378
                        tcg_gen_helper_0_0(helper_fnegs);
2379
                        gen_op_store_FT0_fpr(rd);
2380
                        break;
2381
                    case 0x9: /* fabss */
2382
                        gen_op_load_fpr_FT1(rs2);
2383
                        tcg_gen_helper_0_0(helper_fabss);
2384
                        gen_op_store_FT0_fpr(rd);
2385
                        break;
2386
                    case 0x29: /* fsqrts */
2387
                        CHECK_FPU_FEATURE(dc, FSQRT);
2388
                        gen_op_load_fpr_FT1(rs2);
2389
                        gen_clear_float_exceptions();
2390
                        tcg_gen_helper_0_0(helper_fsqrts);
2391
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2392
                        gen_op_store_FT0_fpr(rd);
2393
                        break;
2394
                    case 0x2a: /* fsqrtd */
2395
                        CHECK_FPU_FEATURE(dc, FSQRT);
2396
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2397
                        gen_clear_float_exceptions();
2398
                        tcg_gen_helper_0_0(helper_fsqrtd);
2399
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2400
                        gen_op_store_DT0_fpr(DFPREG(rd));
2401
                        break;
2402
                    case 0x2b: /* fsqrtq */
2403
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2404
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2405
                        gen_clear_float_exceptions();
2406
                        tcg_gen_helper_0_0(helper_fsqrtq);
2407
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2408
                        gen_op_store_QT0_fpr(QFPREG(rd));
2409
                        break;
2410
                    case 0x41:
2411
                        gen_op_load_fpr_FT0(rs1);
2412
                        gen_op_load_fpr_FT1(rs2);
2413
                        gen_clear_float_exceptions();
2414
                        tcg_gen_helper_0_0(helper_fadds);
2415
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2416
                        gen_op_store_FT0_fpr(rd);
2417
                        break;
2418
                    case 0x42:
2419
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2420
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2421
                        gen_clear_float_exceptions();
2422
                        tcg_gen_helper_0_0(helper_faddd);
2423
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2424
                        gen_op_store_DT0_fpr(DFPREG(rd));
2425
                        break;
2426
                    case 0x43: /* faddq */
2427
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2428
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2429
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2430
                        gen_clear_float_exceptions();
2431
                        tcg_gen_helper_0_0(helper_faddq);
2432
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2433
                        gen_op_store_QT0_fpr(QFPREG(rd));
2434
                        break;
2435
                    case 0x45:
2436
                        gen_op_load_fpr_FT0(rs1);
2437
                        gen_op_load_fpr_FT1(rs2);
2438
                        gen_clear_float_exceptions();
2439
                        tcg_gen_helper_0_0(helper_fsubs);
2440
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2441
                        gen_op_store_FT0_fpr(rd);
2442
                        break;
2443
                    case 0x46:
2444
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2445
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2446
                        gen_clear_float_exceptions();
2447
                        tcg_gen_helper_0_0(helper_fsubd);
2448
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2449
                        gen_op_store_DT0_fpr(DFPREG(rd));
2450
                        break;
2451
                    case 0x47: /* fsubq */
2452
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2453
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2454
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2455
                        gen_clear_float_exceptions();
2456
                        tcg_gen_helper_0_0(helper_fsubq);
2457
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2458
                        gen_op_store_QT0_fpr(QFPREG(rd));
2459
                        break;
2460
                    case 0x49: /* fmuls */
2461
                        CHECK_FPU_FEATURE(dc, FMUL);
2462
                        gen_op_load_fpr_FT0(rs1);
2463
                        gen_op_load_fpr_FT1(rs2);
2464
                        gen_clear_float_exceptions();
2465
                        tcg_gen_helper_0_0(helper_fmuls);
2466
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2467
                        gen_op_store_FT0_fpr(rd);
2468
                        break;
2469
                    case 0x4a: /* fmuld */
2470
                        CHECK_FPU_FEATURE(dc, FMUL);
2471
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2472
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2473
                        gen_clear_float_exceptions();
2474
                        tcg_gen_helper_0_0(helper_fmuld);
2475
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2476
                        gen_op_store_DT0_fpr(DFPREG(rd));
2477
                        break;
2478
                    case 0x4b: /* fmulq */
2479
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2480
                        CHECK_FPU_FEATURE(dc, FMUL);
2481
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2482
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2483
                        gen_clear_float_exceptions();
2484
                        tcg_gen_helper_0_0(helper_fmulq);
2485
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2486
                        gen_op_store_QT0_fpr(QFPREG(rd));
2487
                        break;
2488
                    case 0x4d:
2489
                        gen_op_load_fpr_FT0(rs1);
2490
                        gen_op_load_fpr_FT1(rs2);
2491
                        gen_clear_float_exceptions();
2492
                        tcg_gen_helper_0_0(helper_fdivs);
2493
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2494
                        gen_op_store_FT0_fpr(rd);
2495
                        break;
2496
                    case 0x4e:
2497
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2498
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2499
                        gen_clear_float_exceptions();
2500
                        tcg_gen_helper_0_0(helper_fdivd);
2501
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2502
                        gen_op_store_DT0_fpr(DFPREG(rd));
2503
                        break;
2504
                    case 0x4f: /* fdivq */
2505
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2506
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2507
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2508
                        gen_clear_float_exceptions();
2509
                        tcg_gen_helper_0_0(helper_fdivq);
2510
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2511
                        gen_op_store_QT0_fpr(QFPREG(rd));
2512
                        break;
2513
                    case 0x69:
2514
                        CHECK_FPU_FEATURE(dc, FSMULD);
2515
                        gen_op_load_fpr_FT0(rs1);
2516
                        gen_op_load_fpr_FT1(rs2);
2517
                        gen_clear_float_exceptions();
2518
                        tcg_gen_helper_0_0(helper_fsmuld);
2519
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2520
                        gen_op_store_DT0_fpr(DFPREG(rd));
2521
                        break;
2522
                    case 0x6e: /* fdmulq */
2523
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2524
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2525
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2526
                        gen_clear_float_exceptions();
2527
                        tcg_gen_helper_0_0(helper_fdmulq);
2528
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2529
                        gen_op_store_QT0_fpr(QFPREG(rd));
2530
                        break;
2531
                    case 0xc4:
2532
                        gen_op_load_fpr_FT1(rs2);
2533
                        gen_clear_float_exceptions();
2534
                        tcg_gen_helper_0_0(helper_fitos);
2535
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2536
                        gen_op_store_FT0_fpr(rd);
2537
                        break;
2538
                    case 0xc6:
2539
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2540
                        gen_clear_float_exceptions();
2541
                        tcg_gen_helper_0_0(helper_fdtos);
2542
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2543
                        gen_op_store_FT0_fpr(rd);
2544
                        break;
2545
                    case 0xc7: /* fqtos */
2546
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2547
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2548
                        gen_clear_float_exceptions();
2549
                        tcg_gen_helper_0_0(helper_fqtos);
2550
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2551
                        gen_op_store_FT0_fpr(rd);
2552
                        break;
2553
                    case 0xc8:
2554
                        gen_op_load_fpr_FT1(rs2);
2555
                        tcg_gen_helper_0_0(helper_fitod);
2556
                        gen_op_store_DT0_fpr(DFPREG(rd));
2557
                        break;
2558
                    case 0xc9:
2559
                        gen_op_load_fpr_FT1(rs2);
2560
                        tcg_gen_helper_0_0(helper_fstod);
2561
                        gen_op_store_DT0_fpr(DFPREG(rd));
2562
                        break;
2563
                    case 0xcb: /* fqtod */
2564
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2565
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2566
                        gen_clear_float_exceptions();
2567
                        tcg_gen_helper_0_0(helper_fqtod);
2568
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2569
                        gen_op_store_DT0_fpr(DFPREG(rd));
2570
                        break;
2571
                    case 0xcc: /* fitoq */
2572
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2573
                        gen_op_load_fpr_FT1(rs2);
2574
                        tcg_gen_helper_0_0(helper_fitoq);
2575
                        gen_op_store_QT0_fpr(QFPREG(rd));
2576
                        break;
2577
                    case 0xcd: /* fstoq */
2578
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2579
                        gen_op_load_fpr_FT1(rs2);
2580
                        tcg_gen_helper_0_0(helper_fstoq);
2581
                        gen_op_store_QT0_fpr(QFPREG(rd));
2582
                        break;
2583
                    case 0xce: /* fdtoq */
2584
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2585
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2586
                        tcg_gen_helper_0_0(helper_fdtoq);
2587
                        gen_op_store_QT0_fpr(QFPREG(rd));
2588
                        break;
2589
                    case 0xd1:
2590
                        gen_op_load_fpr_FT1(rs2);
2591
                        gen_clear_float_exceptions();
2592
                        tcg_gen_helper_0_0(helper_fstoi);
2593
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2594
                        gen_op_store_FT0_fpr(rd);
2595
                        break;
2596
                    case 0xd2:
2597
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2598
                        gen_clear_float_exceptions();
2599
                        tcg_gen_helper_0_0(helper_fdtoi);
2600
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2601
                        gen_op_store_FT0_fpr(rd);
2602
                        break;
2603
                    case 0xd3: /* fqtoi */
2604
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2605
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2606
                        gen_clear_float_exceptions();
2607
                        tcg_gen_helper_0_0(helper_fqtoi);
2608
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2609
                        gen_op_store_FT0_fpr(rd);
2610
                        break;
2611
#ifdef TARGET_SPARC64
2612
                    case 0x2: /* V9 fmovd */
2613
                        gen_op_load_fpr_DT0(DFPREG(rs2));
2614
                        gen_op_store_DT0_fpr(DFPREG(rd));
2615
                        break;
2616
                    case 0x3: /* V9 fmovq */
2617
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2618
                        gen_op_load_fpr_QT0(QFPREG(rs2));
2619
                        gen_op_store_QT0_fpr(QFPREG(rd));
2620
                        break;
2621
                    case 0x6: /* V9 fnegd */
2622
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2623
                        tcg_gen_helper_0_0(helper_fnegd);
2624
                        gen_op_store_DT0_fpr(DFPREG(rd));
2625
                        break;
2626
                    case 0x7: /* V9 fnegq */
2627
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2628
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2629
                        tcg_gen_helper_0_0(helper_fnegq);
2630
                        gen_op_store_QT0_fpr(QFPREG(rd));
2631
                        break;
2632
                    case 0xa: /* V9 fabsd */
2633
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2634
                        tcg_gen_helper_0_0(helper_fabsd);
2635
                        gen_op_store_DT0_fpr(DFPREG(rd));
2636
                        break;
2637
                    case 0xb: /* V9 fabsq */
2638
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2639
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2640
                        tcg_gen_helper_0_0(helper_fabsq);
2641
                        gen_op_store_QT0_fpr(QFPREG(rd));
2642
                        break;
2643
                    case 0x81: /* V9 fstox */
2644
                        gen_op_load_fpr_FT1(rs2);
2645
                        gen_clear_float_exceptions();
2646
                        tcg_gen_helper_0_0(helper_fstox);
2647
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2648
                        gen_op_store_DT0_fpr(DFPREG(rd));
2649
                        break;
2650
                    case 0x82: /* V9 fdtox */
2651
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2652
                        gen_clear_float_exceptions();
2653
                        tcg_gen_helper_0_0(helper_fdtox);
2654
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2655
                        gen_op_store_DT0_fpr(DFPREG(rd));
2656
                        break;
2657
                    case 0x83: /* V9 fqtox */
2658
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2659
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2660
                        gen_clear_float_exceptions();
2661
                        tcg_gen_helper_0_0(helper_fqtox);
2662
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2663
                        gen_op_store_DT0_fpr(DFPREG(rd));
2664
                        break;
2665
                    case 0x84: /* V9 fxtos */
2666
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2667
                        gen_clear_float_exceptions();
2668
                        tcg_gen_helper_0_0(helper_fxtos);
2669
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2670
                        gen_op_store_FT0_fpr(rd);
2671
                        break;
2672
                    case 0x88: /* V9 fxtod */
2673
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2674
                        gen_clear_float_exceptions();
2675
                        tcg_gen_helper_0_0(helper_fxtod);
2676
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2677
                        gen_op_store_DT0_fpr(DFPREG(rd));
2678
                        break;
2679
                    case 0x8c: /* V9 fxtoq */
2680
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2681
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2682
                        gen_clear_float_exceptions();
2683
                        tcg_gen_helper_0_0(helper_fxtoq);
2684
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2685
                        gen_op_store_QT0_fpr(QFPREG(rd));
2686
                        break;
2687
#endif
2688
                    default:
2689
                        goto illegal_insn;
2690
                }
2691
            } else if (xop == 0x35) {   /* FPU Operations */
2692
#ifdef TARGET_SPARC64
2693
                int cond;
2694
#endif
2695
                if (gen_trap_ifnofpu(dc, cpu_cond))
2696
                    goto jmp_insn;
2697
                gen_op_clear_ieee_excp_and_FTT();
2698
                rs1 = GET_FIELD(insn, 13, 17);
2699
                rs2 = GET_FIELD(insn, 27, 31);
2700
                xop = GET_FIELD(insn, 18, 26);
2701
#ifdef TARGET_SPARC64
2702
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2703
                    int l1;
2704

    
2705
                    l1 = gen_new_label();
2706
                    cond = GET_FIELD_SP(insn, 14, 17);
2707
                    cpu_src1 = get_src1(insn, cpu_src1);
2708
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2709
                                       0, l1);
2710
                    gen_op_load_fpr_FT0(rs2);
2711
                    gen_op_store_FT0_fpr(rd);
2712
                    gen_set_label(l1);
2713
                    break;
2714
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2715
                    int l1;
2716

    
2717
                    l1 = gen_new_label();
2718
                    cond = GET_FIELD_SP(insn, 14, 17);
2719
                    cpu_src1 = get_src1(insn, cpu_src1);
2720
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2721
                                       0, l1);
2722
                    gen_op_load_fpr_DT0(DFPREG(rs2));
2723
                    gen_op_store_DT0_fpr(DFPREG(rd));
2724
                    gen_set_label(l1);
2725
                    break;
2726
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2727
                    int l1;
2728

    
2729
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2730
                    l1 = gen_new_label();
2731
                    cond = GET_FIELD_SP(insn, 14, 17);
2732
                    cpu_src1 = get_src1(insn, cpu_src1);
2733
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2734
                                       0, l1);
2735
                    gen_op_load_fpr_QT0(QFPREG(rs2));
2736
                    gen_op_store_QT0_fpr(QFPREG(rd));
2737
                    gen_set_label(l1);
2738
                    break;
2739
                }
2740
#endif
2741
                switch (xop) {
2742
#ifdef TARGET_SPARC64
2743
#define FMOVCC(size_FDQ, fcc)                                           \
2744
                    {                                                   \
2745
                        TCGv r_cond;                                    \
2746
                        int l1;                                         \
2747
                                                                        \
2748
                        l1 = gen_new_label();                           \
2749
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2750
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2751
                        gen_fcond(r_cond, fcc, cond);                   \
2752
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2753
                                           0, l1);                      \
2754
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2755
                            (glue(size_FDQ, FPREG(rs2)));               \
2756
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2757
                            (glue(size_FDQ, FPREG(rd)));                \
2758
                        gen_set_label(l1);                              \
2759
                        tcg_temp_free(r_cond);                          \
2760
                    }
2761
                    case 0x001: /* V9 fmovscc %fcc0 */
2762
                        FMOVCC(F, 0);
2763
                        break;
2764
                    case 0x002: /* V9 fmovdcc %fcc0 */
2765
                        FMOVCC(D, 0);
2766
                        break;
2767
                    case 0x003: /* V9 fmovqcc %fcc0 */
2768
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2769
                        FMOVCC(Q, 0);
2770
                        break;
2771
                    case 0x041: /* V9 fmovscc %fcc1 */
2772
                        FMOVCC(F, 1);
2773
                        break;
2774
                    case 0x042: /* V9 fmovdcc %fcc1 */
2775
                        FMOVCC(D, 1);
2776
                        break;
2777
                    case 0x043: /* V9 fmovqcc %fcc1 */
2778
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2779
                        FMOVCC(Q, 1);
2780
                        break;
2781
                    case 0x081: /* V9 fmovscc %fcc2 */
2782
                        FMOVCC(F, 2);
2783
                        break;
2784
                    case 0x082: /* V9 fmovdcc %fcc2 */
2785
                        FMOVCC(D, 2);
2786
                        break;
2787
                    case 0x083: /* V9 fmovqcc %fcc2 */
2788
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2789
                        FMOVCC(Q, 2);
2790
                        break;
2791
                    case 0x0c1: /* V9 fmovscc %fcc3 */
2792
                        FMOVCC(F, 3);
2793
                        break;
2794
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
2795
                        FMOVCC(D, 3);
2796
                        break;
2797
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
2798
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2799
                        FMOVCC(Q, 3);
2800
                        break;
2801
#undef FMOVCC
2802
#define FMOVCC(size_FDQ, icc)                                           \
2803
                    {                                                   \
2804
                        TCGv r_cond;                                    \
2805
                        int l1;                                         \
2806
                                                                        \
2807
                        l1 = gen_new_label();                           \
2808
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2809
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2810
                        gen_cond(r_cond, icc, cond);                    \
2811
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2812
                                           0, l1);                      \
2813
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2814
                            (glue(size_FDQ, FPREG(rs2)));               \
2815
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2816
                            (glue(size_FDQ, FPREG(rd)));                \
2817
                        gen_set_label(l1);                              \
2818
                        tcg_temp_free(r_cond);                          \
2819
                    }
2820

    
2821
                    case 0x101: /* V9 fmovscc %icc */
2822
                        FMOVCC(F, 0);
2823
                        break;
2824
                    case 0x102: /* V9 fmovdcc %icc */
2825
                        FMOVCC(D, 0);
2826
                    case 0x103: /* V9 fmovqcc %icc */
2827
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2828
                        FMOVCC(Q, 0);
2829
                        break;
2830
                    case 0x181: /* V9 fmovscc %xcc */
2831
                        FMOVCC(F, 1);
2832
                        break;
2833
                    case 0x182: /* V9 fmovdcc %xcc */
2834
                        FMOVCC(D, 1);
2835
                        break;
2836
                    case 0x183: /* V9 fmovqcc %xcc */
2837
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2838
                        FMOVCC(Q, 1);
2839
                        break;
2840
#undef FMOVCC
2841
#endif
2842
                    case 0x51: /* fcmps, V9 %fcc */
2843
                        gen_op_load_fpr_FT0(rs1);
2844
                        gen_op_load_fpr_FT1(rs2);
2845
                        gen_op_fcmps(rd & 3);
2846
                        break;
2847
                    case 0x52: /* fcmpd, V9 %fcc */
2848
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2849
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2850
                        gen_op_fcmpd(rd & 3);
2851
                        break;
2852
                    case 0x53: /* fcmpq, V9 %fcc */
2853
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2854
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2855
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2856
                        gen_op_fcmpq(rd & 3);
2857
                        break;
2858
                    case 0x55: /* fcmpes, V9 %fcc */
2859
                        gen_op_load_fpr_FT0(rs1);
2860
                        gen_op_load_fpr_FT1(rs2);
2861
                        gen_op_fcmpes(rd & 3);
2862
                        break;
2863
                    case 0x56: /* fcmped, V9 %fcc */
2864
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2865
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2866
                        gen_op_fcmped(rd & 3);
2867
                        break;
2868
                    case 0x57: /* fcmpeq, V9 %fcc */
2869
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2870
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2871
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2872
                        gen_op_fcmpeq(rd & 3);
2873
                        break;
2874
                    default:
2875
                        goto illegal_insn;
2876
                }
2877
            } else if (xop == 0x2) {
2878
                // clr/mov shortcut
2879

    
2880
                rs1 = GET_FIELD(insn, 13, 17);
2881
                if (rs1 == 0) {
2882
                    // or %g0, x, y -> mov T0, x; mov y, T0
2883
                    if (IS_IMM) {       /* immediate */
2884
                        TCGv r_const;
2885

    
2886
                        rs2 = GET_FIELDs(insn, 19, 31);
2887
                        r_const = tcg_const_tl((int)rs2);
2888
                        gen_movl_TN_reg(rd, r_const);
2889
                        tcg_temp_free(r_const);
2890
                    } else {            /* register */
2891
                        rs2 = GET_FIELD(insn, 27, 31);
2892
                        gen_movl_reg_TN(rs2, cpu_dst);
2893
                        gen_movl_TN_reg(rd, cpu_dst);
2894
                    }
2895
                } else {
2896
                    cpu_src1 = get_src1(insn, cpu_src1);
2897
                    if (IS_IMM) {       /* immediate */
2898
                        rs2 = GET_FIELDs(insn, 19, 31);
2899
                        tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2900
                        gen_movl_TN_reg(rd, cpu_dst);
2901
                    } else {            /* register */
2902
                        // or x, %g0, y -> mov T1, x; mov y, T1
2903
                        rs2 = GET_FIELD(insn, 27, 31);
2904
                        if (rs2 != 0) {
2905
                            gen_movl_reg_TN(rs2, cpu_src2);
2906
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2907
                            gen_movl_TN_reg(rd, cpu_dst);
2908
                        } else
2909
                            gen_movl_TN_reg(rd, cpu_src1);
2910
                    }
2911
                }
2912
#ifdef TARGET_SPARC64
2913
            } else if (xop == 0x25) { /* sll, V9 sllx */
2914
                cpu_src1 = get_src1(insn, cpu_src1);
2915
                if (IS_IMM) {   /* immediate */
2916
                    rs2 = GET_FIELDs(insn, 20, 31);
2917
                    if (insn & (1 << 12)) {
2918
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2919
                    } else {
2920
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2921
                        tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2922
                    }
2923
                } else {                /* register */
2924
                    rs2 = GET_FIELD(insn, 27, 31);
2925
                    gen_movl_reg_TN(rs2, cpu_src2);
2926
                    if (insn & (1 << 12)) {
2927
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2928
                        tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2929
                    } else {
2930
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2931
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2932
                        tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2933
                    }
2934
                }
2935
                gen_movl_TN_reg(rd, cpu_dst);
2936
            } else if (xop == 0x26) { /* srl, V9 srlx */
2937
                cpu_src1 = get_src1(insn, cpu_src1);
2938
                if (IS_IMM) {   /* immediate */
2939
                    rs2 = GET_FIELDs(insn, 20, 31);
2940
                    if (insn & (1 << 12)) {
2941
                        tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2942
                    } else {
2943
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2944
                        tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2945
                    }
2946
                } else {                /* register */
2947
                    rs2 = GET_FIELD(insn, 27, 31);
2948
                    gen_movl_reg_TN(rs2, cpu_src2);
2949
                    if (insn & (1 << 12)) {
2950
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2951
                        tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2952
                    } else {
2953
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2954
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2955
                        tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2956
                    }
2957
                }
2958
                gen_movl_TN_reg(rd, cpu_dst);
2959
            } else if (xop == 0x27) { /* sra, V9 srax */
2960
                cpu_src1 = get_src1(insn, cpu_src1);
2961
                if (IS_IMM) {   /* immediate */
2962
                    rs2 = GET_FIELDs(insn, 20, 31);
2963
                    if (insn & (1 << 12)) {
2964
                        tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2965
                    } else {
2966
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2967
                        tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2968
                        tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2969
                    }
2970
                } else {                /* register */
2971
                    rs2 = GET_FIELD(insn, 27, 31);
2972
                    gen_movl_reg_TN(rs2, cpu_src2);
2973
                    if (insn & (1 << 12)) {
2974
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2975
                        tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2976
                    } else {
2977
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2978
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2979
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2980
                    }
2981
                }
2982
                gen_movl_TN_reg(rd, cpu_dst);
2983
#endif
2984
            } else if (xop < 0x36) {
2985
                cpu_src1 = get_src1(insn, cpu_src1);
2986
                cpu_src2 = get_src2(insn, cpu_src2);
2987
                if (xop < 0x20) {
2988
                    switch (xop & ~0x10) {
2989
                    case 0x0:
2990
                        if (xop & 0x10)
2991
                            gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2992
                        else
2993
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2994
                        break;
2995
                    case 0x1:
2996
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2997
                        if (xop & 0x10)
2998
                            gen_op_logic_cc(cpu_dst);
2999
                        break;
3000
                    case 0x2:
3001
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3002
                        if (xop & 0x10)
3003
                            gen_op_logic_cc(cpu_dst);
3004
                        break;
3005
                    case 0x3:
3006
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3007
                        if (xop & 0x10)
3008
                            gen_op_logic_cc(cpu_dst);
3009
                        break;
3010
                    case 0x4:
3011
                        if (xop & 0x10)
3012
                            gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3013
                        else
3014
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3015
                        break;
3016
                    case 0x5:
3017
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3018
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3019
                        if (xop & 0x10)
3020
                            gen_op_logic_cc(cpu_dst);
3021
                        break;
3022
                    case 0x6:
3023
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3025
                        if (xop & 0x10)
3026
                            gen_op_logic_cc(cpu_dst);
3027
                        break;
3028
                    case 0x7:
3029
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3030
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3031
                        if (xop & 0x10)
3032
                            gen_op_logic_cc(cpu_dst);
3033
                        break;
3034
                    case 0x8:
3035
                        if (xop & 0x10)
3036
                            gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3037
                        else {
3038
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3039
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3040
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3041
                        }
3042
                        break;
3043
#ifdef TARGET_SPARC64
3044
                    case 0x9: /* V9 mulx */
3045
                        tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3046
                        break;
3047
#endif
3048
                    case 0xa:
3049
                        CHECK_IU_FEATURE(dc, MUL);
3050
                        gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3051
                        if (xop & 0x10)
3052
                            gen_op_logic_cc(cpu_dst);
3053
                        break;
3054
                    case 0xb:
3055
                        CHECK_IU_FEATURE(dc, MUL);
3056
                        gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3057
                        if (xop & 0x10)
3058
                            gen_op_logic_cc(cpu_dst);
3059
                        break;
3060
                    case 0xc:
3061
                        if (xop & 0x10)
3062
                            gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3063
                        else {
3064
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3065
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3066
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3067
                        }
3068
                        break;
3069
#ifdef TARGET_SPARC64
3070
                    case 0xd: /* V9 udivx */
3071
                        gen_trap_ifdivzero_tl(cpu_src2);
3072
                        tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
3073
                        break;
3074
#endif
3075
                    case 0xe:
3076
                        CHECK_IU_FEATURE(dc, DIV);
3077
                        tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3078
                                           cpu_src2);
3079
                        if (xop & 0x10)
3080
                            gen_op_div_cc(cpu_dst);
3081
                        break;
3082
                    case 0xf:
3083
                        CHECK_IU_FEATURE(dc, DIV);
3084
                        tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3085
                                           cpu_src2);
3086
                        if (xop & 0x10)
3087
                            gen_op_div_cc(cpu_dst);
3088
                        break;
3089
                    default:
3090
                        goto illegal_insn;
3091
                    }
3092
                    gen_movl_TN_reg(rd, cpu_dst);
3093
                } else {
3094
                    switch (xop) {
3095
                    case 0x20: /* taddcc */
3096
                        gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3097
                        gen_movl_TN_reg(rd, cpu_dst);
3098
                        break;
3099
                    case 0x21: /* tsubcc */
3100
                        gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3101
                        gen_movl_TN_reg(rd, cpu_dst);
3102
                        break;
3103
                    case 0x22: /* taddcctv */
3104
                        save_state(dc, cpu_cond);
3105
                        gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3106
                        gen_movl_TN_reg(rd, cpu_dst);
3107
                        break;
3108
                    case 0x23: /* tsubcctv */
3109
                        save_state(dc, cpu_cond);
3110
                        gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3111
                        gen_movl_TN_reg(rd, cpu_dst);
3112
                        break;
3113
                    case 0x24: /* mulscc */
3114
                        gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3115
                        gen_movl_TN_reg(rd, cpu_dst);
3116
                        break;
3117
#ifndef TARGET_SPARC64
3118
                    case 0x25:  /* sll */
3119
                        if (IS_IMM) { /* immediate */
3120
                            rs2 = GET_FIELDs(insn, 20, 31);
3121
                            tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3122
                        } else { /* register */
3123
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3124
                            tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3125
                        }
3126
                        gen_movl_TN_reg(rd, cpu_dst);
3127
                        break;
3128
                    case 0x26:  /* srl */
3129
                        if (IS_IMM) { /* immediate */
3130
                            rs2 = GET_FIELDs(insn, 20, 31);
3131
                            tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3132
                        } else { /* register */
3133
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3134
                            tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3135
                        }
3136
                        gen_movl_TN_reg(rd, cpu_dst);
3137
                        break;
3138
                    case 0x27:  /* sra */
3139
                        if (IS_IMM) { /* immediate */
3140
                            rs2 = GET_FIELDs(insn, 20, 31);
3141
                            tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3142
                        } else { /* register */
3143
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3144
                            tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3145
                        }
3146
                        gen_movl_TN_reg(rd, cpu_dst);
3147
                        break;
3148
#endif
3149
                    case 0x30:
3150
                        {
3151
                            switch(rd) {
3152
                            case 0: /* wry */
3153
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3154
                                tcg_gen_st_tl(cpu_dst, cpu_env,
3155
                                              offsetof(CPUSPARCState, y));
3156
                                break;
3157
#ifndef TARGET_SPARC64
3158
                            case 0x01 ... 0x0f: /* undefined in the
3159
                                                   SPARCv8 manual, nop
3160
                                                   on the microSPARC
3161
                                                   II */
3162
                            case 0x10 ... 0x1f: /* implementation-dependent
3163
                                                   in the SPARCv8
3164
                                                   manual, nop on the
3165
                                                   microSPARC II */
3166
                                break;
3167
#else
3168
                            case 0x2: /* V9 wrccr */
3169
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3170
                                tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3171
                                break;
3172
                            case 0x3: /* V9 wrasi */
3173
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3174
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3175
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3176
                                               offsetof(CPUSPARCState, asi));
3177
                                break;
3178
                            case 0x6: /* V9 wrfprs */
3179
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3180
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3181
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3182
                                               offsetof(CPUSPARCState, fprs));
3183
                                save_state(dc, cpu_cond);
3184
                                gen_op_next_insn();
3185
                                tcg_gen_exit_tb(0);
3186
                                dc->is_br = 1;
3187
                                break;
3188
                            case 0xf: /* V9 sir, nop if user */
3189
#if !defined(CONFIG_USER_ONLY)
3190
                                if (supervisor(dc))
3191
                                    ; // XXX
3192
#endif
3193
                                break;
3194
                            case 0x13: /* Graphics Status */
3195
                                if (gen_trap_ifnofpu(dc, cpu_cond))
3196
                                    goto jmp_insn;
3197
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3198
                                tcg_gen_st_tl(cpu_dst, cpu_env,
3199
                                              offsetof(CPUSPARCState, gsr));
3200
                                break;
3201
                            case 0x17: /* Tick compare */
3202
#if !defined(CONFIG_USER_ONLY)
3203
                                if (!supervisor(dc))
3204
                                    goto illegal_insn;
3205
#endif
3206
                                {
3207
                                    TCGv r_tickptr;
3208

    
3209
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3210
                                                   cpu_src2);
3211
                                    tcg_gen_st_tl(cpu_dst, cpu_env,
3212
                                                  offsetof(CPUSPARCState,
3213
                                                           tick_cmpr));
3214
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3215
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3216
                                                   offsetof(CPUState, tick));
3217
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3218
                                                       r_tickptr, cpu_dst);
3219
                                    tcg_temp_free(r_tickptr);
3220
                                }
3221
                                break;
3222
                            case 0x18: /* System tick */
3223
#if !defined(CONFIG_USER_ONLY)
3224
                                if (!supervisor(dc))
3225
                                    goto illegal_insn;
3226
#endif
3227
                                {
3228
                                    TCGv r_tickptr;
3229

    
3230
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3231
                                                   cpu_src2);
3232
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3233
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3234
                                                   offsetof(CPUState, stick));
3235
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3236
                                                       r_tickptr, cpu_dst);
3237
                                    tcg_temp_free(r_tickptr);
3238
                                }
3239
                                break;
3240
                            case 0x19: /* System tick compare */
3241
#if !defined(CONFIG_USER_ONLY)
3242
                                if (!supervisor(dc))
3243
                                    goto illegal_insn;
3244
#endif
3245
                                {
3246
                                    TCGv r_tickptr;
3247

    
3248
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3249
                                                   cpu_src2);
3250
                                    tcg_gen_st_tl(cpu_dst, cpu_env,
3251
                                                  offsetof(CPUSPARCState,
3252
                                                           stick_cmpr));
3253
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3254
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3255
                                                   offsetof(CPUState, stick));
3256
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3257
                                                       r_tickptr, cpu_dst);
3258
                                    tcg_temp_free(r_tickptr);
3259
                                }
3260
                                break;
3261

    
3262
                            case 0x10: /* Performance Control */
3263
                            case 0x11: /* Performance Instrumentation
3264
                                          Counter */
3265
                            case 0x12: /* Dispatch Control */
3266
                            case 0x14: /* Softint set */
3267
                            case 0x15: /* Softint clear */
3268
                            case 0x16: /* Softint write */
3269
#endif
3270
                            default:
3271
                                goto illegal_insn;
3272
                            }
3273
                        }
3274
                        break;
3275
#if !defined(CONFIG_USER_ONLY)
3276
                    case 0x31: /* wrpsr, V9 saved, restored */
3277
                        {
3278
                            if (!supervisor(dc))
3279
                                goto priv_insn;
3280
#ifdef TARGET_SPARC64
3281
                            switch (rd) {
3282
                            case 0:
3283
                                tcg_gen_helper_0_0(helper_saved);
3284
                                break;
3285
                            case 1:
3286
                                tcg_gen_helper_0_0(helper_restored);
3287
                                break;
3288
                            case 2: /* UA2005 allclean */
3289
                            case 3: /* UA2005 otherw */
3290
                            case 4: /* UA2005 normalw */
3291
                            case 5: /* UA2005 invalw */
3292
                                // XXX
3293
                            default:
3294
                                goto illegal_insn;
3295
                            }
3296
#else
3297
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3298
                            tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3299
                            save_state(dc, cpu_cond);
3300
                            gen_op_next_insn();
3301
                            tcg_gen_exit_tb(0);
3302
                            dc->is_br = 1;
3303
#endif
3304
                        }
3305
                        break;
3306
                    case 0x32: /* wrwim, V9 wrpr */
3307
                        {
3308
                            if (!supervisor(dc))
3309
                                goto priv_insn;
3310
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3311
#ifdef TARGET_SPARC64
3312
                            switch (rd) {
3313
                            case 0: // tpc
3314
                                {
3315
                                    TCGv r_tsptr;
3316

    
3317
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3318
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3319
                                                   offsetof(CPUState, tsptr));
3320
                                    tcg_gen_st_tl(cpu_dst, r_tsptr,
3321
                                                  offsetof(trap_state, tpc));
3322
                                    tcg_temp_free(r_tsptr);
3323
                                }
3324
                                break;
3325
                            case 1: // tnpc
3326
                                {
3327
                                    TCGv r_tsptr;
3328

    
3329
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3330
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3331
                                                   offsetof(CPUState, tsptr));
3332
                                    tcg_gen_st_tl(cpu_dst, r_tsptr,
3333
                                                  offsetof(trap_state, tnpc));
3334
                                    tcg_temp_free(r_tsptr);
3335
                                }
3336
                                break;
3337
                            case 2: // tstate
3338
                                {
3339
                                    TCGv r_tsptr;
3340

    
3341
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3342
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3343
                                                   offsetof(CPUState, tsptr));
3344
                                    tcg_gen_st_tl(cpu_dst, r_tsptr,
3345
                                                  offsetof(trap_state,
3346
                                                           tstate));
3347
                                    tcg_temp_free(r_tsptr);
3348
                                }
3349
                                break;
3350
                            case 3: // tt
3351
                                {
3352
                                    TCGv r_tsptr;
3353

    
3354
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3355
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3356
                                                   offsetof(CPUState, tsptr));
3357
                                    tcg_gen_st_i32(cpu_dst, r_tsptr,
3358
                                                   offsetof(trap_state, tt));
3359
                                    tcg_temp_free(r_tsptr);
3360
                                }
3361
                                break;
3362
                            case 4: // tick
3363
                                {
3364
                                    TCGv r_tickptr;
3365

    
3366
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3367
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3368
                                                   offsetof(CPUState, tick));
3369
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3370
                                                       r_tickptr, cpu_dst);
3371
                                    tcg_temp_free(r_tickptr);
3372
                                }
3373
                                break;
3374
                            case 5: // tba
3375
                                tcg_gen_st_tl(cpu_dst, cpu_env,
3376
                                              offsetof(CPUSPARCState, tbr));
3377
                                break;
3378
                            case 6: // pstate
3379
                                save_state(dc, cpu_cond);
3380
                                tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3381
                                gen_op_next_insn();
3382
                                tcg_gen_exit_tb(0);
3383
                                dc->is_br = 1;
3384
                                break;
3385
                            case 7: // tl
3386
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3387
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3388
                                               offsetof(CPUSPARCState, tl));
3389
                                break;
3390
                            case 8: // pil
3391
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3392
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3393
                                               offsetof(CPUSPARCState,
3394
                                                        psrpil));
3395
                                break;
3396
                            case 9: // cwp
3397
                                tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3398
                                break;
3399
                            case 10: // cansave
3400
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3401
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3402
                                               offsetof(CPUSPARCState,
3403
                                                        cansave));
3404
                                break;
3405
                            case 11: // canrestore
3406
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3407
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3408
                                               offsetof(CPUSPARCState,
3409
                                                        canrestore));
3410
                                break;
3411
                            case 12: // cleanwin
3412
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3413
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3414
                                               offsetof(CPUSPARCState,
3415
                                                        cleanwin));
3416
                                break;
3417
                            case 13: // otherwin
3418
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3419
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3420
                                               offsetof(CPUSPARCState,
3421
                                                        otherwin));
3422
                                break;
3423
                            case 14: // wstate
3424
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3425
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3426
                                               offsetof(CPUSPARCState,
3427
                                                        wstate));
3428
                                break;
3429
                            case 16: // UA2005 gl
3430
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3431
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3432
                                               offsetof(CPUSPARCState, gl));
3433
                                break;
3434
                            case 26: // UA2005 strand status
3435
                                if (!hypervisor(dc))
3436
                                    goto priv_insn;
3437
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3438
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3439
                                               offsetof(CPUSPARCState, ssr));
3440
                                break;
3441
                            default:
3442
                                goto illegal_insn;
3443
                            }
3444
#else
3445
                            tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3446
                            tcg_gen_st_i32(cpu_tmp32, cpu_env,
3447
                                           offsetof(CPUSPARCState, wim));
3448
#endif
3449
                        }
3450
                        break;
3451
                    case 0x33: /* wrtbr, UA2005 wrhpr */
3452
                        {
3453
#ifndef TARGET_SPARC64
3454
                            if (!supervisor(dc))
3455
                                goto priv_insn;
3456
                            tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3457
                            tcg_gen_st_tl(cpu_dst, cpu_env,
3458
                                          offsetof(CPUSPARCState, tbr));
3459
#else
3460
                            if (!hypervisor(dc))
3461
                                goto priv_insn;
3462
                            tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3463
                            switch (rd) {
3464
                            case 0: // hpstate
3465
                                // XXX gen_op_wrhpstate();
3466
                                save_state(dc, cpu_cond);
3467
                                gen_op_next_insn();
3468
                                tcg_gen_exit_tb(0);
3469
                                dc->is_br = 1;
3470
                                break;
3471
                            case 1: // htstate
3472
                                // XXX gen_op_wrhtstate();
3473
                                break;
3474
                            case 3: // hintp
3475
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3476
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3477
                                               offsetof(CPUSPARCState, hintp));
3478
                                break;
3479
                            case 5: // htba
3480
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3481
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3482
                                               offsetof(CPUSPARCState, htba));
3483
                                break;
3484
                            case 31: // hstick_cmpr
3485
                                {
3486
                                    TCGv r_tickptr;
3487

    
3488
                                    tcg_gen_st_tl(cpu_dst, cpu_env,
3489
                                                  offsetof(CPUSPARCState,
3490
                                                           hstick_cmpr));
3491
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3492
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3493
                                                   offsetof(CPUState, hstick));
3494
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3495
                                                       r_tickptr, cpu_dst);
3496
                                    tcg_temp_free(r_tickptr);
3497
                                }
3498
                                break;
3499
                            case 6: // hver readonly
3500
                            default:
3501
                                goto illegal_insn;
3502
                            }
3503
#endif
3504
                        }
3505
                        break;
3506
#endif
3507
#ifdef TARGET_SPARC64
3508
                    case 0x2c: /* V9 movcc */
3509
                        {
3510
                            int cc = GET_FIELD_SP(insn, 11, 12);
3511
                            int cond = GET_FIELD_SP(insn, 14, 17);
3512
                            TCGv r_cond;
3513
                            int l1;
3514

    
3515
                            r_cond = tcg_temp_new(TCG_TYPE_TL);
3516
                            if (insn & (1 << 18)) {
3517
                                if (cc == 0)
3518
                                    gen_cond(r_cond, 0, cond);
3519
                                else if (cc == 2)
3520
                                    gen_cond(r_cond, 1, cond);
3521
                                else
3522
                                    goto illegal_insn;
3523
                            } else {
3524
                                gen_fcond(r_cond, cc, cond);
3525
                            }
3526

    
3527
                            l1 = gen_new_label();
3528

    
3529
                            tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3530
                            if (IS_IMM) {       /* immediate */
3531
                                TCGv r_const;
3532

    
3533
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
3534
                                r_const = tcg_const_tl((int)rs2);
3535
                                gen_movl_TN_reg(rd, r_const);
3536
                                tcg_temp_free(r_const);
3537
                            } else {
3538
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3539
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3540
                                gen_movl_TN_reg(rd, cpu_tmp0);
3541
                            }
3542
                            gen_set_label(l1);
3543
                            tcg_temp_free(r_cond);
3544
                            break;
3545
                        }
3546
                    case 0x2d: /* V9 sdivx */
3547
                        gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3548
                        gen_movl_TN_reg(rd, cpu_dst);
3549
                        break;
3550
                    case 0x2e: /* V9 popc */
3551
                        {
3552
                            cpu_src2 = get_src2(insn, cpu_src2);
3553
                            tcg_gen_helper_1_1(helper_popc, cpu_dst,
3554
                                               cpu_src2);
3555
                            gen_movl_TN_reg(rd, cpu_dst);
3556
                        }
3557
                    case 0x2f: /* V9 movr */
3558
                        {
3559
                            int cond = GET_FIELD_SP(insn, 10, 12);
3560
                            int l1;
3561

    
3562
                            cpu_src1 = get_src1(insn, cpu_src1);
3563

    
3564
                            l1 = gen_new_label();
3565

    
3566
                            tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3567
                                              cpu_src1, 0, l1);
3568
                            if (IS_IMM) {       /* immediate */
3569
                                TCGv r_const;
3570

    
3571
                                rs2 = GET_FIELD_SPs(insn, 0, 9);
3572
                                r_const = tcg_const_tl((int)rs2);
3573
                                gen_movl_TN_reg(rd, r_const);
3574
                                tcg_temp_free(r_const);
3575
                            } else {
3576
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3577
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3578
                                gen_movl_TN_reg(rd, cpu_tmp0);
3579
                            }
3580
                            gen_set_label(l1);
3581
                            break;
3582
                        }
3583
#endif
3584
                    default:
3585
                        goto illegal_insn;
3586
                    }
3587
                }
3588
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3589
#ifdef TARGET_SPARC64
3590
                int opf = GET_FIELD_SP(insn, 5, 13);
3591
                rs1 = GET_FIELD(insn, 13, 17);
3592
                rs2 = GET_FIELD(insn, 27, 31);
3593
                if (gen_trap_ifnofpu(dc, cpu_cond))
3594
                    goto jmp_insn;
3595

    
3596
                switch (opf) {
3597
                case 0x000: /* VIS I edge8cc */
3598
                case 0x001: /* VIS II edge8n */
3599
                case 0x002: /* VIS I edge8lcc */
3600
                case 0x003: /* VIS II edge8ln */
3601
                case 0x004: /* VIS I edge16cc */
3602
                case 0x005: /* VIS II edge16n */
3603
                case 0x006: /* VIS I edge16lcc */
3604
                case 0x007: /* VIS II edge16ln */
3605
                case 0x008: /* VIS I edge32cc */
3606
                case 0x009: /* VIS II edge32n */
3607
                case 0x00a: /* VIS I edge32lcc */
3608
                case 0x00b: /* VIS II edge32ln */
3609
                    // XXX
3610
                    goto illegal_insn;
3611
                case 0x010: /* VIS I array8 */
3612
                    CHECK_FPU_FEATURE(dc, VIS1);
3613
                    cpu_src1 = get_src1(insn, cpu_src1);
3614
                    gen_movl_reg_TN(rs2, cpu_src2);
3615
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3616
                                       cpu_src2);
3617
                    gen_movl_TN_reg(rd, cpu_dst);
3618
                    break;
3619
                case 0x012: /* VIS I array16 */
3620
                    CHECK_FPU_FEATURE(dc, VIS1);
3621
                    cpu_src1 = get_src1(insn, cpu_src1);
3622
                    gen_movl_reg_TN(rs2, cpu_src2);
3623
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3624
                                       cpu_src2);
3625
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3626
                    gen_movl_TN_reg(rd, cpu_dst);
3627
                    break;
3628
                case 0x014: /* VIS I array32 */
3629
                    CHECK_FPU_FEATURE(dc, VIS1);
3630
                    cpu_src1 = get_src1(insn, cpu_src1);
3631
                    gen_movl_reg_TN(rs2, cpu_src2);
3632
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3633
                                       cpu_src2);
3634
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3635
                    gen_movl_TN_reg(rd, cpu_dst);
3636
                    break;
3637
                case 0x018: /* VIS I alignaddr */
3638
                    CHECK_FPU_FEATURE(dc, VIS1);
3639
                    cpu_src1 = get_src1(insn, cpu_src1);
3640
                    gen_movl_reg_TN(rs2, cpu_src2);
3641
                    tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3642
                                       cpu_src2);
3643
                    gen_movl_TN_reg(rd, cpu_dst);
3644
                    break;
3645
                case 0x019: /* VIS II bmask */
3646
                case 0x01a: /* VIS I alignaddrl */
3647
                    // XXX
3648
                    goto illegal_insn;
3649
                case 0x020: /* VIS I fcmple16 */
3650
                    CHECK_FPU_FEATURE(dc, VIS1);
3651
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3652
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3653
                    tcg_gen_helper_0_0(helper_fcmple16);
3654
                    gen_op_store_DT0_fpr(DFPREG(rd));
3655
                    break;
3656
                case 0x022: /* VIS I fcmpne16 */
3657
                    CHECK_FPU_FEATURE(dc, VIS1);
3658
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3659
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3660
                    tcg_gen_helper_0_0(helper_fcmpne16);
3661
                    gen_op_store_DT0_fpr(DFPREG(rd));
3662
                    break;
3663
                case 0x024: /* VIS I fcmple32 */
3664
                    CHECK_FPU_FEATURE(dc, VIS1);
3665
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3666
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3667
                    tcg_gen_helper_0_0(helper_fcmple32);
3668
                    gen_op_store_DT0_fpr(DFPREG(rd));
3669
                    break;
3670
                case 0x026: /* VIS I fcmpne32 */
3671
                    CHECK_FPU_FEATURE(dc, VIS1);
3672
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3673
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3674
                    tcg_gen_helper_0_0(helper_fcmpne32);
3675
                    gen_op_store_DT0_fpr(DFPREG(rd));
3676
                    break;
3677
                case 0x028: /* VIS I fcmpgt16 */
3678
                    CHECK_FPU_FEATURE(dc, VIS1);
3679
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3680
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3681
                    tcg_gen_helper_0_0(helper_fcmpgt16);
3682
                    gen_op_store_DT0_fpr(DFPREG(rd));
3683
                    break;
3684
                case 0x02a: /* VIS I fcmpeq16 */
3685
                    CHECK_FPU_FEATURE(dc, VIS1);
3686
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3687
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3688
                    tcg_gen_helper_0_0(helper_fcmpeq16);
3689
                    gen_op_store_DT0_fpr(DFPREG(rd));
3690
                    break;
3691
                case 0x02c: /* VIS I fcmpgt32 */
3692
                    CHECK_FPU_FEATURE(dc, VIS1);
3693
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3694
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3695
                    tcg_gen_helper_0_0(helper_fcmpgt32);
3696
                    gen_op_store_DT0_fpr(DFPREG(rd));
3697
                    break;
3698
                case 0x02e: /* VIS I fcmpeq32 */
3699
                    CHECK_FPU_FEATURE(dc, VIS1);
3700
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3701
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3702
                    tcg_gen_helper_0_0(helper_fcmpeq32);
3703
                    gen_op_store_DT0_fpr(DFPREG(rd));
3704
                    break;
3705
                case 0x031: /* VIS I fmul8x16 */
3706
                    CHECK_FPU_FEATURE(dc, VIS1);
3707
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3708
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3709
                    tcg_gen_helper_0_0(helper_fmul8x16);
3710
                    gen_op_store_DT0_fpr(DFPREG(rd));
3711
                    break;
3712
                case 0x033: /* VIS I fmul8x16au */
3713
                    CHECK_FPU_FEATURE(dc, VIS1);
3714
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3715
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3716
                    tcg_gen_helper_0_0(helper_fmul8x16au);
3717
                    gen_op_store_DT0_fpr(DFPREG(rd));
3718
                    break;
3719
                case 0x035: /* VIS I fmul8x16al */
3720
                    CHECK_FPU_FEATURE(dc, VIS1);
3721
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3722
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3723
                    tcg_gen_helper_0_0(helper_fmul8x16al);
3724
                    gen_op_store_DT0_fpr(DFPREG(rd));
3725
                    break;
3726
                case 0x036: /* VIS I fmul8sux16 */
3727
                    CHECK_FPU_FEATURE(dc, VIS1);
3728
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3729
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3730
                    tcg_gen_helper_0_0(helper_fmul8sux16);
3731
                    gen_op_store_DT0_fpr(DFPREG(rd));
3732
                    break;
3733
                case 0x037: /* VIS I fmul8ulx16 */
3734
                    CHECK_FPU_FEATURE(dc, VIS1);
3735
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3736
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3737
                    tcg_gen_helper_0_0(helper_fmul8ulx16);
3738
                    gen_op_store_DT0_fpr(DFPREG(rd));
3739
                    break;
3740
                case 0x038: /* VIS I fmuld8sux16 */
3741
                    CHECK_FPU_FEATURE(dc, VIS1);
3742
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3743
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3744
                    tcg_gen_helper_0_0(helper_fmuld8sux16);
3745
                    gen_op_store_DT0_fpr(DFPREG(rd));
3746
                    break;
3747
                case 0x039: /* VIS I fmuld8ulx16 */
3748
                    CHECK_FPU_FEATURE(dc, VIS1);
3749
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3750
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3751
                    tcg_gen_helper_0_0(helper_fmuld8ulx16);
3752
                    gen_op_store_DT0_fpr(DFPREG(rd));
3753
                    break;
3754
                case 0x03a: /* VIS I fpack32 */
3755
                case 0x03b: /* VIS I fpack16 */
3756
                case 0x03d: /* VIS I fpackfix */
3757
                case 0x03e: /* VIS I pdist */
3758
                    // XXX
3759
                    goto illegal_insn;
3760
                case 0x048: /* VIS I faligndata */
3761
                    CHECK_FPU_FEATURE(dc, VIS1);
3762
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3763
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3764
                    tcg_gen_helper_0_0(helper_faligndata);
3765
                    gen_op_store_DT0_fpr(DFPREG(rd));
3766
                    break;
3767
                case 0x04b: /* VIS I fpmerge */
3768
                    CHECK_FPU_FEATURE(dc, VIS1);
3769
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3770
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3771
                    tcg_gen_helper_0_0(helper_fpmerge);
3772
                    gen_op_store_DT0_fpr(DFPREG(rd));
3773
                    break;
3774
                case 0x04c: /* VIS II bshuffle */
3775
                    // XXX
3776
                    goto illegal_insn;
3777
                case 0x04d: /* VIS I fexpand */
3778
                    CHECK_FPU_FEATURE(dc, VIS1);
3779
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3780
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3781
                    tcg_gen_helper_0_0(helper_fexpand);
3782
                    gen_op_store_DT0_fpr(DFPREG(rd));
3783
                    break;
3784
                case 0x050: /* VIS I fpadd16 */
3785
                    CHECK_FPU_FEATURE(dc, VIS1);
3786
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3787
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3788
                    tcg_gen_helper_0_0(helper_fpadd16);
3789
                    gen_op_store_DT0_fpr(DFPREG(rd));
3790
                    break;
3791
                case 0x051: /* VIS I fpadd16s */
3792
                    CHECK_FPU_FEATURE(dc, VIS1);
3793
                    gen_op_load_fpr_FT0(rs1);
3794
                    gen_op_load_fpr_FT1(rs2);
3795
                    tcg_gen_helper_0_0(helper_fpadd16s);
3796
                    gen_op_store_FT0_fpr(rd);
3797
                    break;
3798
                case 0x052: /* VIS I fpadd32 */
3799
                    CHECK_FPU_FEATURE(dc, VIS1);
3800
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3801
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3802
                    tcg_gen_helper_0_0(helper_fpadd32);
3803
                    gen_op_store_DT0_fpr(DFPREG(rd));
3804
                    break;
3805
                case 0x053: /* VIS I fpadd32s */
3806
                    CHECK_FPU_FEATURE(dc, VIS1);
3807
                    gen_op_load_fpr_FT0(rs1);
3808
                    gen_op_load_fpr_FT1(rs2);
3809
                    tcg_gen_helper_0_0(helper_fpadd32s);
3810
                    gen_op_store_FT0_fpr(rd);
3811
                    break;
3812
                case 0x054: /* VIS I fpsub16 */
3813
                    CHECK_FPU_FEATURE(dc, VIS1);
3814
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3815
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3816
                    tcg_gen_helper_0_0(helper_fpsub16);
3817
                    gen_op_store_DT0_fpr(DFPREG(rd));
3818
                    break;
3819
                case 0x055: /* VIS I fpsub16s */
3820
                    CHECK_FPU_FEATURE(dc, VIS1);
3821
                    gen_op_load_fpr_FT0(rs1);
3822
                    gen_op_load_fpr_FT1(rs2);
3823
                    tcg_gen_helper_0_0(helper_fpsub16s);
3824
                    gen_op_store_FT0_fpr(rd);
3825
                    break;
3826
                case 0x056: /* VIS I fpsub32 */
3827
                    CHECK_FPU_FEATURE(dc, VIS1);
3828
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3829
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3830
                    tcg_gen_helper_0_0(helper_fpadd32);
3831
                    gen_op_store_DT0_fpr(DFPREG(rd));
3832
                    break;
3833
                case 0x057: /* VIS I fpsub32s */
3834
                    CHECK_FPU_FEATURE(dc, VIS1);
3835
                    gen_op_load_fpr_FT0(rs1);
3836
                    gen_op_load_fpr_FT1(rs2);
3837
                    tcg_gen_helper_0_0(helper_fpsub32s);
3838
                    gen_op_store_FT0_fpr(rd);
3839
                    break;
3840
                case 0x060: /* VIS I fzero */
3841
                    CHECK_FPU_FEATURE(dc, VIS1);
3842
                    tcg_gen_helper_0_0(helper_movl_DT0_0);
3843
                    gen_op_store_DT0_fpr(DFPREG(rd));
3844
                    break;
3845
                case 0x061: /* VIS I fzeros */
3846
                    CHECK_FPU_FEATURE(dc, VIS1);
3847
                    tcg_gen_helper_0_0(helper_movl_FT0_0);
3848
                    gen_op_store_FT0_fpr(rd);
3849
                    break;
3850
                case 0x062: /* VIS I fnor */
3851
                    CHECK_FPU_FEATURE(dc, VIS1);
3852
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3853
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3854
                    tcg_gen_helper_0_0(helper_fnor);
3855
                    gen_op_store_DT0_fpr(DFPREG(rd));
3856
                    break;
3857
                case 0x063: /* VIS I fnors */
3858
                    CHECK_FPU_FEATURE(dc, VIS1);
3859
                    gen_op_load_fpr_FT0(rs1);
3860
                    gen_op_load_fpr_FT1(rs2);
3861
                    tcg_gen_helper_0_0(helper_fnors);
3862
                    gen_op_store_FT0_fpr(rd);
3863
                    break;
3864
                case 0x064: /* VIS I fandnot2 */
3865
                    CHECK_FPU_FEATURE(dc, VIS1);
3866
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3867
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3868
                    tcg_gen_helper_0_0(helper_fandnot);
3869
                    gen_op_store_DT0_fpr(DFPREG(rd));
3870
                    break;
3871
                case 0x065: /* VIS I fandnot2s */
3872
                    CHECK_FPU_FEATURE(dc, VIS1);
3873
                    gen_op_load_fpr_FT1(rs1);
3874
                    gen_op_load_fpr_FT0(rs2);
3875
                    tcg_gen_helper_0_0(helper_fandnots);
3876
                    gen_op_store_FT0_fpr(rd);
3877
                    break;
3878
                case 0x066: /* VIS I fnot2 */
3879
                    CHECK_FPU_FEATURE(dc, VIS1);
3880
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3881
                    tcg_gen_helper_0_0(helper_fnot);
3882
                    gen_op_store_DT0_fpr(DFPREG(rd));
3883
                    break;
3884
                case 0x067: /* VIS I fnot2s */
3885
                    CHECK_FPU_FEATURE(dc, VIS1);
3886
                    gen_op_load_fpr_FT1(rs2);
3887
                    tcg_gen_helper_0_0(helper_fnot);
3888
                    gen_op_store_FT0_fpr(rd);
3889
                    break;
3890
                case 0x068: /* VIS I fandnot1 */
3891
                    CHECK_FPU_FEATURE(dc, VIS1);
3892
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3893
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3894
                    tcg_gen_helper_0_0(helper_fandnot);
3895
                    gen_op_store_DT0_fpr(DFPREG(rd));
3896
                    break;
3897
                case 0x069: /* VIS I fandnot1s */
3898
                    CHECK_FPU_FEATURE(dc, VIS1);
3899
                    gen_op_load_fpr_FT0(rs1);
3900
                    gen_op_load_fpr_FT1(rs2);
3901
                    tcg_gen_helper_0_0(helper_fandnots);
3902
                    gen_op_store_FT0_fpr(rd);
3903
                    break;
3904
                case 0x06a: /* VIS I fnot1 */
3905
                    CHECK_FPU_FEATURE(dc, VIS1);
3906
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3907
                    tcg_gen_helper_0_0(helper_fnot);
3908
                    gen_op_store_DT0_fpr(DFPREG(rd));
3909
                    break;
3910
                case 0x06b: /* VIS I fnot1s */
3911
                    CHECK_FPU_FEATURE(dc, VIS1);
3912
                    gen_op_load_fpr_FT1(rs1);
3913
                    tcg_gen_helper_0_0(helper_fnot);
3914
                    gen_op_store_FT0_fpr(rd);
3915
                    break;
3916
                case 0x06c: /* VIS I fxor */
3917
                    CHECK_FPU_FEATURE(dc, VIS1);
3918
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3919
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3920
                    tcg_gen_helper_0_0(helper_fxor);
3921
                    gen_op_store_DT0_fpr(DFPREG(rd));
3922
                    break;
3923
                case 0x06d: /* VIS I fxors */
3924
                    CHECK_FPU_FEATURE(dc, VIS1);
3925
                    gen_op_load_fpr_FT0(rs1);
3926
                    gen_op_load_fpr_FT1(rs2);
3927
                    tcg_gen_helper_0_0(helper_fxors);
3928
                    gen_op_store_FT0_fpr(rd);
3929
                    break;
3930
                case 0x06e: /* VIS I fnand */
3931
                    CHECK_FPU_FEATURE(dc, VIS1);
3932
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3933
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3934
                    tcg_gen_helper_0_0(helper_fnand);
3935
                    gen_op_store_DT0_fpr(DFPREG(rd));
3936
                    break;
3937
                case 0x06f: /* VIS I fnands */
3938
                    CHECK_FPU_FEATURE(dc, VIS1);
3939
                    gen_op_load_fpr_FT0(rs1);
3940
                    gen_op_load_fpr_FT1(rs2);
3941
                    tcg_gen_helper_0_0(helper_fnands);
3942
                    gen_op_store_FT0_fpr(rd);
3943
                    break;
3944
                case 0x070: /* VIS I fand */
3945
                    CHECK_FPU_FEATURE(dc, VIS1);
3946
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3947
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3948
                    tcg_gen_helper_0_0(helper_fand);
3949
                    gen_op_store_DT0_fpr(DFPREG(rd));
3950
                    break;
3951
                case 0x071: /* VIS I fands */
3952
                    CHECK_FPU_FEATURE(dc, VIS1);
3953
                    gen_op_load_fpr_FT0(rs1);
3954
                    gen_op_load_fpr_FT1(rs2);
3955
                    tcg_gen_helper_0_0(helper_fands);
3956
                    gen_op_store_FT0_fpr(rd);
3957
                    break;
3958
                case 0x072: /* VIS I fxnor */
3959
                    CHECK_FPU_FEATURE(dc, VIS1);
3960
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3961
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3962
                    tcg_gen_helper_0_0(helper_fxnor);
3963
                    gen_op_store_DT0_fpr(DFPREG(rd));
3964
                    break;
3965
                case 0x073: /* VIS I fxnors */
3966
                    CHECK_FPU_FEATURE(dc, VIS1);
3967
                    gen_op_load_fpr_FT0(rs1);
3968
                    gen_op_load_fpr_FT1(rs2);
3969
                    tcg_gen_helper_0_0(helper_fxnors);
3970
                    gen_op_store_FT0_fpr(rd);
3971
                    break;
3972
                case 0x074: /* VIS I fsrc1 */
3973
                    CHECK_FPU_FEATURE(dc, VIS1);
3974
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3975
                    gen_op_store_DT0_fpr(DFPREG(rd));
3976
                    break;
3977
                case 0x075: /* VIS I fsrc1s */
3978
                    CHECK_FPU_FEATURE(dc, VIS1);
3979
                    gen_op_load_fpr_FT0(rs1);
3980
                    gen_op_store_FT0_fpr(rd);
3981
                    break;
3982
                case 0x076: /* VIS I fornot2 */
3983
                    CHECK_FPU_FEATURE(dc, VIS1);
3984
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3985
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3986
                    tcg_gen_helper_0_0(helper_fornot);
3987
                    gen_op_store_DT0_fpr(DFPREG(rd));
3988
                    break;
3989
                case 0x077: /* VIS I fornot2s */
3990
                    CHECK_FPU_FEATURE(dc, VIS1);
3991
                    gen_op_load_fpr_FT1(rs1);
3992
                    gen_op_load_fpr_FT0(rs2);
3993
                    tcg_gen_helper_0_0(helper_fornots);
3994
                    gen_op_store_FT0_fpr(rd);
3995
                    break;
3996
                case 0x078: /* VIS I fsrc2 */
3997
                    CHECK_FPU_FEATURE(dc, VIS1);
3998
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3999
                    gen_op_store_DT0_fpr(DFPREG(rd));
4000
                    break;
4001
                case 0x079: /* VIS I fsrc2s */
4002
                    CHECK_FPU_FEATURE(dc, VIS1);
4003
                    gen_op_load_fpr_FT0(rs2);
4004
                    gen_op_store_FT0_fpr(rd);
4005
                    break;
4006
                case 0x07a: /* VIS I fornot1 */
4007
                    CHECK_FPU_FEATURE(dc, VIS1);
4008
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4009
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4010
                    tcg_gen_helper_0_0(helper_fornot);
4011
                    gen_op_store_DT0_fpr(DFPREG(rd));
4012
                    break;
4013
                case 0x07b: /* VIS I fornot1s */
4014
                    CHECK_FPU_FEATURE(dc, VIS1);
4015
                    gen_op_load_fpr_FT0(rs1);
4016
                    gen_op_load_fpr_FT1(rs2);
4017
                    tcg_gen_helper_0_0(helper_fornots);
4018
                    gen_op_store_FT0_fpr(rd);
4019
                    break;
4020
                case 0x07c: /* VIS I for */
4021
                    CHECK_FPU_FEATURE(dc, VIS1);
4022
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4023
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4024
                    tcg_gen_helper_0_0(helper_for);
4025
                    gen_op_store_DT0_fpr(DFPREG(rd));
4026
                    break;
4027
                case 0x07d: /* VIS I fors */
4028
                    CHECK_FPU_FEATURE(dc, VIS1);
4029
                    gen_op_load_fpr_FT0(rs1);
4030
                    gen_op_load_fpr_FT1(rs2);
4031
                    tcg_gen_helper_0_0(helper_fors);
4032
                    gen_op_store_FT0_fpr(rd);
4033
                    break;
4034
                case 0x07e: /* VIS I fone */
4035
                    CHECK_FPU_FEATURE(dc, VIS1);
4036
                    tcg_gen_helper_0_0(helper_movl_DT0_1);
4037
                    gen_op_store_DT0_fpr(DFPREG(rd));
4038
                    break;
4039
                case 0x07f: /* VIS I fones */
4040
                    CHECK_FPU_FEATURE(dc, VIS1);
4041
                    tcg_gen_helper_0_0(helper_movl_FT0_1);
4042
                    gen_op_store_FT0_fpr(rd);
4043
                    break;
4044
                case 0x080: /* VIS I shutdown */
4045
                case 0x081: /* VIS II siam */
4046
                    // XXX
4047
                    goto illegal_insn;
4048
                default:
4049
                    goto illegal_insn;
4050
                }
4051
#else
4052
                goto ncp_insn;
4053
#endif
4054
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4055
#ifdef TARGET_SPARC64
4056
                goto illegal_insn;
4057
#else
4058
                goto ncp_insn;
4059
#endif
4060
#ifdef TARGET_SPARC64
4061
            } else if (xop == 0x39) { /* V9 return */
4062
                TCGv r_const;
4063

    
4064
                save_state(dc, cpu_cond);
4065
                cpu_src1 = get_src1(insn, cpu_src1);
4066
                if (IS_IMM) {   /* immediate */
4067
                    rs2 = GET_FIELDs(insn, 19, 31);
4068
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4069
                } else {                /* register */
4070
                    rs2 = GET_FIELD(insn, 27, 31);
4071
                    if (rs2) {
4072
                        gen_movl_reg_TN(rs2, cpu_src2);
4073
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4074
                    } else
4075
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4076
                }
4077
                tcg_gen_helper_0_0(helper_restore);
4078
                gen_mov_pc_npc(dc, cpu_cond);
4079
                r_const = tcg_const_i32(3);
4080
                tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4081
                tcg_temp_free(r_const);
4082
                tcg_gen_mov_tl(cpu_npc, cpu_dst);
4083
                dc->npc = DYNAMIC_PC;
4084
                goto jmp_insn;
4085
#endif
4086
            } else {
4087
                cpu_src1 = get_src1(insn, cpu_src1);
4088
                if (IS_IMM) {   /* immediate */
4089
                    rs2 = GET_FIELDs(insn, 19, 31);
4090
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4091
                } else {                /* register */
4092
                    rs2 = GET_FIELD(insn, 27, 31);
4093
                    if (rs2) {
4094
                        gen_movl_reg_TN(rs2, cpu_src2);
4095
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4096
                    } else
4097
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4098
                }
4099
                switch (xop) {
4100
                case 0x38:      /* jmpl */
4101
                    {
4102
                        TCGv r_const;
4103

    
4104
                        r_const = tcg_const_tl(dc->pc);
4105
                        gen_movl_TN_reg(rd, r_const);
4106
                        tcg_temp_free(r_const);
4107
                        gen_mov_pc_npc(dc, cpu_cond);
4108
                        r_const = tcg_const_i32(3);
4109
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4110
                                           r_const);
4111
                        tcg_temp_free(r_const);
4112
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4113
                        dc->npc = DYNAMIC_PC;
4114
                    }
4115
                    goto jmp_insn;
4116
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4117
                case 0x39:      /* rett, V9 return */
4118
                    {
4119
                        TCGv r_const;
4120

    
4121
                        if (!supervisor(dc))
4122
                            goto priv_insn;
4123
                        gen_mov_pc_npc(dc, cpu_cond);
4124
                        r_const = tcg_const_i32(3);
4125
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4126
                                           r_const);
4127
                        tcg_temp_free(r_const);
4128
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4129
                        dc->npc = DYNAMIC_PC;
4130
                        tcg_gen_helper_0_0(helper_rett);
4131
                    }
4132
                    goto jmp_insn;
4133
#endif
4134
                case 0x3b: /* flush */
4135
                    if (!((dc)->features & CPU_FEATURE_FLUSH))
4136
                        goto unimp_flush;
4137
                    tcg_gen_helper_0_1(helper_flush, cpu_dst);
4138
                    break;
4139
                case 0x3c:      /* save */
4140
                    save_state(dc, cpu_cond);
4141
                    tcg_gen_helper_0_0(helper_save);
4142
                    gen_movl_TN_reg(rd, cpu_dst);
4143
                    break;
4144
                case 0x3d:      /* restore */
4145
                    save_state(dc, cpu_cond);
4146
                    tcg_gen_helper_0_0(helper_restore);
4147
                    gen_movl_TN_reg(rd, cpu_dst);
4148
                    break;
4149
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4150
                case 0x3e:      /* V9 done/retry */
4151
                    {
4152
                        switch (rd) {
4153
                        case 0:
4154
                            if (!supervisor(dc))
4155
                                goto priv_insn;
4156
                            dc->npc = DYNAMIC_PC;
4157
                            dc->pc = DYNAMIC_PC;
4158
                            tcg_gen_helper_0_0(helper_done);
4159
                            goto jmp_insn;
4160
                        case 1:
4161
                            if (!supervisor(dc))
4162
                                goto priv_insn;
4163
                            dc->npc = DYNAMIC_PC;
4164
                            dc->pc = DYNAMIC_PC;
4165
                            tcg_gen_helper_0_0(helper_retry);
4166
                            goto jmp_insn;
4167
                        default:
4168
                            goto illegal_insn;
4169
                        }
4170
                    }
4171
                    break;
4172
#endif
4173
                default:
4174
                    goto illegal_insn;
4175
                }
4176
            }
4177
            break;
4178
        }
4179
        break;
4180
    case 3:                     /* load/store instructions */
4181
        {
4182
            unsigned int xop = GET_FIELD(insn, 7, 12);
4183

    
4184
            cpu_src1 = get_src1(insn, cpu_src1);
4185
            if (xop == 0x3c || xop == 0x3e)
4186
            {
4187
                rs2 = GET_FIELD(insn, 27, 31);
4188
                gen_movl_reg_TN(rs2, cpu_src2);
4189
            }
4190
            else if (IS_IMM) {       /* immediate */
4191
                rs2 = GET_FIELDs(insn, 19, 31);
4192
                tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4193
            } else {            /* register */
4194
                rs2 = GET_FIELD(insn, 27, 31);
4195
                if (rs2 != 0) {
4196
                    gen_movl_reg_TN(rs2, cpu_src2);
4197
                    tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4198
                } else
4199
                    tcg_gen_mov_tl(cpu_addr, cpu_src1);
4200
            }
4201
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4202
                (xop > 0x17 && xop <= 0x1d ) ||
4203
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4204
                switch (xop) {
4205
                case 0x0:       /* load unsigned word */
4206
                    ABI32_MASK(cpu_addr);
4207
                    tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4208
                    break;
4209
                case 0x1:       /* load unsigned byte */
4210
                    ABI32_MASK(cpu_addr);
4211
                    tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4212
                    break;
4213
                case 0x2:       /* load unsigned halfword */
4214
                    ABI32_MASK(cpu_addr);
4215
                    tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4216
                    break;
4217
                case 0x3:       /* load double word */
4218
                    if (rd & 1)
4219
                        goto illegal_insn;
4220
                    else {
4221
                        TCGv r_const;
4222

    
4223
                        save_state(dc, cpu_cond);
4224
                        r_const = tcg_const_i32(7);
4225
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4226
                                           r_const); // XXX remove
4227
                        tcg_temp_free(r_const);
4228
                        ABI32_MASK(cpu_addr);
4229
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4230
                        tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4231
                        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4232
                        gen_movl_TN_reg(rd + 1, cpu_tmp0);
4233
                        tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4234
                        tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4235
                        tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4236
                    }
4237
                    break;
4238
                case 0x9:       /* load signed byte */
4239
                    ABI32_MASK(cpu_addr);
4240
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4241
                    break;
4242
                case 0xa:       /* load signed halfword */
4243
                    ABI32_MASK(cpu_addr);
4244
                    tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4245
                    break;
4246
                case 0xd:       /* ldstub -- XXX: should be atomically */
4247
                    {
4248
                        TCGv r_const;
4249

    
4250
                        ABI32_MASK(cpu_addr);
4251
                        tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4252
                        r_const = tcg_const_tl(0xff);
4253
                        tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4254
                        tcg_temp_free(r_const);
4255
                    }
4256
                    break;
4257
                case 0x0f:      /* swap register with memory. Also
4258
                                   atomically */
4259
                    CHECK_IU_FEATURE(dc, SWAP);
4260
                    gen_movl_reg_TN(rd, cpu_val);
4261
                    ABI32_MASK(cpu_addr);
4262
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4263
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4264
                    tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4265
                    break;
4266
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4267
                case 0x10:      /* load word alternate */
4268
#ifndef TARGET_SPARC64
4269
                    if (IS_IMM)
4270
                        goto illegal_insn;
4271
                    if (!supervisor(dc))
4272
                        goto priv_insn;
4273
#endif
4274
                    save_state(dc, cpu_cond);
4275
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4276
                    break;
4277
                case 0x11:      /* load unsigned byte alternate */
4278
#ifndef TARGET_SPARC64
4279
                    if (IS_IMM)
4280
                        goto illegal_insn;
4281
                    if (!supervisor(dc))
4282
                        goto priv_insn;
4283
#endif
4284
                    save_state(dc, cpu_cond);
4285
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4286
                    break;
4287
                case 0x12:      /* load unsigned halfword alternate */
4288
#ifndef TARGET_SPARC64
4289
                    if (IS_IMM)
4290
                        goto illegal_insn;
4291
                    if (!supervisor(dc))
4292
                        goto priv_insn;
4293
#endif
4294
                    save_state(dc, cpu_cond);
4295
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4296
                    break;
4297
                case 0x13:      /* load double word alternate */
4298
#ifndef TARGET_SPARC64
4299
                    if (IS_IMM)
4300
                        goto illegal_insn;
4301
                    if (!supervisor(dc))
4302
                        goto priv_insn;
4303
#endif
4304
                    if (rd & 1)
4305
                        goto illegal_insn;
4306
                    save_state(dc, cpu_cond);
4307
                    gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4308
                    gen_movl_TN_reg(rd + 1, cpu_tmp0);
4309
                    break;
4310
                case 0x19:      /* load signed byte alternate */
4311
#ifndef TARGET_SPARC64
4312
                    if (IS_IMM)
4313
                        goto illegal_insn;
4314
                    if (!supervisor(dc))
4315
                        goto priv_insn;
4316
#endif
4317
                    save_state(dc, cpu_cond);
4318
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4319
                    break;
4320
                case 0x1a:      /* load signed halfword alternate */
4321
#ifndef TARGET_SPARC64
4322
                    if (IS_IMM)
4323
                        goto illegal_insn;
4324
                    if (!supervisor(dc))
4325
                        goto priv_insn;
4326
#endif
4327
                    save_state(dc, cpu_cond);
4328
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4329
                    break;
4330
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
4331
#ifndef TARGET_SPARC64
4332
                    if (IS_IMM)
4333
                        goto illegal_insn;
4334
                    if (!supervisor(dc))
4335
                        goto priv_insn;
4336
#endif
4337
                    save_state(dc, cpu_cond);
4338
                    gen_ldstub_asi(cpu_val, cpu_addr, insn);
4339
                    break;
4340
                case 0x1f:      /* swap reg with alt. memory. Also
4341
                                   atomically */
4342
                    CHECK_IU_FEATURE(dc, SWAP);
4343
#ifndef TARGET_SPARC64
4344
                    if (IS_IMM)
4345
                        goto illegal_insn;
4346
                    if (!supervisor(dc))
4347
                        goto priv_insn;
4348
#endif
4349
                    save_state(dc, cpu_cond);
4350
                    gen_movl_reg_TN(rd, cpu_val);
4351
                    gen_swap_asi(cpu_val, cpu_addr, insn);
4352
                    break;
4353

    
4354
#ifndef TARGET_SPARC64
4355
                case 0x30: /* ldc */
4356
                case 0x31: /* ldcsr */
4357
                case 0x33: /* lddc */
4358
                    goto ncp_insn;
4359
#endif
4360
#endif
4361
#ifdef TARGET_SPARC64
4362
                case 0x08: /* V9 ldsw */
4363
                    ABI32_MASK(cpu_addr);
4364
                    tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4365
                    break;
4366
                case 0x0b: /* V9 ldx */
4367
                    ABI32_MASK(cpu_addr);
4368
                    tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4369
                    break;
4370
                case 0x18: /* V9 ldswa */
4371
                    save_state(dc, cpu_cond);
4372
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4373
                    break;
4374
                case 0x1b: /* V9 ldxa */
4375
                    save_state(dc, cpu_cond);
4376
                    gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4377
                    break;
4378
                case 0x2d: /* V9 prefetch, no effect */
4379
                    goto skip_move;
4380
                case 0x30: /* V9 ldfa */
4381
                    save_state(dc, cpu_cond);
4382
                    gen_ldf_asi(cpu_addr, insn, 4, rd);
4383
                    goto skip_move;
4384
                case 0x33: /* V9 lddfa */
4385
                    save_state(dc, cpu_cond);
4386
                    gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4387
                    goto skip_move;
4388
                case 0x3d: /* V9 prefetcha, no effect */
4389
                    goto skip_move;
4390
                case 0x32: /* V9 ldqfa */
4391
                    CHECK_FPU_FEATURE(dc, FLOAT128);
4392
                    save_state(dc, cpu_cond);
4393
                    gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4394
                    goto skip_move;
4395
#endif
4396
                default:
4397
                    goto illegal_insn;
4398
                }
4399
                gen_movl_TN_reg(rd, cpu_val);
4400
#ifdef TARGET_SPARC64
4401
            skip_move: ;
4402
#endif
4403
            } else if (xop >= 0x20 && xop < 0x24) {
4404
                if (gen_trap_ifnofpu(dc, cpu_cond))
4405
                    goto jmp_insn;
4406
                save_state(dc, cpu_cond);
4407
                switch (xop) {
4408
                case 0x20:      /* load fpreg */
4409
                    ABI32_MASK(cpu_addr);
4410
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4411
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4412
                                   offsetof(CPUState, fpr[rd]));
4413
                    break;
4414
                case 0x21:      /* load fsr */
4415
                    ABI32_MASK(cpu_addr);
4416
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4417
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4418
                                   offsetof(CPUState, ft0));
4419
                    tcg_gen_helper_0_0(helper_ldfsr);
4420
                    break;
4421
                case 0x22:      /* load quad fpreg */
4422
                    {
4423
                        TCGv r_const;
4424

    
4425
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4426
                        r_const = tcg_const_i32(dc->mem_idx);
4427
                        tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4428
                        tcg_temp_free(r_const);
4429
                        gen_op_store_QT0_fpr(QFPREG(rd));
4430
                    }
4431
                    break;
4432
                case 0x23:      /* load double fpreg */
4433
                    {
4434
                        TCGv r_const;
4435

    
4436
                        r_const = tcg_const_i32(dc->mem_idx);
4437
                        tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4438
                        tcg_temp_free(r_const);
4439
                        gen_op_store_DT0_fpr(DFPREG(rd));
4440
                    }
4441
                    break;
4442
                default:
4443
                    goto illegal_insn;
4444
                }
4445
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4446
                       xop == 0xe || xop == 0x1e) {
4447
                gen_movl_reg_TN(rd, cpu_val);
4448
                switch (xop) {
4449
                case 0x4: /* store word */
4450
                    ABI32_MASK(cpu_addr);
4451
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4452
                    break;
4453
                case 0x5: /* store byte */
4454
                    ABI32_MASK(cpu_addr);
4455
                    tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4456
                    break;
4457
                case 0x6: /* store halfword */
4458
                    ABI32_MASK(cpu_addr);
4459
                    tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4460
                    break;
4461
                case 0x7: /* store double word */
4462
                    if (rd & 1)
4463
                        goto illegal_insn;
4464
                    else {
4465
                        TCGv r_low, r_const;
4466

    
4467
                        save_state(dc, cpu_cond);
4468
                        ABI32_MASK(cpu_addr);
4469
                        r_const = tcg_const_i32(7);
4470
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4471
                                           r_const); // XXX remove
4472
                        tcg_temp_free(r_const);
4473
                        r_low = tcg_temp_new(TCG_TYPE_TL);
4474
                        gen_movl_reg_TN(rd + 1, r_low);
4475
                        tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4476
                                           r_low);
4477
                        tcg_temp_free(r_low);
4478
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4479
                    }
4480
                    break;
4481
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4482
                case 0x14: /* store word alternate */
4483
#ifndef TARGET_SPARC64
4484
                    if (IS_IMM)
4485
                        goto illegal_insn;
4486
                    if (!supervisor(dc))
4487
                        goto priv_insn;
4488
#endif
4489
                    save_state(dc, cpu_cond);
4490
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4491
                    break;
4492
                case 0x15: /* store byte alternate */
4493
#ifndef TARGET_SPARC64
4494
                    if (IS_IMM)
4495
                        goto illegal_insn;
4496
                    if (!supervisor(dc))
4497
                        goto priv_insn;
4498
#endif
4499
                    save_state(dc, cpu_cond);
4500
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4501
                    break;
4502
                case 0x16: /* store halfword alternate */
4503
#ifndef TARGET_SPARC64
4504
                    if (IS_IMM)
4505
                        goto illegal_insn;
4506
                    if (!supervisor(dc))
4507
                        goto priv_insn;
4508
#endif
4509
                    save_state(dc, cpu_cond);
4510
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4511
                    break;
4512
                case 0x17: /* store double word alternate */
4513
#ifndef TARGET_SPARC64
4514
                    if (IS_IMM)
4515
                        goto illegal_insn;
4516
                    if (!supervisor(dc))
4517
                        goto priv_insn;
4518
#endif
4519
                    if (rd & 1)
4520
                        goto illegal_insn;
4521
                    else {
4522
                        save_state(dc, cpu_cond);
4523
                        gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4524
                    }
4525
                    break;
4526
#endif
4527
#ifdef TARGET_SPARC64
4528
                case 0x0e: /* V9 stx */
4529
                    ABI32_MASK(cpu_addr);
4530
                    tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4531
                    break;
4532
                case 0x1e: /* V9 stxa */
4533
                    save_state(dc, cpu_cond);
4534
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4535
                    break;
4536
#endif
4537
                default:
4538
                    goto illegal_insn;
4539
                }
4540
            } else if (xop > 0x23 && xop < 0x28) {
4541
                if (gen_trap_ifnofpu(dc, cpu_cond))
4542
                    goto jmp_insn;
4543
                save_state(dc, cpu_cond);
4544
                switch (xop) {
4545
                case 0x24: /* store fpreg */
4546
                    ABI32_MASK(cpu_addr);
4547
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4548
                                   offsetof(CPUState, fpr[rd]));
4549
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4550
                    break;
4551
                case 0x25: /* stfsr, V9 stxfsr */
4552
                    ABI32_MASK(cpu_addr);
4553
                    tcg_gen_helper_0_0(helper_stfsr);
4554
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4555
                                   offsetof(CPUState, ft0));
4556
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4557
                    break;
4558
                case 0x26:
4559
#ifdef TARGET_SPARC64
4560
                    /* V9 stqf, store quad fpreg */
4561
                    {
4562
                        TCGv r_const;
4563

    
4564
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4565
                        gen_op_load_fpr_QT0(QFPREG(rd));
4566
                        r_const = tcg_const_i32(dc->mem_idx);
4567
                        tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4568
                        tcg_temp_free(r_const);
4569
                    }
4570
                    break;
4571
#else /* !TARGET_SPARC64 */
4572
                    /* stdfq, store floating point queue */
4573
#if defined(CONFIG_USER_ONLY)
4574
                    goto illegal_insn;
4575
#else
4576
                    if (!supervisor(dc))
4577
                        goto priv_insn;
4578
                    if (gen_trap_ifnofpu(dc, cpu_cond))
4579
                        goto jmp_insn;
4580
                    goto nfq_insn;
4581
#endif
4582
#endif
4583
                case 0x27: /* store double fpreg */
4584
                    {
4585
                        TCGv r_const;
4586

    
4587
                        gen_op_load_fpr_DT0(DFPREG(rd));
4588
                        r_const = tcg_const_i32(dc->mem_idx);
4589
                        tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4590
                        tcg_temp_free(r_const);
4591
                    }
4592
                    break;
4593
                default:
4594
                    goto illegal_insn;
4595
                }
4596
            } else if (xop > 0x33 && xop < 0x3f) {
4597
                save_state(dc, cpu_cond);
4598
                switch (xop) {
4599
#ifdef TARGET_SPARC64
4600
                case 0x34: /* V9 stfa */
4601
                    gen_op_load_fpr_FT0(rd);
4602
                    gen_stf_asi(cpu_addr, insn, 4, rd);
4603
                    break;
4604
                case 0x36: /* V9 stqfa */
4605
                    {
4606
                        TCGv r_const;
4607

    
4608
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4609
                        r_const = tcg_const_i32(7);
4610
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4611
                                           r_const);
4612
                        tcg_temp_free(r_const);
4613
                        gen_op_load_fpr_QT0(QFPREG(rd));
4614
                        gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4615
                    }
4616
                    break;
4617
                case 0x37: /* V9 stdfa */
4618
                    gen_op_load_fpr_DT0(DFPREG(rd));
4619
                    gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4620
                    break;
4621
                case 0x3c: /* V9 casa */
4622
                    gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4623
                    gen_movl_TN_reg(rd, cpu_val);
4624
                    break;
4625
                case 0x3e: /* V9 casxa */
4626
                    gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4627
                    gen_movl_TN_reg(rd, cpu_val);
4628
                    break;
4629
#else
4630
                case 0x34: /* stc */
4631
                case 0x35: /* stcsr */
4632
                case 0x36: /* stdcq */
4633
                case 0x37: /* stdc */
4634
                    goto ncp_insn;
4635
#endif
4636
                default:
4637
                    goto illegal_insn;
4638
                }
4639
            }
4640
            else
4641
                goto illegal_insn;
4642
        }
4643
        break;
4644
    }
4645
    /* default case for non jump instructions */
4646
    if (dc->npc == DYNAMIC_PC) {
4647
        dc->pc = DYNAMIC_PC;
4648
        gen_op_next_insn();
4649
    } else if (dc->npc == JUMP_PC) {
4650
        /* we can do a static jump */
4651
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4652
        dc->is_br = 1;
4653
    } else {
4654
        dc->pc = dc->npc;
4655
        dc->npc = dc->npc + 4;
4656
    }
4657
 jmp_insn:
4658
    return;
4659
 illegal_insn:
4660
    {
4661
        TCGv r_const;
4662

    
4663
        save_state(dc, cpu_cond);
4664
        r_const = tcg_const_i32(TT_ILL_INSN);
4665
        tcg_gen_helper_0_1(raise_exception, r_const);
4666
        tcg_temp_free(r_const);
4667
        dc->is_br = 1;
4668
    }
4669
    return;
4670
 unimp_flush:
4671
    {
4672
        TCGv r_const;
4673

    
4674
        save_state(dc, cpu_cond);
4675
        r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4676
        tcg_gen_helper_0_1(raise_exception, r_const);
4677
        tcg_temp_free(r_const);
4678
        dc->is_br = 1;
4679
    }
4680
    return;
4681
#if !defined(CONFIG_USER_ONLY)
4682
 priv_insn:
4683
    {
4684
        TCGv r_const;
4685

    
4686
        save_state(dc, cpu_cond);
4687
        r_const = tcg_const_i32(TT_PRIV_INSN);
4688
        tcg_gen_helper_0_1(raise_exception, r_const);
4689
        tcg_temp_free(r_const);
4690
        dc->is_br = 1;
4691
    }
4692
    return;
4693
#endif
4694
 nfpu_insn:
4695
    save_state(dc, cpu_cond);
4696
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4697
    dc->is_br = 1;
4698
    return;
4699
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4700
 nfq_insn:
4701
    save_state(dc, cpu_cond);
4702
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4703
    dc->is_br = 1;
4704
    return;
4705
#endif
4706
#ifndef TARGET_SPARC64
4707
 ncp_insn:
4708
    {
4709
        TCGv r_const;
4710

    
4711
        save_state(dc, cpu_cond);
4712
        r_const = tcg_const_i32(TT_NCP_INSN);
4713
        tcg_gen_helper_0_1(raise_exception, r_const);
4714
        tcg_temp_free(r_const);
4715
        dc->is_br = 1;
4716
    }
4717
    return;
4718
#endif
4719
}
4720

    
4721
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4722
                                                 int spc, CPUSPARCState *env)
4723
{
4724
    target_ulong pc_start, last_pc;
4725
    uint16_t *gen_opc_end;
4726
    DisasContext dc1, *dc = &dc1;
4727
    int j, lj = -1;
4728

    
4729
    memset(dc, 0, sizeof(DisasContext));
4730
    dc->tb = tb;
4731
    pc_start = tb->pc;
4732
    dc->pc = pc_start;
4733
    last_pc = dc->pc;
4734
    dc->npc = (target_ulong) tb->cs_base;
4735
    dc->mem_idx = cpu_mmu_index(env);
4736
    dc->features = env->features;
4737
    if ((dc->features & CPU_FEATURE_FLOAT)) {
4738
        dc->fpu_enabled = cpu_fpu_enabled(env);
4739
#if defined(CONFIG_USER_ONLY)
4740
        dc->features |= CPU_FEATURE_FLOAT128;
4741
#endif
4742
    } else
4743
        dc->fpu_enabled = 0;
4744
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4745

    
4746
    cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4747
    cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4748
    cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4749

    
4750
    do {
4751
        if (env->nb_breakpoints > 0) {
4752
            for(j = 0; j < env->nb_breakpoints; j++) {
4753
                if (env->breakpoints[j] == dc->pc) {
4754
                    if (dc->pc != pc_start)
4755
                        save_state(dc, cpu_cond);
4756
                    tcg_gen_helper_0_0(helper_debug);
4757
                    tcg_gen_exit_tb(0);
4758
                    dc->is_br = 1;
4759
                    goto exit_gen_loop;
4760
                }
4761
            }
4762
        }
4763
        if (spc) {
4764
            if (loglevel > 0)
4765
                fprintf(logfile, "Search PC...\n");
4766
            j = gen_opc_ptr - gen_opc_buf;
4767
            if (lj < j) {
4768
                lj++;
4769
                while (lj < j)
4770
                    gen_opc_instr_start[lj++] = 0;
4771
                gen_opc_pc[lj] = dc->pc;
4772
                gen_opc_npc[lj] = dc->npc;
4773
                gen_opc_instr_start[lj] = 1;
4774
            }
4775
        }
4776
        last_pc = dc->pc;
4777
        disas_sparc_insn(dc);
4778

    
4779
        if (dc->is_br)
4780
            break;
4781
        /* if the next PC is different, we abort now */
4782
        if (dc->pc != (last_pc + 4))
4783
            break;
4784
        /* if we reach a page boundary, we stop generation so that the
4785
           PC of a TT_TFAULT exception is always in the right page */
4786
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4787
            break;
4788
        /* if single step mode, we generate only one instruction and
4789
           generate an exception */
4790
        if (env->singlestep_enabled) {
4791
            tcg_gen_movi_tl(cpu_pc, dc->pc);
4792
            tcg_gen_exit_tb(0);
4793
            break;
4794
        }
4795
    } while ((gen_opc_ptr < gen_opc_end) &&
4796
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4797

    
4798
 exit_gen_loop:
4799
    tcg_temp_free(cpu_tmp64);
4800
    tcg_temp_free(cpu_tmp32);
4801
    tcg_temp_free(cpu_tmp0);
4802
    if (!dc->is_br) {
4803
        if (dc->pc != DYNAMIC_PC &&
4804
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4805
            /* static PC and NPC: we can use direct chaining */
4806
            gen_goto_tb(dc, 0, dc->pc, dc->npc);
4807
        } else {
4808
            if (dc->pc != DYNAMIC_PC)
4809
                tcg_gen_movi_tl(cpu_pc, dc->pc);
4810
            save_npc(dc, cpu_cond);
4811
            tcg_gen_exit_tb(0);
4812
        }
4813
    }
4814
    *gen_opc_ptr = INDEX_op_end;
4815
    if (spc) {
4816
        j = gen_opc_ptr - gen_opc_buf;
4817
        lj++;
4818
        while (lj <= j)
4819
            gen_opc_instr_start[lj++] = 0;
4820
#if 0
4821
        if (loglevel > 0) {
4822
            page_dump(logfile);
4823
        }
4824
#endif
4825
        gen_opc_jump_pc[0] = dc->jump_pc[0];
4826
        gen_opc_jump_pc[1] = dc->jump_pc[1];
4827
    } else {
4828
        tb->size = last_pc + 4 - pc_start;
4829
    }
4830
#ifdef DEBUG_DISAS
4831
    if (loglevel & CPU_LOG_TB_IN_ASM) {
4832
        fprintf(logfile, "--------------\n");
4833
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4834
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4835
        fprintf(logfile, "\n");
4836
    }
4837
#endif
4838
    return 0;
4839
}
4840

    
4841
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4842
{
4843
    return gen_intermediate_code_internal(tb, 0, env);
4844
}
4845

    
4846
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4847
{
4848
    return gen_intermediate_code_internal(tb, 1, env);
4849
}
4850

    
4851
void gen_intermediate_code_init(CPUSPARCState *env)
4852
{
4853
    unsigned int i;
4854
    static int inited;
4855
    static const char * const gregnames[8] = {
4856
        NULL, // g0 not used
4857
        "g1",
4858
        "g2",
4859
        "g3",
4860
        "g4",
4861
        "g5",
4862
        "g6",
4863
        "g7",
4864
    };
4865

    
4866
    /* init various static tables */
4867
    if (!inited) {
4868
        inited = 1;
4869

    
4870
        cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4871
        cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4872
                                         offsetof(CPUState, regwptr),
4873
                                         "regwptr");
4874
#ifdef TARGET_SPARC64
4875
        cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4876
                                     TCG_AREG0, offsetof(CPUState, xcc),
4877
                                     "xcc");
4878
#endif
4879
        /* XXX: T0 and T1 should be temporaries */
4880
        cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4881
                                      TCG_AREG0, offsetof(CPUState, t0), "T0");
4882
        cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4883
                                      TCG_AREG0, offsetof(CPUState, t1), "T1");
4884
        cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4885
                                      TCG_AREG0, offsetof(CPUState, cond),
4886
                                      "cond");
4887
        cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4888
                                        TCG_AREG0, offsetof(CPUState, cc_src),
4889
                                        "cc_src");
4890
        cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4891
                                         offsetof(CPUState, cc_src2),
4892
                                         "cc_src2");
4893
        cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4894
                                        TCG_AREG0, offsetof(CPUState, cc_dst),
4895
                                        "cc_dst");
4896
        cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4897
                                     TCG_AREG0, offsetof(CPUState, psr),
4898
                                     "psr");
4899
        cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4900