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/*
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 * On-chip DMA controller framework.
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 *
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 * Copyright (C) 2008 Nokia Corporation
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 * Written by Andrzej Zaborowski <andrew@openedhand.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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struct soc_dma_s;
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struct soc_dma_ch_s;
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typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
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typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch);
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enum soc_dma_port_type {
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    soc_dma_port_mem,
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    soc_dma_port_fifo,
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    soc_dma_port_other,
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};
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enum soc_dma_access_type {
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    soc_dma_access_const,
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    soc_dma_access_linear,
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    soc_dma_access_other,
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};
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struct soc_dma_ch_s {
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    /* Private */
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    struct soc_dma_s *dma;
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    int num;
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    QEMUTimer *timer;
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    /* Set by soc_dma.c */
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    int enable;
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    int update;
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    /* This should be set by dma->setup_fn().  */
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    int bytes;
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    /* Initialised by the DMA module, call soc_dma_ch_update after writing.  */
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    enum soc_dma_access_type type[2];
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    target_phys_addr_t vaddr[2];        /* Updated by .transfer_fn().  */
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    /* Private */
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    void *paddr[2];
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    soc_dma_io_t io_fn[2];
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    void *io_opaque[2];
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    int running;
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    soc_dma_transfer_t transfer_fn;
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    /* Set and used by the DMA module.  */
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    void *opaque;
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};
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struct soc_dma_s {
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    /* Following fields are set by the SoC DMA module and can be used
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     * by anybody.  */
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    uint64_t drqbmp;        /* Is zeroed by soc_dma_reset() */
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    qemu_irq *drq;
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    void *opaque;
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    int64_t freq;
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    soc_dma_transfer_t transfer_fn;
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    soc_dma_transfer_t setup_fn;
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    /* Set by soc_dma_init() for use by the DMA module.  */
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    struct soc_dma_ch_s *ch;
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};
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/* Call to activate or stop a DMA channel.  */
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void soc_dma_set_request(struct soc_dma_ch_s *ch, int level);
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/* Call after every write to one of the following fields and before
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 * calling soc_dma_set_request(ch, 1):
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 *   ch->type[0...1],
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 *   ch->vaddr[0...1],
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 *   ch->paddr[0...1],
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 * or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem().  */
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void soc_dma_ch_update(struct soc_dma_ch_s *ch);
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/* The SoC should call this when the DMA module is being reset.  */
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void soc_dma_reset(struct soc_dma_s *s);
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struct soc_dma_s *soc_dma_init(int n);
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void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
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                soc_dma_io_t fn, void *opaque, int out);
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void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
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                target_phys_addr_t virt_base, size_t size);
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static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
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                target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
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{
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    return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
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}
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static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
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                target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
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{
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    return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
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}
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static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma,
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                ram_addr_t offset, target_phys_addr_t virt_base, size_t size)
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{
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    return soc_dma_port_add_mem(dma, qemu_get_ram_ptr(offset), virt_base, size);
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}