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/*
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 * QEMU model of Xilinx uartlite.
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 *
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 * Copyright (c) 2009 Edgar E. Iglesias.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "sysbus.h"
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#include "qemu-char.h"
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#define DUART(x)
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#define R_RX            0
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#define R_TX            1
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#define R_STATUS        2
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#define R_CTRL          3
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#define R_MAX           4
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#define STATUS_RXVALID    0x01
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#define STATUS_RXFULL     0x02
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#define STATUS_TXEMPTY    0x04
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#define STATUS_TXFULL     0x08
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#define STATUS_IE         0x10
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#define STATUS_OVERRUN    0x20
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#define STATUS_FRAME      0x40
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#define STATUS_PARITY     0x80
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#define CONTROL_RST_TX    0x01
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#define CONTROL_RST_RX    0x02
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#define CONTROL_IE        0x10
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struct xlx_uartlite
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{
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    SysBusDevice busdev;
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    CharDriverState *chr;
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    qemu_irq irq;
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    uint8_t rx_fifo[8];
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    unsigned int rx_fifo_pos;
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    unsigned int rx_fifo_len;
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    uint32_t regs[R_MAX];
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};
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static void uart_update_irq(struct xlx_uartlite *s)
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{
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    unsigned int irq;
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    if (s->rx_fifo_len)
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        s->regs[R_STATUS] |= STATUS_IE;
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    irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
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    qemu_set_irq(s->irq, irq);
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}
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static void uart_update_status(struct xlx_uartlite *s)
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{
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    uint32_t r;
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    r = s->regs[R_STATUS];
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    r &= ~7;
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    r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
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    r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
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    r |= (!!s->rx_fifo_len);
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    s->regs[R_STATUS] = r;
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}
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static uint32_t uart_readl (void *opaque, target_phys_addr_t addr)
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{
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    struct xlx_uartlite *s = opaque;
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    uint32_t r = 0;
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    addr >>= 2;
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    switch (addr)
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    {
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        case R_RX:
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            r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
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            if (s->rx_fifo_len)
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                s->rx_fifo_len--;
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            uart_update_status(s);
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            uart_update_irq(s);
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            break;
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        default:
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            if (addr < ARRAY_SIZE(s->regs))
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                r = s->regs[addr];
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            DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
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            break;
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    }
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    return r;
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}
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static void
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uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    struct xlx_uartlite *s = opaque;
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    unsigned char ch = value;
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    addr >>= 2;
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    switch (addr)
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    {
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        case R_STATUS:
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            hw_error("write to UART STATUS?\n");
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            break;
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        case R_CTRL:
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            if (value & CONTROL_RST_RX) {
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                s->rx_fifo_pos = 0;
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                s->rx_fifo_len = 0;
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            }
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            s->regs[addr] = value;
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            break;
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        case R_TX:
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            if (s->chr)
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                qemu_chr_write(s->chr, &ch, 1);
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            s->regs[addr] = value;
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            /* hax.  */
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            s->regs[R_STATUS] |= STATUS_IE;
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            break;
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        default:
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            DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
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            if (addr < ARRAY_SIZE(s->regs))
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                s->regs[addr] = value;
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            break;
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    }
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    uart_update_status(s);
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    uart_update_irq(s);
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}
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static CPUReadMemoryFunc * const uart_read[] = {
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    &uart_readl,
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    &uart_readl,
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    &uart_readl,
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};
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static CPUWriteMemoryFunc * const uart_write[] = {
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    &uart_writel,
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    &uart_writel,
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    &uart_writel,
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};
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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    struct xlx_uartlite *s = opaque;
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    /* Got a byte.  */
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    if (s->rx_fifo_len >= 8) {
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        printf("WARNING: UART dropped char.\n");
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        return;
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    }
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    s->rx_fifo[s->rx_fifo_pos] = *buf;
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    s->rx_fifo_pos++;
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    s->rx_fifo_pos &= 0x7;
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    s->rx_fifo_len++;
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    uart_update_status(s);
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    uart_update_irq(s);
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}
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static int uart_can_rx(void *opaque)
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{
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    struct xlx_uartlite *s = opaque;
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    int r;
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    r = s->rx_fifo_len < sizeof(s->rx_fifo);
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    if (!r)
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        printf("cannot receive!\n");
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    return r;
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}
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static void uart_event(void *opaque, int event)
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{
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}
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static int xilinx_uartlite_init(SysBusDevice *dev)
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{
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    struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
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    int uart_regs;
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    sysbus_init_irq(dev, &s->irq);
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    uart_update_status(s);
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    uart_regs = cpu_register_io_memory(uart_read, uart_write, s);
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    sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
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    s->chr = qdev_init_chardev(&dev->qdev);
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    if (s->chr)
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        qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
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    return 0;
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}
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static void xilinx_uart_register(void)
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{
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    sysbus_register_dev("xilinx,uartlite", sizeof (struct xlx_uartlite),
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                        xilinx_uartlite_init);
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}
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device_init(xilinx_uart_register)