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/*
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 * QEMU PCI bus manager
3
 *
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 * Copyright (c) 2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pci.h"
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#include "pci_bridge.h"
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#include "pci_internals.h"
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#include "monitor.h"
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#include "net.h"
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#include "sysemu.h"
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#include "loader.h"
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#include "qemu-objects.h"
33

    
34
//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
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#else
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# define PCI_DPRINTF(format, ...)       do { } while (0)
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#endif
40

    
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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static char *pcibus_get_dev_path(DeviceState *dev);
43

    
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struct BusInfo pci_bus_info = {
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    .name       = "PCI",
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    .size       = sizeof(PCIBus),
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    .print_dev  = pcibus_dev_print,
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    .get_dev_path = pcibus_get_dev_path,
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    .props      = (Property[]) {
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        DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
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        DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
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        DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
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        DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
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                        QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
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        DEFINE_PROP_END_OF_LIST()
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    }
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};
58

    
59
static void pci_update_mappings(PCIDevice *d);
60
static void pci_set_irq(void *opaque, int irq_num, int level);
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static int pci_add_option_rom(PCIDevice *pdev);
62
static void pci_del_option_rom(PCIDevice *pdev);
63

    
64
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
65
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
66

    
67
struct PCIHostBus {
68
    int domain;
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    struct PCIBus *bus;
70
    QLIST_ENTRY(PCIHostBus) next;
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};
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static QLIST_HEAD(, PCIHostBus) host_buses;
73

    
74
static const VMStateDescription vmstate_pcibus = {
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    .name = "PCIBUS",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .minimum_version_id_old = 1,
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    .fields      = (VMStateField []) {
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        VMSTATE_INT32_EQUAL(nirq, PCIBus),
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        VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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        VMSTATE_END_OF_LIST()
83
    }
84
};
85

    
86
static int pci_bar(PCIDevice *d, int reg)
87
{
88
    uint8_t type;
89

    
90
    if (reg != PCI_ROM_SLOT)
91
        return PCI_BASE_ADDRESS_0 + reg * 4;
92

    
93
    type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
94
    return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
95
}
96

    
97
static inline int pci_irq_state(PCIDevice *d, int irq_num)
98
{
99
        return (d->irq_state >> irq_num) & 0x1;
100
}
101

    
102
static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
103
{
104
        d->irq_state &= ~(0x1 << irq_num);
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        d->irq_state |= level << irq_num;
106
}
107

    
108
static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
109
{
110
    PCIBus *bus;
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    for (;;) {
112
        bus = pci_dev->bus;
113
        irq_num = bus->map_irq(pci_dev, irq_num);
114
        if (bus->set_irq)
115
            break;
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        pci_dev = bus->parent_dev;
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    }
118
    bus->irq_count[irq_num] += change;
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    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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}
121

    
122
/* Update interrupt status bit in config space on interrupt
123
 * state change. */
124
static void pci_update_irq_status(PCIDevice *dev)
125
{
126
    if (dev->irq_state) {
127
        dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
128
    } else {
129
        dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
130
    }
131
}
132

    
133
static void pci_device_reset(PCIDevice *dev)
134
{
135
    int r;
136

    
137
    dev->irq_state = 0;
138
    pci_update_irq_status(dev);
139
    /* Clear all writeable bits */
140
    pci_set_word(dev->config + PCI_COMMAND,
141
                 pci_get_word(dev->config + PCI_COMMAND) &
142
                 ~pci_get_word(dev->wmask + PCI_COMMAND));
143
    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
144
    dev->config[PCI_INTERRUPT_LINE] = 0x0;
145
    for (r = 0; r < PCI_NUM_REGIONS; ++r) {
146
        PCIIORegion *region = &dev->io_regions[r];
147
        if (!region->size) {
148
            continue;
149
        }
150

    
151
        if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
152
            region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
153
            pci_set_quad(dev->config + pci_bar(dev, r), region->type);
154
        } else {
155
            pci_set_long(dev->config + pci_bar(dev, r), region->type);
156
        }
157
    }
158
    pci_update_mappings(dev);
159
}
160

    
161
static void pci_bus_reset(void *opaque)
162
{
163
    PCIBus *bus = opaque;
164
    int i;
165

    
166
    for (i = 0; i < bus->nirq; i++) {
167
        bus->irq_count[i] = 0;
168
    }
169
    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
170
        if (bus->devices[i]) {
171
            pci_device_reset(bus->devices[i]);
172
        }
173
    }
174
}
175

    
176
static void pci_host_bus_register(int domain, PCIBus *bus)
177
{
178
    struct PCIHostBus *host;
179
    host = qemu_mallocz(sizeof(*host));
180
    host->domain = domain;
181
    host->bus = bus;
182
    QLIST_INSERT_HEAD(&host_buses, host, next);
183
}
184

    
185
PCIBus *pci_find_root_bus(int domain)
186
{
187
    struct PCIHostBus *host;
188

    
189
    QLIST_FOREACH(host, &host_buses, next) {
190
        if (host->domain == domain) {
191
            return host->bus;
192
        }
193
    }
194

    
195
    return NULL;
196
}
197

    
198
int pci_find_domain(const PCIBus *bus)
199
{
200
    PCIDevice *d;
201
    struct PCIHostBus *host;
202

    
203
    /* obtain root bus */
204
    while ((d = bus->parent_dev) != NULL) {
205
        bus = d->bus;
206
    }
207

    
208
    QLIST_FOREACH(host, &host_buses, next) {
209
        if (host->bus == bus) {
210
            return host->domain;
211
        }
212
    }
213

    
214
    abort();    /* should not be reached */
215
    return -1;
216
}
217

    
218
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
219
                         const char *name, int devfn_min)
220
{
221
    qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
222
    assert(PCI_FUNC(devfn_min) == 0);
223
    bus->devfn_min = devfn_min;
224

    
225
    /* host bridge */
226
    QLIST_INIT(&bus->child);
227
    pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
228

    
229
    vmstate_register(NULL, -1, &vmstate_pcibus, bus);
230
    qemu_register_reset(pci_bus_reset, bus);
231
}
232

    
233
PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
234
{
235
    PCIBus *bus;
236

    
237
    bus = qemu_mallocz(sizeof(*bus));
238
    bus->qbus.qdev_allocated = 1;
239
    pci_bus_new_inplace(bus, parent, name, devfn_min);
240
    return bus;
241
}
242

    
243
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
244
                  void *irq_opaque, int nirq)
245
{
246
    bus->set_irq = set_irq;
247
    bus->map_irq = map_irq;
248
    bus->irq_opaque = irq_opaque;
249
    bus->nirq = nirq;
250
    bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
251
}
252

    
253
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
254
{
255
    bus->qbus.allow_hotplug = 1;
256
    bus->hotplug = hotplug;
257
    bus->hotplug_qdev = qdev;
258
}
259

    
260
void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
261
{
262
    bus->mem_base = base;
263
}
264

    
265
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
266
                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
267
                         void *irq_opaque, int devfn_min, int nirq)
268
{
269
    PCIBus *bus;
270

    
271
    bus = pci_bus_new(parent, name, devfn_min);
272
    pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
273
    return bus;
274
}
275

    
276
int pci_bus_num(PCIBus *s)
277
{
278
    if (!s->parent_dev)
279
        return 0;       /* pci host bridge */
280
    return s->parent_dev->config[PCI_SECONDARY_BUS];
281
}
282

    
283
static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
284
{
285
    PCIDevice *s = container_of(pv, PCIDevice, config);
286
    uint8_t *config;
287
    int i;
288

    
289
    assert(size == pci_config_size(s));
290
    config = qemu_malloc(size);
291

    
292
    qemu_get_buffer(f, config, size);
293
    for (i = 0; i < size; ++i) {
294
        if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
295
            qemu_free(config);
296
            return -EINVAL;
297
        }
298
    }
299
    memcpy(s->config, config, size);
300

    
301
    pci_update_mappings(s);
302

    
303
    qemu_free(config);
304
    return 0;
305
}
306

    
307
/* just put buffer */
308
static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
309
{
310
    const uint8_t **v = pv;
311
    assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
312
    qemu_put_buffer(f, *v, size);
313
}
314

    
315
static VMStateInfo vmstate_info_pci_config = {
316
    .name = "pci config",
317
    .get  = get_pci_config_device,
318
    .put  = put_pci_config_device,
319
};
320

    
321
static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
322
{
323
    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
324
    uint32_t irq_state[PCI_NUM_PINS];
325
    int i;
326
    for (i = 0; i < PCI_NUM_PINS; ++i) {
327
        irq_state[i] = qemu_get_be32(f);
328
        if (irq_state[i] != 0x1 && irq_state[i] != 0) {
329
            fprintf(stderr, "irq state %d: must be 0 or 1.\n",
330
                    irq_state[i]);
331
            return -EINVAL;
332
        }
333
    }
334

    
335
    for (i = 0; i < PCI_NUM_PINS; ++i) {
336
        pci_set_irq_state(s, i, irq_state[i]);
337
    }
338

    
339
    return 0;
340
}
341

    
342
static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
343
{
344
    int i;
345
    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
346

    
347
    for (i = 0; i < PCI_NUM_PINS; ++i) {
348
        qemu_put_be32(f, pci_irq_state(s, i));
349
    }
350
}
351

    
352
static VMStateInfo vmstate_info_pci_irq_state = {
353
    .name = "pci irq state",
354
    .get  = get_pci_irq_state,
355
    .put  = put_pci_irq_state,
356
};
357

    
358
const VMStateDescription vmstate_pci_device = {
359
    .name = "PCIDevice",
360
    .version_id = 2,
361
    .minimum_version_id = 1,
362
    .minimum_version_id_old = 1,
363
    .fields      = (VMStateField []) {
364
        VMSTATE_INT32_LE(version_id, PCIDevice),
365
        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
366
                                   vmstate_info_pci_config,
367
                                   PCI_CONFIG_SPACE_SIZE),
368
        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
369
                                   vmstate_info_pci_irq_state,
370
                                   PCI_NUM_PINS * sizeof(int32_t)),
371
        VMSTATE_END_OF_LIST()
372
    }
373
};
374

    
375
const VMStateDescription vmstate_pcie_device = {
376
    .name = "PCIDevice",
377
    .version_id = 2,
378
    .minimum_version_id = 1,
379
    .minimum_version_id_old = 1,
380
    .fields      = (VMStateField []) {
381
        VMSTATE_INT32_LE(version_id, PCIDevice),
382
        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
383
                                   vmstate_info_pci_config,
384
                                   PCIE_CONFIG_SPACE_SIZE),
385
        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
386
                                   vmstate_info_pci_irq_state,
387
                                   PCI_NUM_PINS * sizeof(int32_t)),
388
        VMSTATE_END_OF_LIST()
389
    }
390
};
391

    
392
static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
393
{
394
    return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
395
}
396

    
397
void pci_device_save(PCIDevice *s, QEMUFile *f)
398
{
399
    /* Clear interrupt status bit: it is implicit
400
     * in irq_state which we are saving.
401
     * This makes us compatible with old devices
402
     * which never set or clear this bit. */
403
    s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
404
    vmstate_save_state(f, pci_get_vmstate(s), s);
405
    /* Restore the interrupt status bit. */
406
    pci_update_irq_status(s);
407
}
408

    
409
int pci_device_load(PCIDevice *s, QEMUFile *f)
410
{
411
    int ret;
412
    ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
413
    /* Restore the interrupt status bit. */
414
    pci_update_irq_status(s);
415
    return ret;
416
}
417

    
418
static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
419
{
420
    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
421
                 pci_default_sub_vendor_id);
422
    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
423
                 pci_default_sub_device_id);
424
}
425

    
426
/*
427
 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
428
 *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
429
 */
430
int pci_parse_devaddr(const char *addr, int *domp, int *busp,
431
                      unsigned int *slotp, unsigned int *funcp)
432
{
433
    const char *p;
434
    char *e;
435
    unsigned long val;
436
    unsigned long dom = 0, bus = 0;
437
    unsigned int slot = 0;
438
    unsigned int func = 0;
439

    
440
    p = addr;
441
    val = strtoul(p, &e, 16);
442
    if (e == p)
443
        return -1;
444
    if (*e == ':') {
445
        bus = val;
446
        p = e + 1;
447
        val = strtoul(p, &e, 16);
448
        if (e == p)
449
            return -1;
450
        if (*e == ':') {
451
            dom = bus;
452
            bus = val;
453
            p = e + 1;
454
            val = strtoul(p, &e, 16);
455
            if (e == p)
456
                return -1;
457
        }
458
    }
459

    
460
    slot = val;
461

    
462
    if (funcp != NULL) {
463
        if (*e != '.')
464
            return -1;
465

    
466
        p = e + 1;
467
        val = strtoul(p, &e, 16);
468
        if (e == p)
469
            return -1;
470

    
471
        func = val;
472
    }
473

    
474
    /* if funcp == NULL func is 0 */
475
    if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
476
        return -1;
477

    
478
    if (*e)
479
        return -1;
480

    
481
    /* Note: QEMU doesn't implement domains other than 0 */
482
    if (!pci_find_bus(pci_find_root_bus(dom), bus))
483
        return -1;
484

    
485
    *domp = dom;
486
    *busp = bus;
487
    *slotp = slot;
488
    if (funcp != NULL)
489
        *funcp = func;
490
    return 0;
491
}
492

    
493
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
494
                     unsigned *slotp)
495
{
496
    /* strip legacy tag */
497
    if (!strncmp(addr, "pci_addr=", 9)) {
498
        addr += 9;
499
    }
500
    if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
501
        monitor_printf(mon, "Invalid pci address\n");
502
        return -1;
503
    }
504
    return 0;
505
}
506

    
507
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
508
{
509
    int dom, bus;
510
    unsigned slot;
511

    
512
    if (!devaddr) {
513
        *devfnp = -1;
514
        return pci_find_bus(pci_find_root_bus(0), 0);
515
    }
516

    
517
    if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
518
        return NULL;
519
    }
520

    
521
    *devfnp = slot << 3;
522
    return pci_find_bus(pci_find_root_bus(dom), bus);
523
}
524

    
525
static void pci_init_cmask(PCIDevice *dev)
526
{
527
    pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
528
    pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
529
    dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
530
    dev->cmask[PCI_REVISION_ID] = 0xff;
531
    dev->cmask[PCI_CLASS_PROG] = 0xff;
532
    pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
533
    dev->cmask[PCI_HEADER_TYPE] = 0xff;
534
    dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
535
}
536

    
537
static void pci_init_wmask(PCIDevice *dev)
538
{
539
    int config_size = pci_config_size(dev);
540

    
541
    dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
542
    dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
543
    pci_set_word(dev->wmask + PCI_COMMAND,
544
                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
545
                 PCI_COMMAND_INTX_DISABLE);
546

    
547
    memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
548
           config_size - PCI_CONFIG_HEADER_SIZE);
549
}
550

    
551
static void pci_init_wmask_bridge(PCIDevice *d)
552
{
553
    /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
554
       PCI_SEC_LETENCY_TIMER */
555
    memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
556

    
557
    /* base and limit */
558
    d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
559
    d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
560
    pci_set_word(d->wmask + PCI_MEMORY_BASE,
561
                 PCI_MEMORY_RANGE_MASK & 0xffff);
562
    pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
563
                 PCI_MEMORY_RANGE_MASK & 0xffff);
564
    pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
565
                 PCI_PREF_RANGE_MASK & 0xffff);
566
    pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
567
                 PCI_PREF_RANGE_MASK & 0xffff);
568

    
569
    /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
570
    memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
571

    
572
    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
573
}
574

    
575
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
576
{
577
    uint8_t slot = PCI_SLOT(dev->devfn);
578
    uint8_t func;
579

    
580
    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
581
        dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
582
    }
583

    
584
    /*
585
     * multifuction bit is interpreted in two ways as follows.
586
     *   - all functions must set the bit to 1.
587
     *     Example: Intel X53
588
     *   - function 0 must set the bit, but the rest function (> 0)
589
     *     is allowed to leave the bit to 0.
590
     *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
591
     *
592
     * So OS (at least Linux) checks the bit of only function 0,
593
     * and doesn't see the bit of function > 0.
594
     *
595
     * The below check allows both interpretation.
596
     */
597
    if (PCI_FUNC(dev->devfn)) {
598
        PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
599
        if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
600
            /* function 0 should set multifunction bit */
601
            error_report("PCI: single function device can't be populated "
602
                         "in function %x.%x", slot, PCI_FUNC(dev->devfn));
603
            return -1;
604
        }
605
        return 0;
606
    }
607

    
608
    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
609
        return 0;
610
    }
611
    /* function 0 indicates single function, so function > 0 must be NULL */
612
    for (func = 1; func < PCI_FUNC_MAX; ++func) {
613
        if (bus->devices[PCI_DEVFN(slot, func)]) {
614
            error_report("PCI: %x.0 indicates single function, "
615
                         "but %x.%x is already populated.",
616
                         slot, slot, func);
617
            return -1;
618
        }
619
    }
620
    return 0;
621
}
622

    
623
static void pci_config_alloc(PCIDevice *pci_dev)
624
{
625
    int config_size = pci_config_size(pci_dev);
626

    
627
    pci_dev->config = qemu_mallocz(config_size);
628
    pci_dev->cmask = qemu_mallocz(config_size);
629
    pci_dev->wmask = qemu_mallocz(config_size);
630
    pci_dev->w1cmask = qemu_mallocz(config_size);
631
    pci_dev->used = qemu_mallocz(config_size);
632
}
633

    
634
static void pci_config_free(PCIDevice *pci_dev)
635
{
636
    qemu_free(pci_dev->config);
637
    qemu_free(pci_dev->cmask);
638
    qemu_free(pci_dev->wmask);
639
    qemu_free(pci_dev->w1cmask);
640
    qemu_free(pci_dev->used);
641
}
642

    
643
/* -1 for devfn means auto assign */
644
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
645
                                         const char *name, int devfn,
646
                                         PCIConfigReadFunc *config_read,
647
                                         PCIConfigWriteFunc *config_write,
648
                                         bool is_bridge)
649
{
650
    if (devfn < 0) {
651
        for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
652
            devfn += PCI_FUNC_MAX) {
653
            if (!bus->devices[devfn])
654
                goto found;
655
        }
656
        error_report("PCI: no slot/function available for %s, all in use", name);
657
        return NULL;
658
    found: ;
659
    } else if (bus->devices[devfn]) {
660
        error_report("PCI: slot %d function %d not available for %s, in use by %s",
661
                     PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
662
        return NULL;
663
    }
664
    pci_dev->bus = bus;
665
    pci_dev->devfn = devfn;
666
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
667
    pci_dev->irq_state = 0;
668
    pci_config_alloc(pci_dev);
669

    
670
    if (!is_bridge) {
671
        pci_set_default_subsystem_id(pci_dev);
672
    }
673
    pci_init_cmask(pci_dev);
674
    pci_init_wmask(pci_dev);
675
    if (is_bridge) {
676
        pci_init_wmask_bridge(pci_dev);
677
    }
678
    if (pci_init_multifunction(bus, pci_dev)) {
679
        pci_config_free(pci_dev);
680
        return NULL;
681
    }
682

    
683
    if (!config_read)
684
        config_read = pci_default_read_config;
685
    if (!config_write)
686
        config_write = pci_default_write_config;
687
    pci_dev->config_read = config_read;
688
    pci_dev->config_write = config_write;
689
    bus->devices[devfn] = pci_dev;
690
    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
691
    pci_dev->version_id = 2; /* Current pci device vmstate version */
692
    return pci_dev;
693
}
694

    
695
static void do_pci_unregister_device(PCIDevice *pci_dev)
696
{
697
    qemu_free_irqs(pci_dev->irq);
698
    pci_dev->bus->devices[pci_dev->devfn] = NULL;
699
    pci_config_free(pci_dev);
700
}
701

    
702
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
703
                               int instance_size, int devfn,
704
                               PCIConfigReadFunc *config_read,
705
                               PCIConfigWriteFunc *config_write)
706
{
707
    PCIDevice *pci_dev;
708

    
709
    pci_dev = qemu_mallocz(instance_size);
710
    pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
711
                                     config_read, config_write,
712
                                     PCI_HEADER_TYPE_NORMAL);
713
    if (pci_dev == NULL) {
714
        hw_error("PCI: can't register device\n");
715
    }
716
    return pci_dev;
717
}
718

    
719
static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
720
                                          target_phys_addr_t addr)
721
{
722
    return addr + bus->mem_base;
723
}
724

    
725
static void pci_unregister_io_regions(PCIDevice *pci_dev)
726
{
727
    PCIIORegion *r;
728
    int i;
729

    
730
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
731
        r = &pci_dev->io_regions[i];
732
        if (!r->size || r->addr == PCI_BAR_UNMAPPED)
733
            continue;
734
        if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
735
            isa_unassign_ioport(r->addr, r->filtered_size);
736
        } else {
737
            cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
738
                                                         r->addr),
739
                                         r->filtered_size,
740
                                         IO_MEM_UNASSIGNED);
741
        }
742
    }
743
}
744

    
745
static int pci_unregister_device(DeviceState *dev)
746
{
747
    PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
748
    PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
749
    int ret = 0;
750

    
751
    if (info->exit)
752
        ret = info->exit(pci_dev);
753
    if (ret)
754
        return ret;
755

    
756
    pci_unregister_io_regions(pci_dev);
757
    pci_del_option_rom(pci_dev);
758
    do_pci_unregister_device(pci_dev);
759
    return 0;
760
}
761

    
762
void pci_register_bar(PCIDevice *pci_dev, int region_num,
763
                            pcibus_t size, uint8_t type,
764
                            PCIMapIORegionFunc *map_func)
765
{
766
    PCIIORegion *r;
767
    uint32_t addr;
768
    uint64_t wmask;
769

    
770
    assert(region_num >= 0);
771
    assert(region_num < PCI_NUM_REGIONS);
772
    if (size & (size-1)) {
773
        fprintf(stderr, "ERROR: PCI region size must be pow2 "
774
                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
775
        exit(1);
776
    }
777

    
778
    r = &pci_dev->io_regions[region_num];
779
    r->addr = PCI_BAR_UNMAPPED;
780
    r->size = size;
781
    r->filtered_size = size;
782
    r->type = type;
783
    r->map_func = map_func;
784

    
785
    wmask = ~(size - 1);
786
    addr = pci_bar(pci_dev, region_num);
787
    if (region_num == PCI_ROM_SLOT) {
788
        /* ROM enable bit is writeable */
789
        wmask |= PCI_ROM_ADDRESS_ENABLE;
790
    }
791
    pci_set_long(pci_dev->config + addr, type);
792
    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
793
        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
794
        pci_set_quad(pci_dev->wmask + addr, wmask);
795
        pci_set_quad(pci_dev->cmask + addr, ~0ULL);
796
    } else {
797
        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
798
        pci_set_long(pci_dev->cmask + addr, 0xffffffff);
799
    }
800
}
801

    
802
static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
803
                              uint8_t type)
804
{
805
    pcibus_t base = *addr;
806
    pcibus_t limit = *addr + *size - 1;
807
    PCIDevice *br;
808

    
809
    for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
810
        uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
811

    
812
        if (type & PCI_BASE_ADDRESS_SPACE_IO) {
813
            if (!(cmd & PCI_COMMAND_IO)) {
814
                goto no_map;
815
            }
816
        } else {
817
            if (!(cmd & PCI_COMMAND_MEMORY)) {
818
                goto no_map;
819
            }
820
        }
821

    
822
        base = MAX(base, pci_bridge_get_base(br, type));
823
        limit = MIN(limit, pci_bridge_get_limit(br, type));
824
    }
825

    
826
    if (base > limit) {
827
        goto no_map;
828
    }
829
    *addr = base;
830
    *size = limit - base + 1;
831
    return;
832
no_map:
833
    *addr = PCI_BAR_UNMAPPED;
834
    *size = 0;
835
}
836

    
837
static pcibus_t pci_bar_address(PCIDevice *d,
838
                                int reg, uint8_t type, pcibus_t size)
839
{
840
    pcibus_t new_addr, last_addr;
841
    int bar = pci_bar(d, reg);
842
    uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
843

    
844
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
845
        if (!(cmd & PCI_COMMAND_IO)) {
846
            return PCI_BAR_UNMAPPED;
847
        }
848
        new_addr = pci_get_long(d->config + bar) & ~(size - 1);
849
        last_addr = new_addr + size - 1;
850
        /* NOTE: we have only 64K ioports on PC */
851
        if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
852
            return PCI_BAR_UNMAPPED;
853
        }
854
        return new_addr;
855
    }
856

    
857
    if (!(cmd & PCI_COMMAND_MEMORY)) {
858
        return PCI_BAR_UNMAPPED;
859
    }
860
    if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
861
        new_addr = pci_get_quad(d->config + bar);
862
    } else {
863
        new_addr = pci_get_long(d->config + bar);
864
    }
865
    /* the ROM slot has a specific enable bit */
866
    if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
867
        return PCI_BAR_UNMAPPED;
868
    }
869
    new_addr &= ~(size - 1);
870
    last_addr = new_addr + size - 1;
871
    /* NOTE: we do not support wrapping */
872
    /* XXX: as we cannot support really dynamic
873
       mappings, we handle specific values as invalid
874
       mappings. */
875
    if (last_addr <= new_addr || new_addr == 0 ||
876
        last_addr == PCI_BAR_UNMAPPED) {
877
        return PCI_BAR_UNMAPPED;
878
    }
879

    
880
    /* Now pcibus_t is 64bit.
881
     * Check if 32 bit BAR wraps around explicitly.
882
     * Without this, PC ide doesn't work well.
883
     * TODO: remove this work around.
884
     */
885
    if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
886
        return PCI_BAR_UNMAPPED;
887
    }
888

    
889
    /*
890
     * OS is allowed to set BAR beyond its addressable
891
     * bits. For example, 32 bit OS can set 64bit bar
892
     * to >4G. Check it. TODO: we might need to support
893
     * it in the future for e.g. PAE.
894
     */
895
    if (last_addr >= TARGET_PHYS_ADDR_MAX) {
896
        return PCI_BAR_UNMAPPED;
897
    }
898

    
899
    return new_addr;
900
}
901

    
902
static void pci_update_mappings(PCIDevice *d)
903
{
904
    PCIIORegion *r;
905
    int i;
906
    pcibus_t new_addr, filtered_size;
907

    
908
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
909
        r = &d->io_regions[i];
910

    
911
        /* this region isn't registered */
912
        if (!r->size)
913
            continue;
914

    
915
        new_addr = pci_bar_address(d, i, r->type, r->size);
916

    
917
        /* bridge filtering */
918
        filtered_size = r->size;
919
        if (new_addr != PCI_BAR_UNMAPPED) {
920
            pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
921
        }
922

    
923
        /* This bar isn't changed */
924
        if (new_addr == r->addr && filtered_size == r->filtered_size)
925
            continue;
926

    
927
        /* now do the real mapping */
928
        if (r->addr != PCI_BAR_UNMAPPED) {
929
            if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
930
                int class;
931
                /* NOTE: specific hack for IDE in PC case:
932
                   only one byte must be mapped. */
933
                class = pci_get_word(d->config + PCI_CLASS_DEVICE);
934
                if (class == 0x0101 && r->size == 4) {
935
                    isa_unassign_ioport(r->addr + 2, 1);
936
                } else {
937
                    isa_unassign_ioport(r->addr, r->filtered_size);
938
                }
939
            } else {
940
                cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
941
                                             r->filtered_size,
942
                                             IO_MEM_UNASSIGNED);
943
                qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
944
            }
945
        }
946
        r->addr = new_addr;
947
        r->filtered_size = filtered_size;
948
        if (r->addr != PCI_BAR_UNMAPPED) {
949
            /*
950
             * TODO: currently almost all the map funcions assumes
951
             * filtered_size == size and addr & ~(size - 1) == addr.
952
             * However with bridge filtering, they aren't always true.
953
             * Teach them such cases, such that filtered_size < size and
954
             * addr & (size - 1) != 0.
955
             */
956
            if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
957
                r->map_func(d, i, r->addr, r->filtered_size, r->type);
958
            } else {
959
                r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
960
                            r->filtered_size, r->type);
961
            }
962
        }
963
    }
964
}
965

    
966
static inline int pci_irq_disabled(PCIDevice *d)
967
{
968
    return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
969
}
970

    
971
/* Called after interrupt disabled field update in config space,
972
 * assert/deassert interrupts if necessary.
973
 * Gets original interrupt disable bit value (before update). */
974
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
975
{
976
    int i, disabled = pci_irq_disabled(d);
977
    if (disabled == was_irq_disabled)
978
        return;
979
    for (i = 0; i < PCI_NUM_PINS; ++i) {
980
        int state = pci_irq_state(d, i);
981
        pci_change_irq_level(d, i, disabled ? -state : state);
982
    }
983
}
984

    
985
uint32_t pci_default_read_config(PCIDevice *d,
986
                                 uint32_t address, int len)
987
{
988
    uint32_t val = 0;
989
    assert(len == 1 || len == 2 || len == 4);
990
    len = MIN(len, pci_config_size(d) - address);
991
    memcpy(&val, d->config + address, len);
992
    return le32_to_cpu(val);
993
}
994

    
995
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
996
{
997
    int i, was_irq_disabled = pci_irq_disabled(d);
998
    uint32_t config_size = pci_config_size(d);
999

    
1000
    for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1001
        uint8_t wmask = d->wmask[addr + i];
1002
        uint8_t w1cmask = d->w1cmask[addr + i];
1003
        assert(!(wmask & w1cmask));
1004
        d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1005
        d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1006
    }
1007
    if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1008
        ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1009
        ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1010
        range_covers_byte(addr, l, PCI_COMMAND))
1011
        pci_update_mappings(d);
1012

    
1013
    if (range_covers_byte(addr, l, PCI_COMMAND))
1014
        pci_update_irq_disabled(d, was_irq_disabled);
1015
}
1016

    
1017
/***********************************************************/
1018
/* generic PCI irq support */
1019

    
1020
/* 0 <= irq_num <= 3. level must be 0 or 1 */
1021
static void pci_set_irq(void *opaque, int irq_num, int level)
1022
{
1023
    PCIDevice *pci_dev = opaque;
1024
    int change;
1025

    
1026
    change = level - pci_irq_state(pci_dev, irq_num);
1027
    if (!change)
1028
        return;
1029

    
1030
    pci_set_irq_state(pci_dev, irq_num, level);
1031
    pci_update_irq_status(pci_dev);
1032
    if (pci_irq_disabled(pci_dev))
1033
        return;
1034
    pci_change_irq_level(pci_dev, irq_num, change);
1035
}
1036

    
1037
/***********************************************************/
1038
/* monitor info on PCI */
1039

    
1040
typedef struct {
1041
    uint16_t class;
1042
    const char *desc;
1043
} pci_class_desc;
1044

    
1045
static const pci_class_desc pci_class_descriptions[] =
1046
{
1047
    { 0x0100, "SCSI controller"},
1048
    { 0x0101, "IDE controller"},
1049
    { 0x0102, "Floppy controller"},
1050
    { 0x0103, "IPI controller"},
1051
    { 0x0104, "RAID controller"},
1052
    { 0x0106, "SATA controller"},
1053
    { 0x0107, "SAS controller"},
1054
    { 0x0180, "Storage controller"},
1055
    { 0x0200, "Ethernet controller"},
1056
    { 0x0201, "Token Ring controller"},
1057
    { 0x0202, "FDDI controller"},
1058
    { 0x0203, "ATM controller"},
1059
    { 0x0280, "Network controller"},
1060
    { 0x0300, "VGA controller"},
1061
    { 0x0301, "XGA controller"},
1062
    { 0x0302, "3D controller"},
1063
    { 0x0380, "Display controller"},
1064
    { 0x0400, "Video controller"},
1065
    { 0x0401, "Audio controller"},
1066
    { 0x0402, "Phone"},
1067
    { 0x0480, "Multimedia controller"},
1068
    { 0x0500, "RAM controller"},
1069
    { 0x0501, "Flash controller"},
1070
    { 0x0580, "Memory controller"},
1071
    { 0x0600, "Host bridge"},
1072
    { 0x0601, "ISA bridge"},
1073
    { 0x0602, "EISA bridge"},
1074
    { 0x0603, "MC bridge"},
1075
    { 0x0604, "PCI bridge"},
1076
    { 0x0605, "PCMCIA bridge"},
1077
    { 0x0606, "NUBUS bridge"},
1078
    { 0x0607, "CARDBUS bridge"},
1079
    { 0x0608, "RACEWAY bridge"},
1080
    { 0x0680, "Bridge"},
1081
    { 0x0c03, "USB controller"},
1082
    { 0, NULL}
1083
};
1084

    
1085
static void pci_for_each_device_under_bus(PCIBus *bus,
1086
                                          void (*fn)(PCIBus *b, PCIDevice *d))
1087
{
1088
    PCIDevice *d;
1089
    int devfn;
1090

    
1091
    for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1092
        d = bus->devices[devfn];
1093
        if (d) {
1094
            fn(bus, d);
1095
        }
1096
    }
1097
}
1098

    
1099
void pci_for_each_device(PCIBus *bus, int bus_num,
1100
                         void (*fn)(PCIBus *b, PCIDevice *d))
1101
{
1102
    bus = pci_find_bus(bus, bus_num);
1103

    
1104
    if (bus) {
1105
        pci_for_each_device_under_bus(bus, fn);
1106
    }
1107
}
1108

    
1109
static void pci_device_print(Monitor *mon, QDict *device)
1110
{
1111
    QDict *qdict;
1112
    QListEntry *entry;
1113
    uint64_t addr, size;
1114

    
1115
    monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1116
    monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1117
                        qdict_get_int(device, "slot"),
1118
                        qdict_get_int(device, "function"));
1119
    monitor_printf(mon, "    ");
1120

    
1121
    qdict = qdict_get_qdict(device, "class_info");
1122
    if (qdict_haskey(qdict, "desc")) {
1123
        monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1124
    } else {
1125
        monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1126
    }
1127

    
1128
    qdict = qdict_get_qdict(device, "id");
1129
    monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1130
                        qdict_get_int(qdict, "device"),
1131
                        qdict_get_int(qdict, "vendor"));
1132

    
1133
    if (qdict_haskey(device, "irq")) {
1134
        monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1135
                            qdict_get_int(device, "irq"));
1136
    }
1137

    
1138
    if (qdict_haskey(device, "pci_bridge")) {
1139
        QDict *info;
1140

    
1141
        qdict = qdict_get_qdict(device, "pci_bridge");
1142

    
1143
        info = qdict_get_qdict(qdict, "bus");
1144
        monitor_printf(mon, "      BUS %" PRId64 ".\n",
1145
                            qdict_get_int(info, "number"));
1146
        monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1147
                            qdict_get_int(info, "secondary"));
1148
        monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1149
                            qdict_get_int(info, "subordinate"));
1150

    
1151
        info = qdict_get_qdict(qdict, "io_range");
1152
        monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1153
                       qdict_get_int(info, "base"),
1154
                       qdict_get_int(info, "limit"));
1155

    
1156
        info = qdict_get_qdict(qdict, "memory_range");
1157
        monitor_printf(mon,
1158
                       "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1159
                       qdict_get_int(info, "base"),
1160
                       qdict_get_int(info, "limit"));
1161

    
1162
        info = qdict_get_qdict(qdict, "prefetchable_range");
1163
        monitor_printf(mon, "      prefetchable memory range "
1164
                       "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1165
                       qdict_get_int(info, "base"),
1166
        qdict_get_int(info, "limit"));
1167
    }
1168

    
1169
    QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1170
        qdict = qobject_to_qdict(qlist_entry_obj(entry));
1171
        monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1172

    
1173
        addr = qdict_get_int(qdict, "address");
1174
        size = qdict_get_int(qdict, "size");
1175

    
1176
        if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1177
            monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1178
                                " [0x%04"FMT_PCIBUS"].\n",
1179
                                addr, addr + size - 1);
1180
        } else {
1181
            monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1182
                               " [0x%08"FMT_PCIBUS"].\n",
1183
                                qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1184
                                qdict_get_bool(qdict, "prefetch") ?
1185
                                " prefetchable" : "", addr, addr + size - 1);
1186
        }
1187
    }
1188

    
1189
    monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1190

    
1191
    if (qdict_haskey(device, "pci_bridge")) {
1192
        qdict = qdict_get_qdict(device, "pci_bridge");
1193
        if (qdict_haskey(qdict, "devices")) {
1194
            QListEntry *dev;
1195
            QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1196
                pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1197
            }
1198
        }
1199
    }
1200
}
1201

    
1202
void do_pci_info_print(Monitor *mon, const QObject *data)
1203
{
1204
    QListEntry *bus, *dev;
1205

    
1206
    QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1207
        QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1208
        QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1209
            pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1210
        }
1211
    }
1212
}
1213

    
1214
static QObject *pci_get_dev_class(const PCIDevice *dev)
1215
{
1216
    int class;
1217
    const pci_class_desc *desc;
1218

    
1219
    class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1220
    desc = pci_class_descriptions;
1221
    while (desc->desc && class != desc->class)
1222
        desc++;
1223

    
1224
    if (desc->desc) {
1225
        return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1226
                                  desc->desc, class);
1227
    } else {
1228
        return qobject_from_jsonf("{ 'class': %d }", class);
1229
    }
1230
}
1231

    
1232
static QObject *pci_get_dev_id(const PCIDevice *dev)
1233
{
1234
    return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1235
                              pci_get_word(dev->config + PCI_VENDOR_ID),
1236
                              pci_get_word(dev->config + PCI_DEVICE_ID));
1237
}
1238

    
1239
static QObject *pci_get_regions_list(const PCIDevice *dev)
1240
{
1241
    int i;
1242
    QList *regions_list;
1243

    
1244
    regions_list = qlist_new();
1245

    
1246
    for (i = 0; i < PCI_NUM_REGIONS; i++) {
1247
        QObject *obj;
1248
        const PCIIORegion *r = &dev->io_regions[i];
1249

    
1250
        if (!r->size) {
1251
            continue;
1252
        }
1253

    
1254
        if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1255
            obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1256
                                     "'address': %" PRId64 ", "
1257
                                     "'size': %" PRId64 " }",
1258
                                     i, r->addr, r->size);
1259
        } else {
1260
            int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1261

    
1262
            obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1263
                                     "'mem_type_64': %i, 'prefetch': %i, "
1264
                                     "'address': %" PRId64 ", "
1265
                                     "'size': %" PRId64 " }",
1266
                                     i, mem_type_64,
1267
                                     r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1268
                                     r->addr, r->size);
1269
        }
1270

    
1271
        qlist_append_obj(regions_list, obj);
1272
    }
1273

    
1274
    return QOBJECT(regions_list);
1275
}
1276

    
1277
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1278

    
1279
static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1280
{
1281
    uint8_t type;
1282
    QObject *obj;
1283

    
1284
    obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1285
                              " 'qdev_id': %s }",
1286
                              bus_num,
1287
                              PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1288
                              pci_get_dev_class(dev), pci_get_dev_id(dev),
1289
                              pci_get_regions_list(dev),
1290
                              dev->qdev.id ? dev->qdev.id : "");
1291

    
1292
    if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1293
        QDict *qdict = qobject_to_qdict(obj);
1294
        qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1295
    }
1296

    
1297
    type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1298
    if (type == PCI_HEADER_TYPE_BRIDGE) {
1299
        QDict *qdict;
1300
        QObject *pci_bridge;
1301

    
1302
        pci_bridge = qobject_from_jsonf("{ 'bus': "
1303
        "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1304
        "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1305
        "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1306
        "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1307
        dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1308
        dev->config[PCI_SUBORDINATE_BUS],
1309
        pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1310
        pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1311
        pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1312
        pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1313
        pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1314
                               PCI_BASE_ADDRESS_MEM_PREFETCH),
1315
        pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1316
                                PCI_BASE_ADDRESS_MEM_PREFETCH));
1317

    
1318
        if (dev->config[PCI_SECONDARY_BUS] != 0) {
1319
            PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1320

    
1321
            if (child_bus) {
1322
                qdict = qobject_to_qdict(pci_bridge);
1323
                qdict_put_obj(qdict, "devices",
1324
                              pci_get_devices_list(child_bus,
1325
                                                   dev->config[PCI_SECONDARY_BUS]));
1326
            }
1327
        }
1328
        qdict = qobject_to_qdict(obj);
1329
        qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1330
    }
1331

    
1332
    return obj;
1333
}
1334

    
1335
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1336
{
1337
    int devfn;
1338
    PCIDevice *dev;
1339
    QList *dev_list;
1340

    
1341
    dev_list = qlist_new();
1342

    
1343
    for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1344
        dev = bus->devices[devfn];
1345
        if (dev) {
1346
            qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1347
        }
1348
    }
1349

    
1350
    return QOBJECT(dev_list);
1351
}
1352

    
1353
static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1354
{
1355
    bus = pci_find_bus(bus, bus_num);
1356
    if (bus) {
1357
        return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1358
                                  bus_num, pci_get_devices_list(bus, bus_num));
1359
    }
1360

    
1361
    return NULL;
1362
}
1363

    
1364
void do_pci_info(Monitor *mon, QObject **ret_data)
1365
{
1366
    QList *bus_list;
1367
    struct PCIHostBus *host;
1368

    
1369
    bus_list = qlist_new();
1370

    
1371
    QLIST_FOREACH(host, &host_buses, next) {
1372
        QObject *obj = pci_get_bus_dict(host->bus, 0);
1373
        if (obj) {
1374
            qlist_append_obj(bus_list, obj);
1375
        }
1376
    }
1377

    
1378
    *ret_data = QOBJECT(bus_list);
1379
}
1380

    
1381
static const char * const pci_nic_models[] = {
1382
    "ne2k_pci",
1383
    "i82551",
1384
    "i82557b",
1385
    "i82559er",
1386
    "rtl8139",
1387
    "e1000",
1388
    "pcnet",
1389
    "virtio",
1390
    NULL
1391
};
1392

    
1393
static const char * const pci_nic_names[] = {
1394
    "ne2k_pci",
1395
    "i82551",
1396
    "i82557b",
1397
    "i82559er",
1398
    "rtl8139",
1399
    "e1000",
1400
    "pcnet",
1401
    "virtio-net-pci",
1402
    NULL
1403
};
1404

    
1405
/* Initialize a PCI NIC.  */
1406
/* FIXME callers should check for failure, but don't */
1407
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1408
                        const char *default_devaddr)
1409
{
1410
    const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1411
    PCIBus *bus;
1412
    int devfn;
1413
    PCIDevice *pci_dev;
1414
    DeviceState *dev;
1415
    int i;
1416

    
1417
    i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1418
    if (i < 0)
1419
        return NULL;
1420

    
1421
    bus = pci_get_bus_devfn(&devfn, devaddr);
1422
    if (!bus) {
1423
        error_report("Invalid PCI device address %s for device %s",
1424
                     devaddr, pci_nic_names[i]);
1425
        return NULL;
1426
    }
1427

    
1428
    pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1429
    dev = &pci_dev->qdev;
1430
    qdev_set_nic_properties(dev, nd);
1431
    if (qdev_init(dev) < 0)
1432
        return NULL;
1433
    return pci_dev;
1434
}
1435

    
1436
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1437
                               const char *default_devaddr)
1438
{
1439
    PCIDevice *res;
1440

    
1441
    if (qemu_show_nic_models(nd->model, pci_nic_models))
1442
        exit(0);
1443

    
1444
    res = pci_nic_init(nd, default_model, default_devaddr);
1445
    if (!res)
1446
        exit(1);
1447
    return res;
1448
}
1449

    
1450
static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1451
{
1452
    pci_update_mappings(d);
1453
}
1454

    
1455
void pci_bridge_update_mappings(PCIBus *b)
1456
{
1457
    PCIBus *child;
1458

    
1459
    pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1460

    
1461
    QLIST_FOREACH(child, &b->child, sibling) {
1462
        pci_bridge_update_mappings(child);
1463
    }
1464
}
1465

    
1466
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1467
{
1468
    PCIBus *sec;
1469

    
1470
    if (!bus) {
1471
        return NULL;
1472
    }
1473

    
1474
    if (pci_bus_num(bus) == bus_num) {
1475
        return bus;
1476
    }
1477

    
1478
    /* try child bus */
1479
    if (!bus->parent_dev /* host pci bridge */ ||
1480
        (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1481
         bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1482
        for (; bus; bus = sec) {
1483
            QLIST_FOREACH(sec, &bus->child, sibling) {
1484
                assert(sec->parent_dev);
1485
                if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1486
                    return sec;
1487
                }
1488
                if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1489
                    bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1490
                    break;
1491
                }
1492
            }
1493
        }
1494
    }
1495

    
1496
    return NULL;
1497
}
1498

    
1499
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1500
{
1501
    bus = pci_find_bus(bus, bus_num);
1502

    
1503
    if (!bus)
1504
        return NULL;
1505

    
1506
    return bus->devices[PCI_DEVFN(slot, function)];
1507
}
1508

    
1509
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1510
{
1511
    PCIDevice *pci_dev = (PCIDevice *)qdev;
1512
    PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1513
    PCIBus *bus;
1514
    int devfn, rc;
1515

    
1516
    /* initialize cap_present for pci_is_express() and pci_config_size() */
1517
    if (info->is_express) {
1518
        pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1519
    }
1520

    
1521
    bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1522
    devfn = pci_dev->devfn;
1523
    pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1524
                                     info->config_read, info->config_write,
1525
                                     info->is_bridge);
1526
    if (pci_dev == NULL)
1527
        return -1;
1528
    rc = info->init(pci_dev);
1529
    if (rc != 0) {
1530
        do_pci_unregister_device(pci_dev);
1531
        return rc;
1532
    }
1533

    
1534
    /* rom loading */
1535
    if (pci_dev->romfile == NULL && info->romfile != NULL)
1536
        pci_dev->romfile = qemu_strdup(info->romfile);
1537
    pci_add_option_rom(pci_dev);
1538

    
1539
    if (bus->hotplug) {
1540
        /* lower layer must check qdev->hotplugged */
1541
        rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1542
        if (rc != 0) {
1543
            int r = pci_unregister_device(&pci_dev->qdev);
1544
            assert(!r);
1545
            return rc;
1546
        }
1547
    }
1548
    return 0;
1549
}
1550

    
1551
static int pci_unplug_device(DeviceState *qdev)
1552
{
1553
    PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1554

    
1555
    return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1556
}
1557

    
1558
void pci_qdev_register(PCIDeviceInfo *info)
1559
{
1560
    info->qdev.init = pci_qdev_init;
1561
    info->qdev.unplug = pci_unplug_device;
1562
    info->qdev.exit = pci_unregister_device;
1563
    info->qdev.bus_info = &pci_bus_info;
1564
    qdev_register(&info->qdev);
1565
}
1566

    
1567
void pci_qdev_register_many(PCIDeviceInfo *info)
1568
{
1569
    while (info->qdev.name) {
1570
        pci_qdev_register(info);
1571
        info++;
1572
    }
1573
}
1574

    
1575
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1576
                                    const char *name)
1577
{
1578
    DeviceState *dev;
1579

    
1580
    dev = qdev_create(&bus->qbus, name);
1581
    qdev_prop_set_uint32(dev, "addr", devfn);
1582
    qdev_prop_set_bit(dev, "multifunction", multifunction);
1583
    return DO_UPCAST(PCIDevice, qdev, dev);
1584
}
1585

    
1586
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1587
                                           bool multifunction,
1588
                                           const char *name)
1589
{
1590
    PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1591
    qdev_init_nofail(&dev->qdev);
1592
    return dev;
1593
}
1594

    
1595
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1596
{
1597
    return pci_create_multifunction(bus, devfn, false, name);
1598
}
1599

    
1600
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1601
{
1602
    return pci_create_simple_multifunction(bus, devfn, false, name);
1603
}
1604

    
1605
static int pci_find_space(PCIDevice *pdev, uint8_t size)
1606
{
1607
    int config_size = pci_config_size(pdev);
1608
    int offset = PCI_CONFIG_HEADER_SIZE;
1609
    int i;
1610
    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1611
        if (pdev->used[i])
1612
            offset = i + 1;
1613
        else if (i - offset + 1 == size)
1614
            return offset;
1615
    return 0;
1616
}
1617

    
1618
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1619
                                        uint8_t *prev_p)
1620
{
1621
    uint8_t next, prev;
1622

    
1623
    if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1624
        return 0;
1625

    
1626
    for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1627
         prev = next + PCI_CAP_LIST_NEXT)
1628
        if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1629
            break;
1630

    
1631
    if (prev_p)
1632
        *prev_p = prev;
1633
    return next;
1634
}
1635

    
1636
static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1637
{
1638
    cpu_register_physical_memory(addr, size, pdev->rom_offset);
1639
}
1640

    
1641
/* Add an option rom for the device */
1642
static int pci_add_option_rom(PCIDevice *pdev)
1643
{
1644
    int size;
1645
    char *path;
1646
    void *ptr;
1647
    char name[32];
1648

    
1649
    if (!pdev->romfile)
1650
        return 0;
1651
    if (strlen(pdev->romfile) == 0)
1652
        return 0;
1653

    
1654
    if (!pdev->rom_bar) {
1655
        /*
1656
         * Load rom via fw_cfg instead of creating a rom bar,
1657
         * for 0.11 compatibility.
1658
         */
1659
        int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1660
        if (class == 0x0300) {
1661
            rom_add_vga(pdev->romfile);
1662
        } else {
1663
            rom_add_option(pdev->romfile);
1664
        }
1665
        return 0;
1666
    }
1667

    
1668
    path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1669
    if (path == NULL) {
1670
        path = qemu_strdup(pdev->romfile);
1671
    }
1672

    
1673
    size = get_image_size(path);
1674
    if (size < 0) {
1675
        error_report("%s: failed to find romfile \"%s\"",
1676
                     __FUNCTION__, pdev->romfile);
1677
        return -1;
1678
    }
1679
    if (size & (size - 1)) {
1680
        size = 1 << qemu_fls(size);
1681
    }
1682

    
1683
    if (pdev->qdev.info->vmsd)
1684
        snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1685
    else
1686
        snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1687
    pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1688

    
1689
    ptr = qemu_get_ram_ptr(pdev->rom_offset);
1690
    load_image(path, ptr);
1691
    qemu_free(path);
1692

    
1693
    pci_register_bar(pdev, PCI_ROM_SLOT, size,
1694
                     0, pci_map_option_rom);
1695

    
1696
    return 0;
1697
}
1698

    
1699
static void pci_del_option_rom(PCIDevice *pdev)
1700
{
1701
    if (!pdev->rom_offset)
1702
        return;
1703

    
1704
    qemu_ram_free(pdev->rom_offset);
1705
    pdev->rom_offset = 0;
1706
}
1707

    
1708
/*
1709
 * if !offset
1710
 * Reserve space and add capability to the linked list in pci config space
1711
 *
1712
 * if offset = 0,
1713
 * Find and reserve space and add capability to the linked list
1714
 * in pci config space */
1715
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1716
                       uint8_t offset, uint8_t size)
1717
{
1718
    uint8_t *config;
1719
    if (!offset) {
1720
        offset = pci_find_space(pdev, size);
1721
        if (!offset) {
1722
            return -ENOSPC;
1723
        }
1724
    }
1725

    
1726
    config = pdev->config + offset;
1727
    config[PCI_CAP_LIST_ID] = cap_id;
1728
    config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1729
    pdev->config[PCI_CAPABILITY_LIST] = offset;
1730
    pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1731
    memset(pdev->used + offset, 0xFF, size);
1732
    /* Make capability read-only by default */
1733
    memset(pdev->wmask + offset, 0, size);
1734
    /* Check capability by default */
1735
    memset(pdev->cmask + offset, 0xFF, size);
1736
    return offset;
1737
}
1738

    
1739
/* Unlink capability from the pci config space. */
1740
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1741
{
1742
    uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1743
    if (!offset)
1744
        return;
1745
    pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1746
    /* Make capability writeable again */
1747
    memset(pdev->wmask + offset, 0xff, size);
1748
    memset(pdev->w1cmask + offset, 0, size);
1749
    /* Clear cmask as device-specific registers can't be checked */
1750
    memset(pdev->cmask + offset, 0, size);
1751
    memset(pdev->used + offset, 0, size);
1752

    
1753
    if (!pdev->config[PCI_CAPABILITY_LIST])
1754
        pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1755
}
1756

    
1757
/* Reserve space for capability at a known offset (to call after load). */
1758
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1759
{
1760
    memset(pdev->used + offset, 0xff, size);
1761
}
1762

    
1763
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1764
{
1765
    return pci_find_capability_list(pdev, cap_id, NULL);
1766
}
1767

    
1768
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1769
{
1770
    PCIDevice *d = (PCIDevice *)dev;
1771
    const pci_class_desc *desc;
1772
    char ctxt[64];
1773
    PCIIORegion *r;
1774
    int i, class;
1775

    
1776
    class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1777
    desc = pci_class_descriptions;
1778
    while (desc->desc && class != desc->class)
1779
        desc++;
1780
    if (desc->desc) {
1781
        snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1782
    } else {
1783
        snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1784
    }
1785

    
1786
    monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1787
                   "pci id %04x:%04x (sub %04x:%04x)\n",
1788
                   indent, "", ctxt,
1789
                   d->config[PCI_SECONDARY_BUS],
1790
                   PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1791
                   pci_get_word(d->config + PCI_VENDOR_ID),
1792
                   pci_get_word(d->config + PCI_DEVICE_ID),
1793
                   pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1794
                   pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1795
    for (i = 0; i < PCI_NUM_REGIONS; i++) {
1796
        r = &d->io_regions[i];
1797
        if (!r->size)
1798
            continue;
1799
        monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1800
                       " [0x%"FMT_PCIBUS"]\n",
1801
                       indent, "",
1802
                       i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1803
                       r->addr, r->addr + r->size - 1);
1804
    }
1805
}
1806

    
1807
static char *pcibus_get_dev_path(DeviceState *dev)
1808
{
1809
    PCIDevice *d = (PCIDevice *)dev;
1810
    char path[16];
1811

    
1812
    snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1813
             pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1814
             PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1815

    
1816
    return strdup(path);
1817
}
1818