root / target-sparc / cpu.h @ 1ad2134f
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | af7bf89b | bellard | |
6 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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7 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
8 | af7bf89b | bellard | #define TARGET_FPREGS 32 |
9 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
10 | af7bf89b | bellard | #else
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11 | af7bf89b | bellard | #define TARGET_LONG_BITS 64 |
12 | af7bf89b | bellard | #define TARGET_FPREGS 64 |
13 | 33b37802 | blueswir1 | #define TARGET_PAGE_BITS 13 /* 8k */ |
14 | af7bf89b | bellard | #endif
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15 | 3cf1e035 | bellard | |
16 | c2764719 | pbrook | #define CPUState struct CPUSPARCState |
17 | c2764719 | pbrook | |
18 | 7a3f1944 | bellard | #include "cpu-defs.h" |
19 | 7a3f1944 | bellard | |
20 | 7a0e1f41 | bellard | #include "softfloat.h" |
21 | 7a0e1f41 | bellard | |
22 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
23 | 1fddef4b | bellard | |
24 | 9042c0e2 | ths | #if !defined(TARGET_SPARC64)
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25 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARC
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26 | 9042c0e2 | ths | #else
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27 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARCV9
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28 | 9042c0e2 | ths | #endif
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29 | 9042c0e2 | ths | |
30 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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31 | 7a3f1944 | bellard | |
32 | cf495bcf | bellard | /* trap definitions */
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33 | 3475187d | bellard | #ifndef TARGET_SPARC64
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34 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
35 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
36 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
37 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
38 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
39 | 5fafdf24 | ths | #define TT_WIN_UNF 0x06 |
40 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x07 |
41 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
42 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
43 | e32f879d | blueswir1 | #define TT_TOVF 0x0a |
44 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
45 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x21 |
46 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH 0x25 |
47 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x29 |
48 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
49 | fcc72045 | blueswir1 | #define TT_NCP_INSN 0x24 |
50 | cf495bcf | bellard | #define TT_TRAP 0x80 |
51 | 3475187d | bellard | #else
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52 | 3475187d | bellard | #define TT_TFAULT 0x08 |
53 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x0a |
54 | 3475187d | bellard | #define TT_ILL_INSN 0x10 |
55 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH TT_ILL_INSN
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56 | 3475187d | bellard | #define TT_PRIV_INSN 0x11 |
57 | 3475187d | bellard | #define TT_NFPU_INSN 0x20 |
58 | 3475187d | bellard | #define TT_FP_EXCP 0x21 |
59 | e32f879d | blueswir1 | #define TT_TOVF 0x23 |
60 | 3475187d | bellard | #define TT_CLRWIN 0x24 |
61 | 3475187d | bellard | #define TT_DIV_ZERO 0x28 |
62 | 3475187d | bellard | #define TT_DFAULT 0x30 |
63 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x32 |
64 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x34 |
65 | 83469015 | bellard | #define TT_PRIV_ACT 0x37 |
66 | 3475187d | bellard | #define TT_EXTINT 0x40 |
67 | 74b9decc | blueswir1 | #define TT_IVEC 0x60 |
68 | e19e4efe | blueswir1 | #define TT_TMISS 0x64 |
69 | e19e4efe | blueswir1 | #define TT_DMISS 0x68 |
70 | 74b9decc | blueswir1 | #define TT_DPROT 0x6c |
71 | 3475187d | bellard | #define TT_SPILL 0x80 |
72 | 3475187d | bellard | #define TT_FILL 0xc0 |
73 | 3475187d | bellard | #define TT_WOTHER 0x10 |
74 | 3475187d | bellard | #define TT_TRAP 0x100 |
75 | 3475187d | bellard | #endif
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76 | 7a3f1944 | bellard | |
77 | 4b8b8b76 | blueswir1 | #define PSR_NEG_SHIFT 23 |
78 | 4b8b8b76 | blueswir1 | #define PSR_NEG (1 << PSR_NEG_SHIFT) |
79 | 4b8b8b76 | blueswir1 | #define PSR_ZERO_SHIFT 22 |
80 | 4b8b8b76 | blueswir1 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) |
81 | 4b8b8b76 | blueswir1 | #define PSR_OVF_SHIFT 21 |
82 | 4b8b8b76 | blueswir1 | #define PSR_OVF (1 << PSR_OVF_SHIFT) |
83 | 4b8b8b76 | blueswir1 | #define PSR_CARRY_SHIFT 20 |
84 | 4b8b8b76 | blueswir1 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) |
85 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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86 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
87 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
88 | e8af50a3 | bellard | #define PSR_S (1<<7) |
89 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
90 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
91 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
92 | e8af50a3 | bellard | |
93 | 8393617c | Blue Swirl | #define CC_SRC (env->cc_src)
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94 | 8393617c | Blue Swirl | #define CC_SRC2 (env->cc_src2)
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95 | 8393617c | Blue Swirl | #define CC_DST (env->cc_dst)
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96 | 8393617c | Blue Swirl | #define CC_OP (env->cc_op)
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97 | 8393617c | Blue Swirl | |
98 | 8393617c | Blue Swirl | enum {
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99 | 8393617c | Blue Swirl | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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100 | 8393617c | Blue Swirl | CC_OP_FLAGS, /* all cc are back in status register */
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101 | 8393617c | Blue Swirl | CC_OP_DIV, /* modify N, Z and V, C = 0*/
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102 | 8393617c | Blue Swirl | CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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103 | 8393617c | Blue Swirl | CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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104 | 8393617c | Blue Swirl | CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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105 | 8393617c | Blue Swirl | CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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106 | 8393617c | Blue Swirl | CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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107 | 8393617c | Blue Swirl | CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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108 | 8393617c | Blue Swirl | CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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109 | 8393617c | Blue Swirl | CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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110 | 8393617c | Blue Swirl | CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
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111 | 8393617c | Blue Swirl | CC_OP_NB, |
112 | 8393617c | Blue Swirl | }; |
113 | 8393617c | Blue Swirl | |
114 | e8af50a3 | bellard | /* Trap base register */
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115 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
116 | e8af50a3 | bellard | |
117 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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118 | 83469015 | bellard | #define PS_IG (1<<11) |
119 | 83469015 | bellard | #define PS_MG (1<<10) |
120 | 6ef905f6 | blueswir1 | #define PS_RMO (1<<7) |
121 | 83469015 | bellard | #define PS_RED (1<<5) |
122 | 3475187d | bellard | #define PS_PEF (1<<4) |
123 | 3475187d | bellard | #define PS_AM (1<<3) |
124 | 3475187d | bellard | #define PS_PRIV (1<<2) |
125 | 3475187d | bellard | #define PS_IE (1<<1) |
126 | 83469015 | bellard | #define PS_AG (1<<0) |
127 | a80dde08 | bellard | |
128 | a80dde08 | bellard | #define FPRS_FEF (1<<2) |
129 | 6f27aba6 | blueswir1 | |
130 | 6f27aba6 | blueswir1 | #define HS_PRIV (1<<2) |
131 | 3475187d | bellard | #endif
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132 | 3475187d | bellard | |
133 | e8af50a3 | bellard | /* Fcc */
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134 | ba6a9d8c | blueswir1 | #define FSR_RD1 (1ULL << 31) |
135 | ba6a9d8c | blueswir1 | #define FSR_RD0 (1ULL << 30) |
136 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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137 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
138 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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139 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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140 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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141 | e8af50a3 | bellard | |
142 | ba6a9d8c | blueswir1 | #define FSR_NVM (1ULL << 27) |
143 | ba6a9d8c | blueswir1 | #define FSR_OFM (1ULL << 26) |
144 | ba6a9d8c | blueswir1 | #define FSR_UFM (1ULL << 25) |
145 | ba6a9d8c | blueswir1 | #define FSR_DZM (1ULL << 24) |
146 | ba6a9d8c | blueswir1 | #define FSR_NXM (1ULL << 23) |
147 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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148 | e8af50a3 | bellard | |
149 | ba6a9d8c | blueswir1 | #define FSR_NVA (1ULL << 9) |
150 | ba6a9d8c | blueswir1 | #define FSR_OFA (1ULL << 8) |
151 | ba6a9d8c | blueswir1 | #define FSR_UFA (1ULL << 7) |
152 | ba6a9d8c | blueswir1 | #define FSR_DZA (1ULL << 6) |
153 | ba6a9d8c | blueswir1 | #define FSR_NXA (1ULL << 5) |
154 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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155 | e8af50a3 | bellard | |
156 | ba6a9d8c | blueswir1 | #define FSR_NVC (1ULL << 4) |
157 | ba6a9d8c | blueswir1 | #define FSR_OFC (1ULL << 3) |
158 | ba6a9d8c | blueswir1 | #define FSR_UFC (1ULL << 2) |
159 | ba6a9d8c | blueswir1 | #define FSR_DZC (1ULL << 1) |
160 | ba6a9d8c | blueswir1 | #define FSR_NXC (1ULL << 0) |
161 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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162 | e8af50a3 | bellard | |
163 | ba6a9d8c | blueswir1 | #define FSR_FTT2 (1ULL << 16) |
164 | ba6a9d8c | blueswir1 | #define FSR_FTT1 (1ULL << 15) |
165 | ba6a9d8c | blueswir1 | #define FSR_FTT0 (1ULL << 14) |
166 | 47ad35f1 | blueswir1 | //gcc warns about constant overflow for ~FSR_FTT_MASK
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167 | 47ad35f1 | blueswir1 | //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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168 | 47ad35f1 | blueswir1 | #ifdef TARGET_SPARC64
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169 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffffffffffe3fffULL |
170 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL |
171 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
172 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL |
173 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL |
174 | 47ad35f1 | blueswir1 | #else
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175 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffe3fffULL |
176 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL |
177 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x000fc000ULL |
178 | 47ad35f1 | blueswir1 | #endif
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179 | 3a3b925d | blueswir1 | #define FSR_LDFSR_MASK 0xcfc00fffULL |
180 | ba6a9d8c | blueswir1 | #define FSR_FTT_IEEE_EXCP (1ULL << 14) |
181 | ba6a9d8c | blueswir1 | #define FSR_FTT_UNIMPFPOP (3ULL << 14) |
182 | ba6a9d8c | blueswir1 | #define FSR_FTT_SEQ_ERROR (4ULL << 14) |
183 | ba6a9d8c | blueswir1 | #define FSR_FTT_INVAL_FPR (6ULL << 14) |
184 | e8af50a3 | bellard | |
185 | 4b8b8b76 | blueswir1 | #define FSR_FCC1_SHIFT 11 |
186 | ba6a9d8c | blueswir1 | #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) |
187 | 4b8b8b76 | blueswir1 | #define FSR_FCC0_SHIFT 10 |
188 | ba6a9d8c | blueswir1 | #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) |
189 | e8af50a3 | bellard | |
190 | e8af50a3 | bellard | /* MMU */
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191 | 0f8a249a | blueswir1 | #define MMU_E (1<<0) |
192 | 0f8a249a | blueswir1 | #define MMU_NF (1<<1) |
193 | e8af50a3 | bellard | |
194 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
195 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
196 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
197 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
198 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
199 | e8af50a3 | bellard | |
200 | 0f8a249a | blueswir1 | #define PG_ACCESSED_BIT 5 |
201 | 0f8a249a | blueswir1 | #define PG_MODIFIED_BIT 6 |
202 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
203 | e8af50a3 | bellard | |
204 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
205 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
206 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
207 | e8af50a3 | bellard | |
208 | 1a14026e | blueswir1 | /* 3 <= NWINDOWS <= 32. */
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209 | 1a14026e | blueswir1 | #define MIN_NWINDOWS 3 |
210 | 1a14026e | blueswir1 | #define MAX_NWINDOWS 32 |
211 | cf495bcf | bellard | |
212 | 6f27aba6 | blueswir1 | #if !defined(TARGET_SPARC64)
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213 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
214 | 6f27aba6 | blueswir1 | #else
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215 | 6f27aba6 | blueswir1 | #define NB_MMU_MODES 3 |
216 | 375ee38b | blueswir1 | typedef struct trap_state { |
217 | 375ee38b | blueswir1 | uint64_t tpc; |
218 | 375ee38b | blueswir1 | uint64_t tnpc; |
219 | 375ee38b | blueswir1 | uint64_t tstate; |
220 | 375ee38b | blueswir1 | uint32_t tt; |
221 | 375ee38b | blueswir1 | } trap_state; |
222 | 6f27aba6 | blueswir1 | #endif
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223 | 6ebbf390 | j_mayer | |
224 | 5578ceab | blueswir1 | typedef struct sparc_def_t { |
225 | 5578ceab | blueswir1 | const char *name; |
226 | 5578ceab | blueswir1 | target_ulong iu_version; |
227 | 5578ceab | blueswir1 | uint32_t fpu_version; |
228 | 5578ceab | blueswir1 | uint32_t mmu_version; |
229 | 5578ceab | blueswir1 | uint32_t mmu_bm; |
230 | 5578ceab | blueswir1 | uint32_t mmu_ctpr_mask; |
231 | 5578ceab | blueswir1 | uint32_t mmu_cxr_mask; |
232 | 5578ceab | blueswir1 | uint32_t mmu_sfsr_mask; |
233 | 5578ceab | blueswir1 | uint32_t mmu_trcr_mask; |
234 | 963262de | blueswir1 | uint32_t mxcc_version; |
235 | 5578ceab | blueswir1 | uint32_t features; |
236 | 5578ceab | blueswir1 | uint32_t nwindows; |
237 | 5578ceab | blueswir1 | uint32_t maxtl; |
238 | 5578ceab | blueswir1 | } sparc_def_t; |
239 | 5578ceab | blueswir1 | |
240 | 5578ceab | blueswir1 | #define CPU_FEATURE_FLOAT (1 << 0) |
241 | 5578ceab | blueswir1 | #define CPU_FEATURE_FLOAT128 (1 << 1) |
242 | 5578ceab | blueswir1 | #define CPU_FEATURE_SWAP (1 << 2) |
243 | 5578ceab | blueswir1 | #define CPU_FEATURE_MUL (1 << 3) |
244 | 5578ceab | blueswir1 | #define CPU_FEATURE_DIV (1 << 4) |
245 | 5578ceab | blueswir1 | #define CPU_FEATURE_FLUSH (1 << 5) |
246 | 5578ceab | blueswir1 | #define CPU_FEATURE_FSQRT (1 << 6) |
247 | 5578ceab | blueswir1 | #define CPU_FEATURE_FMUL (1 << 7) |
248 | 5578ceab | blueswir1 | #define CPU_FEATURE_VIS1 (1 << 8) |
249 | 5578ceab | blueswir1 | #define CPU_FEATURE_VIS2 (1 << 9) |
250 | 5578ceab | blueswir1 | #define CPU_FEATURE_FSMULD (1 << 10) |
251 | 5578ceab | blueswir1 | #define CPU_FEATURE_HYPV (1 << 11) |
252 | 5578ceab | blueswir1 | #define CPU_FEATURE_CMT (1 << 12) |
253 | 5578ceab | blueswir1 | #define CPU_FEATURE_GL (1 << 13) |
254 | 5578ceab | blueswir1 | #ifndef TARGET_SPARC64
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255 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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256 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
257 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
258 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) |
259 | 5578ceab | blueswir1 | #else
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260 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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261 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
262 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
263 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ |
264 | 5578ceab | blueswir1 | CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) |
265 | 5578ceab | blueswir1 | enum {
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266 | 5578ceab | blueswir1 | mmu_us_12, // Ultrasparc < III (64 entry TLB)
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267 | 5578ceab | blueswir1 | mmu_us_3, // Ultrasparc III (512 entry TLB)
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268 | 5578ceab | blueswir1 | mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
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269 | 5578ceab | blueswir1 | mmu_sun4v, // T1, T2
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270 | 5578ceab | blueswir1 | }; |
271 | 5578ceab | blueswir1 | #endif
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272 | 5578ceab | blueswir1 | |
273 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
274 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
275 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
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276 | af7bf89b | bellard | target_ulong pc; /* program counter */
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277 | af7bf89b | bellard | target_ulong npc; /* next program counter */
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278 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
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279 | dc99a3f2 | blueswir1 | |
280 | dc99a3f2 | blueswir1 | /* emulator internal flags handling */
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281 | d9bdab86 | blueswir1 | target_ulong cc_src, cc_src2; |
282 | dc99a3f2 | blueswir1 | target_ulong cc_dst; |
283 | 8393617c | Blue Swirl | uint32_t cc_op; |
284 | dc99a3f2 | blueswir1 | |
285 | 7c60cc4b | bellard | target_ulong t0, t1; /* temporaries live across basic blocks */
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286 | 7c60cc4b | bellard | target_ulong cond; /* conditional branch result (XXX: save it in a
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287 | 7c60cc4b | bellard | temporary register when possible) */
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288 | 7c60cc4b | bellard | |
289 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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290 | 3475187d | bellard | target_ulong fsr; /* FPU state register */
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291 | 7c60cc4b | bellard | float32 fpr[TARGET_FPREGS]; /* floating point registers */
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292 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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293 | cf495bcf | bellard | from PSR) */
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294 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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295 | 3475187d | bellard | target_ulong tbr; /* trap base register */
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296 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
297 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
298 | e8af50a3 | bellard | int psret; /* enable traps */ |
299 | 327ac2e7 | blueswir1 | uint32_t psrpil; /* interrupt blocking level */
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300 | 327ac2e7 | blueswir1 | uint32_t pil_in; /* incoming interrupt level bitmap */
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301 | e80cfcfc | bellard | int psref; /* enable fpu */ |
302 | 62724a37 | blueswir1 | target_ulong version; |
303 | cf495bcf | bellard | int interrupt_index;
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304 | 1a14026e | blueswir1 | uint32_t nwindows; |
305 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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306 | 1a14026e | blueswir1 | target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
307 | d720b93d | bellard | |
308 | a316d335 | bellard | CPU_COMMON |
309 | a316d335 | bellard | |
310 | e8af50a3 | bellard | /* MMU regs */
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311 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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312 | 3475187d | bellard | uint64_t lsu; |
313 | 3475187d | bellard | #define DMMU_E 0x8 |
314 | 3475187d | bellard | #define IMMU_E 0x4 |
315 | 3475187d | bellard | uint64_t immuregs[16];
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316 | 3475187d | bellard | uint64_t dmmuregs[16];
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317 | 3475187d | bellard | uint64_t itlb_tag[64];
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318 | 3475187d | bellard | uint64_t itlb_tte[64];
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319 | 3475187d | bellard | uint64_t dtlb_tag[64];
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320 | 3475187d | bellard | uint64_t dtlb_tte[64];
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321 | fb79ceb9 | blueswir1 | uint32_t mmu_version; |
322 | 3475187d | bellard | #else
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323 | 3dd9a152 | blueswir1 | uint32_t mmuregs[32];
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324 | 952a328f | blueswir1 | uint64_t mxccdata[4];
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325 | 952a328f | blueswir1 | uint64_t mxccregs[8];
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326 | 4017190e | blueswir1 | uint64_t mmubpregs[4];
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327 | 3ebf5aaf | blueswir1 | uint64_t prom_addr; |
328 | 3475187d | bellard | #endif
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329 | e8af50a3 | bellard | /* temporary float registers */
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330 | 65ce8c2f | bellard | float64 dt0, dt1; |
331 | 1f587329 | blueswir1 | float128 qt0, qt1; |
332 | 7a0e1f41 | bellard | float_status fp_status; |
333 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
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334 | c19148bd | blueswir1 | #define MAXTL_MAX 8 |
335 | c19148bd | blueswir1 | #define MAXTL_MASK (MAXTL_MAX - 1) |
336 | 375ee38b | blueswir1 | trap_state *tsptr; |
337 | c19148bd | blueswir1 | trap_state ts[MAXTL_MAX]; |
338 | 0f8a249a | blueswir1 | uint32_t xcc; /* Extended integer condition codes */
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339 | 3475187d | bellard | uint32_t asi; |
340 | 3475187d | bellard | uint32_t pstate; |
341 | 3475187d | bellard | uint32_t tl; |
342 | c19148bd | blueswir1 | uint32_t maxtl; |
343 | 3475187d | bellard | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
344 | 83469015 | bellard | uint64_t agregs[8]; /* alternate general registers */ |
345 | 83469015 | bellard | uint64_t bgregs[8]; /* backup for normal global registers */ |
346 | 83469015 | bellard | uint64_t igregs[8]; /* interrupt general registers */ |
347 | 83469015 | bellard | uint64_t mgregs[8]; /* mmu general registers */ |
348 | 3475187d | bellard | uint64_t fprs; |
349 | 83469015 | bellard | uint64_t tick_cmpr, stick_cmpr; |
350 | 20c9f095 | blueswir1 | void *tick, *stick;
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351 | 725cb90b | bellard | uint64_t gsr; |
352 | e9ebed4d | blueswir1 | uint32_t gl; // UA2005
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353 | e9ebed4d | blueswir1 | /* UA 2005 hyperprivileged registers */
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354 | c19148bd | blueswir1 | uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
355 | 20c9f095 | blueswir1 | void *hstick; // UA 2005 |
356 | 9d926598 | blueswir1 | uint32_t softint; |
357 | 8fa211e8 | blueswir1 | #define SOFTINT_TIMER 1 |
358 | 8fa211e8 | blueswir1 | #define SOFTINT_STIMER (1 << 16) |
359 | 3475187d | bellard | #endif
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360 | 5578ceab | blueswir1 | sparc_def_t *def; |
361 | 7a3f1944 | bellard | } CPUSPARCState; |
362 | 64a88d5d | blueswir1 | |
363 | 91736d37 | blueswir1 | /* helper.c */
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364 | aaed909a | bellard | CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
365 | 91736d37 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
366 | 62724a37 | blueswir1 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
367 | 62724a37 | blueswir1 | ...)); |
368 | 48585ec5 | blueswir1 | void cpu_lock(void); |
369 | 48585ec5 | blueswir1 | void cpu_unlock(void); |
370 | 48585ec5 | blueswir1 | int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, |
371 | 48585ec5 | blueswir1 | int mmu_idx, int is_softmmu); |
372 | 48585ec5 | blueswir1 | target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
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373 | 48585ec5 | blueswir1 | void dump_mmu(CPUSPARCState *env);
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374 | 91736d37 | blueswir1 | |
375 | 91736d37 | blueswir1 | /* translate.c */
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376 | 91736d37 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env);
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377 | 91736d37 | blueswir1 | |
378 | 91736d37 | blueswir1 | /* cpu-exec.c */
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379 | 91736d37 | blueswir1 | int cpu_sparc_exec(CPUSPARCState *s);
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380 | 7a3f1944 | bellard | |
381 | 62724a37 | blueswir1 | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
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382 | 0f8a249a | blueswir1 | (env->psref? PSR_EF : 0) | \
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383 | 0f8a249a | blueswir1 | (env->psrpil << 8) | \
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384 | 0f8a249a | blueswir1 | (env->psrs? PSR_S : 0) | \
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385 | 0f8a249a | blueswir1 | (env->psrps? PSR_PS : 0) | \
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386 | 0f8a249a | blueswir1 | (env->psret? PSR_ET : 0) | env->cwp)
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387 | b4ff5987 | bellard | |
388 | b4ff5987 | bellard | #ifndef NO_CPU_IO_DEFS
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389 | 91736d37 | blueswir1 | static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
390 | 91736d37 | blueswir1 | { |
391 | 91736d37 | blueswir1 | dst[0] = src[0]; |
392 | 91736d37 | blueswir1 | dst[1] = src[1]; |
393 | 91736d37 | blueswir1 | dst[2] = src[2]; |
394 | 91736d37 | blueswir1 | dst[3] = src[3]; |
395 | 91736d37 | blueswir1 | dst[4] = src[4]; |
396 | 91736d37 | blueswir1 | dst[5] = src[5]; |
397 | 91736d37 | blueswir1 | dst[6] = src[6]; |
398 | 91736d37 | blueswir1 | dst[7] = src[7]; |
399 | 91736d37 | blueswir1 | } |
400 | 91736d37 | blueswir1 | |
401 | 91736d37 | blueswir1 | static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp) |
402 | 91736d37 | blueswir1 | { |
403 | 91736d37 | blueswir1 | /* put the modified wrap registers at their proper location */
|
404 | 91736d37 | blueswir1 | if (env1->cwp == env1->nwindows - 1) |
405 | 91736d37 | blueswir1 | memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
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406 | 91736d37 | blueswir1 | env1->cwp = new_cwp; |
407 | 91736d37 | blueswir1 | /* put the wrap registers at their temporary location */
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408 | 91736d37 | blueswir1 | if (new_cwp == env1->nwindows - 1) |
409 | 91736d37 | blueswir1 | memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
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410 | 91736d37 | blueswir1 | env1->regwptr = env1->regbase + (new_cwp * 16);
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411 | 91736d37 | blueswir1 | } |
412 | 1a14026e | blueswir1 | |
413 | 1a14026e | blueswir1 | static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) |
414 | 1a14026e | blueswir1 | { |
415 | 1a14026e | blueswir1 | if (unlikely(cwp >= env1->nwindows))
|
416 | 1a14026e | blueswir1 | cwp -= env1->nwindows; |
417 | 1a14026e | blueswir1 | return cwp;
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418 | 1a14026e | blueswir1 | } |
419 | 1a14026e | blueswir1 | |
420 | 1a14026e | blueswir1 | static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) |
421 | 1a14026e | blueswir1 | { |
422 | 1a14026e | blueswir1 | if (unlikely(cwp < 0)) |
423 | 1a14026e | blueswir1 | cwp += env1->nwindows; |
424 | 1a14026e | blueswir1 | return cwp;
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425 | 1a14026e | blueswir1 | } |
426 | b4ff5987 | bellard | #endif
|
427 | b4ff5987 | bellard | |
428 | 0f8a249a | blueswir1 | #define PUT_PSR(env, val) do { int _tmp = val; \ |
429 | 0f8a249a | blueswir1 | env->psr = _tmp & PSR_ICC; \ |
430 | 0f8a249a | blueswir1 | env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
431 | 0f8a249a | blueswir1 | env->psrpil = (_tmp & PSR_PIL) >> 8; \
|
432 | 0f8a249a | blueswir1 | env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
433 | 0f8a249a | blueswir1 | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
434 | 0f8a249a | blueswir1 | env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
435 | d4218d99 | blueswir1 | cpu_set_cwp(env, _tmp & PSR_CWP); \ |
436 | 8393617c | Blue Swirl | CC_OP = CC_OP_FLAGS; \ |
437 | b4ff5987 | bellard | } while (0) |
438 | b4ff5987 | bellard | |
439 | 3475187d | bellard | #ifdef TARGET_SPARC64
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440 | 17d996e1 | blueswir1 | #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
441 | 0f8a249a | blueswir1 | #define PUT_CCR(env, val) do { int _tmp = val; \ |
442 | 77f193da | blueswir1 | env->xcc = (_tmp >> 4) << 20; \ |
443 | 0f8a249a | blueswir1 | env->psr = (_tmp & 0xf) << 20; \ |
444 | 8393617c | Blue Swirl | CC_OP = CC_OP_FLAGS; \ |
445 | 3475187d | bellard | } while (0) |
446 | 1a14026e | blueswir1 | #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp) |
447 | 1a14026e | blueswir1 | |
448 | 0bbd4a0d | blueswir1 | #ifndef NO_CPU_IO_DEFS
|
449 | 1a14026e | blueswir1 | static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) |
450 | 1a14026e | blueswir1 | { |
451 | 1a14026e | blueswir1 | if (unlikely(cwp >= env1->nwindows || cwp < 0)) |
452 | 1a14026e | blueswir1 | cwp = 0;
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453 | 1a14026e | blueswir1 | cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
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454 | 1a14026e | blueswir1 | } |
455 | 0bbd4a0d | blueswir1 | #endif
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456 | 3475187d | bellard | #endif
|
457 | 3475187d | bellard | |
458 | 91736d37 | blueswir1 | /* cpu-exec.c */
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459 | 5dcb6b91 | blueswir1 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
460 | e18231a3 | blueswir1 | int is_asi, int size); |
461 | f0d5e471 | blueswir1 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
462 | 7a3f1944 | bellard | |
463 | 9467d44c | ths | #define cpu_init cpu_sparc_init
|
464 | 9467d44c | ths | #define cpu_exec cpu_sparc_exec
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465 | 9467d44c | ths | #define cpu_gen_code cpu_sparc_gen_code
|
466 | 9467d44c | ths | #define cpu_signal_handler cpu_sparc_signal_handler
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467 | c732abe2 | j_mayer | #define cpu_list sparc_cpu_list
|
468 | 9467d44c | ths | |
469 | 0b8f1b10 | blueswir1 | #define CPU_SAVE_VERSION 5 |
470 | b3c7724c | pbrook | |
471 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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472 | 6f27aba6 | blueswir1 | #define MMU_MODE0_SUFFIX _user
|
473 | 6f27aba6 | blueswir1 | #define MMU_MODE1_SUFFIX _kernel
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474 | 6f27aba6 | blueswir1 | #ifdef TARGET_SPARC64
|
475 | 6f27aba6 | blueswir1 | #define MMU_MODE2_SUFFIX _hypv
|
476 | 6f27aba6 | blueswir1 | #endif
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477 | 9e31b9e2 | blueswir1 | #define MMU_USER_IDX 0 |
478 | 9e31b9e2 | blueswir1 | #define MMU_KERNEL_IDX 1 |
479 | 9e31b9e2 | blueswir1 | #define MMU_HYPV_IDX 2 |
480 | 9e31b9e2 | blueswir1 | |
481 | 22548760 | blueswir1 | static inline int cpu_mmu_index(CPUState *env1) |
482 | 6ebbf390 | j_mayer | { |
483 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
484 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
|
485 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
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486 | 22548760 | blueswir1 | return env1->psrs;
|
487 | 6f27aba6 | blueswir1 | #else
|
488 | 22548760 | blueswir1 | if (!env1->psrs)
|
489 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
|
490 | 22548760 | blueswir1 | else if ((env1->hpstate & HS_PRIV) == 0) |
491 | 9e31b9e2 | blueswir1 | return MMU_KERNEL_IDX;
|
492 | 6f27aba6 | blueswir1 | else
|
493 | 9e31b9e2 | blueswir1 | return MMU_HYPV_IDX;
|
494 | 6f27aba6 | blueswir1 | #endif
|
495 | 6f27aba6 | blueswir1 | } |
496 | 6f27aba6 | blueswir1 | |
497 | 22548760 | blueswir1 | static inline int cpu_fpu_enabled(CPUState *env1) |
498 | 6f27aba6 | blueswir1 | { |
499 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
500 | 6f27aba6 | blueswir1 | return 1; |
501 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
|
502 | 22548760 | blueswir1 | return env1->psref;
|
503 | 6f27aba6 | blueswir1 | #else
|
504 | 22548760 | blueswir1 | return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0); |
505 | 6f27aba6 | blueswir1 | #endif
|
506 | 6ebbf390 | j_mayer | } |
507 | 6ebbf390 | j_mayer | |
508 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
|
509 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
510 | 6e68e076 | pbrook | { |
511 | f8ed7070 | pbrook | if (newsp)
|
512 | 6e68e076 | pbrook | env->regwptr[22] = newsp;
|
513 | 6e68e076 | pbrook | env->regwptr[0] = 0; |
514 | 6e68e076 | pbrook | /* FIXME: Do we also need to clear CF? */
|
515 | 6e68e076 | pbrook | /* XXXXX */
|
516 | 6e68e076 | pbrook | printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
|
517 | 6e68e076 | pbrook | } |
518 | 6e68e076 | pbrook | #endif
|
519 | 6e68e076 | pbrook | |
520 | 7a3f1944 | bellard | #include "cpu-all.h" |
521 | 622ed360 | aliguori | #include "exec-all.h" |
522 | 7a3f1944 | bellard | |
523 | 48585ec5 | blueswir1 | /* sum4m.c, sun4u.c */
|
524 | 48585ec5 | blueswir1 | void cpu_check_irqs(CPUSPARCState *env);
|
525 | 48585ec5 | blueswir1 | |
526 | f4b1a842 | blueswir1 | #ifdef TARGET_SPARC64
|
527 | f4b1a842 | blueswir1 | /* sun4u.c */
|
528 | f4b1a842 | blueswir1 | void cpu_tick_set_count(void *opaque, uint64_t count); |
529 | f4b1a842 | blueswir1 | uint64_t cpu_tick_get_count(void *opaque);
|
530 | f4b1a842 | blueswir1 | void cpu_tick_set_limit(void *opaque, uint64_t limit); |
531 | f4b1a842 | blueswir1 | #endif
|
532 | f4b1a842 | blueswir1 | |
533 | 622ed360 | aliguori | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
534 | 622ed360 | aliguori | { |
535 | 622ed360 | aliguori | env->pc = tb->pc; |
536 | 622ed360 | aliguori | env->npc = tb->cs_base; |
537 | 622ed360 | aliguori | } |
538 | 622ed360 | aliguori | |
539 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
540 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
541 | 6b917547 | aliguori | { |
542 | 6b917547 | aliguori | *pc = env->pc; |
543 | 6b917547 | aliguori | *cs_base = env->npc; |
544 | 6b917547 | aliguori | #ifdef TARGET_SPARC64
|
545 | 6b917547 | aliguori | // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
|
546 | 6b917547 | aliguori | *flags = ((env->pstate & PS_AM) << 2)
|
547 | 6b917547 | aliguori | | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) |
548 | 6b917547 | aliguori | | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
|
549 | 6b917547 | aliguori | #else
|
550 | 6b917547 | aliguori | // FPU enable . Supervisor
|
551 | 6b917547 | aliguori | *flags = (env->psref << 4) | env->psrs;
|
552 | 6b917547 | aliguori | #endif
|
553 | 6b917547 | aliguori | } |
554 | 6b917547 | aliguori | |
555 | 7a3f1944 | bellard | #endif |