Revision 1b050077
| b/target-i386/cpu.h | ||
|---|---|---|
| 322 | 322 |
#define MSR_FSBASE 0xc0000100 |
| 323 | 323 |
#define MSR_GSBASE 0xc0000101 |
| 324 | 324 |
#define MSR_KERNELGSBASE 0xc0000102 |
| 325 |
#define MSR_TSC_AUX 0xc0000103 |
|
| 325 | 326 |
|
| 326 | 327 |
#define MSR_VM_HSAVE_PA 0xc0010117 |
| 327 | 328 |
|
| ... | ... | |
| 694 | 695 |
uint64 mcg_status; |
| 695 | 696 |
uint64 mcg_ctl; |
| 696 | 697 |
uint64 *mce_banks; |
| 698 |
|
|
| 699 |
uint64_t tsc_aux; |
|
| 697 | 700 |
} CPUX86State; |
| 698 | 701 |
|
| 699 | 702 |
CPUX86State *cpu_x86_init(const char *cpu_model); |
| ... | ... | |
| 854 | 857 |
#define cpu_signal_handler cpu_x86_signal_handler |
| 855 | 858 |
#define cpu_list x86_cpu_list |
| 856 | 859 |
|
| 857 |
#define CPU_SAVE_VERSION 10
|
|
| 860 |
#define CPU_SAVE_VERSION 11
|
|
| 858 | 861 |
|
| 859 | 862 |
/* MMU modes definitions */ |
| 860 | 863 |
#define MMU_MODE0_SUFFIX _kernel |
| b/target-i386/helper.h | ||
|---|---|---|
| 80 | 80 |
DEF_HELPER_0(single_step, void) |
| 81 | 81 |
DEF_HELPER_0(cpuid, void) |
| 82 | 82 |
DEF_HELPER_0(rdtsc, void) |
| 83 |
DEF_HELPER_0(rdtscp, void) |
|
| 83 | 84 |
DEF_HELPER_0(rdpmc, void) |
| 84 | 85 |
DEF_HELPER_0(rdmsr, void) |
| 85 | 86 |
DEF_HELPER_0(wrmsr, void) |
| b/target-i386/machine.c | ||
|---|---|---|
| 171 | 171 |
qemu_put_be64s(f, &env->mce_banks[4*i + 3]); |
| 172 | 172 |
} |
| 173 | 173 |
} |
| 174 |
qemu_put_be64s(f, &env->tsc_aux); |
|
| 174 | 175 |
} |
| 175 | 176 |
|
| 176 | 177 |
#ifdef USE_X86LDOUBLE |
| ... | ... | |
| 377 | 378 |
} |
| 378 | 379 |
} |
| 379 | 380 |
|
| 381 |
if (version_id >= 11) {
|
|
| 382 |
qemu_get_be64s(f, &env->tsc_aux); |
|
| 383 |
} |
|
| 380 | 384 |
/* XXX: ensure compatiblity for halted bit ? */ |
| 381 | 385 |
/* XXX: compute redundant hflags bits */ |
| 382 | 386 |
env->hflags = hflags; |
| b/target-i386/op_helper.c | ||
|---|---|---|
| 2969 | 2969 |
EDX = (uint32_t)(val >> 32); |
| 2970 | 2970 |
} |
| 2971 | 2971 |
|
| 2972 |
void helper_rdtscp(void) |
|
| 2973 |
{
|
|
| 2974 |
helper_rdtsc(); |
|
| 2975 |
ECX = (uint32_t)(env->tsc_aux); |
|
| 2976 |
} |
|
| 2977 |
|
|
| 2972 | 2978 |
void helper_rdpmc(void) |
| 2973 | 2979 |
{
|
| 2974 | 2980 |
if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
|
| ... | ... | |
| 3107 | 3113 |
&& (val == 0 || val == ~(uint64_t)0)) |
| 3108 | 3114 |
env->mcg_ctl = val; |
| 3109 | 3115 |
break; |
| 3116 |
case MSR_TSC_AUX: |
|
| 3117 |
env->tsc_aux = val; |
|
| 3118 |
break; |
|
| 3110 | 3119 |
default: |
| 3111 | 3120 |
if ((uint32_t)ECX >= MSR_MC0_CTL |
| 3112 | 3121 |
&& (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
|
| ... | ... | |
| 3177 | 3186 |
case MSR_KERNELGSBASE: |
| 3178 | 3187 |
val = env->kernelgsbase; |
| 3179 | 3188 |
break; |
| 3189 |
case MSR_TSC_AUX: |
|
| 3190 |
val = env->tsc_aux; |
|
| 3191 |
break; |
|
| 3180 | 3192 |
#endif |
| 3181 | 3193 |
case MSR_MTRRphysBase(0): |
| 3182 | 3194 |
case MSR_MTRRphysBase(1): |
| b/target-i386/translate.c | ||
|---|---|---|
| 7206 | 7206 |
gen_eob(s); |
| 7207 | 7207 |
} |
| 7208 | 7208 |
break; |
| 7209 |
case 7: /* invlpg */ |
|
| 7210 |
if (s->cpl != 0) {
|
|
| 7211 |
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
|
| 7209 |
case 7: |
|
| 7210 |
if (mod != 3) { /* invlpg */
|
|
| 7211 |
if (s->cpl != 0) {
|
|
| 7212 |
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
|
| 7213 |
} else {
|
|
| 7214 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 7215 |
gen_op_set_cc_op(s->cc_op); |
|
| 7216 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 7217 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
|
| 7218 |
gen_helper_invlpg(cpu_A0); |
|
| 7219 |
gen_jmp_im(s->pc - s->cs_base); |
|
| 7220 |
gen_eob(s); |
|
| 7221 |
} |
|
| 7212 | 7222 |
} else {
|
| 7213 |
if (mod == 3) {
|
|
| 7223 |
switch (rm) {
|
|
| 7224 |
case 0: /* swapgs */ |
|
| 7214 | 7225 |
#ifdef TARGET_X86_64 |
| 7215 |
if (CODE64(s) && rm == 0) {
|
|
| 7216 |
/* swapgs */ |
|
| 7217 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); |
|
| 7218 |
tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase)); |
|
| 7219 |
tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); |
|
| 7220 |
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase)); |
|
| 7226 |
if (CODE64(s)) {
|
|
| 7227 |
if (s->cpl != 0) {
|
|
| 7228 |
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
|
| 7229 |
} else {
|
|
| 7230 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, |
|
| 7231 |
offsetof(CPUX86State,segs[R_GS].base)); |
|
| 7232 |
tcg_gen_ld_tl(cpu_T[1], cpu_env, |
|
| 7233 |
offsetof(CPUX86State,kernelgsbase)); |
|
| 7234 |
tcg_gen_st_tl(cpu_T[1], cpu_env, |
|
| 7235 |
offsetof(CPUX86State,segs[R_GS].base)); |
|
| 7236 |
tcg_gen_st_tl(cpu_T[0], cpu_env, |
|
| 7237 |
offsetof(CPUX86State,kernelgsbase)); |
|
| 7238 |
} |
|
| 7221 | 7239 |
} else |
| 7222 | 7240 |
#endif |
| 7223 | 7241 |
{
|
| 7224 | 7242 |
goto illegal_op; |
| 7225 | 7243 |
} |
| 7226 |
} else {
|
|
| 7244 |
break; |
|
| 7245 |
case 1: /* rdtscp */ |
|
| 7246 |
if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) |
|
| 7247 |
goto illegal_op; |
|
| 7227 | 7248 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 7228 | 7249 |
gen_op_set_cc_op(s->cc_op); |
| 7229 | 7250 |
gen_jmp_im(pc_start - s->cs_base); |
| 7230 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
|
| 7231 |
gen_helper_invlpg(cpu_A0); |
|
| 7232 |
gen_jmp_im(s->pc - s->cs_base); |
|
| 7233 |
gen_eob(s); |
|
| 7251 |
if (use_icount) |
|
| 7252 |
gen_io_start(); |
|
| 7253 |
gen_helper_rdtscp(); |
|
| 7254 |
if (use_icount) {
|
|
| 7255 |
gen_io_end(); |
|
| 7256 |
gen_jmp(s, s->pc - s->cs_base); |
|
| 7257 |
} |
|
| 7258 |
break; |
|
| 7259 |
default: |
|
| 7260 |
goto illegal_op; |
|
| 7234 | 7261 |
} |
| 7235 | 7262 |
} |
| 7236 | 7263 |
break; |
Also available in: Unified diff