Revision 1b2b0af5
| b/fpu/softfloat-native.c | ||
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| 23 | 23 |
#endif |
| 24 | 24 |
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#if defined(_BSD) |
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#define lrint(d) ((int32_t)rint(d))
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#define llrint(d) ((int64_t)rint(d))
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#define lrint(d) ((long)rint(d))
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#define llrint(d) ((long long)rint(d))
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| 28 | 28 |
#endif |
| 29 | 29 |
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| 30 | 30 |
#if defined(__powerpc__) |
| ... | ... | |
| 80 | 80 |
} |
| 81 | 81 |
#endif |
| 82 | 82 |
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/* XXX: this code implements the x86 behaviour, not the IEEE one. */ |
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#if HOST_LONG_BITS == 32 |
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static inline int long_to_int32(long a) |
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{
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return a; |
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} |
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#else |
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static inline int long_to_int32(long a) |
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{
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if (a != (int32_t)a) |
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a = 0x80000000; |
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return a; |
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} |
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#endif |
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| 83 | 98 |
/*---------------------------------------------------------------------------- |
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| Software IEC/IEEE single-precision conversion routines. |
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*----------------------------------------------------------------------------*/ |
| 86 | 101 |
int float32_to_int32( float32 a STATUS_PARAM) |
| 87 | 102 |
{
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return lrintf(a);
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return long_to_int32(lrintf(a));
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| 89 | 104 |
} |
| 90 | 105 |
int float32_to_int32_round_to_zero( float32 a STATUS_PARAM) |
| 91 | 106 |
{
|
| ... | ... | |
| 167 | 182 |
*----------------------------------------------------------------------------*/ |
| 168 | 183 |
int float64_to_int32( float64 a STATUS_PARAM) |
| 169 | 184 |
{
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return lrint(a);
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return long_to_int32(lrint(a));
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} |
| 172 | 187 |
int float64_to_int32_round_to_zero( float64 a STATUS_PARAM) |
| 173 | 188 |
{
|
| ... | ... | |
| 276 | 291 |
*----------------------------------------------------------------------------*/ |
| 277 | 292 |
int floatx80_to_int32( floatx80 a STATUS_PARAM) |
| 278 | 293 |
{
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return lrintl(a);
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return long_to_int32(lrintl(a));
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| 280 | 295 |
} |
| 281 | 296 |
int floatx80_to_int32_round_to_zero( floatx80 a STATUS_PARAM) |
| 282 | 297 |
{
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