| 426 |
426 |
/*****************************************************************************/
|
| 427 |
427 |
/* PowerPC Instructions types definitions */
|
| 428 |
428 |
enum {
|
| 429 |
|
PPC_NONE = 0x0000000000000000ULL,
|
|
429 |
PPC_NONE = 0x0000000000000000ULL,
|
| 430 |
430 |
/* PowerPC base instructions set */
|
| 431 |
|
PPC_INSNS_BASE = 0x0000000000000001ULL,
|
| 432 |
|
/* integer operations instructions */
|
|
431 |
PPC_INSNS_BASE = 0x0000000000000001ULL,
|
|
432 |
/* integer operations instructions */
|
| 433 |
433 |
#define PPC_INTEGER PPC_INSNS_BASE
|
| 434 |
|
/* flow control instructions */
|
|
434 |
/* flow control instructions */
|
| 435 |
435 |
#define PPC_FLOW PPC_INSNS_BASE
|
| 436 |
|
/* virtual memory instructions */
|
|
436 |
/* virtual memory instructions */
|
| 437 |
437 |
#define PPC_MEM PPC_INSNS_BASE
|
| 438 |
|
/* ld/st with reservation instructions */
|
|
438 |
/* ld/st with reservation instructions */
|
| 439 |
439 |
#define PPC_RES PPC_INSNS_BASE
|
| 440 |
|
/* cache control instructions */
|
| 441 |
|
#define PPC_CACHE PPC_INSNS_BASE
|
| 442 |
|
/* spr/msr access instructions */
|
|
440 |
/* spr/msr access instructions */
|
| 443 |
441 |
#define PPC_MISC PPC_INSNS_BASE
|
| 444 |
|
/* Optional floating point instructions */
|
| 445 |
|
PPC_FLOAT = 0x0000000000000002ULL,
|
| 446 |
|
PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
|
| 447 |
|
PPC_FLOAT_FRES = 0x0000000000000008ULL,
|
| 448 |
|
PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
|
| 449 |
|
PPC_FLOAT_FSEL = 0x0000000000000020ULL,
|
| 450 |
|
PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
|
| 451 |
|
/* external control instructions */
|
| 452 |
|
PPC_EXTERN = 0x0000000000000080ULL,
|
| 453 |
|
/* segment register access instructions */
|
| 454 |
|
PPC_SEGMENT = 0x0000000000000100ULL,
|
| 455 |
|
/* Optional cache control instruction */
|
| 456 |
|
PPC_CACHE_DCBA = 0x0000000000000200ULL,
|
|
442 |
/* Deprecated instruction sets */
|
|
443 |
/* Original POWER instruction set */
|
|
444 |
PPC_POWER = 0x0000000000000001ULL,
|
|
445 |
/* POWER2 instruction set extension */
|
|
446 |
PPC_POWER2 = 0x0000000000000002ULL,
|
|
447 |
/* Power RTC support */
|
|
448 |
PPC_POWER_RTC = 0x0000000000000004ULL,
|
|
449 |
/* Power-to-PowerPC bridge (601) */
|
|
450 |
PPC_POWER_BR = 0x0000000000000008ULL,
|
|
451 |
/* 64 bits PowerPC instruction set */
|
|
452 |
PPC_64B = 0x0000000000000010ULL,
|
|
453 |
/* New 64 bits extensions (PowerPC 2.0x) */
|
|
454 |
PPC_64BX = 0x0000000000000020ULL,
|
|
455 |
/* 64 bits hypervisor extensions */
|
|
456 |
PPC_64H = 0x0000000000000040ULL,
|
|
457 |
/* New wait instruction (PowerPC 2.0x) */
|
|
458 |
PPC_WAIT = 0x0000000000000080ULL,
|
|
459 |
/* Time base mftb instruction */
|
|
460 |
PPC_MFTB = 0x0000000000000100ULL,
|
|
461 |
|
|
462 |
/* Fixed-point unit extensions */
|
|
463 |
/* PowerPC 602 specific */
|
|
464 |
PPC_602_SPEC = 0x0000000000000200ULL,
|
|
465 |
/* PowerPC 2.03 specification extensions */
|
|
466 |
PPC_203 = 0x0000000000000400ULL,
|
|
467 |
|
|
468 |
/* Floating-point unit extensions */
|
|
469 |
/* Optional floating point instructions */
|
|
470 |
PPC_FLOAT = 0x0000000000010000ULL,
|
|
471 |
/* New floating-point extensions (PowerPC 2.0x) */
|
|
472 |
PPC_FLOAT_EXT = 0x0000000000020000ULL,
|
|
473 |
PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
|
|
474 |
PPC_FLOAT_FRES = 0x0000000000080000ULL,
|
|
475 |
PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
|
|
476 |
PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
|
|
477 |
PPC_FLOAT_FSEL = 0x0000000000400000ULL,
|
|
478 |
PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
|
|
479 |
|
|
480 |
/* Vector/SIMD extensions */
|
|
481 |
/* Altivec support */
|
|
482 |
PPC_ALTIVEC = 0x0000000001000000ULL,
|
|
483 |
/* e500 vector instructions */
|
|
484 |
PPC_E500_VECTOR = 0x0000000002000000ULL,
|
|
485 |
/* PowerPC 2.03 SPE extension */
|
|
486 |
PPC_SPE = 0x0000000004000000ULL,
|
|
487 |
/* PowerPC 2.03 SPE floating-point extension */
|
|
488 |
PPC_SPEFPU = 0x0000000008000000ULL,
|
|
489 |
|
| 457 |
490 |
/* Optional memory control instructions */
|
| 458 |
|
PPC_MEM_TLBIA = 0x0000000000000400ULL,
|
| 459 |
|
PPC_MEM_TLBIE = 0x0000000000000800ULL,
|
| 460 |
|
PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
|
| 461 |
|
/* eieio & sync */
|
| 462 |
|
PPC_MEM_SYNC = 0x0000000000002000ULL,
|
| 463 |
|
/* PowerPC 6xx TLB management instructions */
|
| 464 |
|
PPC_6xx_TLB = 0x0000000000004000ULL,
|
| 465 |
|
/* Altivec support */
|
| 466 |
|
PPC_ALTIVEC = 0x0000000000008000ULL,
|
| 467 |
|
/* Time base mftb instruction */
|
| 468 |
|
PPC_MFTB = 0x0000000000010000ULL,
|
|
491 |
PPC_MEM_TLBIA = 0x0000000010000000ULL,
|
|
492 |
PPC_MEM_TLBIE = 0x0000000020000000ULL,
|
|
493 |
PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
|
|
494 |
/* sync instruction */
|
|
495 |
PPC_MEM_SYNC = 0x0000000080000000ULL,
|
|
496 |
/* eieio instruction */
|
|
497 |
PPC_MEM_EIEIO = 0x0000000100000000ULL,
|
|
498 |
|
|
499 |
/* Cache control instructions */
|
|
500 |
PPC_CACHE = 0x0000001000000000ULL,
|
|
501 |
/* icbi instruction */
|
|
502 |
PPC_CACHE_ICBI = 0x0000002000000000ULL,
|
|
503 |
/* dcbz instruction with fixed cache line size */
|
|
504 |
PPC_CACHE_DCBZ = 0x0000004000000000ULL,
|
|
505 |
/* dcbz instruction with tunable cache line size */
|
|
506 |
PPC_CACHE_DCBZT = 0x0000008000000000ULL,
|
|
507 |
/* dcba instruction */
|
|
508 |
PPC_CACHE_DCBA = 0x0000010000000000ULL,
|
|
509 |
|
|
510 |
/* MMU related extensions */
|
|
511 |
/* external control instructions */
|
|
512 |
PPC_EXTERN = 0x0000100000000000ULL,
|
|
513 |
/* segment register access instructions */
|
|
514 |
PPC_SEGMENT = 0x0000200000000000ULL,
|
|
515 |
/* PowerPC 6xx TLB management instructions */
|
|
516 |
PPC_6xx_TLB = 0x0000400000000000ULL,
|
|
517 |
/* PowerPC 74xx TLB management instructions */
|
|
518 |
PPC_74xx_TLB = 0x0000800000000000ULL,
|
|
519 |
/* PowerPC 40x TLB management instructions */
|
|
520 |
PPC_40x_TLB = 0x0001000000000000ULL,
|
|
521 |
/* segment register access instructions for PowerPC 64 "bridge" */
|
|
522 |
PPC_SEGMENT_64B = 0x0002000000000000ULL,
|
|
523 |
/* SLB management */
|
|
524 |
PPC_SLBI = 0x0004000000000000ULL,
|
|
525 |
|
| 469 |
526 |
/* Embedded PowerPC dedicated instructions */
|
| 470 |
|
PPC_EMB_COMMON = 0x0000000000020000ULL,
|
|
527 |
PPC_EMB_COMMON = 0x0010000000000000ULL,
|
| 471 |
528 |
/* PowerPC 40x exception model */
|
| 472 |
|
PPC_40x_EXCP = 0x0000000000040000ULL,
|
| 473 |
|
/* PowerPC 40x TLB management instructions */
|
| 474 |
|
PPC_40x_TLB = 0x0000000000080000ULL,
|
|
529 |
PPC_40x_EXCP = 0x0020000000000000ULL,
|
| 475 |
530 |
/* PowerPC 405 Mac instructions */
|
| 476 |
|
PPC_405_MAC = 0x0000000000100000ULL,
|
|
531 |
PPC_405_MAC = 0x0040000000000000ULL,
|
| 477 |
532 |
/* PowerPC 440 specific instructions */
|
| 478 |
|
PPC_440_SPEC = 0x0000000000200000ULL,
|
| 479 |
|
/* Power-to-PowerPC bridge (601) */
|
| 480 |
|
PPC_POWER_BR = 0x0000000000400000ULL,
|
| 481 |
|
/* PowerPC 602 specific */
|
| 482 |
|
PPC_602_SPEC = 0x0000000000800000ULL,
|
| 483 |
|
/* Deprecated instructions */
|
| 484 |
|
/* Original POWER instruction set */
|
| 485 |
|
PPC_POWER = 0x0000000001000000ULL,
|
| 486 |
|
/* POWER2 instruction set extension */
|
| 487 |
|
PPC_POWER2 = 0x0000000002000000ULL,
|
| 488 |
|
/* Power RTC support */
|
| 489 |
|
PPC_POWER_RTC = 0x0000000004000000ULL,
|
| 490 |
|
/* 64 bits PowerPC instruction set */
|
| 491 |
|
PPC_64B = 0x0000000008000000ULL,
|
| 492 |
|
/* 64 bits hypervisor extensions */
|
| 493 |
|
PPC_64H = 0x0000000010000000ULL,
|
| 494 |
|
/* segment register access instructions for PowerPC 64 "bridge" */
|
| 495 |
|
PPC_SEGMENT_64B = 0x0000000020000000ULL,
|
|
533 |
PPC_440_SPEC = 0x0080000000000000ULL,
|
| 496 |
534 |
/* BookE (embedded) PowerPC specification */
|
| 497 |
|
PPC_BOOKE = 0x0000000040000000ULL,
|
| 498 |
|
/* eieio */
|
| 499 |
|
PPC_MEM_EIEIO = 0x0000000080000000ULL,
|
| 500 |
|
/* e500 vector instructions */
|
| 501 |
|
PPC_E500_VECTOR = 0x0000000100000000ULL,
|
|
535 |
PPC_BOOKE = 0x0100000000000000ULL,
|
|
536 |
/* More BookE (embedded) instructions... */
|
|
537 |
PPC_BOOKE_EXT = 0x0200000000000000ULL,
|
| 502 |
538 |
/* PowerPC 4xx dedicated instructions */
|
| 503 |
|
PPC_4xx_COMMON = 0x0000000200000000ULL,
|
| 504 |
|
/* PowerPC 2.03 specification extensions */
|
| 505 |
|
PPC_203 = 0x0000000400000000ULL,
|
| 506 |
|
/* PowerPC 2.03 SPE extension */
|
| 507 |
|
PPC_SPE = 0x0000000800000000ULL,
|
| 508 |
|
/* PowerPC 2.03 SPE floating-point extension */
|
| 509 |
|
PPC_SPEFPU = 0x0000001000000000ULL,
|
| 510 |
|
/* SLB management */
|
| 511 |
|
PPC_SLBI = 0x0000002000000000ULL,
|
|
539 |
PPC_4xx_COMMON = 0x0400000000000000ULL,
|
| 512 |
540 |
/* PowerPC 40x ibct instructions */
|
| 513 |
|
PPC_40x_ICBT = 0x0000004000000000ULL,
|
| 514 |
|
/* PowerPC 74xx TLB management instructions */
|
| 515 |
|
PPC_74xx_TLB = 0x0000008000000000ULL,
|
| 516 |
|
/* More BookE (embedded) instructions... */
|
| 517 |
|
PPC_BOOKE_EXT = 0x0000010000000000ULL,
|
|
541 |
PPC_40x_ICBT = 0x0800000000000000ULL,
|
| 518 |
542 |
/* rfmci is not implemented in all BookE PowerPC */
|
| 519 |
|
PPC_RFMCI = 0x0000020000000000ULL,
|
|
543 |
PPC_RFMCI = 0x1000000000000000ULL,
|
| 520 |
544 |
/* user-mode DCR access, implemented in PowerPC 460 */
|
| 521 |
|
PPC_DCRUX = 0x0000040000000000ULL,
|
| 522 |
|
/* New floating-point extensions (PowerPC 2.0x) */
|
| 523 |
|
PPC_FLOAT_EXT = 0x0000080000000000ULL,
|
| 524 |
|
/* New wait instruction (PowerPC 2.0x) */
|
| 525 |
|
PPC_WAIT = 0x0000100000000000ULL,
|
| 526 |
|
/* New 64 bits extensions (PowerPC 2.0x) */
|
| 527 |
|
PPC_64BX = 0x0000200000000000ULL,
|
| 528 |
|
/* dcbz instruction with fixed cache line size */
|
| 529 |
|
PPC_CACHE_DCBZ = 0x0000400000000000ULL,
|
| 530 |
|
/* dcbz instruction with tunable cache line size */
|
| 531 |
|
PPC_CACHE_DCBZT = 0x0000800000000000ULL,
|
| 532 |
|
/* frsqrtes extension */
|
| 533 |
|
PPC_FLOAT_FRSQRTES = 0x0001000000000000ULL,
|
|
545 |
PPC_DCRUX = 0x2000000000000000ULL,
|
| 534 |
546 |
};
|
| 535 |
547 |
|
| 536 |
548 |
/*****************************************************************************/
|
| ... | ... | |
| 1805 |
1817 |
gen_op_frsqrte();
|
| 1806 |
1818 |
gen_op_frsp();
|
| 1807 |
1819 |
}
|
| 1808 |
|
GEN_FLOAT_BS(rsqrtes, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTES);
|
|
1820 |
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
|
| 1809 |
1821 |
|
| 1810 |
1822 |
/* fsel */
|
| 1811 |
1823 |
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
|
| ... | ... | |
| 3980 |
3992 |
#endif
|
| 3981 |
3993 |
#endif
|
| 3982 |
3994 |
|
| 3983 |
|
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
|
|
3995 |
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
|
| 3984 |
3996 |
{
|
| 3985 |
3997 |
/* NIP cannot be restored if the memory exception comes from an helper */
|
| 3986 |
3998 |
gen_update_nip(ctx, ctx->nip - 4);
|