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1
/*
2
 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20
#include <stdarg.h>
21
#include <stdlib.h>
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#include <stdio.h>
23
#include <string.h>
24
#include <inttypes.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
28
#include "disas.h"
29

    
30
/* Include definitions for instructions classes and implementations flags */
31
//#define DO_SINGLE_STEP
32
//#define PPC_DEBUG_DISAS
33
//#define DEBUG_MEMORY_ACCESSES
34
//#define DO_PPC_STATISTICS
35
//#define OPTIMIZE_FPRF_UPDATE
36

    
37
/*****************************************************************************/
38
/* Code translation helpers                                                  */
39
#if defined(USE_DIRECT_JUMP)
40
#define TBPARAM(x)
41
#else
42
#define TBPARAM(x) (long)(x)
43
#endif
44

    
45
enum {
46
#define DEF(s, n, copy_size) INDEX_op_ ## s,
47
#include "opc.h"
48
#undef DEF
49
    NB_OPS,
50
};
51

    
52
static uint16_t *gen_opc_ptr;
53
static uint32_t *gen_opparam_ptr;
54
#if defined(OPTIMIZE_FPRF_UPDATE)
55
static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
56
static uint16_t **gen_fprf_ptr;
57
#endif
58

    
59
#include "gen-op.h"
60

    
61
static always_inline void gen_set_T0 (target_ulong val)
62
{
63
#if defined(TARGET_PPC64)
64
    if (val >> 32)
65
        gen_op_set_T0_64(val >> 32, val);
66
    else
67
#endif
68
        gen_op_set_T0(val);
69
}
70

    
71
static always_inline void gen_set_T1 (target_ulong val)
72
{
73
#if defined(TARGET_PPC64)
74
    if (val >> 32)
75
        gen_op_set_T1_64(val >> 32, val);
76
    else
77
#endif
78
        gen_op_set_T1(val);
79
}
80

    
81
#define GEN8(func, NAME)                                                      \
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static GenOpFunc *NAME ## _table [8] = {                                      \
83
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
85
};                                                                            \
86
static always_inline void func (int n)                                        \
87
{                                                                             \
88
    NAME ## _table[n]();                                                      \
89
}
90

    
91
#define GEN16(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [16] = {                                     \
93
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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};                                                                            \
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static always_inline void func (int n)                                        \
99
{                                                                             \
100
    NAME ## _table[n]();                                                      \
101
}
102

    
103
#define GEN32(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [32] = {                                     \
105
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
107
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
109
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
110
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
111
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
112
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
113
};                                                                            \
114
static always_inline void func (int n)                                        \
115
{                                                                             \
116
    NAME ## _table[n]();                                                      \
117
}
118

    
119
/* Condition register moves */
120
GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
121
GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
122
GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
123
#if 0 // Unused
124
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
125
#endif
126

    
127
/* General purpose registers moves */
128
GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
129
GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
130
GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
131

    
132
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
133
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
134
#if 0 // unused
135
GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
136
#endif
137

    
138
/* floating point registers moves */
139
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
140
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
141
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
142
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
143
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
144
#if 0 // unused
145
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
146
#endif
147

    
148
/* internal defines */
149
typedef struct DisasContext {
150
    struct TranslationBlock *tb;
151
    target_ulong nip;
152
    uint32_t opcode;
153
    uint32_t exception;
154
    /* Routine used to access memory */
155
    int mem_idx;
156
    /* Translation flags */
157
#if !defined(CONFIG_USER_ONLY)
158
    int supervisor;
159
#endif
160
#if defined(TARGET_PPC64)
161
    int sf_mode;
162
#endif
163
    int fpu_enabled;
164
    int altivec_enabled;
165
    int spe_enabled;
166
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
167
    int singlestep_enabled;
168
    int dcache_line_size;
169
} DisasContext;
170

    
171
struct opc_handler_t {
172
    /* invalid bits */
173
    uint32_t inval;
174
    /* instruction type */
175
    uint64_t type;
176
    /* handler */
177
    void (*handler)(DisasContext *ctx);
178
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
179
    const unsigned char *oname;
180
#endif
181
#if defined(DO_PPC_STATISTICS)
182
    uint64_t count;
183
#endif
184
};
185

    
186
static always_inline void gen_set_Rc0 (DisasContext *ctx)
187
{
188
#if defined(TARGET_PPC64)
189
    if (ctx->sf_mode)
190
        gen_op_cmpi_64(0);
191
    else
192
#endif
193
        gen_op_cmpi(0);
194
    gen_op_set_Rc0();
195
}
196

    
197
static always_inline void gen_reset_fpstatus (void)
198
{
199
#ifdef CONFIG_SOFTFLOAT
200
    gen_op_reset_fpstatus();
201
#endif
202
}
203

    
204
static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
205
{
206
    if (set_fprf != 0) {
207
        /* This case might be optimized later */
208
#if defined(OPTIMIZE_FPRF_UPDATE)
209
        *gen_fprf_ptr++ = gen_opc_ptr;
210
#endif
211
        gen_op_compute_fprf(1);
212
        if (unlikely(set_rc))
213
            gen_op_store_T0_crf(1);
214
        gen_op_float_check_status();
215
    } else if (unlikely(set_rc)) {
216
        /* We always need to compute fpcc */
217
        gen_op_compute_fprf(0);
218
        gen_op_store_T0_crf(1);
219
        if (set_fprf)
220
            gen_op_float_check_status();
221
    }
222
}
223

    
224
static always_inline void gen_optimize_fprf (void)
225
{
226
#if defined(OPTIMIZE_FPRF_UPDATE)
227
    uint16_t **ptr;
228

    
229
    for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
230
        *ptr = INDEX_op_nop1;
231
    gen_fprf_ptr = gen_fprf_buf;
232
#endif
233
}
234

    
235
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
236
{
237
#if defined(TARGET_PPC64)
238
    if (ctx->sf_mode)
239
        gen_op_update_nip_64(nip >> 32, nip);
240
    else
241
#endif
242
        gen_op_update_nip(nip);
243
}
244

    
245
#define GEN_EXCP(ctx, excp, error)                                            \
246
do {                                                                          \
247
    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \
248
        gen_update_nip(ctx, (ctx)->nip);                                      \
249
    }                                                                         \
250
    gen_op_raise_exception_err((excp), (error));                              \
251
    ctx->exception = (excp);                                                  \
252
} while (0)
253

    
254
#define GEN_EXCP_INVAL(ctx)                                                   \
255
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
256
         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
257

    
258
#define GEN_EXCP_PRIVOPC(ctx)                                                 \
259
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
260
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
261

    
262
#define GEN_EXCP_PRIVREG(ctx)                                                 \
263
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
264
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
265

    
266
#define GEN_EXCP_NO_FP(ctx)                                                   \
267
GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
268

    
269
#define GEN_EXCP_NO_AP(ctx)                                                   \
270
GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
271

    
272
#define GEN_EXCP_NO_VR(ctx)                                                   \
273
GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
274

    
275
/* Stop translation */
276
static always_inline void GEN_STOP (DisasContext *ctx)
277
{
278
    gen_update_nip(ctx, ctx->nip);
279
    ctx->exception = POWERPC_EXCP_STOP;
280
}
281

    
282
/* No need to update nip here, as execution flow will change */
283
static always_inline void GEN_SYNC (DisasContext *ctx)
284
{
285
    ctx->exception = POWERPC_EXCP_SYNC;
286
}
287

    
288
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
289
static void gen_##name (DisasContext *ctx);                                   \
290
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
291
static void gen_##name (DisasContext *ctx)
292

    
293
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
294
static void gen_##name (DisasContext *ctx);                                   \
295
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
296
static void gen_##name (DisasContext *ctx)
297

    
298
typedef struct opcode_t {
299
    unsigned char opc1, opc2, opc3;
300
#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
301
    unsigned char pad[5];
302
#else
303
    unsigned char pad[1];
304
#endif
305
    opc_handler_t handler;
306
    const unsigned char *oname;
307
} opcode_t;
308

    
309
/*****************************************************************************/
310
/***                           Instruction decoding                        ***/
311
#define EXTRACT_HELPER(name, shift, nb)                                       \
312
static always_inline uint32_t name (uint32_t opcode)                          \
313
{                                                                             \
314
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
315
}
316

    
317
#define EXTRACT_SHELPER(name, shift, nb)                                      \
318
static always_inline int32_t name (uint32_t opcode)                           \
319
{                                                                             \
320
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
321
}
322

    
323
/* Opcode part 1 */
324
EXTRACT_HELPER(opc1, 26, 6);
325
/* Opcode part 2 */
326
EXTRACT_HELPER(opc2, 1, 5);
327
/* Opcode part 3 */
328
EXTRACT_HELPER(opc3, 6, 5);
329
/* Update Cr0 flags */
330
EXTRACT_HELPER(Rc, 0, 1);
331
/* Destination */
332
EXTRACT_HELPER(rD, 21, 5);
333
/* Source */
334
EXTRACT_HELPER(rS, 21, 5);
335
/* First operand */
336
EXTRACT_HELPER(rA, 16, 5);
337
/* Second operand */
338
EXTRACT_HELPER(rB, 11, 5);
339
/* Third operand */
340
EXTRACT_HELPER(rC, 6, 5);
341
/***                               Get CRn                                 ***/
342
EXTRACT_HELPER(crfD, 23, 3);
343
EXTRACT_HELPER(crfS, 18, 3);
344
EXTRACT_HELPER(crbD, 21, 5);
345
EXTRACT_HELPER(crbA, 16, 5);
346
EXTRACT_HELPER(crbB, 11, 5);
347
/* SPR / TBL */
348
EXTRACT_HELPER(_SPR, 11, 10);
349
static always_inline uint32_t SPR (uint32_t opcode)
350
{
351
    uint32_t sprn = _SPR(opcode);
352

    
353
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
354
}
355
/***                              Get constants                            ***/
356
EXTRACT_HELPER(IMM, 12, 8);
357
/* 16 bits signed immediate value */
358
EXTRACT_SHELPER(SIMM, 0, 16);
359
/* 16 bits unsigned immediate value */
360
EXTRACT_HELPER(UIMM, 0, 16);
361
/* Bit count */
362
EXTRACT_HELPER(NB, 11, 5);
363
/* Shift count */
364
EXTRACT_HELPER(SH, 11, 5);
365
/* Mask start */
366
EXTRACT_HELPER(MB, 6, 5);
367
/* Mask end */
368
EXTRACT_HELPER(ME, 1, 5);
369
/* Trap operand */
370
EXTRACT_HELPER(TO, 21, 5);
371

    
372
EXTRACT_HELPER(CRM, 12, 8);
373
EXTRACT_HELPER(FM, 17, 8);
374
EXTRACT_HELPER(SR, 16, 4);
375
EXTRACT_HELPER(FPIMM, 20, 4);
376

    
377
/***                            Jump target decoding                       ***/
378
/* Displacement */
379
EXTRACT_SHELPER(d, 0, 16);
380
/* Immediate address */
381
static always_inline target_ulong LI (uint32_t opcode)
382
{
383
    return (opcode >> 0) & 0x03FFFFFC;
384
}
385

    
386
static always_inline uint32_t BD (uint32_t opcode)
387
{
388
    return (opcode >> 0) & 0xFFFC;
389
}
390

    
391
EXTRACT_HELPER(BO, 21, 5);
392
EXTRACT_HELPER(BI, 16, 5);
393
/* Absolute/relative address */
394
EXTRACT_HELPER(AA, 1, 1);
395
/* Link */
396
EXTRACT_HELPER(LK, 0, 1);
397

    
398
/* Create a mask between <start> and <end> bits */
399
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
400
{
401
    target_ulong ret;
402

    
403
#if defined(TARGET_PPC64)
404
    if (likely(start == 0)) {
405
        ret = UINT64_MAX << (63 - end);
406
    } else if (likely(end == 63)) {
407
        ret = UINT64_MAX >> start;
408
    }
409
#else
410
    if (likely(start == 0)) {
411
        ret = UINT32_MAX << (31  - end);
412
    } else if (likely(end == 31)) {
413
        ret = UINT32_MAX >> start;
414
    }
415
#endif
416
    else {
417
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
418
            (((target_ulong)(-1ULL) >> (end)) >> 1);
419
        if (unlikely(start > end))
420
            return ~ret;
421
    }
422

    
423
    return ret;
424
}
425

    
426
/*****************************************************************************/
427
/* PowerPC Instructions types definitions                                    */
428
enum {
429
    PPC_NONE           = 0x0000000000000000ULL,
430
    /* PowerPC base instructions set                                         */
431
    PPC_INSNS_BASE     = 0x0000000000000001ULL,
432
    /*   integer operations instructions                                     */
433
#define PPC_INTEGER PPC_INSNS_BASE
434
    /*   flow control instructions                                           */
435
#define PPC_FLOW    PPC_INSNS_BASE
436
    /*   virtual memory instructions                                         */
437
#define PPC_MEM     PPC_INSNS_BASE
438
    /*   ld/st with reservation instructions                                 */
439
#define PPC_RES     PPC_INSNS_BASE
440
    /*   spr/msr access instructions                                         */
441
#define PPC_MISC    PPC_INSNS_BASE
442
    /* Deprecated instruction sets                                           */
443
    /*   Original POWER instruction set                                      */
444
    PPC_POWER          = 0x0000000000000001ULL,
445
    /*   POWER2 instruction set extension                                    */
446
    PPC_POWER2         = 0x0000000000000002ULL,
447
    /*   Power RTC support                                                   */
448
    PPC_POWER_RTC      = 0x0000000000000004ULL,
449
    /*   Power-to-PowerPC bridge (601)                                       */
450
    PPC_POWER_BR       = 0x0000000000000008ULL,
451
    /* 64 bits PowerPC instruction set                                       */
452
    PPC_64B            = 0x0000000000000010ULL,
453
    /*   New 64 bits extensions (PowerPC 2.0x)                               */
454
    PPC_64BX           = 0x0000000000000020ULL,
455
    /*   64 bits hypervisor extensions                                       */
456
    PPC_64H            = 0x0000000000000040ULL,
457
    /*   New wait instruction (PowerPC 2.0x)                                 */
458
    PPC_WAIT           = 0x0000000000000080ULL,
459
    /*   Time base mftb instruction                                          */
460
    PPC_MFTB           = 0x0000000000000100ULL,
461

    
462
    /* Fixed-point unit extensions                                           */
463
    /*   PowerPC 602 specific                                                */
464
    PPC_602_SPEC       = 0x0000000000000200ULL,
465
    /*   PowerPC 2.03 specification extensions                               */
466
    PPC_203            = 0x0000000000000400ULL,
467

    
468
    /* Floating-point unit extensions                                        */
469
    /*   Optional floating point instructions                                */
470
    PPC_FLOAT          = 0x0000000000010000ULL,
471
    /* New floating-point extensions (PowerPC 2.0x)                          */
472
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
473
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
474
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
475
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
476
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
477
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
478
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
479

    
480
    /* Vector/SIMD extensions                                                */
481
    /*   Altivec support                                                     */
482
    PPC_ALTIVEC        = 0x0000000001000000ULL,
483
    /*   e500 vector instructions                                            */
484
    PPC_E500_VECTOR    = 0x0000000002000000ULL,
485
    /*   PowerPC 2.03 SPE extension                                          */
486
    PPC_SPE            = 0x0000000004000000ULL,
487
    /*   PowerPC 2.03 SPE floating-point extension                           */
488
    PPC_SPEFPU         = 0x0000000008000000ULL,
489

    
490
    /* Optional memory control instructions                                  */
491
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
492
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
493
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
494
    /*   sync instruction                                                    */
495
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
496
    /*   eieio instruction                                                   */
497
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
498

    
499
    /* Cache control instructions                                            */
500
    PPC_CACHE          = 0x0000001000000000ULL,
501
    /*   icbi instruction                                                    */
502
    PPC_CACHE_ICBI     = 0x0000002000000000ULL,
503
    /*   dcbz instruction with fixed cache line size                         */
504
    PPC_CACHE_DCBZ     = 0x0000004000000000ULL,
505
    /*   dcbz instruction with tunable cache line size                       */
506
    PPC_CACHE_DCBZT    = 0x0000008000000000ULL,
507
    /*   dcba instruction                                                    */
508
    PPC_CACHE_DCBA     = 0x0000010000000000ULL,
509

    
510
    /* MMU related extensions                                                */
511
    /*   external control instructions                                       */
512
    PPC_EXTERN         = 0x0000100000000000ULL,
513
    /*   segment register access instructions                                */
514
    PPC_SEGMENT        = 0x0000200000000000ULL,
515
    /*   PowerPC 6xx TLB management instructions                             */
516
    PPC_6xx_TLB        = 0x0000400000000000ULL,
517
    /* PowerPC 74xx TLB management instructions                              */
518
    PPC_74xx_TLB       = 0x0000800000000000ULL,
519
    /*   PowerPC 40x TLB management instructions                             */
520
    PPC_40x_TLB        = 0x0001000000000000ULL,
521
    /*   segment register access instructions for PowerPC 64 "bridge"        */
522
    PPC_SEGMENT_64B    = 0x0002000000000000ULL,
523
    /*   SLB management                                                      */
524
    PPC_SLBI           = 0x0004000000000000ULL,
525

    
526
    /* Embedded PowerPC dedicated instructions                               */
527
    PPC_EMB_COMMON     = 0x0010000000000000ULL,
528
    /* PowerPC 40x exception model                                           */
529
    PPC_40x_EXCP       = 0x0020000000000000ULL,
530
    /* PowerPC 405 Mac instructions                                          */
531
    PPC_405_MAC        = 0x0040000000000000ULL,
532
    /* PowerPC 440 specific instructions                                     */
533
    PPC_440_SPEC       = 0x0080000000000000ULL,
534
    /* BookE (embedded) PowerPC specification                                */
535
    PPC_BOOKE          = 0x0100000000000000ULL,
536
    /* More BookE (embedded) instructions...                                 */
537
    PPC_BOOKE_EXT      = 0x0200000000000000ULL,
538
    /* PowerPC 4xx dedicated instructions                                    */
539
    PPC_4xx_COMMON     = 0x0400000000000000ULL,
540
    /* PowerPC 40x ibct instructions                                         */
541
    PPC_40x_ICBT       = 0x0800000000000000ULL,
542
    /* rfmci is not implemented in all BookE PowerPC                         */
543
    PPC_RFMCI          = 0x1000000000000000ULL,
544
    /* user-mode DCR access, implemented in PowerPC 460                      */
545
    PPC_DCRUX          = 0x2000000000000000ULL,
546
};
547

    
548
/*****************************************************************************/
549
/* PowerPC instructions table                                                */
550
#if HOST_LONG_BITS == 64
551
#define OPC_ALIGN 8
552
#else
553
#define OPC_ALIGN 4
554
#endif
555
#if defined(__APPLE__)
556
#define OPCODES_SECTION                                                       \
557
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
558
#else
559
#define OPCODES_SECTION                                                       \
560
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
561
#endif
562

    
563
#if defined(DO_PPC_STATISTICS)
564
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
565
OPCODES_SECTION opcode_t opc_##name = {                                       \
566
    .opc1 = op1,                                                              \
567
    .opc2 = op2,                                                              \
568
    .opc3 = op3,                                                              \
569
    .pad  = { 0, },                                                           \
570
    .handler = {                                                              \
571
        .inval   = invl,                                                      \
572
        .type = _typ,                                                         \
573
        .handler = &gen_##name,                                               \
574
        .oname = stringify(name),                                             \
575
    },                                                                        \
576
    .oname = stringify(name),                                                 \
577
}
578
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
579
OPCODES_SECTION opcode_t opc_##name = {                                       \
580
    .opc1 = op1,                                                              \
581
    .opc2 = op2,                                                              \
582
    .opc3 = op3,                                                              \
583
    .pad  = { 0, },                                                           \
584
    .handler = {                                                              \
585
        .inval   = invl,                                                      \
586
        .type = _typ,                                                         \
587
        .handler = &gen_##name,                                               \
588
        .oname = onam,                                                        \
589
    },                                                                        \
590
    .oname = onam,                                                            \
591
}
592
#else
593
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
594
OPCODES_SECTION opcode_t opc_##name = {                                       \
595
    .opc1 = op1,                                                              \
596
    .opc2 = op2,                                                              \
597
    .opc3 = op3,                                                              \
598
    .pad  = { 0, },                                                           \
599
    .handler = {                                                              \
600
        .inval   = invl,                                                      \
601
        .type = _typ,                                                         \
602
        .handler = &gen_##name,                                               \
603
    },                                                                        \
604
    .oname = stringify(name),                                                 \
605
}
606
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
607
OPCODES_SECTION opcode_t opc_##name = {                                       \
608
    .opc1 = op1,                                                              \
609
    .opc2 = op2,                                                              \
610
    .opc3 = op3,                                                              \
611
    .pad  = { 0, },                                                           \
612
    .handler = {                                                              \
613
        .inval   = invl,                                                      \
614
        .type = _typ,                                                         \
615
        .handler = &gen_##name,                                               \
616
    },                                                                        \
617
    .oname = onam,                                                            \
618
}
619
#endif
620

    
621
#define GEN_OPCODE_MARK(name)                                                 \
622
OPCODES_SECTION opcode_t opc_##name = {                                       \
623
    .opc1 = 0xFF,                                                             \
624
    .opc2 = 0xFF,                                                             \
625
    .opc3 = 0xFF,                                                             \
626
    .pad  = { 0, },                                                           \
627
    .handler = {                                                              \
628
        .inval   = 0x00000000,                                                \
629
        .type = 0x00,                                                         \
630
        .handler = NULL,                                                      \
631
    },                                                                        \
632
    .oname = stringify(name),                                                 \
633
}
634

    
635
/* Start opcode list */
636
GEN_OPCODE_MARK(start);
637

    
638
/* Invalid instruction */
639
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
640
{
641
    GEN_EXCP_INVAL(ctx);
642
}
643

    
644
static opc_handler_t invalid_handler = {
645
    .inval   = 0xFFFFFFFF,
646
    .type    = PPC_NONE,
647
    .handler = gen_invalid,
648
};
649

    
650
/***                           Integer arithmetic                          ***/
651
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \
652
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
653
{                                                                             \
654
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
655
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
656
    gen_op_##name();                                                          \
657
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
658
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
659
        gen_set_Rc0(ctx);                                                     \
660
}
661

    
662
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \
663
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
664
{                                                                             \
665
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
666
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
667
    gen_op_##name();                                                          \
668
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
669
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
670
        gen_set_Rc0(ctx);                                                     \
671
}
672

    
673
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \
674
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
675
{                                                                             \
676
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
677
    gen_op_##name();                                                          \
678
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
679
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
680
        gen_set_Rc0(ctx);                                                     \
681
}
682
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \
683
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
684
{                                                                             \
685
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
686
    gen_op_##name();                                                          \
687
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
688
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
689
        gen_set_Rc0(ctx);                                                     \
690
}
691

    
692
/* Two operands arithmetic functions */
693
#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type)                          \
694
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type)                    \
695
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
696

    
697
/* Two operands arithmetic functions with no overflow allowed */
698
#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type)                          \
699
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
700

    
701
/* One operand arithmetic functions */
702
#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                          \
703
__GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                                \
704
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
705

    
706
#if defined(TARGET_PPC64)
707
#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)              \
708
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
709
{                                                                             \
710
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
711
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
712
    if (ctx->sf_mode)                                                         \
713
        gen_op_##name##_64();                                                 \
714
    else                                                                      \
715
        gen_op_##name();                                                      \
716
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
717
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
718
        gen_set_Rc0(ctx);                                                     \
719
}
720

    
721
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \
722
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
723
{                                                                             \
724
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
725
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
726
    if (ctx->sf_mode)                                                         \
727
        gen_op_##name##_64();                                                 \
728
    else                                                                      \
729
        gen_op_##name();                                                      \
730
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
731
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
732
        gen_set_Rc0(ctx);                                                     \
733
}
734

    
735
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \
736
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
737
{                                                                             \
738
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
739
    if (ctx->sf_mode)                                                         \
740
        gen_op_##name##_64();                                                 \
741
    else                                                                      \
742
        gen_op_##name();                                                      \
743
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
744
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
745
        gen_set_Rc0(ctx);                                                     \
746
}
747
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \
748
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
749
{                                                                             \
750
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
751
    if (ctx->sf_mode)                                                         \
752
        gen_op_##name##_64();                                                 \
753
    else                                                                      \
754
        gen_op_##name();                                                      \
755
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
756
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
757
        gen_set_Rc0(ctx);                                                     \
758
}
759

    
760
/* Two operands arithmetic functions */
761
#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type)                       \
762
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type)                 \
763
__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
764

    
765
/* Two operands arithmetic functions with no overflow allowed */
766
#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type)                       \
767
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
768

    
769
/* One operand arithmetic functions */
770
#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                       \
771
__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                             \
772
__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
773
#else
774
#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
775
#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
776
#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
777
#endif
778

    
779
/* add    add.    addo    addo.    */
780
static always_inline void gen_op_addo (void)
781
{
782
    gen_op_move_T2_T0();
783
    gen_op_add();
784
    gen_op_check_addo();
785
}
786
#if defined(TARGET_PPC64)
787
#define gen_op_add_64 gen_op_add
788
static always_inline void gen_op_addo_64 (void)
789
{
790
    gen_op_move_T2_T0();
791
    gen_op_add();
792
    gen_op_check_addo_64();
793
}
794
#endif
795
GEN_INT_ARITH2_64 (add,    0x1F, 0x0A, 0x08, PPC_INTEGER);
796
/* addc   addc.   addco   addco.   */
797
static always_inline void gen_op_addc (void)
798
{
799
    gen_op_move_T2_T0();
800
    gen_op_add();
801
    gen_op_check_addc();
802
}
803
static always_inline void gen_op_addco (void)
804
{
805
    gen_op_move_T2_T0();
806
    gen_op_add();
807
    gen_op_check_addc();
808
    gen_op_check_addo();
809
}
810
#if defined(TARGET_PPC64)
811
static always_inline void gen_op_addc_64 (void)
812
{
813
    gen_op_move_T2_T0();
814
    gen_op_add();
815
    gen_op_check_addc_64();
816
}
817
static always_inline void gen_op_addco_64 (void)
818
{
819
    gen_op_move_T2_T0();
820
    gen_op_add();
821
    gen_op_check_addc_64();
822
    gen_op_check_addo_64();
823
}
824
#endif
825
GEN_INT_ARITH2_64 (addc,   0x1F, 0x0A, 0x00, PPC_INTEGER);
826
/* adde   adde.   addeo   addeo.   */
827
static always_inline void gen_op_addeo (void)
828
{
829
    gen_op_move_T2_T0();
830
    gen_op_adde();
831
    gen_op_check_addo();
832
}
833
#if defined(TARGET_PPC64)
834
static always_inline void gen_op_addeo_64 (void)
835
{
836
    gen_op_move_T2_T0();
837
    gen_op_adde_64();
838
    gen_op_check_addo_64();
839
}
840
#endif
841
GEN_INT_ARITH2_64 (adde,   0x1F, 0x0A, 0x04, PPC_INTEGER);
842
/* addme  addme.  addmeo  addmeo.  */
843
static always_inline void gen_op_addme (void)
844
{
845
    gen_op_move_T1_T0();
846
    gen_op_add_me();
847
}
848
#if defined(TARGET_PPC64)
849
static always_inline void gen_op_addme_64 (void)
850
{
851
    gen_op_move_T1_T0();
852
    gen_op_add_me_64();
853
}
854
#endif
855
GEN_INT_ARITH1_64 (addme,  0x1F, 0x0A, 0x07, PPC_INTEGER);
856
/* addze  addze.  addzeo  addzeo.  */
857
static always_inline void gen_op_addze (void)
858
{
859
    gen_op_move_T2_T0();
860
    gen_op_add_ze();
861
    gen_op_check_addc();
862
}
863
static always_inline void gen_op_addzeo (void)
864
{
865
    gen_op_move_T2_T0();
866
    gen_op_add_ze();
867
    gen_op_check_addc();
868
    gen_op_check_addo();
869
}
870
#if defined(TARGET_PPC64)
871
static always_inline void gen_op_addze_64 (void)
872
{
873
    gen_op_move_T2_T0();
874
    gen_op_add_ze();
875
    gen_op_check_addc_64();
876
}
877
static always_inline void gen_op_addzeo_64 (void)
878
{
879
    gen_op_move_T2_T0();
880
    gen_op_add_ze();
881
    gen_op_check_addc_64();
882
    gen_op_check_addo_64();
883
}
884
#endif
885
GEN_INT_ARITH1_64 (addze,  0x1F, 0x0A, 0x06, PPC_INTEGER);
886
/* divw   divw.   divwo   divwo.   */
887
GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F, PPC_INTEGER);
888
/* divwu  divwu.  divwuo  divwuo.  */
889
GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E, PPC_INTEGER);
890
/* mulhw  mulhw.                   */
891
GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02, PPC_INTEGER);
892
/* mulhwu mulhwu.                  */
893
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
894
/* mullw  mullw.  mullwo  mullwo.  */
895
GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07, PPC_INTEGER);
896
/* neg    neg.    nego    nego.    */
897
GEN_INT_ARITH1_64 (neg,    0x1F, 0x08, 0x03, PPC_INTEGER);
898
/* subf   subf.   subfo   subfo.   */
899
static always_inline void gen_op_subfo (void)
900
{
901
    gen_op_moven_T2_T0();
902
    gen_op_subf();
903
    gen_op_check_addo();
904
}
905
#if defined(TARGET_PPC64)
906
#define gen_op_subf_64 gen_op_subf
907
static always_inline void gen_op_subfo_64 (void)
908
{
909
    gen_op_moven_T2_T0();
910
    gen_op_subf();
911
    gen_op_check_addo_64();
912
}
913
#endif
914
GEN_INT_ARITH2_64 (subf,   0x1F, 0x08, 0x01, PPC_INTEGER);
915
/* subfc  subfc.  subfco  subfco.  */
916
static always_inline void gen_op_subfc (void)
917
{
918
    gen_op_subf();
919
    gen_op_check_subfc();
920
}
921
static always_inline void gen_op_subfco (void)
922
{
923
    gen_op_moven_T2_T0();
924
    gen_op_subf();
925
    gen_op_check_subfc();
926
    gen_op_check_addo();
927
}
928
#if defined(TARGET_PPC64)
929
static always_inline void gen_op_subfc_64 (void)
930
{
931
    gen_op_subf();
932
    gen_op_check_subfc_64();
933
}
934
static always_inline void gen_op_subfco_64 (void)
935
{
936
    gen_op_moven_T2_T0();
937
    gen_op_subf();
938
    gen_op_check_subfc_64();
939
    gen_op_check_addo_64();
940
}
941
#endif
942
GEN_INT_ARITH2_64 (subfc,  0x1F, 0x08, 0x00, PPC_INTEGER);
943
/* subfe  subfe.  subfeo  subfeo.  */
944
static always_inline void gen_op_subfeo (void)
945
{
946
    gen_op_moven_T2_T0();
947
    gen_op_subfe();
948
    gen_op_check_addo();
949
}
950
#if defined(TARGET_PPC64)
951
#define gen_op_subfe_64 gen_op_subfe
952
static always_inline void gen_op_subfeo_64 (void)
953
{
954
    gen_op_moven_T2_T0();
955
    gen_op_subfe_64();
956
    gen_op_check_addo_64();
957
}
958
#endif
959
GEN_INT_ARITH2_64 (subfe,  0x1F, 0x08, 0x04, PPC_INTEGER);
960
/* subfme subfme. subfmeo subfmeo. */
961
GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
962
/* subfze subfze. subfzeo subfzeo. */
963
GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
964
/* addi */
965
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
966
{
967
    target_long simm = SIMM(ctx->opcode);
968

    
969
    if (rA(ctx->opcode) == 0) {
970
        /* li case */
971
        gen_set_T0(simm);
972
    } else {
973
        gen_op_load_gpr_T0(rA(ctx->opcode));
974
        if (likely(simm != 0))
975
            gen_op_addi(simm);
976
    }
977
    gen_op_store_T0_gpr(rD(ctx->opcode));
978
}
979
/* addic */
980
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
981
{
982
    target_long simm = SIMM(ctx->opcode);
983

    
984
    gen_op_load_gpr_T0(rA(ctx->opcode));
985
    if (likely(simm != 0)) {
986
        gen_op_move_T2_T0();
987
        gen_op_addi(simm);
988
#if defined(TARGET_PPC64)
989
        if (ctx->sf_mode)
990
            gen_op_check_addc_64();
991
        else
992
#endif
993
            gen_op_check_addc();
994
    } else {
995
        gen_op_clear_xer_ca();
996
    }
997
    gen_op_store_T0_gpr(rD(ctx->opcode));
998
}
999
/* addic. */
1000
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1001
{
1002
    target_long simm = SIMM(ctx->opcode);
1003

    
1004
    gen_op_load_gpr_T0(rA(ctx->opcode));
1005
    if (likely(simm != 0)) {
1006
        gen_op_move_T2_T0();
1007
        gen_op_addi(simm);
1008
#if defined(TARGET_PPC64)
1009
        if (ctx->sf_mode)
1010
            gen_op_check_addc_64();
1011
        else
1012
#endif
1013
            gen_op_check_addc();
1014
    } else {
1015
        gen_op_clear_xer_ca();
1016
    }
1017
    gen_op_store_T0_gpr(rD(ctx->opcode));
1018
    gen_set_Rc0(ctx);
1019
}
1020
/* addis */
1021
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1022
{
1023
    target_long simm = SIMM(ctx->opcode);
1024

    
1025
    if (rA(ctx->opcode) == 0) {
1026
        /* lis case */
1027
        gen_set_T0(simm << 16);
1028
    } else {
1029
        gen_op_load_gpr_T0(rA(ctx->opcode));
1030
        if (likely(simm != 0))
1031
            gen_op_addi(simm << 16);
1032
    }
1033
    gen_op_store_T0_gpr(rD(ctx->opcode));
1034
}
1035
/* mulli */
1036
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1037
{
1038
    gen_op_load_gpr_T0(rA(ctx->opcode));
1039
    gen_op_mulli(SIMM(ctx->opcode));
1040
    gen_op_store_T0_gpr(rD(ctx->opcode));
1041
}
1042
/* subfic */
1043
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044
{
1045
    gen_op_load_gpr_T0(rA(ctx->opcode));
1046
#if defined(TARGET_PPC64)
1047
    if (ctx->sf_mode)
1048
        gen_op_subfic_64(SIMM(ctx->opcode));
1049
    else
1050
#endif
1051
        gen_op_subfic(SIMM(ctx->opcode));
1052
    gen_op_store_T0_gpr(rD(ctx->opcode));
1053
}
1054

    
1055
#if defined(TARGET_PPC64)
1056
/* mulhd  mulhd.                   */
1057
GEN_INT_ARITHN (mulhd,  0x1F, 0x09, 0x02, PPC_64B);
1058
/* mulhdu mulhdu.                  */
1059
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1060
/* mulld  mulld.  mulldo  mulldo.  */
1061
GEN_INT_ARITH2 (mulld,  0x1F, 0x09, 0x07, PPC_64B);
1062
/* divd   divd.   divdo   divdo.   */
1063
GEN_INT_ARITH2 (divd,   0x1F, 0x09, 0x0F, PPC_64B);
1064
/* divdu  divdu.  divduo  divduo.  */
1065
GEN_INT_ARITH2 (divdu,  0x1F, 0x09, 0x0E, PPC_64B);
1066
#endif
1067

    
1068
/***                           Integer comparison                          ***/
1069
#if defined(TARGET_PPC64)
1070
#define GEN_CMP(name, opc, type)                                              \
1071
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1072
{                                                                             \
1073
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1074
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1075
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))                           \
1076
        gen_op_##name##_64();                                                 \
1077
    else                                                                      \
1078
        gen_op_##name();                                                      \
1079
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1080
}
1081
#else
1082
#define GEN_CMP(name, opc, type)                                              \
1083
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1084
{                                                                             \
1085
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1086
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1087
    gen_op_##name();                                                          \
1088
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1089
}
1090
#endif
1091

    
1092
/* cmp */
1093
GEN_CMP(cmp, 0x00, PPC_INTEGER);
1094
/* cmpi */
1095
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1096
{
1097
    gen_op_load_gpr_T0(rA(ctx->opcode));
1098
#if defined(TARGET_PPC64)
1099
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1100
        gen_op_cmpi_64(SIMM(ctx->opcode));
1101
    else
1102
#endif
1103
        gen_op_cmpi(SIMM(ctx->opcode));
1104
    gen_op_store_T0_crf(crfD(ctx->opcode));
1105
}
1106
/* cmpl */
1107
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1108
/* cmpli */
1109
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1110
{
1111
    gen_op_load_gpr_T0(rA(ctx->opcode));
1112
#if defined(TARGET_PPC64)
1113
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1114
        gen_op_cmpli_64(UIMM(ctx->opcode));
1115
    else
1116
#endif
1117
        gen_op_cmpli(UIMM(ctx->opcode));
1118
    gen_op_store_T0_crf(crfD(ctx->opcode));
1119
}
1120

    
1121
/* isel (PowerPC 2.03 specification) */
1122
GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1123
{
1124
    uint32_t bi = rC(ctx->opcode);
1125
    uint32_t mask;
1126

    
1127
    if (rA(ctx->opcode) == 0) {
1128
        gen_set_T0(0);
1129
    } else {
1130
        gen_op_load_gpr_T1(rA(ctx->opcode));
1131
    }
1132
    gen_op_load_gpr_T2(rB(ctx->opcode));
1133
    mask = 1 << (3 - (bi & 0x03));
1134
    gen_op_load_crf_T0(bi >> 2);
1135
    gen_op_test_true(mask);
1136
    gen_op_isel();
1137
    gen_op_store_T0_gpr(rD(ctx->opcode));
1138
}
1139

    
1140
/***                            Integer logical                            ***/
1141
#define __GEN_LOGICAL2(name, opc2, opc3, type)                                \
1142
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)                         \
1143
{                                                                             \
1144
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1145
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1146
    gen_op_##name();                                                          \
1147
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1148
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1149
        gen_set_Rc0(ctx);                                                     \
1150
}
1151
#define GEN_LOGICAL2(name, opc, type)                                         \
1152
__GEN_LOGICAL2(name, 0x1C, opc, type)
1153

    
1154
#define GEN_LOGICAL1(name, opc, type)                                         \
1155
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
1156
{                                                                             \
1157
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1158
    gen_op_##name();                                                          \
1159
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1160
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1161
        gen_set_Rc0(ctx);                                                     \
1162
}
1163

    
1164
/* and & and. */
1165
GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1166
/* andc & andc. */
1167
GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1168
/* andi. */
1169
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1170
{
1171
    gen_op_load_gpr_T0(rS(ctx->opcode));
1172
    gen_op_andi_T0(UIMM(ctx->opcode));
1173
    gen_op_store_T0_gpr(rA(ctx->opcode));
1174
    gen_set_Rc0(ctx);
1175
}
1176
/* andis. */
1177
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1178
{
1179
    gen_op_load_gpr_T0(rS(ctx->opcode));
1180
    gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1181
    gen_op_store_T0_gpr(rA(ctx->opcode));
1182
    gen_set_Rc0(ctx);
1183
}
1184

    
1185
/* cntlzw */
1186
GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1187
/* eqv & eqv. */
1188
GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1189
/* extsb & extsb. */
1190
GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1191
/* extsh & extsh. */
1192
GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1193
/* nand & nand. */
1194
GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1195
/* nor & nor. */
1196
GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1197

    
1198
/* or & or. */
1199
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1200
{
1201
    int rs, ra, rb;
1202

    
1203
    rs = rS(ctx->opcode);
1204
    ra = rA(ctx->opcode);
1205
    rb = rB(ctx->opcode);
1206
    /* Optimisation for mr. ri case */
1207
    if (rs != ra || rs != rb) {
1208
        gen_op_load_gpr_T0(rs);
1209
        if (rs != rb) {
1210
            gen_op_load_gpr_T1(rb);
1211
            gen_op_or();
1212
        }
1213
        gen_op_store_T0_gpr(ra);
1214
        if (unlikely(Rc(ctx->opcode) != 0))
1215
            gen_set_Rc0(ctx);
1216
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1217
        gen_op_load_gpr_T0(rs);
1218
        gen_set_Rc0(ctx);
1219
#if defined(TARGET_PPC64)
1220
    } else {
1221
        switch (rs) {
1222
        case 1:
1223
            /* Set process priority to low */
1224
            gen_op_store_pri(2);
1225
            break;
1226
        case 6:
1227
            /* Set process priority to medium-low */
1228
            gen_op_store_pri(3);
1229
            break;
1230
        case 2:
1231
            /* Set process priority to normal */
1232
            gen_op_store_pri(4);
1233
            break;
1234
#if !defined(CONFIG_USER_ONLY)
1235
        case 31:
1236
            if (ctx->supervisor > 0) {
1237
                /* Set process priority to very low */
1238
                gen_op_store_pri(1);
1239
            }
1240
            break;
1241
        case 5:
1242
            if (ctx->supervisor > 0) {
1243
                /* Set process priority to medium-hight */
1244
                gen_op_store_pri(5);
1245
            }
1246
            break;
1247
        case 3:
1248
            if (ctx->supervisor > 0) {
1249
                /* Set process priority to high */
1250
                gen_op_store_pri(6);
1251
            }
1252
            break;
1253
#if defined(TARGET_PPC64H)
1254
        case 7:
1255
            if (ctx->supervisor > 1) {
1256
                /* Set process priority to very high */
1257
                gen_op_store_pri(7);
1258
            }
1259
            break;
1260
#endif
1261
#endif
1262
        default:
1263
            /* nop */
1264
            break;
1265
        }
1266
#endif
1267
    }
1268
}
1269

    
1270
/* orc & orc. */
1271
GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1272
/* xor & xor. */
1273
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1274
{
1275
    gen_op_load_gpr_T0(rS(ctx->opcode));
1276
    /* Optimisation for "set to zero" case */
1277
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
1278
        gen_op_load_gpr_T1(rB(ctx->opcode));
1279
        gen_op_xor();
1280
    } else {
1281
        gen_op_reset_T0();
1282
    }
1283
    gen_op_store_T0_gpr(rA(ctx->opcode));
1284
    if (unlikely(Rc(ctx->opcode) != 0))
1285
        gen_set_Rc0(ctx);
1286
}
1287
/* ori */
1288
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1289
{
1290
    target_ulong uimm = UIMM(ctx->opcode);
1291

    
1292
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1293
        /* NOP */
1294
        /* XXX: should handle special NOPs for POWER series */
1295
        return;
1296
    }
1297
    gen_op_load_gpr_T0(rS(ctx->opcode));
1298
    if (likely(uimm != 0))
1299
        gen_op_ori(uimm);
1300
    gen_op_store_T0_gpr(rA(ctx->opcode));
1301
}
1302
/* oris */
1303
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1304
{
1305
    target_ulong uimm = UIMM(ctx->opcode);
1306

    
1307
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1308
        /* NOP */
1309
        return;
1310
    }
1311
    gen_op_load_gpr_T0(rS(ctx->opcode));
1312
    if (likely(uimm != 0))
1313
        gen_op_ori(uimm << 16);
1314
    gen_op_store_T0_gpr(rA(ctx->opcode));
1315
}
1316
/* xori */
1317
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1318
{
1319
    target_ulong uimm = UIMM(ctx->opcode);
1320

    
1321
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1322
        /* NOP */
1323
        return;
1324
    }
1325
    gen_op_load_gpr_T0(rS(ctx->opcode));
1326
    if (likely(uimm != 0))
1327
        gen_op_xori(uimm);
1328
    gen_op_store_T0_gpr(rA(ctx->opcode));
1329
}
1330

    
1331
/* xoris */
1332
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1333
{
1334
    target_ulong uimm = UIMM(ctx->opcode);
1335

    
1336
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1337
        /* NOP */
1338
        return;
1339
    }
1340
    gen_op_load_gpr_T0(rS(ctx->opcode));
1341
    if (likely(uimm != 0))
1342
        gen_op_xori(uimm << 16);
1343
    gen_op_store_T0_gpr(rA(ctx->opcode));
1344
}
1345

    
1346
/* popcntb : PowerPC 2.03 specification */
1347
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1348
{
1349
    gen_op_load_gpr_T0(rS(ctx->opcode));
1350
#if defined(TARGET_PPC64)
1351
    if (ctx->sf_mode)
1352
        gen_op_popcntb_64();
1353
    else
1354
#endif
1355
        gen_op_popcntb();
1356
    gen_op_store_T0_gpr(rA(ctx->opcode));
1357
}
1358

    
1359
#if defined(TARGET_PPC64)
1360
/* extsw & extsw. */
1361
GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1362
/* cntlzd */
1363
GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1364
#endif
1365

    
1366
/***                             Integer rotate                            ***/
1367
/* rlwimi & rlwimi. */
1368
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1369
{
1370
    target_ulong mask;
1371
    uint32_t mb, me, sh;
1372

    
1373
    mb = MB(ctx->opcode);
1374
    me = ME(ctx->opcode);
1375
    sh = SH(ctx->opcode);
1376
    if (likely(sh == 0)) {
1377
        if (likely(mb == 0 && me == 31)) {
1378
            gen_op_load_gpr_T0(rS(ctx->opcode));
1379
            goto do_store;
1380
        } else if (likely(mb == 31 && me == 0)) {
1381
            gen_op_load_gpr_T0(rA(ctx->opcode));
1382
            goto do_store;
1383
        }
1384
        gen_op_load_gpr_T0(rS(ctx->opcode));
1385
        gen_op_load_gpr_T1(rA(ctx->opcode));
1386
        goto do_mask;
1387
    }
1388
    gen_op_load_gpr_T0(rS(ctx->opcode));
1389
    gen_op_load_gpr_T1(rA(ctx->opcode));
1390
    gen_op_rotli32_T0(SH(ctx->opcode));
1391
 do_mask:
1392
#if defined(TARGET_PPC64)
1393
    mb += 32;
1394
    me += 32;
1395
#endif
1396
    mask = MASK(mb, me);
1397
    gen_op_andi_T0(mask);
1398
    gen_op_andi_T1(~mask);
1399
    gen_op_or();
1400
 do_store:
1401
    gen_op_store_T0_gpr(rA(ctx->opcode));
1402
    if (unlikely(Rc(ctx->opcode) != 0))
1403
        gen_set_Rc0(ctx);
1404
}
1405
/* rlwinm & rlwinm. */
1406
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1407
{
1408
    uint32_t mb, me, sh;
1409

    
1410
    sh = SH(ctx->opcode);
1411
    mb = MB(ctx->opcode);
1412
    me = ME(ctx->opcode);
1413
    gen_op_load_gpr_T0(rS(ctx->opcode));
1414
    if (likely(sh == 0)) {
1415
        goto do_mask;
1416
    }
1417
    if (likely(mb == 0)) {
1418
        if (likely(me == 31)) {
1419
            gen_op_rotli32_T0(sh);
1420
            goto do_store;
1421
        } else if (likely(me == (31 - sh))) {
1422
            gen_op_sli_T0(sh);
1423
            goto do_store;
1424
        }
1425
    } else if (likely(me == 31)) {
1426
        if (likely(sh == (32 - mb))) {
1427
            gen_op_srli_T0(mb);
1428
            goto do_store;
1429
        }
1430
    }
1431
    gen_op_rotli32_T0(sh);
1432
 do_mask:
1433
#if defined(TARGET_PPC64)
1434
    mb += 32;
1435
    me += 32;
1436
#endif
1437
    gen_op_andi_T0(MASK(mb, me));
1438
 do_store:
1439
    gen_op_store_T0_gpr(rA(ctx->opcode));
1440
    if (unlikely(Rc(ctx->opcode) != 0))
1441
        gen_set_Rc0(ctx);
1442
}
1443
/* rlwnm & rlwnm. */
1444
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1445
{
1446
    uint32_t mb, me;
1447

    
1448
    mb = MB(ctx->opcode);
1449
    me = ME(ctx->opcode);
1450
    gen_op_load_gpr_T0(rS(ctx->opcode));
1451
    gen_op_load_gpr_T1(rB(ctx->opcode));
1452
    gen_op_rotl32_T0_T1();
1453
    if (unlikely(mb != 0 || me != 31)) {
1454
#if defined(TARGET_PPC64)
1455
        mb += 32;
1456
        me += 32;
1457
#endif
1458
        gen_op_andi_T0(MASK(mb, me));
1459
    }
1460
    gen_op_store_T0_gpr(rA(ctx->opcode));
1461
    if (unlikely(Rc(ctx->opcode) != 0))
1462
        gen_set_Rc0(ctx);
1463
}
1464

    
1465
#if defined(TARGET_PPC64)
1466
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1467
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1468
{                                                                             \
1469
    gen_##name(ctx, 0);                                                       \
1470
}                                                                             \
1471
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1472
             PPC_64B)                                                         \
1473
{                                                                             \
1474
    gen_##name(ctx, 1);                                                       \
1475
}
1476
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1477
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1478
{                                                                             \
1479
    gen_##name(ctx, 0, 0);                                                    \
1480
}                                                                             \
1481
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
1482
             PPC_64B)                                                         \
1483
{                                                                             \
1484
    gen_##name(ctx, 0, 1);                                                    \
1485
}                                                                             \
1486
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1487
             PPC_64B)                                                         \
1488
{                                                                             \
1489
    gen_##name(ctx, 1, 0);                                                    \
1490
}                                                                             \
1491
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
1492
             PPC_64B)                                                         \
1493
{                                                                             \
1494
    gen_##name(ctx, 1, 1);                                                    \
1495
}
1496

    
1497
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1498
{
1499
    if (mask >> 32)
1500
        gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1501
    else
1502
        gen_op_andi_T0(mask);
1503
}
1504

    
1505
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1506
{
1507
    if (mask >> 32)
1508
        gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1509
    else
1510
        gen_op_andi_T1(mask);
1511
}
1512

    
1513
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1514
                                      uint32_t me, uint32_t sh)
1515
{
1516
    gen_op_load_gpr_T0(rS(ctx->opcode));
1517
    if (likely(sh == 0)) {
1518
        goto do_mask;
1519
    }
1520
    if (likely(mb == 0)) {
1521
        if (likely(me == 63)) {
1522
            gen_op_rotli64_T0(sh);
1523
            goto do_store;
1524
        } else if (likely(me == (63 - sh))) {
1525
            gen_op_sli_T0(sh);
1526
            goto do_store;
1527
        }
1528
    } else if (likely(me == 63)) {
1529
        if (likely(sh == (64 - mb))) {
1530
            gen_op_srli_T0_64(mb);
1531
            goto do_store;
1532
        }
1533
    }
1534
    gen_op_rotli64_T0(sh);
1535
 do_mask:
1536
    gen_andi_T0_64(ctx, MASK(mb, me));
1537
 do_store:
1538
    gen_op_store_T0_gpr(rA(ctx->opcode));
1539
    if (unlikely(Rc(ctx->opcode) != 0))
1540
        gen_set_Rc0(ctx);
1541
}
1542
/* rldicl - rldicl. */
1543
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1544
{
1545
    uint32_t sh, mb;
1546

    
1547
    sh = SH(ctx->opcode) | (shn << 5);
1548
    mb = MB(ctx->opcode) | (mbn << 5);
1549
    gen_rldinm(ctx, mb, 63, sh);
1550
}
1551
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1552
/* rldicr - rldicr. */
1553
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1554
{
1555
    uint32_t sh, me;
1556

    
1557
    sh = SH(ctx->opcode) | (shn << 5);
1558
    me = MB(ctx->opcode) | (men << 5);
1559
    gen_rldinm(ctx, 0, me, sh);
1560
}
1561
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1562
/* rldic - rldic. */
1563
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1564
{
1565
    uint32_t sh, mb;
1566

    
1567
    sh = SH(ctx->opcode) | (shn << 5);
1568
    mb = MB(ctx->opcode) | (mbn << 5);
1569
    gen_rldinm(ctx, mb, 63 - sh, sh);
1570
}
1571
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1572

    
1573
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1574
                                     uint32_t me)
1575
{
1576
    gen_op_load_gpr_T0(rS(ctx->opcode));
1577
    gen_op_load_gpr_T1(rB(ctx->opcode));
1578
    gen_op_rotl64_T0_T1();
1579
    if (unlikely(mb != 0 || me != 63)) {
1580
        gen_andi_T0_64(ctx, MASK(mb, me));
1581
    }
1582
    gen_op_store_T0_gpr(rA(ctx->opcode));
1583
    if (unlikely(Rc(ctx->opcode) != 0))
1584
        gen_set_Rc0(ctx);
1585
}
1586

    
1587
/* rldcl - rldcl. */
1588
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1589
{
1590
    uint32_t mb;
1591

    
1592
    mb = MB(ctx->opcode) | (mbn << 5);
1593
    gen_rldnm(ctx, mb, 63);
1594
}
1595
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1596
/* rldcr - rldcr. */
1597
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1598
{
1599
    uint32_t me;
1600

    
1601
    me = MB(ctx->opcode) | (men << 5);
1602
    gen_rldnm(ctx, 0, me);
1603
}
1604
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1605
/* rldimi - rldimi. */
1606
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1607
{
1608
    uint64_t mask;
1609
    uint32_t sh, mb;
1610

    
1611
    sh = SH(ctx->opcode) | (shn << 5);
1612
    mb = MB(ctx->opcode) | (mbn << 5);
1613
    if (likely(sh == 0)) {
1614
        if (likely(mb == 0)) {
1615
            gen_op_load_gpr_T0(rS(ctx->opcode));
1616
            goto do_store;
1617
        } else if (likely(mb == 63)) {
1618
            gen_op_load_gpr_T0(rA(ctx->opcode));
1619
            goto do_store;
1620
        }
1621
        gen_op_load_gpr_T0(rS(ctx->opcode));
1622
        gen_op_load_gpr_T1(rA(ctx->opcode));
1623
        goto do_mask;
1624
    }
1625
    gen_op_load_gpr_T0(rS(ctx->opcode));
1626
    gen_op_load_gpr_T1(rA(ctx->opcode));
1627
    gen_op_rotli64_T0(sh);
1628
 do_mask:
1629
    mask = MASK(mb, 63 - sh);
1630
    gen_andi_T0_64(ctx, mask);
1631
    gen_andi_T1_64(ctx, ~mask);
1632
    gen_op_or();
1633
 do_store:
1634
    gen_op_store_T0_gpr(rA(ctx->opcode));
1635
    if (unlikely(Rc(ctx->opcode) != 0))
1636
        gen_set_Rc0(ctx);
1637
}
1638
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1639
#endif
1640

    
1641
/***                             Integer shift                             ***/
1642
/* slw & slw. */
1643
__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1644
/* sraw & sraw. */
1645
__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1646
/* srawi & srawi. */
1647
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1648
{
1649
    int mb, me;
1650
    gen_op_load_gpr_T0(rS(ctx->opcode));
1651
    if (SH(ctx->opcode) != 0) {
1652
        gen_op_move_T1_T0();
1653
        mb = 32 - SH(ctx->opcode);
1654
        me = 31;
1655
#if defined(TARGET_PPC64)
1656
        mb += 32;
1657
        me += 32;
1658
#endif
1659
        gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1660
    }
1661
    gen_op_store_T0_gpr(rA(ctx->opcode));
1662
    if (unlikely(Rc(ctx->opcode) != 0))
1663
        gen_set_Rc0(ctx);
1664
}
1665
/* srw & srw. */
1666
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1667

    
1668
#if defined(TARGET_PPC64)
1669
/* sld & sld. */
1670
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1671
/* srad & srad. */
1672
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1673
/* sradi & sradi. */
1674
static always_inline void gen_sradi (DisasContext *ctx, int n)
1675
{
1676
    uint64_t mask;
1677
    int sh, mb, me;
1678

    
1679
    gen_op_load_gpr_T0(rS(ctx->opcode));
1680
    sh = SH(ctx->opcode) + (n << 5);
1681
    if (sh != 0) {
1682
        gen_op_move_T1_T0();
1683
        mb = 64 - SH(ctx->opcode);
1684
        me = 63;
1685
        mask = MASK(mb, me);
1686
        gen_op_sradi(sh, mask >> 32, mask);
1687
    }
1688
    gen_op_store_T0_gpr(rA(ctx->opcode));
1689
    if (unlikely(Rc(ctx->opcode) != 0))
1690
        gen_set_Rc0(ctx);
1691
}
1692
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1693
{
1694
    gen_sradi(ctx, 0);
1695
}
1696
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1697
{
1698
    gen_sradi(ctx, 1);
1699
}
1700
/* srd & srd. */
1701
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1702
#endif
1703

    
1704
/***                       Floating-Point arithmetic                       ***/
1705
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
1706
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
1707
{                                                                             \
1708
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1709
        GEN_EXCP_NO_FP(ctx);                                                  \
1710
        return;                                                               \
1711
    }                                                                         \
1712
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1713
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1714
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
1715
    gen_reset_fpstatus();                                                     \
1716
    gen_op_f##op();                                                           \
1717
    if (isfloat) {                                                            \
1718
        gen_op_frsp();                                                        \
1719
    }                                                                         \
1720
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1721
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1722
}
1723

    
1724
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
1725
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
1726
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1727

    
1728
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1729
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1730
{                                                                             \
1731
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1732
        GEN_EXCP_NO_FP(ctx);                                                  \
1733
        return;                                                               \
1734
    }                                                                         \
1735
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1736
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
1737
    gen_reset_fpstatus();                                                     \
1738
    gen_op_f##op();                                                           \
1739
    if (isfloat) {                                                            \
1740
        gen_op_frsp();                                                        \
1741
    }                                                                         \
1742
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1743
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1744
}
1745
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
1746
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1747
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1748

    
1749
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1750
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1751
{                                                                             \
1752
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1753
        GEN_EXCP_NO_FP(ctx);                                                  \
1754
        return;                                                               \
1755
    }                                                                         \
1756
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1757
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1758
    gen_reset_fpstatus();                                                     \
1759
    gen_op_f##op();                                                           \
1760
    if (isfloat) {                                                            \
1761
        gen_op_frsp();                                                        \
1762
    }                                                                         \
1763
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1764
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1765
}
1766
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
1767
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1768
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1769

    
1770
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
1771
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
1772
{                                                                             \
1773
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1774
        GEN_EXCP_NO_FP(ctx);                                                  \
1775
        return;                                                               \
1776
    }                                                                         \
1777
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1778
    gen_reset_fpstatus();                                                     \
1779
    gen_op_f##name();                                                         \
1780
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1781
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1782
}
1783

    
1784
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
1785
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
1786
{                                                                             \
1787
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1788
        GEN_EXCP_NO_FP(ctx);                                                  \
1789
        return;                                                               \
1790
    }                                                                         \
1791
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1792
    gen_reset_fpstatus();                                                     \
1793
    gen_op_f##name();                                                         \
1794
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1795
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1796
}
1797

    
1798
/* fadd - fadds */
1799
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1800
/* fdiv - fdivs */
1801
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1802
/* fmul - fmuls */
1803
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1804

    
1805
/* fre */
1806
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1807

    
1808
/* fres */
1809
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1810

    
1811
/* frsqrte */
1812
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1813

    
1814
/* frsqrtes */
1815
static always_inline void gen_op_frsqrtes (void)
1816
{
1817
    gen_op_frsqrte();
1818
    gen_op_frsp();
1819
}
1820
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1821

    
1822
/* fsel */
1823
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1824
/* fsub - fsubs */
1825
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1826
/* Optional: */
1827
/* fsqrt */
1828
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1829
{
1830
    if (unlikely(!ctx->fpu_enabled)) {
1831
        GEN_EXCP_NO_FP(ctx);
1832
        return;
1833
    }
1834
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1835
    gen_reset_fpstatus();
1836
    gen_op_fsqrt();
1837
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1838
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1839
}
1840

    
1841
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1842
{
1843
    if (unlikely(!ctx->fpu_enabled)) {
1844
        GEN_EXCP_NO_FP(ctx);
1845
        return;
1846
    }
1847
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1848
    gen_reset_fpstatus();
1849
    gen_op_fsqrt();
1850
    gen_op_frsp();
1851
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1852
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1853
}
1854

    
1855
/***                     Floating-Point multiply-and-add                   ***/
1856
/* fmadd - fmadds */
1857
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1858
/* fmsub - fmsubs */
1859
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1860
/* fnmadd - fnmadds */
1861
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1862
/* fnmsub - fnmsubs */
1863
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1864

    
1865
/***                     Floating-Point round & convert                    ***/
1866
/* fctiw */
1867
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1868
/* fctiwz */
1869
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1870
/* frsp */
1871
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1872
#if defined(TARGET_PPC64)
1873
/* fcfid */
1874
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1875
/* fctid */
1876
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1877
/* fctidz */
1878
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1879
#endif
1880

    
1881
/* frin */
1882
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1883
/* friz */
1884
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1885
/* frip */
1886
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1887
/* frim */
1888
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1889

    
1890
/***                         Floating-Point compare                        ***/
1891
/* fcmpo */
1892
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1893
{
1894
    if (unlikely(!ctx->fpu_enabled)) {
1895
        GEN_EXCP_NO_FP(ctx);
1896
        return;
1897
    }
1898
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1899
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1900
    gen_reset_fpstatus();
1901
    gen_op_fcmpo();
1902
    gen_op_store_T0_crf(crfD(ctx->opcode));
1903
    gen_op_float_check_status();
1904
}
1905

    
1906
/* fcmpu */
1907
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1908
{
1909
    if (unlikely(!ctx->fpu_enabled)) {
1910
        GEN_EXCP_NO_FP(ctx);
1911
        return;
1912
    }
1913
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1914
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1915
    gen_reset_fpstatus();
1916
    gen_op_fcmpu();
1917
    gen_op_store_T0_crf(crfD(ctx->opcode));
1918
    gen_op_float_check_status();
1919
}
1920

    
1921
/***                         Floating-point move                           ***/
1922
/* fabs */
1923
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1924
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1925

    
1926
/* fmr  - fmr. */
1927
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1928
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1929
{
1930
    if (unlikely(!ctx->fpu_enabled)) {
1931
        GEN_EXCP_NO_FP(ctx);
1932
        return;
1933
    }
1934
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1935
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1936
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1937
}
1938

    
1939
/* fnabs */
1940
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1941
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1942
/* fneg */
1943
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1944
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1945

    
1946
/***                  Floating-Point status & ctrl register                ***/
1947
/* mcrfs */
1948
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1949
{
1950
    int bfa;
1951

    
1952
    if (unlikely(!ctx->fpu_enabled)) {
1953
        GEN_EXCP_NO_FP(ctx);
1954
        return;
1955
    }
1956
    gen_optimize_fprf();
1957
    bfa = 4 * (7 - crfS(ctx->opcode));
1958
    gen_op_load_fpscr_T0(bfa);
1959
    gen_op_store_T0_crf(crfD(ctx->opcode));
1960
    gen_op_fpscr_resetbit(~(0xF << bfa));
1961
}
1962

    
1963
/* mffs */
1964
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1965
{
1966
    if (unlikely(!ctx->fpu_enabled)) {
1967
        GEN_EXCP_NO_FP(ctx);
1968
        return;
1969
    }
1970
    gen_optimize_fprf();
1971
    gen_reset_fpstatus();
1972
    gen_op_load_fpscr_FT0();
1973
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1974
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1975
}
1976

    
1977
/* mtfsb0 */
1978
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1979
{
1980
    uint8_t crb;
1981

    
1982
    if (unlikely(!ctx->fpu_enabled)) {
1983
        GEN_EXCP_NO_FP(ctx);
1984
        return;
1985
    }
1986
    crb = 32 - (crbD(ctx->opcode) >> 2);
1987
    gen_optimize_fprf();
1988
    gen_reset_fpstatus();
1989
    if (likely(crb != 30 && crb != 29))
1990
        gen_op_fpscr_resetbit(~(1 << crb));
1991
    if (unlikely(Rc(ctx->opcode) != 0)) {
1992
        gen_op_load_fpcc();
1993
        gen_op_set_Rc0();
1994
    }
1995
}
1996

    
1997
/* mtfsb1 */
1998
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1999
{
2000
    uint8_t crb;
2001

    
2002
    if (unlikely(!ctx->fpu_enabled)) {
2003
        GEN_EXCP_NO_FP(ctx);
2004
        return;
2005
    }
2006
    crb = 32 - (crbD(ctx->opcode) >> 2);
2007
    gen_optimize_fprf();
2008
    gen_reset_fpstatus();
2009
    /* XXX: we pretend we can only do IEEE floating-point computations */
2010
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2011
        gen_op_fpscr_setbit(crb);
2012
    if (unlikely(Rc(ctx->opcode) != 0)) {
2013
        gen_op_load_fpcc();
2014
        gen_op_set_Rc0();
2015
    }
2016
    /* We can raise a differed exception */
2017
    gen_op_float_check_status();
2018
}
2019

    
2020
/* mtfsf */
2021
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2022
{
2023
    if (unlikely(!ctx->fpu_enabled)) {
2024
        GEN_EXCP_NO_FP(ctx);
2025
        return;
2026
    }
2027
    gen_optimize_fprf();
2028
    gen_op_load_fpr_FT0(rB(ctx->opcode));
2029
    gen_reset_fpstatus();
2030
    gen_op_store_fpscr(FM(ctx->opcode));
2031
    if (unlikely(Rc(ctx->opcode) != 0)) {
2032
        gen_op_load_fpcc();
2033
        gen_op_set_Rc0();
2034
    }
2035
    /* We can raise a differed exception */
2036
    gen_op_float_check_status();
2037
}
2038

    
2039
/* mtfsfi */
2040
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2041
{
2042
    int bf, sh;
2043

    
2044
    if (unlikely(!ctx->fpu_enabled)) {
2045
        GEN_EXCP_NO_FP(ctx);
2046
        return;
2047
    }
2048
    bf = crbD(ctx->opcode) >> 2;
2049
    sh = 7 - bf;
2050
    gen_optimize_fprf();
2051
    gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2052
    gen_reset_fpstatus();
2053
    gen_op_store_fpscr(1 << sh);
2054
    if (unlikely(Rc(ctx->opcode) != 0)) {
2055
        gen_op_load_fpcc();
2056
        gen_op_set_Rc0();
2057
    }
2058
    /* We can raise a differed exception */
2059
    gen_op_float_check_status();
2060
}
2061

    
2062
/***                           Addressing modes                            ***/
2063
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2064
static always_inline void gen_addr_imm_index (DisasContext *ctx,
2065
                                              target_long maskl)
2066
{
2067
    target_long simm = SIMM(ctx->opcode);
2068

    
2069
    simm &= ~maskl;
2070
    if (rA(ctx->opcode) == 0) {
2071
        gen_set_T0(simm);
2072
    } else {
2073
        gen_op_load_gpr_T0(rA(ctx->opcode));
2074
        if (likely(simm != 0))
2075
            gen_op_addi(simm);
2076
    }
2077
#ifdef DEBUG_MEMORY_ACCESSES
2078
    gen_op_print_mem_EA();
2079
#endif
2080
}
2081

    
2082
static always_inline void gen_addr_reg_index (DisasContext *ctx)
2083
{
2084
    if (rA(ctx->opcode) == 0) {
2085
        gen_op_load_gpr_T0(rB(ctx->opcode));
2086
    } else {
2087
        gen_op_load_gpr_T0(rA(ctx->opcode));
2088
        gen_op_load_gpr_T1(rB(ctx->opcode));
2089
        gen_op_add();
2090
    }
2091
#ifdef DEBUG_MEMORY_ACCESSES
2092
    gen_op_print_mem_EA();
2093
#endif
2094
}
2095

    
2096
static always_inline void gen_addr_register (DisasContext *ctx)
2097
{
2098
    if (rA(ctx->opcode) == 0) {
2099
        gen_op_reset_T0();
2100
    } else {
2101
        gen_op_load_gpr_T0(rA(ctx->opcode));
2102
    }
2103
#ifdef DEBUG_MEMORY_ACCESSES
2104
    gen_op_print_mem_EA();
2105
#endif
2106
}
2107

    
2108
/***                             Integer load                              ***/
2109
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
2110
#if defined(CONFIG_USER_ONLY)
2111
#if defined(TARGET_PPC64)
2112
/* User mode only - 64 bits */
2113
#define OP_LD_TABLE(width)                                                    \
2114
static GenOpFunc *gen_op_l##width[] = {                                       \
2115
    &gen_op_l##width##_raw,                                                   \
2116
    &gen_op_l##width##_le_raw,                                                \
2117
    &gen_op_l##width##_64_raw,                                                \
2118
    &gen_op_l##width##_le_64_raw,                                             \
2119
};
2120
#define OP_ST_TABLE(width)                                                    \
2121
static GenOpFunc *gen_op_st##width[] = {                                      \
2122
    &gen_op_st##width##_raw,                                                  \
2123
    &gen_op_st##width##_le_raw,                                               \
2124
    &gen_op_st##width##_64_raw,                                               \
2125
    &gen_op_st##width##_le_64_raw,                                            \
2126
};
2127
/* Byte access routine are endian safe */
2128
#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2129
#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2130
#else
2131
/* User mode only - 32 bits */
2132
#define OP_LD_TABLE(width)                                                    \
2133
static GenOpFunc *gen_op_l##width[] = {                                       \
2134
    &gen_op_l##width##_raw,                                                   \
2135
    &gen_op_l##width##_le_raw,                                                \
2136
};
2137
#define OP_ST_TABLE(width)                                                    \
2138
static GenOpFunc *gen_op_st##width[] = {                                      \
2139
    &gen_op_st##width##_raw,                                                  \
2140
    &gen_op_st##width##_le_raw,                                               \
2141
};
2142
#endif
2143
/* Byte access routine are endian safe */
2144
#define gen_op_stb_le_raw gen_op_stb_raw
2145
#define gen_op_lbz_le_raw gen_op_lbz_raw
2146
#else
2147
#if defined(TARGET_PPC64)
2148
#if defined(TARGET_PPC64H)
2149
/* Full system - 64 bits with hypervisor mode */
2150
#define OP_LD_TABLE(width)                                                    \
2151
static GenOpFunc *gen_op_l##width[] = {                                       \
2152
    &gen_op_l##width##_user,                                                  \
2153
    &gen_op_l##width##_le_user,                                               \
2154
    &gen_op_l##width##_64_user,                                               \
2155
    &gen_op_l##width##_le_64_user,                                            \
2156
    &gen_op_l##width##_kernel,                                                \
2157
    &gen_op_l##width##_le_kernel,                                             \
2158
    &gen_op_l##width##_64_kernel,                                             \
2159
    &gen_op_l##width##_le_64_kernel,                                          \
2160
    &gen_op_l##width##_hypv,                                                  \
2161
    &gen_op_l##width##_le_hypv,                                               \
2162
    &gen_op_l##width##_64_hypv,                                               \
2163
    &gen_op_l##width##_le_64_hypv,                                            \
2164
};
2165
#define OP_ST_TABLE(width)                                                    \
2166
static GenOpFunc *gen_op_st##width[] = {                                      \
2167
    &gen_op_st##width##_user,                                                 \
2168
    &gen_op_st##width##_le_user,                                              \
2169
    &gen_op_st##width##_64_user,                                              \
2170
    &gen_op_st##width##_le_64_user,                                           \
2171
    &gen_op_st##width##_kernel,                                               \
2172
    &gen_op_st##width##_le_kernel,                                            \
2173
    &gen_op_st##width##_64_kernel,                                            \
2174
    &gen_op_st##width##_le_64_kernel,                                         \
2175
    &gen_op_st##width##_hypv,                                                 \
2176
    &gen_op_st##width##_le_hypv,                                              \
2177
    &gen_op_st##width##_64_hypv,                                              \
2178
    &gen_op_st##width##_le_64_hypv,                                           \
2179
};
2180
/* Byte access routine are endian safe */
2181
#define gen_op_stb_le_hypv      gen_op_stb_64_hypv
2182
#define gen_op_lbz_le_hypv      gen_op_lbz_64_hypv
2183
#define gen_op_stb_le_64_hypv   gen_op_stb_64_hypv
2184
#define gen_op_lbz_le_64_hypv   gen_op_lbz_64_hypv
2185
#else
2186
/* Full system - 64 bits */
2187
#define OP_LD_TABLE(width)                                                    \
2188
static GenOpFunc *gen_op_l##width[] = {                                       \
2189
    &gen_op_l##width##_user,                                                  \
2190
    &gen_op_l##width##_le_user,                                               \
2191
    &gen_op_l##width##_64_user,                                               \
2192
    &gen_op_l##width##_le_64_user,                                            \
2193
    &gen_op_l##width##_kernel,                                                \
2194
    &gen_op_l##width##_le_kernel,                                             \
2195
    &gen_op_l##width##_64_kernel,                                             \
2196
    &gen_op_l##width##_le_64_kernel,                                          \
2197
};
2198
#define OP_ST_TABLE(width)                                                    \
2199
static GenOpFunc *gen_op_st##width[] = {                                      \
2200
    &gen_op_st##width##_user,                                                 \
2201
    &gen_op_st##width##_le_user,                                              \
2202
    &gen_op_st##width##_64_user,                                              \
2203
    &gen_op_st##width##_le_64_user,                                           \
2204
    &gen_op_st##width##_kernel,                                               \
2205
    &gen_op_st##width##_le_kernel,                                            \
2206
    &gen_op_st##width##_64_kernel,                                            \
2207
    &gen_op_st##width##_le_64_kernel,                                         \
2208
};
2209
#endif
2210
/* Byte access routine are endian safe */
2211
#define gen_op_stb_le_64_user   gen_op_stb_64_user
2212
#define gen_op_lbz_le_64_user   gen_op_lbz_64_user
2213
#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2214
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2215
#else
2216
/* Full system - 32 bits */
2217
#define OP_LD_TABLE(width)                                                    \
2218
static GenOpFunc *gen_op_l##width[] = {                                       \
2219
    &gen_op_l##width##_user,                                                  \
2220
    &gen_op_l##width##_le_user,                                               \
2221
    &gen_op_l##width##_kernel,                                                \
2222
    &gen_op_l##width##_le_kernel,                                             \
2223
};
2224
#define OP_ST_TABLE(width)                                                    \
2225
static GenOpFunc *gen_op_st##width[] = {                                      \
2226
    &gen_op_st##width##_user,                                                 \
2227
    &gen_op_st##width##_le_user,                                              \
2228
    &gen_op_st##width##_kernel,                                               \
2229
    &gen_op_st##width##_le_kernel,                                            \
2230
};
2231
#endif
2232
/* Byte access routine are endian safe */
2233
#define gen_op_stb_le_user   gen_op_stb_user
2234
#define gen_op_lbz_le_user   gen_op_lbz_user
2235
#define gen_op_stb_le_kernel gen_op_stb_kernel
2236
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2237
#endif
2238

    
2239
#define GEN_LD(width, opc, type)                                              \
2240
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2241
{                                                                             \
2242
    gen_addr_imm_index(ctx, 0);                                               \
2243
    op_ldst(l##width);                                                        \
2244
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2245
}
2246

    
2247
#define GEN_LDU(width, opc, type)                                             \
2248
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2249
{                                                                             \
2250
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2251
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2252
        GEN_EXCP_INVAL(ctx);                                                  \
2253
        return;                                                               \
2254
    }                                                                         \
2255
    if (type == PPC_64B)                                                      \
2256
        gen_addr_imm_index(ctx, 0x03);                                        \
2257
    else                                                                      \
2258
        gen_addr_imm_index(ctx, 0);                                           \
2259
    op_ldst(l##width);                                                        \
2260
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2261
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2262
}
2263

    
2264
#define GEN_LDUX(width, opc2, opc3, type)                                     \
2265
GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                 \
2266
{                                                                             \
2267
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2268
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2269
        GEN_EXCP_INVAL(ctx);                                                  \
2270
        return;                                                               \
2271
    }                                                                         \
2272
    gen_addr_reg_index(ctx);                                                  \
2273
    op_ldst(l##width);                                                        \
2274
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2275
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2276
}
2277

    
2278
#define GEN_LDX(width, opc2, opc3, type)                                      \
2279
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2280
{                                                                             \
2281
    gen_addr_reg_index(ctx);                                                  \
2282
    op_ldst(l##width);                                                        \
2283
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2284
}
2285

    
2286
#define GEN_LDS(width, op, type)                                              \
2287
OP_LD_TABLE(width);                                                           \
2288
GEN_LD(width, op | 0x20, type);                                               \
2289
GEN_LDU(width, op | 0x21, type);                                              \
2290
GEN_LDUX(width, 0x17, op | 0x01, type);                                       \
2291
GEN_LDX(width, 0x17, op | 0x00, type)
2292

    
2293
/* lbz lbzu lbzux lbzx */
2294
GEN_LDS(bz, 0x02, PPC_INTEGER);
2295
/* lha lhau lhaux lhax */
2296
GEN_LDS(ha, 0x0A, PPC_INTEGER);
2297
/* lhz lhzu lhzux lhzx */
2298
GEN_LDS(hz, 0x08, PPC_INTEGER);
2299
/* lwz lwzu lwzux lwzx */
2300
GEN_LDS(wz, 0x00, PPC_INTEGER);
2301
#if defined(TARGET_PPC64)
2302
OP_LD_TABLE(wa);
2303
OP_LD_TABLE(d);
2304
/* lwaux */
2305
GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2306
/* lwax */
2307
GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2308
/* ldux */
2309
GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2310
/* ldx */
2311
GEN_LDX(d, 0x15, 0x00, PPC_64B);
2312
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2313
{
2314
    if (Rc(ctx->opcode)) {
2315
        if (unlikely(rA(ctx->opcode) == 0 ||
2316
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2317
            GEN_EXCP_INVAL(ctx);
2318
            return;
2319
        }
2320
    }
2321
    gen_addr_imm_index(ctx, 0x03);
2322
    if (ctx->opcode & 0x02) {
2323
        /* lwa (lwau is undefined) */
2324
        op_ldst(lwa);
2325
    } else {
2326
        /* ld - ldu */
2327
        op_ldst(ld);
2328
    }
2329
    gen_op_store_T1_gpr(rD(ctx->opcode));
2330
    if (Rc(ctx->opcode))
2331
        gen_op_store_T0_gpr(rA(ctx->opcode));
2332
}
2333
/* lq */
2334
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2335
{
2336
#if defined(CONFIG_USER_ONLY)
2337
    GEN_EXCP_PRIVOPC(ctx);
2338
#else
2339
    int ra, rd;
2340

    
2341
    /* Restore CPU state */
2342
    if (unlikely(ctx->supervisor == 0)) {
2343
        GEN_EXCP_PRIVOPC(ctx);
2344
        return;
2345
    }
2346
    ra = rA(ctx->opcode);
2347
    rd = rD(ctx->opcode);
2348
    if (unlikely((rd & 1) || rd == ra)) {
2349
        GEN_EXCP_INVAL(ctx);
2350
        return;
2351
    }
2352
    if (unlikely(ctx->mem_idx & 1)) {
2353
        /* Little-endian mode is not handled */
2354
        GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2355
        return;
2356
    }
2357
    gen_addr_imm_index(ctx, 0x0F);
2358
    op_ldst(ld);
2359
    gen_op_store_T1_gpr(rd);
2360
    gen_op_addi(8);
2361
    op_ldst(ld);
2362
    gen_op_store_T1_gpr(rd + 1);
2363
#endif
2364
}
2365
#endif
2366

    
2367
/***                              Integer store                            ***/
2368
#define GEN_ST(width, opc, type)                                              \
2369
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2370
{                                                                             \
2371
    gen_addr_imm_index(ctx, 0);                                               \
2372
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2373
    op_ldst(st##width);                                                       \
2374
}
2375

    
2376
#define GEN_STU(width, opc, type)                                             \
2377
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2378
{                                                                             \
2379
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2380
        GEN_EXCP_INVAL(ctx);                                                  \
2381
        return;                                                               \
2382
    }                                                                         \
2383
    if (type == PPC_64B)                                                      \
2384
        gen_addr_imm_index(ctx, 0x03);                                        \
2385
    else                                                                      \
2386
        gen_addr_imm_index(ctx, 0);                                           \
2387
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2388
    op_ldst(st##width);                                                       \
2389
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2390
}
2391

    
2392
#define GEN_STUX(width, opc2, opc3, type)                                     \
2393
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
2394
{                                                                             \
2395
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2396
        GEN_EXCP_INVAL(ctx);                                                  \
2397
        return;                                                               \
2398
    }                                                                         \
2399
    gen_addr_reg_index(ctx);                                                  \
2400
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2401
    op_ldst(st##width);                                                       \
2402
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2403
}
2404

    
2405
#define GEN_STX(width, opc2, opc3, type)                                      \
2406
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2407
{                                                                             \
2408
    gen_addr_reg_index(ctx);                                                  \
2409
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2410
    op_ldst(st##width);                                                       \
2411
}
2412

    
2413
#define GEN_STS(width, op, type)                                              \
2414
OP_ST_TABLE(width);                                                           \
2415
GEN_ST(width, op | 0x20, type);                                               \
2416
GEN_STU(width, op | 0x21, type);                                              \
2417
GEN_STUX(width, 0x17, op | 0x01, type);                                       \
2418
GEN_STX(width, 0x17, op | 0x00, type)
2419

    
2420
/* stb stbu stbux stbx */
2421
GEN_STS(b, 0x06, PPC_INTEGER);
2422
/* sth sthu sthux sthx */
2423
GEN_STS(h, 0x0C, PPC_INTEGER);
2424
/* stw stwu stwux stwx */
2425
GEN_STS(w, 0x04, PPC_INTEGER);
2426
#if defined(TARGET_PPC64)
2427
OP_ST_TABLE(d);
2428
GEN_STUX(d, 0x15, 0x05, PPC_64B);
2429
GEN_STX(d, 0x15, 0x04, PPC_64B);
2430
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2431
{
2432
    int rs;
2433

    
2434
    rs = rS(ctx->opcode);
2435
    if ((ctx->opcode & 0x3) == 0x2) {
2436
#if defined(CONFIG_USER_ONLY)
2437
        GEN_EXCP_PRIVOPC(ctx);
2438
#else
2439
        /* stq */
2440
        if (unlikely(ctx->supervisor == 0)) {
2441
            GEN_EXCP_PRIVOPC(ctx);
2442
            return;
2443
        }
2444
        if (unlikely(rs & 1)) {
2445
            GEN_EXCP_INVAL(ctx);
2446
            return;
2447
        }
2448
        if (unlikely(ctx->mem_idx & 1)) {
2449
            /* Little-endian mode is not handled */
2450
            GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2451
            return;
2452
        }
2453
        gen_addr_imm_index(ctx, 0x03);
2454
        gen_op_load_gpr_T1(rs);
2455
        op_ldst(std);
2456
        gen_op_addi(8);
2457
        gen_op_load_gpr_T1(rs + 1);
2458
        op_ldst(std);
2459
#endif
2460
    } else {
2461
        /* std / stdu */
2462
        if (Rc(ctx->opcode)) {
2463
            if (unlikely(rA(ctx->opcode) == 0)) {
2464
                GEN_EXCP_INVAL(ctx);
2465
                return;
2466
            }
2467
        }
2468
        gen_addr_imm_index(ctx, 0x03);
2469
        gen_op_load_gpr_T1(rs);
2470
        op_ldst(std);
2471
        if (Rc(ctx->opcode))
2472
            gen_op_store_T0_gpr(rA(ctx->opcode));
2473
    }
2474
}
2475
#endif
2476
/***                Integer load and store with byte reverse               ***/
2477
/* lhbrx */
2478
OP_LD_TABLE(hbr);
2479
GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2480
/* lwbrx */
2481
OP_LD_TABLE(wbr);
2482
GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2483
/* sthbrx */
2484
OP_ST_TABLE(hbr);
2485
GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2486
/* stwbrx */
2487
OP_ST_TABLE(wbr);
2488
GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2489

    
2490
/***                    Integer load and store multiple                    ***/
2491
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2492
#if defined(CONFIG_USER_ONLY)
2493
/* User-mode only */
2494
static GenOpFunc1 *gen_op_lmw[] = {
2495
    &gen_op_lmw_raw,
2496
    &gen_op_lmw_le_raw,
2497
#if defined(TARGET_PPC64)
2498
    &gen_op_lmw_64_raw,
2499
    &gen_op_lmw_le_64_raw,
2500
#endif
2501
};
2502
static GenOpFunc1 *gen_op_stmw[] = {
2503
    &gen_op_stmw_raw,
2504
    &gen_op_stmw_le_raw,
2505
#if defined(TARGET_PPC64)
2506
    &gen_op_stmw_64_raw,
2507
    &gen_op_stmw_le_64_raw,
2508
#endif
2509
};
2510
#else
2511
#if defined(TARGET_PPC64)
2512
/* Full system - 64 bits mode */
2513
static GenOpFunc1 *gen_op_lmw[] = {
2514
    &gen_op_lmw_user,
2515
    &gen_op_lmw_le_user,
2516
    &gen_op_lmw_64_user,
2517
    &gen_op_lmw_le_64_user,
2518
    &gen_op_lmw_kernel,
2519
    &gen_op_lmw_le_kernel,
2520
    &gen_op_lmw_64_kernel,
2521
    &gen_op_lmw_le_64_kernel,
2522
#if defined(TARGET_PPC64H)
2523
    &gen_op_lmw_hypv,
2524
    &gen_op_lmw_le_hypv,
2525
    &gen_op_lmw_64_hypv,
2526
    &gen_op_lmw_le_64_hypv,
2527
#endif
2528
};
2529
static GenOpFunc1 *gen_op_stmw[] = {
2530
    &gen_op_stmw_user,
2531
    &gen_op_stmw_le_user,
2532
    &gen_op_stmw_64_user,
2533
    &gen_op_stmw_le_64_user,
2534
    &gen_op_stmw_kernel,
2535
    &gen_op_stmw_le_kernel,
2536
    &gen_op_stmw_64_kernel,
2537
    &gen_op_stmw_le_64_kernel,
2538
#if defined(TARGET_PPC64H)
2539
    &gen_op_stmw_hypv,
2540
    &gen_op_stmw_le_hypv,
2541
    &gen_op_stmw_64_hypv,
2542
    &gen_op_stmw_le_64_hypv,
2543
#endif
2544
};
2545
#else
2546
/* Full system - 32 bits mode */
2547
static GenOpFunc1 *gen_op_lmw[] = {
2548
    &gen_op_lmw_user,
2549
    &gen_op_lmw_le_user,
2550
    &gen_op_lmw_kernel,
2551
    &gen_op_lmw_le_kernel,
2552
};
2553
static GenOpFunc1 *gen_op_stmw[] = {
2554
    &gen_op_stmw_user,
2555
    &gen_op_stmw_le_user,
2556
    &gen_op_stmw_kernel,
2557
    &gen_op_stmw_le_kernel,
2558
};
2559
#endif
2560
#endif
2561

    
2562
/* lmw */
2563
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2564
{
2565
    /* NIP cannot be restored if the memory exception comes from an helper */
2566
    gen_update_nip(ctx, ctx->nip - 4);
2567
    gen_addr_imm_index(ctx, 0);
2568
    op_ldstm(lmw, rD(ctx->opcode));
2569
}
2570

    
2571
/* stmw */
2572
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2573
{
2574
    /* NIP cannot be restored if the memory exception comes from an helper */
2575
    gen_update_nip(ctx, ctx->nip - 4);
2576
    gen_addr_imm_index(ctx, 0);
2577
    op_ldstm(stmw, rS(ctx->opcode));
2578
}
2579

    
2580
/***                    Integer load and store strings                     ***/
2581
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2582
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2583
#if defined(CONFIG_USER_ONLY)
2584
/* User-mode only */
2585
static GenOpFunc1 *gen_op_lswi[] = {
2586
    &gen_op_lswi_raw,
2587
    &gen_op_lswi_le_raw,
2588
#if defined(TARGET_PPC64)
2589
    &gen_op_lswi_64_raw,
2590
    &gen_op_lswi_le_64_raw,
2591
#endif
2592
};
2593
static GenOpFunc3 *gen_op_lswx[] = {
2594
    &gen_op_lswx_raw,
2595
    &gen_op_lswx_le_raw,
2596
#if defined(TARGET_PPC64)
2597
    &gen_op_lswx_64_raw,
2598
    &gen_op_lswx_le_64_raw,
2599
#endif
2600
};
2601
static GenOpFunc1 *gen_op_stsw[] = {
2602
    &gen_op_stsw_raw,
2603
    &gen_op_stsw_le_raw,
2604
#if defined(TARGET_PPC64)
2605
    &gen_op_stsw_64_raw,
2606
    &gen_op_stsw_le_64_raw,
2607
#endif
2608
};
2609
#else
2610
#if defined(TARGET_PPC64)
2611
/* Full system - 64 bits mode */
2612
static GenOpFunc1 *gen_op_lswi[] = {
2613
    &gen_op_lswi_user,
2614
    &gen_op_lswi_le_user,
2615
    &gen_op_lswi_64_user,
2616
    &gen_op_lswi_le_64_user,
2617
    &gen_op_lswi_kernel,
2618
    &gen_op_lswi_le_kernel,
2619
    &gen_op_lswi_64_kernel,
2620
    &gen_op_lswi_le_64_kernel,
2621
#if defined(TARGET_PPC64H)
2622
    &gen_op_lswi_hypv,
2623
    &gen_op_lswi_le_hypv,
2624
    &gen_op_lswi_64_hypv,
2625
    &gen_op_lswi_le_64_hypv,
2626
#endif
2627
};
2628
static GenOpFunc3 *gen_op_lswx[] = {
2629
    &gen_op_lswx_user,
2630
    &gen_op_lswx_le_user,
2631
    &gen_op_lswx_64_user,
2632
    &gen_op_lswx_le_64_user,
2633
    &gen_op_lswx_kernel,
2634
    &gen_op_lswx_le_kernel,
2635
    &gen_op_lswx_64_kernel,
2636
    &gen_op_lswx_le_64_kernel,
2637
#if defined(TARGET_PPC64H)
2638
    &gen_op_lswx_hypv,
2639
    &gen_op_lswx_le_hypv,
2640
    &gen_op_lswx_64_hypv,
2641
    &gen_op_lswx_le_64_hypv,
2642
#endif
2643
};
2644
static GenOpFunc1 *gen_op_stsw[] = {
2645
    &gen_op_stsw_user,
2646
    &gen_op_stsw_le_user,
2647
    &gen_op_stsw_64_user,
2648
    &gen_op_stsw_le_64_user,
2649
    &gen_op_stsw_kernel,
2650
    &gen_op_stsw_le_kernel,
2651
    &gen_op_stsw_64_kernel,
2652
    &gen_op_stsw_le_64_kernel,
2653
#if defined(TARGET_PPC64H)
2654
    &gen_op_stsw_hypv,
2655
    &gen_op_stsw_le_hypv,
2656
    &gen_op_stsw_64_hypv,
2657
    &gen_op_stsw_le_64_hypv,
2658
#endif
2659
};
2660
#else
2661
/* Full system - 32 bits mode */
2662
static GenOpFunc1 *gen_op_lswi[] = {
2663
    &gen_op_lswi_user,
2664
    &gen_op_lswi_le_user,
2665
    &gen_op_lswi_kernel,
2666
    &gen_op_lswi_le_kernel,
2667
};
2668
static GenOpFunc3 *gen_op_lswx[] = {
2669
    &gen_op_lswx_user,
2670
    &gen_op_lswx_le_user,
2671
    &gen_op_lswx_kernel,
2672
    &gen_op_lswx_le_kernel,
2673
};
2674
static GenOpFunc1 *gen_op_stsw[] = {
2675
    &gen_op_stsw_user,
2676
    &gen_op_stsw_le_user,
2677
    &gen_op_stsw_kernel,
2678
    &gen_op_stsw_le_kernel,
2679
};
2680
#endif
2681
#endif
2682

    
2683
/* lswi */
2684
/* PowerPC32 specification says we must generate an exception if
2685
 * rA is in the range of registers to be loaded.
2686
 * In an other hand, IBM says this is valid, but rA won't be loaded.
2687
 * For now, I'll follow the spec...
2688
 */
2689
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2690
{
2691
    int nb = NB(ctx->opcode);
2692
    int start = rD(ctx->opcode);
2693
    int ra = rA(ctx->opcode);
2694
    int nr;
2695

    
2696
    if (nb == 0)
2697
        nb = 32;
2698
    nr = nb / 4;
2699
    if (unlikely(((start + nr) > 32  &&
2700
                  start <= ra && (start + nr - 32) > ra) ||
2701
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2702
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2703
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2704
        return;
2705
    }
2706
    /* NIP cannot be restored if the memory exception comes from an helper */
2707
    gen_update_nip(ctx, ctx->nip - 4);
2708
    gen_addr_register(ctx);
2709
    gen_op_set_T1(nb);
2710
    op_ldsts(lswi, start);
2711
}
2712

    
2713
/* lswx */
2714
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2715
{
2716
    int ra = rA(ctx->opcode);
2717
    int rb = rB(ctx->opcode);
2718

    
2719
    /* NIP cannot be restored if the memory exception comes from an helper */
2720
    gen_update_nip(ctx, ctx->nip - 4);
2721
    gen_addr_reg_index(ctx);
2722
    if (ra == 0) {
2723
        ra = rb;
2724
    }
2725
    gen_op_load_xer_bc();
2726
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2727
}
2728

    
2729
/* stswi */
2730
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2731
{
2732
    int nb = NB(ctx->opcode);
2733

    
2734
    /* NIP cannot be restored if the memory exception comes from an helper */
2735
    gen_update_nip(ctx, ctx->nip - 4);
2736
    gen_addr_register(ctx);
2737
    if (nb == 0)
2738
        nb = 32;
2739
    gen_op_set_T1(nb);
2740
    op_ldsts(stsw, rS(ctx->opcode));
2741
}
2742

    
2743
/* stswx */
2744
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2745
{
2746
    /* NIP cannot be restored if the memory exception comes from an helper */
2747
    gen_update_nip(ctx, ctx->nip - 4);
2748
    gen_addr_reg_index(ctx);
2749
    gen_op_load_xer_bc();
2750
    op_ldsts(stsw, rS(ctx->opcode));
2751
}
2752

    
2753
/***                        Memory synchronisation                         ***/
2754
/* eieio */
2755
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2756
{
2757
}
2758

    
2759
/* isync */
2760
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2761
{
2762
    GEN_STOP(ctx);
2763
}
2764

    
2765
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2766
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2767
#if defined(CONFIG_USER_ONLY)
2768
/* User-mode only */
2769
static GenOpFunc *gen_op_lwarx[] = {
2770
    &gen_op_lwarx_raw,
2771
    &gen_op_lwarx_le_raw,
2772
#if defined(TARGET_PPC64)
2773
    &gen_op_lwarx_64_raw,
2774
    &gen_op_lwarx_le_64_raw,
2775
#endif
2776
};
2777
static GenOpFunc *gen_op_stwcx[] = {
2778
    &gen_op_stwcx_raw,
2779
    &gen_op_stwcx_le_raw,
2780
#if defined(TARGET_PPC64)
2781
    &gen_op_stwcx_64_raw,
2782
    &gen_op_stwcx_le_64_raw,
2783
#endif
2784
};
2785
#else
2786
#if defined(TARGET_PPC64)
2787
/* Full system - 64 bits mode */
2788
static GenOpFunc *gen_op_lwarx[] = {
2789
    &gen_op_lwarx_user,
2790
    &gen_op_lwarx_le_user,
2791
    &gen_op_lwarx_64_user,
2792
    &gen_op_lwarx_le_64_user,
2793
    &gen_op_lwarx_kernel,
2794
    &gen_op_lwarx_le_kernel,
2795
    &gen_op_lwarx_64_kernel,
2796
    &gen_op_lwarx_le_64_kernel,
2797
#if defined(TARGET_PPC64H)
2798
    &gen_op_lwarx_hypv,
2799
    &gen_op_lwarx_le_hypv,
2800
    &gen_op_lwarx_64_hypv,
2801
    &gen_op_lwarx_le_64_hypv,
2802
#endif
2803
};
2804
static GenOpFunc *gen_op_stwcx[] = {
2805
    &gen_op_stwcx_user,
2806
    &gen_op_stwcx_le_user,
2807
    &gen_op_stwcx_64_user,
2808
    &gen_op_stwcx_le_64_user,
2809
    &gen_op_stwcx_kernel,
2810
    &gen_op_stwcx_le_kernel,
2811
    &gen_op_stwcx_64_kernel,
2812
    &gen_op_stwcx_le_64_kernel,
2813
#if defined(TARGET_PPC64H)
2814
    &gen_op_stwcx_hypv,
2815
    &gen_op_stwcx_le_hypv,
2816
    &gen_op_stwcx_64_hypv,
2817
    &gen_op_stwcx_le_64_hypv,
2818
#endif
2819
};
2820
#else
2821
/* Full system - 32 bits mode */
2822
static GenOpFunc *gen_op_lwarx[] = {
2823
    &gen_op_lwarx_user,
2824
    &gen_op_lwarx_le_user,
2825
    &gen_op_lwarx_kernel,
2826
    &gen_op_lwarx_le_kernel,
2827
};
2828
static GenOpFunc *gen_op_stwcx[] = {
2829
    &gen_op_stwcx_user,
2830
    &gen_op_stwcx_le_user,
2831
    &gen_op_stwcx_kernel,
2832
    &gen_op_stwcx_le_kernel,
2833
};
2834
#endif
2835
#endif
2836

    
2837
/* lwarx */
2838
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2839
{
2840
    /* NIP cannot be restored if the memory exception comes from an helper */
2841
    gen_update_nip(ctx, ctx->nip - 4);
2842
    gen_addr_reg_index(ctx);
2843
    op_lwarx();
2844
    gen_op_store_T1_gpr(rD(ctx->opcode));
2845
}
2846

    
2847
/* stwcx. */
2848
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2849
{
2850
    /* NIP cannot be restored if the memory exception comes from an helper */
2851
    gen_update_nip(ctx, ctx->nip - 4);
2852
    gen_addr_reg_index(ctx);
2853
    gen_op_load_gpr_T1(rS(ctx->opcode));
2854
    op_stwcx();
2855
}
2856

    
2857
#if defined(TARGET_PPC64)
2858
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2859
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2860
#if defined(CONFIG_USER_ONLY)
2861
/* User-mode only */
2862
static GenOpFunc *gen_op_ldarx[] = {
2863
    &gen_op_ldarx_raw,
2864
    &gen_op_ldarx_le_raw,
2865
    &gen_op_ldarx_64_raw,
2866
    &gen_op_ldarx_le_64_raw,
2867
};
2868
static GenOpFunc *gen_op_stdcx[] = {
2869
    &gen_op_stdcx_raw,
2870
    &gen_op_stdcx_le_raw,
2871
    &gen_op_stdcx_64_raw,
2872
    &gen_op_stdcx_le_64_raw,
2873
};
2874
#else
2875
/* Full system */
2876
static GenOpFunc *gen_op_ldarx[] = {
2877
    &gen_op_ldarx_user,
2878
    &gen_op_ldarx_le_user,
2879
    &gen_op_ldarx_64_user,
2880
    &gen_op_ldarx_le_64_user,
2881
    &gen_op_ldarx_kernel,
2882
    &gen_op_ldarx_le_kernel,
2883
    &gen_op_ldarx_64_kernel,
2884
    &gen_op_ldarx_le_64_kernel,
2885
#if defined(TARGET_PPC64H)
2886
    &gen_op_ldarx_hypv,
2887
    &gen_op_ldarx_le_hypv,
2888
    &gen_op_ldarx_64_hypv,
2889
    &gen_op_ldarx_le_64_hypv,
2890
#endif
2891
};
2892
static GenOpFunc *gen_op_stdcx[] = {
2893
    &gen_op_stdcx_user,
2894
    &gen_op_stdcx_le_user,
2895
    &gen_op_stdcx_64_user,
2896
    &gen_op_stdcx_le_64_user,
2897
    &gen_op_stdcx_kernel,
2898
    &gen_op_stdcx_le_kernel,
2899
    &gen_op_stdcx_64_kernel,
2900
    &gen_op_stdcx_le_64_kernel,
2901
#if defined(TARGET_PPC64H)
2902
    &gen_op_stdcx_hypv,
2903
    &gen_op_stdcx_le_hypv,
2904
    &gen_op_stdcx_64_hypv,
2905
    &gen_op_stdcx_le_64_hypv,
2906
#endif
2907
};
2908
#endif
2909

    
2910
/* ldarx */
2911
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2912
{
2913
    /* NIP cannot be restored if the memory exception comes from an helper */
2914
    gen_update_nip(ctx, ctx->nip - 4);
2915
    gen_addr_reg_index(ctx);
2916
    op_ldarx();
2917
    gen_op_store_T1_gpr(rD(ctx->opcode));
2918
}
2919

    
2920
/* stdcx. */
2921
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2922
{
2923
    /* NIP cannot be restored if the memory exception comes from an helper */
2924
    gen_update_nip(ctx, ctx->nip - 4);
2925
    gen_addr_reg_index(ctx);
2926
    gen_op_load_gpr_T1(rS(ctx->opcode));
2927
    op_stdcx();
2928
}
2929
#endif /* defined(TARGET_PPC64) */
2930

    
2931
/* sync */
2932
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2933
{
2934
}
2935

    
2936
/* wait */
2937
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2938
{
2939
    /* Stop translation, as the CPU is supposed to sleep from now */
2940
    gen_op_wait();
2941
    GEN_EXCP(ctx, EXCP_HLT, 1);
2942
}
2943

    
2944
/***                         Floating-point load                           ***/
2945
#define GEN_LDF(width, opc, type)                                             \
2946
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2947
{                                                                             \
2948
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2949
        GEN_EXCP_NO_FP(ctx);                                                  \
2950
        return;                                                               \
2951
    }                                                                         \
2952
    gen_addr_imm_index(ctx, 0);                                               \
2953
    op_ldst(l##width);                                                        \
2954
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2955
}
2956

    
2957
#define GEN_LDUF(width, opc, type)                                            \
2958
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2959
{                                                                             \
2960
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2961
        GEN_EXCP_NO_FP(ctx);                                                  \
2962
        return;                                                               \
2963
    }                                                                         \
2964
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2965
        GEN_EXCP_INVAL(ctx);                                                  \
2966
        return;                                                               \
2967
    }                                                                         \
2968
    gen_addr_imm_index(ctx, 0);                                               \
2969
    op_ldst(l##width);                                                        \
2970
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2971
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2972
}
2973

    
2974
#define GEN_LDUXF(width, opc, type)                                           \
2975
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                  \
2976
{                                                                             \
2977
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2978
        GEN_EXCP_NO_FP(ctx);                                                  \
2979
        return;                                                               \
2980
    }                                                                         \
2981
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2982
        GEN_EXCP_INVAL(ctx);                                                  \
2983
        return;                                                               \
2984
    }                                                                         \
2985
    gen_addr_reg_index(ctx);                                                  \
2986
    op_ldst(l##width);                                                        \
2987
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2988
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2989
}
2990

    
2991
#define GEN_LDXF(width, opc2, opc3, type)                                     \
2992
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2993
{                                                                             \
2994
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2995
        GEN_EXCP_NO_FP(ctx);                                                  \
2996
        return;                                                               \
2997
    }                                                                         \
2998
    gen_addr_reg_index(ctx);                                                  \
2999
    op_ldst(l##width);                                                        \
3000
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
3001
}
3002

    
3003
#define GEN_LDFS(width, op, type)                                             \
3004
OP_LD_TABLE(width);                                                           \
3005
GEN_LDF(width, op | 0x20, type);                                              \
3006
GEN_LDUF(width, op | 0x21, type);                                             \
3007
GEN_LDUXF(width, op | 0x01, type);                                            \
3008
GEN_LDXF(width, 0x17, op | 0x00, type)
3009

    
3010
/* lfd lfdu lfdux lfdx */
3011
GEN_LDFS(fd, 0x12, PPC_FLOAT);
3012
/* lfs lfsu lfsux lfsx */
3013
GEN_LDFS(fs, 0x10, PPC_FLOAT);
3014

    
3015
/***                         Floating-point store                          ***/
3016
#define GEN_STF(width, opc, type)                                             \
3017
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
3018
{                                                                             \
3019
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3020
        GEN_EXCP_NO_FP(ctx);                                                  \
3021
        return;                                                               \
3022
    }                                                                         \
3023
    gen_addr_imm_index(ctx, 0);                                               \
3024
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3025
    op_ldst(st##width);                                                       \
3026
}
3027

    
3028
#define GEN_STUF(width, opc, type)                                            \
3029
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
3030
{                                                                             \
3031
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3032
        GEN_EXCP_NO_FP(ctx);                                                  \
3033
        return;                                                               \
3034
    }                                                                         \
3035
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3036
        GEN_EXCP_INVAL(ctx);                                                  \
3037
        return;                                                               \
3038
    }                                                                         \
3039
    gen_addr_imm_index(ctx, 0);                                               \
3040
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3041
    op_ldst(st##width);                                                       \
3042
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
3043
}
3044

    
3045
#define GEN_STUXF(width, opc, type)                                           \
3046
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                 \
3047
{                                                                             \
3048
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3049
        GEN_EXCP_NO_FP(ctx);                                                  \
3050
        return;                                                               \
3051
    }                                                                         \
3052
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3053
        GEN_EXCP_INVAL(ctx);                                                  \
3054
        return;                                                               \
3055
    }                                                                         \
3056
    gen_addr_reg_index(ctx);                                                  \
3057
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3058
    op_ldst(st##width);                                                       \
3059
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
3060
}
3061

    
3062
#define GEN_STXF(width, opc2, opc3, type)                                     \
3063
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
3064
{                                                                             \
3065
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3066
        GEN_EXCP_NO_FP(ctx);                                                  \
3067
        return;                                                               \
3068
    }                                                                         \
3069
    gen_addr_reg_index(ctx);                                                  \
3070
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3071
    op_ldst(st##width);                                                       \
3072
}
3073

    
3074
#define GEN_STFS(width, op, type)                                             \
3075
OP_ST_TABLE(width);                                                           \
3076
GEN_STF(width, op | 0x20, type);                                              \
3077
GEN_STUF(width, op | 0x21, type);                                             \
3078
GEN_STUXF(width, op | 0x01, type);                                            \
3079
GEN_STXF(width, 0x17, op | 0x00, type)
3080

    
3081
/* stfd stfdu stfdux stfdx */
3082
GEN_STFS(fd, 0x16, PPC_FLOAT);
3083
/* stfs stfsu stfsux stfsx */
3084
GEN_STFS(fs, 0x14, PPC_FLOAT);
3085

    
3086
/* Optional: */
3087
/* stfiwx */
3088
OP_ST_TABLE(fiwx);
3089
GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3090

    
3091
/***                                Branch                                 ***/
3092
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3093
                                       target_ulong dest)
3094
{
3095
    TranslationBlock *tb;
3096
    tb = ctx->tb;
3097
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3098
        if (n == 0)
3099
            gen_op_goto_tb0(TBPARAM(tb));
3100
        else
3101
            gen_op_goto_tb1(TBPARAM(tb));
3102
        gen_set_T1(dest);
3103
#if defined(TARGET_PPC64)
3104
        if (ctx->sf_mode)
3105
            gen_op_b_T1_64();
3106
        else
3107
#endif
3108
            gen_op_b_T1();
3109
        gen_op_set_T0((long)tb + n);
3110
        if (ctx->singlestep_enabled)
3111
            gen_op_debug();
3112
        gen_op_exit_tb();
3113
    } else {
3114
        gen_set_T1(dest);
3115
#if defined(TARGET_PPC64)
3116
        if (ctx->sf_mode)
3117
            gen_op_b_T1_64();
3118
        else
3119
#endif
3120
            gen_op_b_T1();
3121
        gen_op_reset_T0();
3122
        if (ctx->singlestep_enabled)
3123
            gen_op_debug();
3124
        gen_op_exit_tb();
3125
    }
3126
}
3127

    
3128
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3129
{
3130
#if defined(TARGET_PPC64)
3131
    if (ctx->sf_mode != 0 && (nip >> 32))
3132
        gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3133
    else
3134
#endif
3135
        gen_op_setlr(ctx->nip);
3136
}
3137

    
3138
/* b ba bl bla */
3139
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3140
{
3141
    target_ulong li, target;
3142

    
3143
    /* sign extend LI */
3144
#if defined(TARGET_PPC64)
3145
    if (ctx->sf_mode)
3146
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3147
    else
3148
#endif
3149
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3150
    if (likely(AA(ctx->opcode) == 0))
3151
        target = ctx->nip + li - 4;
3152
    else
3153
        target = li;
3154
#if defined(TARGET_PPC64)
3155
    if (!ctx->sf_mode)
3156
        target = (uint32_t)target;
3157
#endif
3158
    if (LK(ctx->opcode))
3159
        gen_setlr(ctx, ctx->nip);
3160
    gen_goto_tb(ctx, 0, target);
3161
    ctx->exception = POWERPC_EXCP_BRANCH;
3162
}
3163

    
3164
#define BCOND_IM  0
3165
#define BCOND_LR  1
3166
#define BCOND_CTR 2
3167

    
3168
static always_inline void gen_bcond (DisasContext *ctx, int type)
3169
{
3170
    target_ulong target = 0;
3171
    target_ulong li;
3172
    uint32_t bo = BO(ctx->opcode);
3173
    uint32_t bi = BI(ctx->opcode);
3174
    uint32_t mask;
3175

    
3176
    if ((bo & 0x4) == 0)
3177
        gen_op_dec_ctr();
3178
    switch(type) {
3179
    case BCOND_IM:
3180
        li = (target_long)((int16_t)(BD(ctx->opcode)));
3181
        if (likely(AA(ctx->opcode) == 0)) {
3182
            target = ctx->nip + li - 4;
3183
        } else {
3184
            target = li;
3185
        }
3186
#if defined(TARGET_PPC64)
3187
        if (!ctx->sf_mode)
3188
            target = (uint32_t)target;
3189
#endif
3190
        break;
3191
    case BCOND_CTR:
3192
        gen_op_movl_T1_ctr();
3193
        break;
3194
    default:
3195
    case BCOND_LR:
3196
        gen_op_movl_T1_lr();
3197
        break;
3198
    }
3199
    if (LK(ctx->opcode))
3200
        gen_setlr(ctx, ctx->nip);
3201
    if (bo & 0x10) {
3202
        /* No CR condition */
3203
        switch (bo & 0x6) {
3204
        case 0:
3205
#if defined(TARGET_PPC64)
3206
            if (ctx->sf_mode)
3207
                gen_op_test_ctr_64();
3208
            else
3209
#endif
3210
                gen_op_test_ctr();
3211
            break;
3212
        case 2:
3213
#if defined(TARGET_PPC64)
3214
            if (ctx->sf_mode)
3215
                gen_op_test_ctrz_64();
3216
            else
3217
#endif
3218
                gen_op_test_ctrz();
3219
            break;
3220
        default:
3221
        case 4:
3222
        case 6:
3223
            if (type == BCOND_IM) {
3224
                gen_goto_tb(ctx, 0, target);
3225
                goto out;
3226
            } else {
3227
#if defined(TARGET_PPC64)
3228
                if (ctx->sf_mode)
3229
                    gen_op_b_T1_64();
3230
                else
3231
#endif
3232
                    gen_op_b_T1();
3233
                gen_op_reset_T0();
3234
                goto no_test;
3235
            }
3236
            break;
3237
        }
3238
    } else {
3239
        mask = 1 << (3 - (bi & 0x03));
3240
        gen_op_load_crf_T0(bi >> 2);
3241
        if (bo & 0x8) {
3242
            switch (bo & 0x6) {
3243
            case 0:
3244
#if defined(TARGET_PPC64)
3245
                if (ctx->sf_mode)
3246
                    gen_op_test_ctr_true_64(mask);
3247
                else
3248
#endif
3249
                    gen_op_test_ctr_true(mask);
3250
                break;
3251
            case 2:
3252
#if defined(TARGET_PPC64)
3253
                if (ctx->sf_mode)
3254
                    gen_op_test_ctrz_true_64(mask);
3255
                else
3256
#endif
3257
                    gen_op_test_ctrz_true(mask);
3258
                break;
3259
            default:
3260
            case 4:
3261
            case 6:
3262
                gen_op_test_true(mask);
3263
                break;
3264
            }
3265
        } else {
3266
            switch (bo & 0x6) {
3267
            case 0:
3268
#if defined(TARGET_PPC64)
3269
                if (ctx->sf_mode)
3270
                    gen_op_test_ctr_false_64(mask);
3271
                else
3272
#endif
3273
                    gen_op_test_ctr_false(mask);
3274
                break;
3275
            case 2:
3276
#if defined(TARGET_PPC64)
3277
                if (ctx->sf_mode)
3278
                    gen_op_test_ctrz_false_64(mask);
3279
                else
3280
#endif
3281
                    gen_op_test_ctrz_false(mask);
3282
                break;
3283
            default:
3284
            case 4:
3285
            case 6:
3286
                gen_op_test_false(mask);
3287
                break;
3288
            }
3289
        }
3290
    }
3291
    if (type == BCOND_IM) {
3292
        int l1 = gen_new_label();
3293
        gen_op_jz_T0(l1);
3294
        gen_goto_tb(ctx, 0, target);
3295
        gen_set_label(l1);
3296
        gen_goto_tb(ctx, 1, ctx->nip);
3297
    } else {
3298
#if defined(TARGET_PPC64)
3299
        if (ctx->sf_mode)
3300
            gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3301
        else
3302
#endif
3303
            gen_op_btest_T1(ctx->nip);
3304
        gen_op_reset_T0();
3305
    no_test:
3306
        if (ctx->singlestep_enabled)
3307
            gen_op_debug();
3308
        gen_op_exit_tb();
3309
    }
3310
 out:
3311
    ctx->exception = POWERPC_EXCP_BRANCH;
3312
}
3313

    
3314
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3315
{
3316
    gen_bcond(ctx, BCOND_IM);
3317
}
3318

    
3319
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3320
{
3321
    gen_bcond(ctx, BCOND_CTR);
3322
}
3323

    
3324
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3325
{
3326
    gen_bcond(ctx, BCOND_LR);
3327
}
3328

    
3329
/***                      Condition register logical                       ***/
3330
#define GEN_CRLOGIC(op, opc)                                                  \
3331
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
3332
{                                                                             \
3333
    uint8_t bitmask;                                                          \
3334
    int sh;                                                                   \
3335
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
3336
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3337
    if (sh > 0)                                                               \
3338
        gen_op_srli_T0(sh);                                                   \
3339
    else if (sh < 0)                                                          \
3340
        gen_op_sli_T0(-sh);                                                   \
3341
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
3342
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3343
    if (sh > 0)                                                               \
3344
        gen_op_srli_T1(sh);                                                   \
3345
    else if (sh < 0)                                                          \
3346
        gen_op_sli_T1(-sh);                                                   \
3347
    gen_op_##op();                                                            \
3348
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3349
    gen_op_andi_T0(bitmask);                                                  \
3350
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
3351
    gen_op_andi_T1(~bitmask);                                                 \
3352
    gen_op_or();                                                              \
3353
    gen_op_store_T0_crf(crbD(ctx->opcode) >> 2);                              \
3354
}
3355

    
3356
/* crand */
3357
GEN_CRLOGIC(and, 0x08);
3358
/* crandc */
3359
GEN_CRLOGIC(andc, 0x04);
3360
/* creqv */
3361
GEN_CRLOGIC(eqv, 0x09);
3362
/* crnand */
3363
GEN_CRLOGIC(nand, 0x07);
3364
/* crnor */
3365
GEN_CRLOGIC(nor, 0x01);
3366
/* cror */
3367
GEN_CRLOGIC(or, 0x0E);
3368
/* crorc */
3369
GEN_CRLOGIC(orc, 0x0D);
3370
/* crxor */
3371
GEN_CRLOGIC(xor, 0x06);
3372
/* mcrf */
3373
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3374
{
3375
    gen_op_load_crf_T0(crfS(ctx->opcode));
3376
    gen_op_store_T0_crf(crfD(ctx->opcode));
3377
}
3378

    
3379
/***                           System linkage                              ***/
3380
/* rfi (supervisor only) */
3381
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3382
{
3383
#if defined(CONFIG_USER_ONLY)
3384
    GEN_EXCP_PRIVOPC(ctx);
3385
#else
3386
    /* Restore CPU state */
3387
    if (unlikely(!ctx->supervisor)) {
3388
        GEN_EXCP_PRIVOPC(ctx);
3389
        return;
3390
    }
3391
    gen_op_rfi();
3392
    GEN_SYNC(ctx);
3393
#endif
3394
}
3395

    
3396
#if defined(TARGET_PPC64)
3397
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3398
{
3399
#if defined(CONFIG_USER_ONLY)
3400
    GEN_EXCP_PRIVOPC(ctx);
3401
#else
3402
    /* Restore CPU state */
3403
    if (unlikely(!ctx->supervisor)) {
3404
        GEN_EXCP_PRIVOPC(ctx);
3405
        return;
3406
    }
3407
    gen_op_rfid();
3408
    GEN_SYNC(ctx);
3409
#endif
3410
}
3411
#endif
3412

    
3413
#if defined(TARGET_PPC64H)
3414
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3415
{
3416
#if defined(CONFIG_USER_ONLY)
3417
    GEN_EXCP_PRIVOPC(ctx);
3418
#else
3419
    /* Restore CPU state */
3420
    if (unlikely(ctx->supervisor <= 1)) {
3421
        GEN_EXCP_PRIVOPC(ctx);
3422
        return;
3423
    }
3424
    gen_op_hrfid();
3425
    GEN_SYNC(ctx);
3426
#endif
3427
}
3428
#endif
3429

    
3430
/* sc */
3431
#if defined(CONFIG_USER_ONLY)
3432
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3433
#else
3434
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3435
#endif
3436
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3437
{
3438
    uint32_t lev;
3439

    
3440
    lev = (ctx->opcode >> 5) & 0x7F;
3441
    GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3442
}
3443

    
3444
/***                                Trap                                   ***/
3445
/* tw */
3446
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3447
{
3448
    gen_op_load_gpr_T0(rA(ctx->opcode));
3449
    gen_op_load_gpr_T1(rB(ctx->opcode));
3450
    /* Update the nip since this might generate a trap exception */
3451
    gen_update_nip(ctx, ctx->nip);
3452
    gen_op_tw(TO(ctx->opcode));
3453
}
3454

    
3455
/* twi */
3456
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3457
{
3458
    gen_op_load_gpr_T0(rA(ctx->opcode));
3459
    gen_set_T1(SIMM(ctx->opcode));
3460
    /* Update the nip since this might generate a trap exception */
3461
    gen_update_nip(ctx, ctx->nip);
3462
    gen_op_tw(TO(ctx->opcode));
3463
}
3464

    
3465
#if defined(TARGET_PPC64)
3466
/* td */
3467
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3468
{
3469
    gen_op_load_gpr_T0(rA(ctx->opcode));
3470
    gen_op_load_gpr_T1(rB(ctx->opcode));
3471
    /* Update the nip since this might generate a trap exception */
3472
    gen_update_nip(ctx, ctx->nip);
3473
    gen_op_td(TO(ctx->opcode));
3474
}
3475

    
3476
/* tdi */
3477
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3478
{
3479
    gen_op_load_gpr_T0(rA(ctx->opcode));
3480
    gen_set_T1(SIMM(ctx->opcode));
3481
    /* Update the nip since this might generate a trap exception */
3482
    gen_update_nip(ctx, ctx->nip);
3483
    gen_op_td(TO(ctx->opcode));
3484
}
3485
#endif
3486

    
3487
/***                          Processor control                            ***/
3488
/* mcrxr */
3489
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3490
{
3491
    gen_op_load_xer_cr();
3492
    gen_op_store_T0_crf(crfD(ctx->opcode));
3493
    gen_op_clear_xer_ov();
3494
    gen_op_clear_xer_ca();
3495
}
3496

    
3497
/* mfcr */
3498
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3499
{
3500
    uint32_t crm, crn;
3501

    
3502
    if (likely(ctx->opcode & 0x00100000)) {
3503
        crm = CRM(ctx->opcode);
3504
        if (likely((crm ^ (crm - 1)) == 0)) {
3505
            crn = ffs(crm);
3506
            gen_op_load_cro(7 - crn);
3507
        }
3508
    } else {
3509
        gen_op_load_cr();
3510
    }
3511
    gen_op_store_T0_gpr(rD(ctx->opcode));
3512
}
3513

    
3514
/* mfmsr */
3515
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3516
{
3517
#if defined(CONFIG_USER_ONLY)
3518
    GEN_EXCP_PRIVREG(ctx);
3519
#else
3520
    if (unlikely(!ctx->supervisor)) {
3521
        GEN_EXCP_PRIVREG(ctx);
3522
        return;
3523
    }
3524
    gen_op_load_msr();
3525
    gen_op_store_T0_gpr(rD(ctx->opcode));
3526
#endif
3527
}
3528

    
3529
#if 1
3530
#define SPR_NOACCESS ((void *)(-1UL))
3531
#else
3532
static void spr_noaccess (void *opaque, int sprn)
3533
{
3534
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3535
    printf("ERROR: try to access SPR %d !\n", sprn);
3536
}
3537
#define SPR_NOACCESS (&spr_noaccess)
3538
#endif
3539

    
3540
/* mfspr */
3541
static always_inline void gen_op_mfspr (DisasContext *ctx)
3542
{
3543
    void (*read_cb)(void *opaque, int sprn);
3544
    uint32_t sprn = SPR(ctx->opcode);
3545

    
3546
#if !defined(CONFIG_USER_ONLY)
3547
#if defined(TARGET_PPC64H)
3548
    if (ctx->supervisor == 2)
3549
        read_cb = ctx->spr_cb[sprn].hea_read;
3550
    else
3551
#endif
3552
    if (ctx->supervisor)
3553
        read_cb = ctx->spr_cb[sprn].oea_read;
3554
    else
3555
#endif
3556
        read_cb = ctx->spr_cb[sprn].uea_read;
3557
    if (likely(read_cb != NULL)) {
3558
        if (likely(read_cb != SPR_NOACCESS)) {
3559
            (*read_cb)(ctx, sprn);
3560
            gen_op_store_T0_gpr(rD(ctx->opcode));
3561
        } else {
3562
            /* Privilege exception */
3563
            /* This is a hack to avoid warnings when running Linux:
3564
             * this OS breaks the PowerPC virtualisation model,
3565
             * allowing userland application to read the PVR
3566
             */
3567
            if (sprn != SPR_PVR) {
3568
                if (loglevel != 0) {
3569
                    fprintf(logfile, "Trying to read privileged spr %d %03x at"
3570
                            ADDRX "\n", sprn, sprn, ctx->nip);
3571
                }
3572
                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3573
                       sprn, sprn, ctx->nip);
3574
            }
3575
            GEN_EXCP_PRIVREG(ctx);
3576
        }
3577
    } else {
3578
        /* Not defined */
3579
        if (loglevel != 0) {
3580
            fprintf(logfile, "Trying to read invalid spr %d %03x at "
3581
                    ADDRX "\n", sprn, sprn, ctx->nip);
3582
        }
3583
        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3584
               sprn, sprn, ctx->nip);
3585
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3586
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3587
    }
3588
}
3589

    
3590
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3591
{
3592
    gen_op_mfspr(ctx);
3593
}
3594

    
3595
/* mftb */
3596
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3597
{
3598
    gen_op_mfspr(ctx);
3599
}
3600

    
3601
/* mtcrf */
3602
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3603
{
3604
    uint32_t crm, crn;
3605

    
3606
    gen_op_load_gpr_T0(rS(ctx->opcode));
3607
    crm = CRM(ctx->opcode);
3608
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3609
        crn = ffs(crm);
3610
        gen_op_srli_T0(crn * 4);
3611
        gen_op_andi_T0(0xF);
3612
        gen_op_store_cro(7 - crn);
3613
    } else {
3614
        gen_op_store_cr(crm);
3615
    }
3616
}
3617

    
3618
/* mtmsr */
3619
#if defined(TARGET_PPC64)
3620
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3621
{
3622
#if defined(CONFIG_USER_ONLY)
3623
    GEN_EXCP_PRIVREG(ctx);
3624
#else
3625
    if (unlikely(!ctx->supervisor)) {
3626
        GEN_EXCP_PRIVREG(ctx);
3627
        return;
3628
    }
3629
    gen_op_load_gpr_T0(rS(ctx->opcode));
3630
    if (ctx->opcode & 0x00010000) {
3631
        /* Special form that does not need any synchronisation */
3632
        gen_op_update_riee();
3633
    } else {
3634
        /* XXX: we need to update nip before the store
3635
         *      if we enter power saving mode, we will exit the loop
3636
         *      directly from ppc_store_msr
3637
         */
3638
        gen_update_nip(ctx, ctx->nip);
3639
        gen_op_store_msr();
3640
        /* Must stop the translation as machine state (may have) changed */
3641
        /* Note that mtmsr is not always defined as context-synchronizing */
3642
        ctx->exception = POWERPC_EXCP_STOP;
3643
    }
3644
#endif
3645
}
3646
#endif
3647

    
3648
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3649
{
3650
#if defined(CONFIG_USER_ONLY)
3651
    GEN_EXCP_PRIVREG(ctx);
3652
#else
3653
    if (unlikely(!ctx->supervisor)) {
3654
        GEN_EXCP_PRIVREG(ctx);
3655
        return;
3656
    }
3657
    gen_op_load_gpr_T0(rS(ctx->opcode));
3658
    if (ctx->opcode & 0x00010000) {
3659
        /* Special form that does not need any synchronisation */
3660
        gen_op_update_riee();
3661
    } else {
3662
        /* XXX: we need to update nip before the store
3663
         *      if we enter power saving mode, we will exit the loop
3664
         *      directly from ppc_store_msr
3665
         */
3666
        gen_update_nip(ctx, ctx->nip);
3667
#if defined(TARGET_PPC64)
3668
        if (!ctx->sf_mode)
3669
            gen_op_store_msr_32();
3670
        else
3671
#endif
3672
            gen_op_store_msr();
3673
        /* Must stop the translation as machine state (may have) changed */
3674
        /* Note that mtmsrd is not always defined as context-synchronizing */
3675
        ctx->exception = POWERPC_EXCP_STOP;
3676
    }
3677
#endif
3678
}
3679

    
3680
/* mtspr */
3681
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3682
{
3683
    void (*write_cb)(void *opaque, int sprn);
3684
    uint32_t sprn = SPR(ctx->opcode);
3685

    
3686
#if !defined(CONFIG_USER_ONLY)
3687
#if defined(TARGET_PPC64H)
3688
    if (ctx->supervisor == 2)
3689
        write_cb = ctx->spr_cb[sprn].hea_write;
3690
    else
3691
#endif
3692
    if (ctx->supervisor)
3693
        write_cb = ctx->spr_cb[sprn].oea_write;
3694
    else
3695
#endif
3696
        write_cb = ctx->spr_cb[sprn].uea_write;
3697
    if (likely(write_cb != NULL)) {
3698
        if (likely(write_cb != SPR_NOACCESS)) {
3699
            gen_op_load_gpr_T0(rS(ctx->opcode));
3700
            (*write_cb)(ctx, sprn);
3701
        } else {
3702
            /* Privilege exception */
3703
            if (loglevel != 0) {
3704
                fprintf(logfile, "Trying to write privileged spr %d %03x at "
3705
                        ADDRX "\n", sprn, sprn, ctx->nip);
3706
            }
3707
            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3708
                   sprn, sprn, ctx->nip);
3709
            GEN_EXCP_PRIVREG(ctx);
3710
        }
3711
    } else {
3712
        /* Not defined */
3713
        if (loglevel != 0) {
3714
            fprintf(logfile, "Trying to write invalid spr %d %03x at "
3715
                    ADDRX "\n", sprn, sprn, ctx->nip);
3716
        }
3717
        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3718
               sprn, sprn, ctx->nip);
3719
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3720
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3721
    }
3722
}
3723

    
3724
/***                         Cache management                              ***/
3725
/* dcbf */
3726
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3727
{
3728
    /* XXX: specification says this is treated as a load by the MMU */
3729
    gen_addr_reg_index(ctx);
3730
    op_ldst(lbz);
3731
}
3732

    
3733
/* dcbi (Supervisor only) */
3734
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3735
{
3736
#if defined(CONFIG_USER_ONLY)
3737
    GEN_EXCP_PRIVOPC(ctx);
3738
#else
3739
    if (unlikely(!ctx->supervisor)) {
3740
        GEN_EXCP_PRIVOPC(ctx);
3741
        return;
3742
    }
3743
    gen_addr_reg_index(ctx);
3744
    /* XXX: specification says this should be treated as a store by the MMU */
3745
    op_ldst(lbz);
3746
    op_ldst(stb);
3747
#endif
3748
}
3749

    
3750
/* dcdst */
3751
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3752
{
3753
    /* XXX: specification say this is treated as a load by the MMU */
3754
    gen_addr_reg_index(ctx);
3755
    op_ldst(lbz);
3756
}
3757

    
3758
/* dcbt */
3759
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3760
{
3761
    /* interpreted as no-op */
3762
    /* XXX: specification say this is treated as a load by the MMU
3763
     *      but does not generate any exception
3764
     */
3765
}
3766

    
3767
/* dcbtst */
3768
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3769
{
3770
    /* interpreted as no-op */
3771
    /* XXX: specification say this is treated as a load by the MMU
3772
     *      but does not generate any exception
3773
     */
3774
}
3775

    
3776
/* dcbz */
3777
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3778
#if defined(CONFIG_USER_ONLY)
3779
/* User-mode only */
3780
static GenOpFunc *gen_op_dcbz[4][4] = {
3781
    {
3782
        &gen_op_dcbz_l32_raw,
3783
        &gen_op_dcbz_l32_raw,
3784
#if defined(TARGET_PPC64)
3785
        &gen_op_dcbz_l32_64_raw,
3786
        &gen_op_dcbz_l32_64_raw,
3787
#endif
3788
    },
3789
    {
3790
        &gen_op_dcbz_l64_raw,
3791
        &gen_op_dcbz_l64_raw,
3792
#if defined(TARGET_PPC64)
3793
        &gen_op_dcbz_l64_64_raw,
3794
        &gen_op_dcbz_l64_64_raw,
3795
#endif
3796
    },
3797
    {
3798
        &gen_op_dcbz_l128_raw,
3799
        &gen_op_dcbz_l128_raw,
3800
#if defined(TARGET_PPC64)
3801
        &gen_op_dcbz_l128_64_raw,
3802
        &gen_op_dcbz_l128_64_raw,
3803
#endif
3804
    },
3805
    {
3806
        &gen_op_dcbz_raw,
3807
        &gen_op_dcbz_raw,
3808
#if defined(TARGET_PPC64)
3809
        &gen_op_dcbz_64_raw,
3810
        &gen_op_dcbz_64_raw,
3811
#endif
3812
    },
3813
};
3814
#else
3815
#if defined(TARGET_PPC64)
3816
/* Full system - 64 bits mode */
3817
static GenOpFunc *gen_op_dcbz[4][12] = {
3818
    {
3819
        &gen_op_dcbz_l32_user,
3820
        &gen_op_dcbz_l32_user,
3821
        &gen_op_dcbz_l32_64_user,
3822
        &gen_op_dcbz_l32_64_user,
3823
        &gen_op_dcbz_l32_kernel,
3824
        &gen_op_dcbz_l32_kernel,
3825
        &gen_op_dcbz_l32_64_kernel,
3826
        &gen_op_dcbz_l32_64_kernel,
3827
#if defined(TARGET_PPC64H)
3828
        &gen_op_dcbz_l32_hypv,
3829
        &gen_op_dcbz_l32_hypv,
3830
        &gen_op_dcbz_l32_64_hypv,
3831
        &gen_op_dcbz_l32_64_hypv,
3832
#endif
3833
    },
3834
    {
3835
        &gen_op_dcbz_l64_user,
3836
        &gen_op_dcbz_l64_user,
3837
        &gen_op_dcbz_l64_64_user,
3838
        &gen_op_dcbz_l64_64_user,
3839
        &gen_op_dcbz_l64_kernel,
3840
        &gen_op_dcbz_l64_kernel,
3841
        &gen_op_dcbz_l64_64_kernel,
3842
        &gen_op_dcbz_l64_64_kernel,
3843
#if defined(TARGET_PPC64H)
3844
        &gen_op_dcbz_l64_hypv,
3845
        &gen_op_dcbz_l64_hypv,
3846
        &gen_op_dcbz_l64_64_hypv,
3847
        &gen_op_dcbz_l64_64_hypv,
3848
#endif
3849
    },
3850
    {
3851
        &gen_op_dcbz_l128_user,
3852
        &gen_op_dcbz_l128_user,
3853
        &gen_op_dcbz_l128_64_user,
3854
        &gen_op_dcbz_l128_64_user,
3855
        &gen_op_dcbz_l128_kernel,
3856
        &gen_op_dcbz_l128_kernel,
3857
        &gen_op_dcbz_l128_64_kernel,
3858
        &gen_op_dcbz_l128_64_kernel,
3859
#if defined(TARGET_PPC64H)
3860
        &gen_op_dcbz_l128_hypv,
3861
        &gen_op_dcbz_l128_hypv,
3862
        &gen_op_dcbz_l128_64_hypv,
3863
        &gen_op_dcbz_l128_64_hypv,
3864
#endif
3865
    },
3866
    {
3867
        &gen_op_dcbz_user,
3868
        &gen_op_dcbz_user,
3869
        &gen_op_dcbz_64_user,
3870
        &gen_op_dcbz_64_user,
3871
        &gen_op_dcbz_kernel,
3872
        &gen_op_dcbz_kernel,
3873
        &gen_op_dcbz_64_kernel,
3874
        &gen_op_dcbz_64_kernel,
3875
#if defined(TARGET_PPC64H)
3876
        &gen_op_dcbz_hypv,
3877
        &gen_op_dcbz_hypv,
3878
        &gen_op_dcbz_64_hypv,
3879
        &gen_op_dcbz_64_hypv,
3880
#endif
3881
    },
3882
};
3883
#else
3884
/* Full system - 32 bits mode */
3885
static GenOpFunc *gen_op_dcbz[4][4] = {
3886
    {
3887
        &gen_op_dcbz_l32_user,
3888
        &gen_op_dcbz_l32_user,
3889
        &gen_op_dcbz_l32_kernel,
3890
        &gen_op_dcbz_l32_kernel,
3891
    },
3892
    {
3893
        &gen_op_dcbz_l64_user,
3894
        &gen_op_dcbz_l64_user,
3895
        &gen_op_dcbz_l64_kernel,
3896
        &gen_op_dcbz_l64_kernel,
3897
    },
3898
    {
3899
        &gen_op_dcbz_l128_user,
3900
        &gen_op_dcbz_l128_user,
3901
        &gen_op_dcbz_l128_kernel,
3902
        &gen_op_dcbz_l128_kernel,
3903
    },
3904
    {
3905
        &gen_op_dcbz_user,
3906
        &gen_op_dcbz_user,
3907
        &gen_op_dcbz_kernel,
3908
        &gen_op_dcbz_kernel,
3909
    },
3910
};
3911
#endif
3912
#endif
3913

    
3914
static always_inline void handler_dcbz (DisasContext *ctx,
3915
                                        int dcache_line_size)
3916
{
3917
    int n;
3918

    
3919
    switch (dcache_line_size) {
3920
    case 32:
3921
        n = 0;
3922
        break;
3923
    case 64:
3924
        n = 1;
3925
        break;
3926
    case 128:
3927
        n = 2;
3928
        break;
3929
    default:
3930
        n = 3;
3931
        break;
3932
    }
3933
    op_dcbz(n);
3934
}
3935

    
3936
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3937
{
3938
    gen_addr_reg_index(ctx);
3939
    handler_dcbz(ctx, ctx->dcache_line_size);
3940
    gen_op_check_reservation();
3941
}
3942

    
3943
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3944
{
3945
    gen_addr_reg_index(ctx);
3946
    if (ctx->opcode & 0x00200000)
3947
        handler_dcbz(ctx, ctx->dcache_line_size);
3948
    else
3949
        handler_dcbz(ctx, -1);
3950
    gen_op_check_reservation();
3951
}
3952

    
3953
/* icbi */
3954
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3955
#if defined(CONFIG_USER_ONLY)
3956
/* User-mode only */
3957
static GenOpFunc *gen_op_icbi[] = {
3958
    &gen_op_icbi_raw,
3959
    &gen_op_icbi_raw,
3960
#if defined(TARGET_PPC64)
3961
    &gen_op_icbi_64_raw,
3962
    &gen_op_icbi_64_raw,
3963
#endif
3964
};
3965
#else
3966
/* Full system - 64 bits mode */
3967
#if defined(TARGET_PPC64)
3968
static GenOpFunc *gen_op_icbi[] = {
3969
    &gen_op_icbi_user,
3970
    &gen_op_icbi_user,
3971
    &gen_op_icbi_64_user,
3972
    &gen_op_icbi_64_user,
3973
    &gen_op_icbi_kernel,
3974
    &gen_op_icbi_kernel,
3975
    &gen_op_icbi_64_kernel,
3976
    &gen_op_icbi_64_kernel,
3977
#if defined(TARGET_PPC64H)
3978
    &gen_op_icbi_hypv,
3979
    &gen_op_icbi_hypv,
3980
    &gen_op_icbi_64_hypv,
3981
    &gen_op_icbi_64_hypv,
3982
#endif
3983
};
3984
#else
3985
/* Full system - 32 bits mode */
3986
static GenOpFunc *gen_op_icbi[] = {
3987
    &gen_op_icbi_user,
3988
    &gen_op_icbi_user,
3989
    &gen_op_icbi_kernel,
3990
    &gen_op_icbi_kernel,
3991
};
3992
#endif
3993
#endif
3994

    
3995
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
3996
{
3997
    /* NIP cannot be restored if the memory exception comes from an helper */
3998
    gen_update_nip(ctx, ctx->nip - 4);
3999
    gen_addr_reg_index(ctx);
4000
    op_icbi();
4001
}
4002

    
4003
/* Optional: */
4004
/* dcba */
4005
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4006
{
4007
    /* interpreted as no-op */
4008
    /* XXX: specification say this is treated as a store by the MMU
4009
     *      but does not generate any exception
4010
     */
4011
}
4012

    
4013
/***                    Segment register manipulation                      ***/
4014
/* Supervisor only: */
4015
/* mfsr */
4016
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4017
{
4018
#if defined(CONFIG_USER_ONLY)
4019
    GEN_EXCP_PRIVREG(ctx);
4020
#else
4021
    if (unlikely(!ctx->supervisor)) {
4022
        GEN_EXCP_PRIVREG(ctx);
4023
        return;
4024
    }
4025
    gen_op_set_T1(SR(ctx->opcode));
4026
    gen_op_load_sr();
4027
    gen_op_store_T0_gpr(rD(ctx->opcode));
4028
#endif
4029
}
4030

    
4031
/* mfsrin */
4032
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4033
{
4034
#if defined(CONFIG_USER_ONLY)
4035
    GEN_EXCP_PRIVREG(ctx);
4036
#else
4037
    if (unlikely(!ctx->supervisor)) {
4038
        GEN_EXCP_PRIVREG(ctx);
4039
        return;
4040
    }
4041
    gen_op_load_gpr_T1(rB(ctx->opcode));
4042
    gen_op_srli_T1(28);
4043
    gen_op_load_sr();
4044
    gen_op_store_T0_gpr(rD(ctx->opcode));
4045
#endif
4046
}
4047

    
4048
/* mtsr */
4049
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4050
{
4051
#if defined(CONFIG_USER_ONLY)
4052
    GEN_EXCP_PRIVREG(ctx);
4053
#else
4054
    if (unlikely(!ctx->supervisor)) {
4055
        GEN_EXCP_PRIVREG(ctx);
4056
        return;
4057
    }
4058
    gen_op_load_gpr_T0(rS(ctx->opcode));
4059
    gen_op_set_T1(SR(ctx->opcode));
4060
    gen_op_store_sr();
4061
#endif
4062
}
4063

    
4064
/* mtsrin */
4065
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4066
{
4067
#if defined(CONFIG_USER_ONLY)
4068
    GEN_EXCP_PRIVREG(ctx);
4069
#else
4070
    if (unlikely(!ctx->supervisor)) {
4071
        GEN_EXCP_PRIVREG(ctx);
4072
        return;
4073
    }
4074
    gen_op_load_gpr_T0(rS(ctx->opcode));
4075
    gen_op_load_gpr_T1(rB(ctx->opcode));
4076
    gen_op_srli_T1(28);
4077
    gen_op_store_sr();
4078
#endif
4079
}
4080

    
4081
#if defined(TARGET_PPC64)
4082
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4083
/* mfsr */
4084
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4085
{
4086
#if defined(CONFIG_USER_ONLY)
4087
    GEN_EXCP_PRIVREG(ctx);
4088
#else
4089
    if (unlikely(!ctx->supervisor)) {
4090
        GEN_EXCP_PRIVREG(ctx);
4091
        return;
4092
    }
4093
    gen_op_set_T1(SR(ctx->opcode));
4094
    gen_op_load_slb();
4095
    gen_op_store_T0_gpr(rD(ctx->opcode));
4096
#endif
4097
}
4098

    
4099
/* mfsrin */
4100
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4101
             PPC_SEGMENT_64B)
4102
{
4103
#if defined(CONFIG_USER_ONLY)
4104
    GEN_EXCP_PRIVREG(ctx);
4105
#else
4106
    if (unlikely(!ctx->supervisor)) {
4107
        GEN_EXCP_PRIVREG(ctx);
4108
        return;
4109
    }
4110
    gen_op_load_gpr_T1(rB(ctx->opcode));
4111
    gen_op_srli_T1(28);
4112
    gen_op_load_slb();
4113
    gen_op_store_T0_gpr(rD(ctx->opcode));
4114
#endif
4115
}
4116

    
4117
/* mtsr */
4118
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4119
{
4120
#if defined(CONFIG_USER_ONLY)
4121
    GEN_EXCP_PRIVREG(ctx);
4122
#else
4123
    if (unlikely(!ctx->supervisor)) {
4124
        GEN_EXCP_PRIVREG(ctx);
4125
        return;
4126
    }
4127
    gen_op_load_gpr_T0(rS(ctx->opcode));
4128
    gen_op_set_T1(SR(ctx->opcode));
4129
    gen_op_store_slb();
4130
#endif
4131
}
4132

    
4133
/* mtsrin */
4134
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4135
             PPC_SEGMENT_64B)
4136
{
4137
#if defined(CONFIG_USER_ONLY)
4138
    GEN_EXCP_PRIVREG(ctx);
4139
#else
4140
    if (unlikely(!ctx->supervisor)) {
4141
        GEN_EXCP_PRIVREG(ctx);
4142
        return;
4143
    }
4144
    gen_op_load_gpr_T0(rS(ctx->opcode));
4145
    gen_op_load_gpr_T1(rB(ctx->opcode));
4146
    gen_op_srli_T1(28);
4147
    gen_op_store_slb();
4148
#endif
4149
}
4150
#endif /* defined(TARGET_PPC64) */
4151

    
4152
/***                      Lookaside buffer management                      ***/
4153
/* Optional & supervisor only: */
4154
/* tlbia */
4155
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4156
{
4157
#if defined(CONFIG_USER_ONLY)
4158
    GEN_EXCP_PRIVOPC(ctx);
4159
#else
4160
    if (unlikely(!ctx->supervisor)) {
4161
        if (loglevel != 0)
4162
            fprintf(logfile, "%s: ! supervisor\n", __func__);
4163
        GEN_EXCP_PRIVOPC(ctx);
4164
        return;
4165
    }
4166
    gen_op_tlbia();
4167
#endif
4168
}
4169

    
4170
/* tlbie */
4171
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4172
{
4173
#if defined(CONFIG_USER_ONLY)
4174
    GEN_EXCP_PRIVOPC(ctx);
4175
#else
4176
    if (unlikely(!ctx->supervisor)) {
4177
        GEN_EXCP_PRIVOPC(ctx);
4178
        return;
4179
    }
4180
    gen_op_load_gpr_T0(rB(ctx->opcode));
4181
#if defined(TARGET_PPC64)
4182
    if (ctx->sf_mode)
4183
        gen_op_tlbie_64();
4184
    else
4185
#endif
4186
        gen_op_tlbie();
4187
#endif
4188
}
4189

    
4190
/* tlbsync */
4191
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4192
{
4193
#if defined(CONFIG_USER_ONLY)
4194
    GEN_EXCP_PRIVOPC(ctx);
4195
#else
4196
    if (unlikely(!ctx->supervisor)) {
4197
        GEN_EXCP_PRIVOPC(ctx);
4198
        return;
4199
    }
4200
    /* This has no effect: it should ensure that all previous
4201
     * tlbie have completed
4202
     */
4203
    GEN_STOP(ctx);
4204
#endif
4205
}
4206

    
4207
#if defined(TARGET_PPC64)
4208
/* slbia */
4209
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4210
{
4211
#if defined(CONFIG_USER_ONLY)
4212
    GEN_EXCP_PRIVOPC(ctx);
4213
#else
4214
    if (unlikely(!ctx->supervisor)) {
4215
        if (loglevel != 0)
4216
            fprintf(logfile, "%s: ! supervisor\n", __func__);
4217
        GEN_EXCP_PRIVOPC(ctx);
4218
        return;
4219
    }
4220
    gen_op_slbia();
4221
#endif
4222
}
4223

    
4224
/* slbie */
4225
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4226
{
4227
#if defined(CONFIG_USER_ONLY)
4228
    GEN_EXCP_PRIVOPC(ctx);
4229
#else
4230
    if (unlikely(!ctx->supervisor)) {
4231
        GEN_EXCP_PRIVOPC(ctx);
4232
        return;
4233
    }
4234
    gen_op_load_gpr_T0(rB(ctx->opcode));
4235
    gen_op_slbie();
4236
#endif
4237
}
4238
#endif
4239

    
4240
/***                              External control                         ***/
4241
/* Optional: */
4242
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4243
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4244
#if defined(CONFIG_USER_ONLY)
4245
/* User-mode only */
4246
static GenOpFunc *gen_op_eciwx[] = {
4247
    &gen_op_eciwx_raw,
4248
    &gen_op_eciwx_le_raw,
4249
#if defined(TARGET_PPC64)
4250
    &gen_op_eciwx_64_raw,
4251
    &gen_op_eciwx_le_64_raw,
4252
#endif
4253
};
4254
static GenOpFunc *gen_op_ecowx[] = {
4255
    &gen_op_ecowx_raw,
4256
    &gen_op_ecowx_le_raw,
4257
#if defined(TARGET_PPC64)
4258
    &gen_op_ecowx_64_raw,
4259
    &gen_op_ecowx_le_64_raw,
4260
#endif
4261
};
4262
#else
4263
#if defined(TARGET_PPC64)
4264
/* Full system - 64 bits mode */
4265
static GenOpFunc *gen_op_eciwx[] = {
4266
    &gen_op_eciwx_user,
4267
    &gen_op_eciwx_le_user,
4268
    &gen_op_eciwx_64_user,
4269
    &gen_op_eciwx_le_64_user,
4270
    &gen_op_eciwx_kernel,
4271
    &gen_op_eciwx_le_kernel,
4272
    &gen_op_eciwx_64_kernel,
4273
    &gen_op_eciwx_le_64_kernel,
4274
#if defined(TARGET_PPC64H)
4275
    &gen_op_eciwx_hypv,
4276
    &gen_op_eciwx_le_hypv,
4277
    &gen_op_eciwx_64_hypv,
4278
    &gen_op_eciwx_le_64_hypv,
4279
#endif
4280
};
4281
static GenOpFunc *gen_op_ecowx[] = {
4282
    &gen_op_ecowx_user,
4283
    &gen_op_ecowx_le_user,
4284
    &gen_op_ecowx_64_user,
4285
    &gen_op_ecowx_le_64_user,
4286
    &gen_op_ecowx_kernel,
4287
    &gen_op_ecowx_le_kernel,
4288
    &gen_op_ecowx_64_kernel,
4289
    &gen_op_ecowx_le_64_kernel,
4290
#if defined(TARGET_PPC64H)
4291
    &gen_op_ecowx_hypv,
4292
    &gen_op_ecowx_le_hypv,
4293
    &gen_op_ecowx_64_hypv,
4294
    &gen_op_ecowx_le_64_hypv,
4295
#endif
4296
};
4297
#else
4298
/* Full system - 32 bits mode */
4299
static GenOpFunc *gen_op_eciwx[] = {
4300
    &gen_op_eciwx_user,
4301
    &gen_op_eciwx_le_user,
4302
    &gen_op_eciwx_kernel,
4303
    &gen_op_eciwx_le_kernel,
4304
};
4305
static GenOpFunc *gen_op_ecowx[] = {
4306
    &gen_op_ecowx_user,
4307
    &gen_op_ecowx_le_user,
4308
    &gen_op_ecowx_kernel,
4309
    &gen_op_ecowx_le_kernel,
4310
};
4311
#endif
4312
#endif
4313

    
4314
/* eciwx */
4315
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4316
{
4317
    /* Should check EAR[E] & alignment ! */
4318
    gen_addr_reg_index(ctx);
4319
    op_eciwx();
4320
    gen_op_store_T0_gpr(rD(ctx->opcode));
4321
}
4322

    
4323
/* ecowx */
4324
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4325
{
4326
    /* Should check EAR[E] & alignment ! */
4327
    gen_addr_reg_index(ctx);
4328
    gen_op_load_gpr_T1(rS(ctx->opcode));
4329
    op_ecowx();
4330
}
4331

    
4332
/* PowerPC 601 specific instructions */
4333
/* abs - abs. */
4334
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4335
{
4336
    gen_op_load_gpr_T0(rA(ctx->opcode));
4337
    gen_op_POWER_abs();
4338
    gen_op_store_T0_gpr(rD(ctx->opcode));
4339
    if (unlikely(Rc(ctx->opcode) != 0))
4340
        gen_set_Rc0(ctx);
4341
}
4342

    
4343
/* abso - abso. */
4344
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4345
{
4346
    gen_op_load_gpr_T0(rA(ctx->opcode));
4347
    gen_op_POWER_abso();
4348
    gen_op_store_T0_gpr(rD(ctx->opcode));
4349
    if (unlikely(Rc(ctx->opcode) != 0))
4350
        gen_set_Rc0(ctx);
4351
}
4352

    
4353
/* clcs */
4354
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4355
{
4356
    gen_op_load_gpr_T0(rA(ctx->opcode));
4357
    gen_op_POWER_clcs();
4358
    /* Rc=1 sets CR0 to an undefined state */
4359
    gen_op_store_T0_gpr(rD(ctx->opcode));
4360
}
4361

    
4362
/* div - div. */
4363
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4364
{
4365
    gen_op_load_gpr_T0(rA(ctx->opcode));
4366
    gen_op_load_gpr_T1(rB(ctx->opcode));
4367
    gen_op_POWER_div();
4368
    gen_op_store_T0_gpr(rD(ctx->opcode));
4369
    if (unlikely(Rc(ctx->opcode) != 0))
4370
        gen_set_Rc0(ctx);
4371
}
4372

    
4373
/* divo - divo. */
4374
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4375
{
4376
    gen_op_load_gpr_T0(rA(ctx->opcode));
4377
    gen_op_load_gpr_T1(rB(ctx->opcode));
4378
    gen_op_POWER_divo();
4379
    gen_op_store_T0_gpr(rD(ctx->opcode));
4380
    if (unlikely(Rc(ctx->opcode) != 0))
4381
        gen_set_Rc0(ctx);
4382
}
4383

    
4384
/* divs - divs. */
4385
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4386
{
4387
    gen_op_load_gpr_T0(rA(ctx->opcode));
4388
    gen_op_load_gpr_T1(rB(ctx->opcode));
4389
    gen_op_POWER_divs();
4390
    gen_op_store_T0_gpr(rD(ctx->opcode));
4391
    if (unlikely(Rc(ctx->opcode) != 0))
4392
        gen_set_Rc0(ctx);
4393
}
4394

    
4395
/* divso - divso. */
4396
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4397
{
4398
    gen_op_load_gpr_T0(rA(ctx->opcode));
4399
    gen_op_load_gpr_T1(rB(ctx->opcode));
4400
    gen_op_POWER_divso();
4401
    gen_op_store_T0_gpr(rD(ctx->opcode));
4402
    if (unlikely(Rc(ctx->opcode) != 0))
4403
        gen_set_Rc0(ctx);
4404
}
4405

    
4406
/* doz - doz. */
4407
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4408
{
4409
    gen_op_load_gpr_T0(rA(ctx->opcode));
4410
    gen_op_load_gpr_T1(rB(ctx->opcode));
4411
    gen_op_POWER_doz();
4412
    gen_op_store_T0_gpr(rD(ctx->opcode));
4413
    if (unlikely(Rc(ctx->opcode) != 0))
4414
        gen_set_Rc0(ctx);
4415
}
4416

    
4417
/* dozo - dozo. */
4418
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4419
{
4420
    gen_op_load_gpr_T0(rA(ctx->opcode));
4421
    gen_op_load_gpr_T1(rB(ctx->opcode));
4422
    gen_op_POWER_dozo();
4423
    gen_op_store_T0_gpr(rD(ctx->opcode));
4424
    if (unlikely(Rc(ctx->opcode) != 0))
4425
        gen_set_Rc0(ctx);
4426
}
4427

    
4428
/* dozi */
4429
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4430
{
4431
    gen_op_load_gpr_T0(rA(ctx->opcode));
4432
    gen_op_set_T1(SIMM(ctx->opcode));
4433
    gen_op_POWER_doz();
4434
    gen_op_store_T0_gpr(rD(ctx->opcode));
4435
}
4436

    
4437
/* As lscbx load from memory byte after byte, it's always endian safe */
4438
#define op_POWER_lscbx(start, ra, rb)                                         \
4439
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4440
#if defined(CONFIG_USER_ONLY)
4441
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4442
    &gen_op_POWER_lscbx_raw,
4443
    &gen_op_POWER_lscbx_raw,
4444
};
4445
#else
4446
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4447
    &gen_op_POWER_lscbx_user,
4448
    &gen_op_POWER_lscbx_user,
4449
    &gen_op_POWER_lscbx_kernel,
4450
    &gen_op_POWER_lscbx_kernel,
4451
};
4452
#endif
4453

    
4454
/* lscbx - lscbx. */
4455
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4456
{
4457
    int ra = rA(ctx->opcode);
4458
    int rb = rB(ctx->opcode);
4459

    
4460
    gen_addr_reg_index(ctx);
4461
    if (ra == 0) {
4462
        ra = rb;
4463
    }
4464
    /* NIP cannot be restored if the memory exception comes from an helper */
4465
    gen_update_nip(ctx, ctx->nip - 4);
4466
    gen_op_load_xer_bc();
4467
    gen_op_load_xer_cmp();
4468
    op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4469
    gen_op_store_xer_bc();
4470
    if (unlikely(Rc(ctx->opcode) != 0))
4471
        gen_set_Rc0(ctx);
4472
}
4473

    
4474
/* maskg - maskg. */
4475
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4476
{
4477
    gen_op_load_gpr_T0(rS(ctx->opcode));
4478
    gen_op_load_gpr_T1(rB(ctx->opcode));
4479
    gen_op_POWER_maskg();
4480
    gen_op_store_T0_gpr(rA(ctx->opcode));
4481
    if (unlikely(Rc(ctx->opcode) != 0))
4482
        gen_set_Rc0(ctx);
4483
}
4484

    
4485
/* maskir - maskir. */
4486
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4487
{
4488
    gen_op_load_gpr_T0(rA(ctx->opcode));
4489
    gen_op_load_gpr_T1(rS(ctx->opcode));
4490
    gen_op_load_gpr_T2(rB(ctx->opcode));
4491
    gen_op_POWER_maskir();
4492
    gen_op_store_T0_gpr(rA(ctx->opcode));
4493
    if (unlikely(Rc(ctx->opcode) != 0))
4494
        gen_set_Rc0(ctx);
4495
}
4496

    
4497
/* mul - mul. */
4498
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4499
{
4500
    gen_op_load_gpr_T0(rA(ctx->opcode));
4501
    gen_op_load_gpr_T1(rB(ctx->opcode));
4502
    gen_op_POWER_mul();
4503
    gen_op_store_T0_gpr(rD(ctx->opcode));
4504
    if (unlikely(Rc(ctx->opcode) != 0))
4505
        gen_set_Rc0(ctx);
4506
}
4507

    
4508
/* mulo - mulo. */
4509
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4510
{
4511
    gen_op_load_gpr_T0(rA(ctx->opcode));
4512
    gen_op_load_gpr_T1(rB(ctx->opcode));
4513
    gen_op_POWER_mulo();
4514
    gen_op_store_T0_gpr(rD(ctx->opcode));
4515
    if (unlikely(Rc(ctx->opcode) != 0))
4516
        gen_set_Rc0(ctx);
4517
}
4518

    
4519
/* nabs - nabs. */
4520
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4521
{
4522
    gen_op_load_gpr_T0(rA(ctx->opcode));
4523
    gen_op_POWER_nabs();
4524
    gen_op_store_T0_gpr(rD(ctx->opcode));
4525
    if (unlikely(Rc(ctx->opcode) != 0))
4526
        gen_set_Rc0(ctx);
4527
}
4528

    
4529
/* nabso - nabso. */
4530
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4531
{
4532
    gen_op_load_gpr_T0(rA(ctx->opcode));
4533
    gen_op_POWER_nabso();
4534
    gen_op_store_T0_gpr(rD(ctx->opcode));
4535
    if (unlikely(Rc(ctx->opcode) != 0))
4536
        gen_set_Rc0(ctx);
4537
}
4538

    
4539
/* rlmi - rlmi. */
4540
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4541
{
4542
    uint32_t mb, me;
4543

    
4544
    mb = MB(ctx->opcode);
4545
    me = ME(ctx->opcode);
4546
    gen_op_load_gpr_T0(rS(ctx->opcode));
4547
    gen_op_load_gpr_T1(rA(ctx->opcode));
4548
    gen_op_load_gpr_T2(rB(ctx->opcode));
4549
    gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4550
    gen_op_store_T0_gpr(rA(ctx->opcode));
4551
    if (unlikely(Rc(ctx->opcode) != 0))
4552
        gen_set_Rc0(ctx);
4553
}
4554

    
4555
/* rrib - rrib. */
4556
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4557
{
4558
    gen_op_load_gpr_T0(rS(ctx->opcode));
4559
    gen_op_load_gpr_T1(rA(ctx->opcode));
4560
    gen_op_load_gpr_T2(rB(ctx->opcode));
4561
    gen_op_POWER_rrib();
4562
    gen_op_store_T0_gpr(rA(ctx->opcode));
4563
    if (unlikely(Rc(ctx->opcode) != 0))
4564
        gen_set_Rc0(ctx);
4565
}
4566

    
4567
/* sle - sle. */
4568
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4569
{
4570
    gen_op_load_gpr_T0(rS(ctx->opcode));
4571
    gen_op_load_gpr_T1(rB(ctx->opcode));
4572
    gen_op_POWER_sle();
4573
    gen_op_store_T0_gpr(rA(ctx->opcode));
4574
    if (unlikely(Rc(ctx->opcode) != 0))
4575
        gen_set_Rc0(ctx);
4576
}
4577

    
4578
/* sleq - sleq. */
4579
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4580
{
4581
    gen_op_load_gpr_T0(rS(ctx->opcode));
4582
    gen_op_load_gpr_T1(rB(ctx->opcode));
4583
    gen_op_POWER_sleq();
4584
    gen_op_store_T0_gpr(rA(ctx->opcode));
4585
    if (unlikely(Rc(ctx->opcode) != 0))
4586
        gen_set_Rc0(ctx);
4587
}
4588

    
4589
/* sliq - sliq. */
4590
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4591
{
4592
    gen_op_load_gpr_T0(rS(ctx->opcode));
4593
    gen_op_set_T1(SH(ctx->opcode));
4594
    gen_op_POWER_sle();
4595
    gen_op_store_T0_gpr(rA(ctx->opcode));
4596
    if (unlikely(Rc(ctx->opcode) != 0))
4597
        gen_set_Rc0(ctx);
4598
}
4599

    
4600
/* slliq - slliq. */
4601
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4602
{
4603
    gen_op_load_gpr_T0(rS(ctx->opcode));
4604
    gen_op_set_T1(SH(ctx->opcode));
4605
    gen_op_POWER_sleq();
4606
    gen_op_store_T0_gpr(rA(ctx->opcode));
4607
    if (unlikely(Rc(ctx->opcode) != 0))
4608
        gen_set_Rc0(ctx);
4609
}
4610

    
4611
/* sllq - sllq. */
4612
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4613
{
4614
    gen_op_load_gpr_T0(rS(ctx->opcode));
4615
    gen_op_load_gpr_T1(rB(ctx->opcode));
4616
    gen_op_POWER_sllq();
4617
    gen_op_store_T0_gpr(rA(ctx->opcode));
4618
    if (unlikely(Rc(ctx->opcode) != 0))
4619
        gen_set_Rc0(ctx);
4620
}
4621

    
4622
/* slq - slq. */
4623
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4624
{
4625
    gen_op_load_gpr_T0(rS(ctx->opcode));
4626
    gen_op_load_gpr_T1(rB(ctx->opcode));
4627
    gen_op_POWER_slq();
4628
    gen_op_store_T0_gpr(rA(ctx->opcode));
4629
    if (unlikely(Rc(ctx->opcode) != 0))
4630
        gen_set_Rc0(ctx);
4631
}
4632

    
4633
/* sraiq - sraiq. */
4634
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4635
{
4636
    gen_op_load_gpr_T0(rS(ctx->opcode));
4637
    gen_op_set_T1(SH(ctx->opcode));
4638
    gen_op_POWER_sraq();
4639
    gen_op_store_T0_gpr(rA(ctx->opcode));
4640
    if (unlikely(Rc(ctx->opcode) != 0))
4641
        gen_set_Rc0(ctx);
4642
}
4643

    
4644
/* sraq - sraq. */
4645
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4646
{
4647
    gen_op_load_gpr_T0(rS(ctx->opcode));
4648
    gen_op_load_gpr_T1(rB(ctx->opcode));
4649
    gen_op_POWER_sraq();
4650
    gen_op_store_T0_gpr(rA(ctx->opcode));
4651
    if (unlikely(Rc(ctx->opcode) != 0))
4652
        gen_set_Rc0(ctx);
4653
}
4654

    
4655
/* sre - sre. */
4656
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4657
{
4658
    gen_op_load_gpr_T0(rS(ctx->opcode));
4659
    gen_op_load_gpr_T1(rB(ctx->opcode));
4660
    gen_op_POWER_sre();
4661
    gen_op_store_T0_gpr(rA(ctx->opcode));
4662
    if (unlikely(Rc(ctx->opcode) != 0))
4663
        gen_set_Rc0(ctx);
4664
}
4665

    
4666
/* srea - srea. */
4667
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4668
{
4669
    gen_op_load_gpr_T0(rS(ctx->opcode));
4670
    gen_op_load_gpr_T1(rB(ctx->opcode));
4671
    gen_op_POWER_srea();
4672
    gen_op_store_T0_gpr(rA(ctx->opcode));
4673
    if (unlikely(Rc(ctx->opcode) != 0))
4674
        gen_set_Rc0(ctx);
4675
}
4676

    
4677
/* sreq */
4678
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4679
{
4680
    gen_op_load_gpr_T0(rS(ctx->opcode));
4681
    gen_op_load_gpr_T1(rB(ctx->opcode));
4682
    gen_op_POWER_sreq();
4683
    gen_op_store_T0_gpr(rA(ctx->opcode));
4684
    if (unlikely(Rc(ctx->opcode) != 0))
4685
        gen_set_Rc0(ctx);
4686
}
4687

    
4688
/* sriq */
4689
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4690
{
4691
    gen_op_load_gpr_T0(rS(ctx->opcode));
4692
    gen_op_set_T1(SH(ctx->opcode));
4693
    gen_op_POWER_srq();
4694
    gen_op_store_T0_gpr(rA(ctx->opcode));
4695
    if (unlikely(Rc(ctx->opcode) != 0))
4696
        gen_set_Rc0(ctx);
4697
}
4698

    
4699
/* srliq */
4700
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4701
{
4702
    gen_op_load_gpr_T0(rS(ctx->opcode));
4703
    gen_op_load_gpr_T1(rB(ctx->opcode));
4704
    gen_op_set_T1(SH(ctx->opcode));
4705
    gen_op_POWER_srlq();
4706
    gen_op_store_T0_gpr(rA(ctx->opcode));
4707
    if (unlikely(Rc(ctx->opcode) != 0))
4708
        gen_set_Rc0(ctx);
4709
}
4710

    
4711
/* srlq */
4712
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4713
{
4714
    gen_op_load_gpr_T0(rS(ctx->opcode));
4715
    gen_op_load_gpr_T1(rB(ctx->opcode));
4716
    gen_op_POWER_srlq();
4717
    gen_op_store_T0_gpr(rA(ctx->opcode));
4718
    if (unlikely(Rc(ctx->opcode) != 0))
4719
        gen_set_Rc0(ctx);
4720
}
4721

    
4722
/* srq */
4723
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4724
{
4725
    gen_op_load_gpr_T0(rS(ctx->opcode));
4726
    gen_op_load_gpr_T1(rB(ctx->opcode));
4727
    gen_op_POWER_srq();
4728
    gen_op_store_T0_gpr(rA(ctx->opcode));
4729
    if (unlikely(Rc(ctx->opcode) != 0))
4730
        gen_set_Rc0(ctx);
4731
}
4732

    
4733
/* PowerPC 602 specific instructions */
4734
/* dsa  */
4735
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4736
{
4737
    /* XXX: TODO */
4738
    GEN_EXCP_INVAL(ctx);
4739
}
4740

    
4741
/* esa */
4742
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4743
{
4744
    /* XXX: TODO */
4745
    GEN_EXCP_INVAL(ctx);
4746
}
4747

    
4748
/* mfrom */
4749
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4750
{
4751
#if defined(CONFIG_USER_ONLY)
4752
    GEN_EXCP_PRIVOPC(ctx);
4753
#else
4754
    if (unlikely(!ctx->supervisor)) {
4755
        GEN_EXCP_PRIVOPC(ctx);
4756
        return;
4757
    }
4758
    gen_op_load_gpr_T0(rA(ctx->opcode));
4759
    gen_op_602_mfrom();
4760
    gen_op_store_T0_gpr(rD(ctx->opcode));
4761
#endif
4762
}
4763

    
4764
/* 602 - 603 - G2 TLB management */
4765
/* tlbld */
4766
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4767
{
4768
#if defined(CONFIG_USER_ONLY)
4769
    GEN_EXCP_PRIVOPC(ctx);
4770
#else
4771
    if (unlikely(!ctx->supervisor)) {
4772
        GEN_EXCP_PRIVOPC(ctx);
4773
        return;
4774
    }
4775
    gen_op_load_gpr_T0(rB(ctx->opcode));
4776
    gen_op_6xx_tlbld();
4777
#endif
4778
}
4779

    
4780
/* tlbli */
4781
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4782
{
4783
#if defined(CONFIG_USER_ONLY)
4784
    GEN_EXCP_PRIVOPC(ctx);
4785
#else
4786
    if (unlikely(!ctx->supervisor)) {
4787
        GEN_EXCP_PRIVOPC(ctx);
4788
        return;
4789
    }
4790
    gen_op_load_gpr_T0(rB(ctx->opcode));
4791
    gen_op_6xx_tlbli();
4792
#endif
4793
}
4794

    
4795
/* 74xx TLB management */
4796
/* tlbld */
4797
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4798
{
4799
#if defined(CONFIG_USER_ONLY)
4800
    GEN_EXCP_PRIVOPC(ctx);
4801
#else
4802
    if (unlikely(!ctx->supervisor)) {
4803
        GEN_EXCP_PRIVOPC(ctx);
4804
        return;
4805
    }
4806
    gen_op_load_gpr_T0(rB(ctx->opcode));
4807
    gen_op_74xx_tlbld();
4808
#endif
4809
}
4810

    
4811
/* tlbli */
4812
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4813
{
4814
#if defined(CONFIG_USER_ONLY)
4815
    GEN_EXCP_PRIVOPC(ctx);
4816
#else
4817
    if (unlikely(!ctx->supervisor)) {
4818
        GEN_EXCP_PRIVOPC(ctx);
4819
        return;
4820
    }
4821
    gen_op_load_gpr_T0(rB(ctx->opcode));
4822
    gen_op_74xx_tlbli();
4823
#endif
4824
}
4825

    
4826
/* POWER instructions not in PowerPC 601 */
4827
/* clf */
4828
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4829
{
4830
    /* Cache line flush: implemented as no-op */
4831
}
4832

    
4833
/* cli */
4834
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4835
{
4836
    /* Cache line invalidate: privileged and treated as no-op */
4837
#if defined(CONFIG_USER_ONLY)
4838
    GEN_EXCP_PRIVOPC(ctx);
4839
#else
4840
    if (unlikely(!ctx->supervisor)) {
4841
        GEN_EXCP_PRIVOPC(ctx);
4842
        return;
4843
    }
4844
#endif
4845
}
4846

    
4847
/* dclst */
4848
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4849
{
4850
    /* Data cache line store: treated as no-op */
4851
}
4852

    
4853
GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4854
{
4855
#if defined(CONFIG_USER_ONLY)
4856
    GEN_EXCP_PRIVOPC(ctx);
4857
#else
4858
    if (unlikely(!ctx->supervisor)) {
4859
        GEN_EXCP_PRIVOPC(ctx);
4860
        return;
4861
    }
4862
    int ra = rA(ctx->opcode);
4863
    int rd = rD(ctx->opcode);
4864

    
4865
    gen_addr_reg_index(ctx);
4866
    gen_op_POWER_mfsri();
4867
    gen_op_store_T0_gpr(rd);
4868
    if (ra != 0 && ra != rd)
4869
        gen_op_store_T1_gpr(ra);
4870
#endif
4871
}
4872

    
4873
GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4874
{
4875
#if defined(CONFIG_USER_ONLY)
4876
    GEN_EXCP_PRIVOPC(ctx);
4877
#else
4878
    if (unlikely(!ctx->supervisor)) {
4879
        GEN_EXCP_PRIVOPC(ctx);
4880
        return;
4881
    }
4882
    gen_addr_reg_index(ctx);
4883
    gen_op_POWER_rac();
4884
    gen_op_store_T0_gpr(rD(ctx->opcode));
4885
#endif
4886
}
4887

    
4888
GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4889
{
4890
#if defined(CONFIG_USER_ONLY)
4891
    GEN_EXCP_PRIVOPC(ctx);
4892
#else
4893
    if (unlikely(!ctx->supervisor)) {
4894
        GEN_EXCP_PRIVOPC(ctx);
4895
        return;
4896
    }
4897
    gen_op_POWER_rfsvc();
4898
    GEN_SYNC(ctx);
4899
#endif
4900
}
4901

    
4902
/* svc is not implemented for now */
4903

    
4904
/* POWER2 specific instructions */
4905
/* Quad manipulation (load/store two floats at a time) */
4906
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4907
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4908
#if defined(CONFIG_USER_ONLY)
4909
static GenOpFunc *gen_op_POWER2_lfq[] = {
4910
    &gen_op_POWER2_lfq_le_raw,
4911
    &gen_op_POWER2_lfq_raw,
4912
};
4913
static GenOpFunc *gen_op_POWER2_stfq[] = {
4914
    &gen_op_POWER2_stfq_le_raw,
4915
    &gen_op_POWER2_stfq_raw,
4916
};
4917
#else
4918
static GenOpFunc *gen_op_POWER2_lfq[] = {
4919
    &gen_op_POWER2_lfq_le_user,
4920
    &gen_op_POWER2_lfq_user,
4921
    &gen_op_POWER2_lfq_le_kernel,
4922
    &gen_op_POWER2_lfq_kernel,
4923
};
4924
static GenOpFunc *gen_op_POWER2_stfq[] = {
4925
    &gen_op_POWER2_stfq_le_user,
4926
    &gen_op_POWER2_stfq_user,
4927
    &gen_op_POWER2_stfq_le_kernel,
4928
    &gen_op_POWER2_stfq_kernel,