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1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* A lot of PowerPC definition have been included here.
22
 * Most of them are not usable for now but have been kept
23
 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24
 */
25

    
26
#include "dis-asm.h"
27
#include "host-utils.h"
28

    
29
//#define PPC_DUMP_CPU
30
//#define PPC_DEBUG_SPR
31
//#define PPC_DEBUG_IRQ
32

    
33
struct ppc_def_t {
34
    const unsigned char *name;
35
    uint32_t pvr;
36
    uint64_t insns_flags;
37
    uint64_t msr_mask;
38
    uint8_t mmu_model;
39
    uint8_t excp_model;
40
    uint8_t bus_model;
41
    uint8_t pad;
42
    uint32_t flags;
43
    int bfd_mach;
44
    void (*init_proc)(CPUPPCState *env);
45
    int (*check_pow)(CPUPPCState *env);
46
};
47

    
48
/* For user-mode emulation, we don't emulate any IRQ controller */
49
#if defined(CONFIG_USER_ONLY)
50
#define PPC_IRQ_INIT_FN(name)                                                 \
51
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
52
{                                                                             \
53
}
54
#else
55
#define PPC_IRQ_INIT_FN(name)                                                 \
56
void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
57
#endif
58

    
59
PPC_IRQ_INIT_FN(40x);
60
PPC_IRQ_INIT_FN(6xx);
61
PPC_IRQ_INIT_FN(970);
62

    
63
/* Generic callbacks:
64
 * do nothing but store/retrieve spr value
65
 */
66
#ifdef PPC_DUMP_SPR_ACCESSES
67
static void spr_read_generic (void *opaque, int sprn)
68
{
69
    gen_op_load_dump_spr(sprn);
70
}
71

    
72
static void spr_write_generic (void *opaque, int sprn)
73
{
74
    gen_op_store_dump_spr(sprn);
75
}
76
#else
77
static void spr_read_generic (void *opaque, int sprn)
78
{
79
    gen_op_load_spr(sprn);
80
}
81

    
82
static void spr_write_generic (void *opaque, int sprn)
83
{
84
    gen_op_store_spr(sprn);
85
}
86
#endif
87

    
88
#if !defined(CONFIG_USER_ONLY)
89
static void spr_write_clear (void *opaque, int sprn)
90
{
91
    gen_op_mask_spr(sprn);
92
}
93
#endif
94

    
95
/* SPR common to all PowerPC */
96
/* XER */
97
static void spr_read_xer (void *opaque, int sprn)
98
{
99
    gen_op_load_xer();
100
}
101

    
102
static void spr_write_xer (void *opaque, int sprn)
103
{
104
    gen_op_store_xer();
105
}
106

    
107
/* LR */
108
static void spr_read_lr (void *opaque, int sprn)
109
{
110
    gen_op_load_lr();
111
}
112

    
113
static void spr_write_lr (void *opaque, int sprn)
114
{
115
    gen_op_store_lr();
116
}
117

    
118
/* CTR */
119
static void spr_read_ctr (void *opaque, int sprn)
120
{
121
    gen_op_load_ctr();
122
}
123

    
124
static void spr_write_ctr (void *opaque, int sprn)
125
{
126
    gen_op_store_ctr();
127
}
128

    
129
/* User read access to SPR */
130
/* USPRx */
131
/* UMMCRx */
132
/* UPMCx */
133
/* USIA */
134
/* UDECR */
135
static void spr_read_ureg (void *opaque, int sprn)
136
{
137
    gen_op_load_spr(sprn + 0x10);
138
}
139

    
140
/* SPR common to all non-embedded PowerPC */
141
/* DECR */
142
#if !defined(CONFIG_USER_ONLY)
143
static void spr_read_decr (void *opaque, int sprn)
144
{
145
    gen_op_load_decr();
146
}
147

    
148
static void spr_write_decr (void *opaque, int sprn)
149
{
150
    gen_op_store_decr();
151
}
152
#endif
153

    
154
/* SPR common to all non-embedded PowerPC, except 601 */
155
/* Time base */
156
static void spr_read_tbl (void *opaque, int sprn)
157
{
158
    gen_op_load_tbl();
159
}
160

    
161
static void spr_read_tbu (void *opaque, int sprn)
162
{
163
    gen_op_load_tbu();
164
}
165

    
166
__attribute__ (( unused ))
167
static void spr_read_atbl (void *opaque, int sprn)
168
{
169
    gen_op_load_atbl();
170
}
171

    
172
__attribute__ (( unused ))
173
static void spr_read_atbu (void *opaque, int sprn)
174
{
175
    gen_op_load_atbu();
176
}
177

    
178
#if !defined(CONFIG_USER_ONLY)
179
static void spr_write_tbl (void *opaque, int sprn)
180
{
181
    gen_op_store_tbl();
182
}
183

    
184
static void spr_write_tbu (void *opaque, int sprn)
185
{
186
    gen_op_store_tbu();
187
}
188

    
189
__attribute__ (( unused ))
190
static void spr_write_atbl (void *opaque, int sprn)
191
{
192
    gen_op_store_atbl();
193
}
194

    
195
__attribute__ (( unused ))
196
static void spr_write_atbu (void *opaque, int sprn)
197
{
198
    gen_op_store_atbu();
199
}
200
#endif
201

    
202
#if !defined(CONFIG_USER_ONLY)
203
/* IBAT0U...IBAT0U */
204
/* IBAT0L...IBAT7L */
205
static void spr_read_ibat (void *opaque, int sprn)
206
{
207
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
208
}
209

    
210
static void spr_read_ibat_h (void *opaque, int sprn)
211
{
212
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
213
}
214

    
215
static void spr_write_ibatu (void *opaque, int sprn)
216
{
217
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
218
}
219

    
220
static void spr_write_ibatu_h (void *opaque, int sprn)
221
{
222
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
223
}
224

    
225
static void spr_write_ibatl (void *opaque, int sprn)
226
{
227
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
228
}
229

    
230
static void spr_write_ibatl_h (void *opaque, int sprn)
231
{
232
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
233
}
234

    
235
/* DBAT0U...DBAT7U */
236
/* DBAT0L...DBAT7L */
237
static void spr_read_dbat (void *opaque, int sprn)
238
{
239
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
240
}
241

    
242
static void spr_read_dbat_h (void *opaque, int sprn)
243
{
244
    gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
245
}
246

    
247
static void spr_write_dbatu (void *opaque, int sprn)
248
{
249
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
250
}
251

    
252
static void spr_write_dbatu_h (void *opaque, int sprn)
253
{
254
    gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
255
}
256

    
257
static void spr_write_dbatl (void *opaque, int sprn)
258
{
259
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
260
}
261

    
262
static void spr_write_dbatl_h (void *opaque, int sprn)
263
{
264
    gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
265
}
266

    
267
/* SDR1 */
268
static void spr_read_sdr1 (void *opaque, int sprn)
269
{
270
    gen_op_load_sdr1();
271
}
272

    
273
static void spr_write_sdr1 (void *opaque, int sprn)
274
{
275
    gen_op_store_sdr1();
276
}
277

    
278
/* 64 bits PowerPC specific SPRs */
279
/* ASR */
280
#if defined(TARGET_PPC64)
281
__attribute__ (( unused ))
282
static void spr_read_asr (void *opaque, int sprn)
283
{
284
    gen_op_load_asr();
285
}
286

    
287
__attribute__ (( unused ))
288
static void spr_write_asr (void *opaque, int sprn)
289
{
290
    gen_op_store_asr();
291
}
292
#endif
293
#endif
294

    
295
/* PowerPC 601 specific registers */
296
/* RTC */
297
static void spr_read_601_rtcl (void *opaque, int sprn)
298
{
299
    gen_op_load_601_rtcl();
300
}
301

    
302
static void spr_read_601_rtcu (void *opaque, int sprn)
303
{
304
    gen_op_load_601_rtcu();
305
}
306

    
307
#if !defined(CONFIG_USER_ONLY)
308
static void spr_write_601_rtcu (void *opaque, int sprn)
309
{
310
    gen_op_store_601_rtcu();
311
}
312

    
313
static void spr_write_601_rtcl (void *opaque, int sprn)
314
{
315
    gen_op_store_601_rtcl();
316
}
317

    
318
static void spr_write_hid0_601 (void *opaque, int sprn)
319
{
320
    DisasContext *ctx = opaque;
321

    
322
    gen_op_store_hid0_601();
323
    /* Must stop the translation as endianness may have changed */
324
    GEN_STOP(ctx);
325
}
326
#endif
327

    
328
/* Unified bats */
329
#if !defined(CONFIG_USER_ONLY)
330
static void spr_read_601_ubat (void *opaque, int sprn)
331
{
332
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
333
}
334

    
335
static void spr_write_601_ubatu (void *opaque, int sprn)
336
{
337
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
338
}
339

    
340
static void spr_write_601_ubatl (void *opaque, int sprn)
341
{
342
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
343
}
344
#endif
345

    
346
/* PowerPC 40x specific registers */
347
#if !defined(CONFIG_USER_ONLY)
348
static void spr_read_40x_pit (void *opaque, int sprn)
349
{
350
    gen_op_load_40x_pit();
351
}
352

    
353
static void spr_write_40x_pit (void *opaque, int sprn)
354
{
355
    gen_op_store_40x_pit();
356
}
357

    
358
static void spr_write_40x_dbcr0 (void *opaque, int sprn)
359
{
360
    DisasContext *ctx = opaque;
361

    
362
    gen_op_store_40x_dbcr0();
363
    /* We must stop translation as we may have rebooted */
364
    GEN_STOP(ctx);
365
}
366

    
367
static void spr_write_40x_sler (void *opaque, int sprn)
368
{
369
    gen_op_store_40x_sler();
370
}
371

    
372
static void spr_write_booke_tcr (void *opaque, int sprn)
373
{
374
    gen_op_store_booke_tcr();
375
}
376

    
377
static void spr_write_booke_tsr (void *opaque, int sprn)
378
{
379
    gen_op_store_booke_tsr();
380
}
381
#endif
382

    
383
/* PowerPC 403 specific registers */
384
/* PBL1 / PBU1 / PBL2 / PBU2 */
385
#if !defined(CONFIG_USER_ONLY)
386
static void spr_read_403_pbr (void *opaque, int sprn)
387
{
388
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
389
}
390

    
391
static void spr_write_403_pbr (void *opaque, int sprn)
392
{
393
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
394
}
395

    
396
static void spr_write_pir (void *opaque, int sprn)
397
{
398
    gen_op_store_pir();
399
}
400
#endif
401

    
402
#if !defined(CONFIG_USER_ONLY)
403
/* Callback used to write the exception vector base */
404
static void spr_write_excp_prefix (void *opaque, int sprn)
405
{
406
    gen_op_store_excp_prefix();
407
    gen_op_store_spr(sprn);
408
}
409

    
410
static void spr_write_excp_vector (void *opaque, int sprn)
411
{
412
    DisasContext *ctx = opaque;
413

    
414
    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
415
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
416
        gen_op_store_spr(sprn);
417
    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
418
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
419
        gen_op_store_spr(sprn);
420
    } else {
421
        printf("Trying to write an unknown exception vector %d %03x\n",
422
               sprn, sprn);
423
        GEN_EXCP_PRIVREG(ctx);
424
    }
425
}
426
#endif
427

    
428
#if defined(CONFIG_USER_ONLY)
429
#define spr_register(env, num, name, uea_read, uea_write,                     \
430
                     oea_read, oea_write, initial_value)                      \
431
do {                                                                          \
432
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
433
} while (0)
434
static inline void _spr_register (CPUPPCState *env, int num,
435
                                  const unsigned char *name,
436
                                  void (*uea_read)(void *opaque, int sprn),
437
                                  void (*uea_write)(void *opaque, int sprn),
438
                                  target_ulong initial_value)
439
#else
440
static inline void spr_register (CPUPPCState *env, int num,
441
                                 const unsigned char *name,
442
                                 void (*uea_read)(void *opaque, int sprn),
443
                                 void (*uea_write)(void *opaque, int sprn),
444
                                 void (*oea_read)(void *opaque, int sprn),
445
                                 void (*oea_write)(void *opaque, int sprn),
446
                                 target_ulong initial_value)
447
#endif
448
{
449
    ppc_spr_t *spr;
450

    
451
    spr = &env->spr_cb[num];
452
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
453
#if !defined(CONFIG_USER_ONLY)
454
        spr->oea_read != NULL || spr->oea_write != NULL ||
455
#endif
456
        spr->uea_read != NULL || spr->uea_write != NULL) {
457
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
458
        exit(1);
459
    }
460
#if defined(PPC_DEBUG_SPR)
461
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
462
           initial_value);
463
#endif
464
    spr->name = name;
465
    spr->uea_read = uea_read;
466
    spr->uea_write = uea_write;
467
#if !defined(CONFIG_USER_ONLY)
468
    spr->oea_read = oea_read;
469
    spr->oea_write = oea_write;
470
#endif
471
    env->spr[num] = initial_value;
472
}
473

    
474
/* Generic PowerPC SPRs */
475
static void gen_spr_generic (CPUPPCState *env)
476
{
477
    /* Integer processing */
478
    spr_register(env, SPR_XER, "XER",
479
                 &spr_read_xer, &spr_write_xer,
480
                 &spr_read_xer, &spr_write_xer,
481
                 0x00000000);
482
    /* Branch contol */
483
    spr_register(env, SPR_LR, "LR",
484
                 &spr_read_lr, &spr_write_lr,
485
                 &spr_read_lr, &spr_write_lr,
486
                 0x00000000);
487
    spr_register(env, SPR_CTR, "CTR",
488
                 &spr_read_ctr, &spr_write_ctr,
489
                 &spr_read_ctr, &spr_write_ctr,
490
                 0x00000000);
491
    /* Interrupt processing */
492
    spr_register(env, SPR_SRR0, "SRR0",
493
                 SPR_NOACCESS, SPR_NOACCESS,
494
                 &spr_read_generic, &spr_write_generic,
495
                 0x00000000);
496
    spr_register(env, SPR_SRR1, "SRR1",
497
                 SPR_NOACCESS, SPR_NOACCESS,
498
                 &spr_read_generic, &spr_write_generic,
499
                 0x00000000);
500
    /* Processor control */
501
    spr_register(env, SPR_SPRG0, "SPRG0",
502
                 SPR_NOACCESS, SPR_NOACCESS,
503
                 &spr_read_generic, &spr_write_generic,
504
                 0x00000000);
505
    spr_register(env, SPR_SPRG1, "SPRG1",
506
                 SPR_NOACCESS, SPR_NOACCESS,
507
                 &spr_read_generic, &spr_write_generic,
508
                 0x00000000);
509
    spr_register(env, SPR_SPRG2, "SPRG2",
510
                 SPR_NOACCESS, SPR_NOACCESS,
511
                 &spr_read_generic, &spr_write_generic,
512
                 0x00000000);
513
    spr_register(env, SPR_SPRG3, "SPRG3",
514
                 SPR_NOACCESS, SPR_NOACCESS,
515
                 &spr_read_generic, &spr_write_generic,
516
                 0x00000000);
517
}
518

    
519
/* SPR common to all non-embedded PowerPC, including 601 */
520
static void gen_spr_ne_601 (CPUPPCState *env)
521
{
522
    /* Exception processing */
523
    spr_register(env, SPR_DSISR, "DSISR",
524
                 SPR_NOACCESS, SPR_NOACCESS,
525
                 &spr_read_generic, &spr_write_generic,
526
                 0x00000000);
527
    spr_register(env, SPR_DAR, "DAR",
528
                 SPR_NOACCESS, SPR_NOACCESS,
529
                 &spr_read_generic, &spr_write_generic,
530
                 0x00000000);
531
    /* Timer */
532
    spr_register(env, SPR_DECR, "DECR",
533
                 SPR_NOACCESS, SPR_NOACCESS,
534
                 &spr_read_decr, &spr_write_decr,
535
                 0x00000000);
536
    /* Memory management */
537
    spr_register(env, SPR_SDR1, "SDR1",
538
                 SPR_NOACCESS, SPR_NOACCESS,
539
                 &spr_read_sdr1, &spr_write_sdr1,
540
                 0x00000000);
541
}
542

    
543
/* BATs 0-3 */
544
static void gen_low_BATs (CPUPPCState *env)
545
{
546
#if !defined(CONFIG_USER_ONLY)
547
    spr_register(env, SPR_IBAT0U, "IBAT0U",
548
                 SPR_NOACCESS, SPR_NOACCESS,
549
                 &spr_read_ibat, &spr_write_ibatu,
550
                 0x00000000);
551
    spr_register(env, SPR_IBAT0L, "IBAT0L",
552
                 SPR_NOACCESS, SPR_NOACCESS,
553
                 &spr_read_ibat, &spr_write_ibatl,
554
                 0x00000000);
555
    spr_register(env, SPR_IBAT1U, "IBAT1U",
556
                 SPR_NOACCESS, SPR_NOACCESS,
557
                 &spr_read_ibat, &spr_write_ibatu,
558
                 0x00000000);
559
    spr_register(env, SPR_IBAT1L, "IBAT1L",
560
                 SPR_NOACCESS, SPR_NOACCESS,
561
                 &spr_read_ibat, &spr_write_ibatl,
562
                 0x00000000);
563
    spr_register(env, SPR_IBAT2U, "IBAT2U",
564
                 SPR_NOACCESS, SPR_NOACCESS,
565
                 &spr_read_ibat, &spr_write_ibatu,
566
                 0x00000000);
567
    spr_register(env, SPR_IBAT2L, "IBAT2L",
568
                 SPR_NOACCESS, SPR_NOACCESS,
569
                 &spr_read_ibat, &spr_write_ibatl,
570
                 0x00000000);
571
    spr_register(env, SPR_IBAT3U, "IBAT3U",
572
                 SPR_NOACCESS, SPR_NOACCESS,
573
                 &spr_read_ibat, &spr_write_ibatu,
574
                 0x00000000);
575
    spr_register(env, SPR_IBAT3L, "IBAT3L",
576
                 SPR_NOACCESS, SPR_NOACCESS,
577
                 &spr_read_ibat, &spr_write_ibatl,
578
                 0x00000000);
579
    spr_register(env, SPR_DBAT0U, "DBAT0U",
580
                 SPR_NOACCESS, SPR_NOACCESS,
581
                 &spr_read_dbat, &spr_write_dbatu,
582
                 0x00000000);
583
    spr_register(env, SPR_DBAT0L, "DBAT0L",
584
                 SPR_NOACCESS, SPR_NOACCESS,
585
                 &spr_read_dbat, &spr_write_dbatl,
586
                 0x00000000);
587
    spr_register(env, SPR_DBAT1U, "DBAT1U",
588
                 SPR_NOACCESS, SPR_NOACCESS,
589
                 &spr_read_dbat, &spr_write_dbatu,
590
                 0x00000000);
591
    spr_register(env, SPR_DBAT1L, "DBAT1L",
592
                 SPR_NOACCESS, SPR_NOACCESS,
593
                 &spr_read_dbat, &spr_write_dbatl,
594
                 0x00000000);
595
    spr_register(env, SPR_DBAT2U, "DBAT2U",
596
                 SPR_NOACCESS, SPR_NOACCESS,
597
                 &spr_read_dbat, &spr_write_dbatu,
598
                 0x00000000);
599
    spr_register(env, SPR_DBAT2L, "DBAT2L",
600
                 SPR_NOACCESS, SPR_NOACCESS,
601
                 &spr_read_dbat, &spr_write_dbatl,
602
                 0x00000000);
603
    spr_register(env, SPR_DBAT3U, "DBAT3U",
604
                 SPR_NOACCESS, SPR_NOACCESS,
605
                 &spr_read_dbat, &spr_write_dbatu,
606
                 0x00000000);
607
    spr_register(env, SPR_DBAT3L, "DBAT3L",
608
                 SPR_NOACCESS, SPR_NOACCESS,
609
                 &spr_read_dbat, &spr_write_dbatl,
610
                 0x00000000);
611
    env->nb_BATs += 4;
612
#endif
613
}
614

    
615
/* BATs 4-7 */
616
static void gen_high_BATs (CPUPPCState *env)
617
{
618
#if !defined(CONFIG_USER_ONLY)
619
    spr_register(env, SPR_IBAT4U, "IBAT4U",
620
                 SPR_NOACCESS, SPR_NOACCESS,
621
                 &spr_read_ibat_h, &spr_write_ibatu_h,
622
                 0x00000000);
623
    spr_register(env, SPR_IBAT4L, "IBAT4L",
624
                 SPR_NOACCESS, SPR_NOACCESS,
625
                 &spr_read_ibat_h, &spr_write_ibatl_h,
626
                 0x00000000);
627
    spr_register(env, SPR_IBAT5U, "IBAT5U",
628
                 SPR_NOACCESS, SPR_NOACCESS,
629
                 &spr_read_ibat_h, &spr_write_ibatu_h,
630
                 0x00000000);
631
    spr_register(env, SPR_IBAT5L, "IBAT5L",
632
                 SPR_NOACCESS, SPR_NOACCESS,
633
                 &spr_read_ibat_h, &spr_write_ibatl_h,
634
                 0x00000000);
635
    spr_register(env, SPR_IBAT6U, "IBAT6U",
636
                 SPR_NOACCESS, SPR_NOACCESS,
637
                 &spr_read_ibat_h, &spr_write_ibatu_h,
638
                 0x00000000);
639
    spr_register(env, SPR_IBAT6L, "IBAT6L",
640
                 SPR_NOACCESS, SPR_NOACCESS,
641
                 &spr_read_ibat_h, &spr_write_ibatl_h,
642
                 0x00000000);
643
    spr_register(env, SPR_IBAT7U, "IBAT7U",
644
                 SPR_NOACCESS, SPR_NOACCESS,
645
                 &spr_read_ibat_h, &spr_write_ibatu_h,
646
                 0x00000000);
647
    spr_register(env, SPR_IBAT7L, "IBAT7L",
648
                 SPR_NOACCESS, SPR_NOACCESS,
649
                 &spr_read_ibat_h, &spr_write_ibatl_h,
650
                 0x00000000);
651
    spr_register(env, SPR_DBAT4U, "DBAT4U",
652
                 SPR_NOACCESS, SPR_NOACCESS,
653
                 &spr_read_dbat_h, &spr_write_dbatu_h,
654
                 0x00000000);
655
    spr_register(env, SPR_DBAT4L, "DBAT4L",
656
                 SPR_NOACCESS, SPR_NOACCESS,
657
                 &spr_read_dbat_h, &spr_write_dbatl_h,
658
                 0x00000000);
659
    spr_register(env, SPR_DBAT5U, "DBAT5U",
660
                 SPR_NOACCESS, SPR_NOACCESS,
661
                 &spr_read_dbat_h, &spr_write_dbatu_h,
662
                 0x00000000);
663
    spr_register(env, SPR_DBAT5L, "DBAT5L",
664
                 SPR_NOACCESS, SPR_NOACCESS,
665
                 &spr_read_dbat_h, &spr_write_dbatl_h,
666
                 0x00000000);
667
    spr_register(env, SPR_DBAT6U, "DBAT6U",
668
                 SPR_NOACCESS, SPR_NOACCESS,
669
                 &spr_read_dbat_h, &spr_write_dbatu_h,
670
                 0x00000000);
671
    spr_register(env, SPR_DBAT6L, "DBAT6L",
672
                 SPR_NOACCESS, SPR_NOACCESS,
673
                 &spr_read_dbat_h, &spr_write_dbatl_h,
674
                 0x00000000);
675
    spr_register(env, SPR_DBAT7U, "DBAT7U",
676
                 SPR_NOACCESS, SPR_NOACCESS,
677
                 &spr_read_dbat_h, &spr_write_dbatu_h,
678
                 0x00000000);
679
    spr_register(env, SPR_DBAT7L, "DBAT7L",
680
                 SPR_NOACCESS, SPR_NOACCESS,
681
                 &spr_read_dbat_h, &spr_write_dbatl_h,
682
                 0x00000000);
683
    env->nb_BATs += 4;
684
#endif
685
}
686

    
687
/* Generic PowerPC time base */
688
static void gen_tbl (CPUPPCState *env)
689
{
690
    spr_register(env, SPR_VTBL,  "TBL",
691
                 &spr_read_tbl, SPR_NOACCESS,
692
                 &spr_read_tbl, SPR_NOACCESS,
693
                 0x00000000);
694
    spr_register(env, SPR_TBL,   "TBL",
695
                 SPR_NOACCESS, SPR_NOACCESS,
696
                 SPR_NOACCESS, &spr_write_tbl,
697
                 0x00000000);
698
    spr_register(env, SPR_VTBU,  "TBU",
699
                 &spr_read_tbu, SPR_NOACCESS,
700
                 &spr_read_tbu, SPR_NOACCESS,
701
                 0x00000000);
702
    spr_register(env, SPR_TBU,   "TBU",
703
                 SPR_NOACCESS, SPR_NOACCESS,
704
                 SPR_NOACCESS, &spr_write_tbu,
705
                 0x00000000);
706
}
707

    
708
/* Softare table search registers */
709
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
710
{
711
#if !defined(CONFIG_USER_ONLY)
712
    env->nb_tlb = nb_tlbs;
713
    env->nb_ways = nb_ways;
714
    env->id_tlbs = 1;
715
    spr_register(env, SPR_DMISS, "DMISS",
716
                 SPR_NOACCESS, SPR_NOACCESS,
717
                 &spr_read_generic, SPR_NOACCESS,
718
                 0x00000000);
719
    spr_register(env, SPR_DCMP, "DCMP",
720
                 SPR_NOACCESS, SPR_NOACCESS,
721
                 &spr_read_generic, SPR_NOACCESS,
722
                 0x00000000);
723
    spr_register(env, SPR_HASH1, "HASH1",
724
                 SPR_NOACCESS, SPR_NOACCESS,
725
                 &spr_read_generic, SPR_NOACCESS,
726
                 0x00000000);
727
    spr_register(env, SPR_HASH2, "HASH2",
728
                 SPR_NOACCESS, SPR_NOACCESS,
729
                 &spr_read_generic, SPR_NOACCESS,
730
                 0x00000000);
731
    spr_register(env, SPR_IMISS, "IMISS",
732
                 SPR_NOACCESS, SPR_NOACCESS,
733
                 &spr_read_generic, SPR_NOACCESS,
734
                 0x00000000);
735
    spr_register(env, SPR_ICMP, "ICMP",
736
                 SPR_NOACCESS, SPR_NOACCESS,
737
                 &spr_read_generic, SPR_NOACCESS,
738
                 0x00000000);
739
    spr_register(env, SPR_RPA, "RPA",
740
                 SPR_NOACCESS, SPR_NOACCESS,
741
                 &spr_read_generic, &spr_write_generic,
742
                 0x00000000);
743
#endif
744
}
745

    
746
/* SPR common to MPC755 and G2 */
747
static void gen_spr_G2_755 (CPUPPCState *env)
748
{
749
    /* SGPRs */
750
    spr_register(env, SPR_SPRG4, "SPRG4",
751
                 SPR_NOACCESS, SPR_NOACCESS,
752
                 &spr_read_generic, &spr_write_generic,
753
                 0x00000000);
754
    spr_register(env, SPR_SPRG5, "SPRG5",
755
                 SPR_NOACCESS, SPR_NOACCESS,
756
                 &spr_read_generic, &spr_write_generic,
757
                 0x00000000);
758
    spr_register(env, SPR_SPRG6, "SPRG6",
759
                 SPR_NOACCESS, SPR_NOACCESS,
760
                 &spr_read_generic, &spr_write_generic,
761
                 0x00000000);
762
    spr_register(env, SPR_SPRG7, "SPRG7",
763
                 SPR_NOACCESS, SPR_NOACCESS,
764
                 &spr_read_generic, &spr_write_generic,
765
                 0x00000000);
766
    /* External access control */
767
    /* XXX : not implemented */
768
    spr_register(env, SPR_EAR, "EAR",
769
                 SPR_NOACCESS, SPR_NOACCESS,
770
                 &spr_read_generic, &spr_write_generic,
771
                 0x00000000);
772
}
773

    
774
/* SPR common to all 7xx PowerPC implementations */
775
static void gen_spr_7xx (CPUPPCState *env)
776
{
777
    /* Breakpoints */
778
    /* XXX : not implemented */
779
    spr_register(env, SPR_DABR, "DABR",
780
                 SPR_NOACCESS, SPR_NOACCESS,
781
                 &spr_read_generic, &spr_write_generic,
782
                 0x00000000);
783
    /* XXX : not implemented */
784
    spr_register(env, SPR_IABR, "IABR",
785
                 SPR_NOACCESS, SPR_NOACCESS,
786
                 &spr_read_generic, &spr_write_generic,
787
                 0x00000000);
788
    /* Cache management */
789
    /* XXX : not implemented */
790
    spr_register(env, SPR_ICTC, "ICTC",
791
                 SPR_NOACCESS, SPR_NOACCESS,
792
                 &spr_read_generic, &spr_write_generic,
793
                 0x00000000);
794
    /* XXX : not implemented */
795
    spr_register(env, SPR_L2CR, "L2CR",
796
                 SPR_NOACCESS, SPR_NOACCESS,
797
                 &spr_read_generic, &spr_write_generic,
798
                 0x00000000);
799
    /* Performance monitors */
800
    /* XXX : not implemented */
801
    spr_register(env, SPR_MMCR0, "MMCR0",
802
                 SPR_NOACCESS, SPR_NOACCESS,
803
                 &spr_read_generic, &spr_write_generic,
804
                 0x00000000);
805
    /* XXX : not implemented */
806
    spr_register(env, SPR_MMCR1, "MMCR1",
807
                 SPR_NOACCESS, SPR_NOACCESS,
808
                 &spr_read_generic, &spr_write_generic,
809
                 0x00000000);
810
    /* XXX : not implemented */
811
    spr_register(env, SPR_PMC1, "PMC1",
812
                 SPR_NOACCESS, SPR_NOACCESS,
813
                 &spr_read_generic, &spr_write_generic,
814
                 0x00000000);
815
    /* XXX : not implemented */
816
    spr_register(env, SPR_PMC2, "PMC2",
817
                 SPR_NOACCESS, SPR_NOACCESS,
818
                 &spr_read_generic, &spr_write_generic,
819
                 0x00000000);
820
    /* XXX : not implemented */
821
    spr_register(env, SPR_PMC3, "PMC3",
822
                 SPR_NOACCESS, SPR_NOACCESS,
823
                 &spr_read_generic, &spr_write_generic,
824
                 0x00000000);
825
    /* XXX : not implemented */
826
    spr_register(env, SPR_PMC4, "PMC4",
827
                 SPR_NOACCESS, SPR_NOACCESS,
828
                 &spr_read_generic, &spr_write_generic,
829
                 0x00000000);
830
    /* XXX : not implemented */
831
    spr_register(env, SPR_SIAR, "SIAR",
832
                 SPR_NOACCESS, SPR_NOACCESS,
833
                 &spr_read_generic, SPR_NOACCESS,
834
                 0x00000000);
835
    /* XXX : not implemented */
836
    spr_register(env, SPR_UMMCR0, "UMMCR0",
837
                 &spr_read_ureg, SPR_NOACCESS,
838
                 &spr_read_ureg, SPR_NOACCESS,
839
                 0x00000000);
840
    /* XXX : not implemented */
841
    spr_register(env, SPR_UMMCR1, "UMMCR1",
842
                 &spr_read_ureg, SPR_NOACCESS,
843
                 &spr_read_ureg, SPR_NOACCESS,
844
                 0x00000000);
845
    /* XXX : not implemented */
846
    spr_register(env, SPR_UPMC1, "UPMC1",
847
                 &spr_read_ureg, SPR_NOACCESS,
848
                 &spr_read_ureg, SPR_NOACCESS,
849
                 0x00000000);
850
    /* XXX : not implemented */
851
    spr_register(env, SPR_UPMC2, "UPMC2",
852
                 &spr_read_ureg, SPR_NOACCESS,
853
                 &spr_read_ureg, SPR_NOACCESS,
854
                 0x00000000);
855
    /* XXX : not implemented */
856
    spr_register(env, SPR_UPMC3, "UPMC3",
857
                 &spr_read_ureg, SPR_NOACCESS,
858
                 &spr_read_ureg, SPR_NOACCESS,
859
                 0x00000000);
860
    /* XXX : not implemented */
861
    spr_register(env, SPR_UPMC4, "UPMC4",
862
                 &spr_read_ureg, SPR_NOACCESS,
863
                 &spr_read_ureg, SPR_NOACCESS,
864
                 0x00000000);
865
    /* XXX : not implemented */
866
    spr_register(env, SPR_USIAR, "USIAR",
867
                 &spr_read_ureg, SPR_NOACCESS,
868
                 &spr_read_ureg, SPR_NOACCESS,
869
                 0x00000000);
870
    /* External access control */
871
    /* XXX : not implemented */
872
    spr_register(env, SPR_EAR, "EAR",
873
                 SPR_NOACCESS, SPR_NOACCESS,
874
                 &spr_read_generic, &spr_write_generic,
875
                 0x00000000);
876
}
877

    
878
static void gen_spr_thrm (CPUPPCState *env)
879
{
880
    /* Thermal management */
881
    /* XXX : not implemented */
882
    spr_register(env, SPR_THRM1, "THRM1",
883
                 SPR_NOACCESS, SPR_NOACCESS,
884
                 &spr_read_generic, &spr_write_generic,
885
                 0x00000000);
886
    /* XXX : not implemented */
887
    spr_register(env, SPR_THRM2, "THRM2",
888
                 SPR_NOACCESS, SPR_NOACCESS,
889
                 &spr_read_generic, &spr_write_generic,
890
                 0x00000000);
891
    /* XXX : not implemented */
892
    spr_register(env, SPR_THRM3, "THRM3",
893
                 SPR_NOACCESS, SPR_NOACCESS,
894
                 &spr_read_generic, &spr_write_generic,
895
                 0x00000000);
896
}
897

    
898
/* SPR specific to PowerPC 604 implementation */
899
static void gen_spr_604 (CPUPPCState *env)
900
{
901
    /* Processor identification */
902
    spr_register(env, SPR_PIR, "PIR",
903
                 SPR_NOACCESS, SPR_NOACCESS,
904
                 &spr_read_generic, &spr_write_pir,
905
                 0x00000000);
906
    /* Breakpoints */
907
    /* XXX : not implemented */
908
    spr_register(env, SPR_IABR, "IABR",
909
                 SPR_NOACCESS, SPR_NOACCESS,
910
                 &spr_read_generic, &spr_write_generic,
911
                 0x00000000);
912
    /* XXX : not implemented */
913
    spr_register(env, SPR_DABR, "DABR",
914
                 SPR_NOACCESS, SPR_NOACCESS,
915
                 &spr_read_generic, &spr_write_generic,
916
                 0x00000000);
917
    /* Performance counters */
918
    /* XXX : not implemented */
919
    spr_register(env, SPR_MMCR0, "MMCR0",
920
                 SPR_NOACCESS, SPR_NOACCESS,
921
                 &spr_read_generic, &spr_write_generic,
922
                 0x00000000);
923
    /* XXX : not implemented */
924
    spr_register(env, SPR_MMCR1, "MMCR1",
925
                 SPR_NOACCESS, SPR_NOACCESS,
926
                 &spr_read_generic, &spr_write_generic,
927
                 0x00000000);
928
    /* XXX : not implemented */
929
    spr_register(env, SPR_PMC1, "PMC1",
930
                 SPR_NOACCESS, SPR_NOACCESS,
931
                 &spr_read_generic, &spr_write_generic,
932
                 0x00000000);
933
    /* XXX : not implemented */
934
    spr_register(env, SPR_PMC2, "PMC2",
935
                 SPR_NOACCESS, SPR_NOACCESS,
936
                 &spr_read_generic, &spr_write_generic,
937
                 0x00000000);
938
    /* XXX : not implemented */
939
    spr_register(env, SPR_PMC3, "PMC3",
940
                 SPR_NOACCESS, SPR_NOACCESS,
941
                 &spr_read_generic, &spr_write_generic,
942
                 0x00000000);
943
    /* XXX : not implemented */
944
    spr_register(env, SPR_PMC4, "PMC4",
945
                 SPR_NOACCESS, SPR_NOACCESS,
946
                 &spr_read_generic, &spr_write_generic,
947
                 0x00000000);
948
    /* XXX : not implemented */
949
    spr_register(env, SPR_SIAR, "SIAR",
950
                 SPR_NOACCESS, SPR_NOACCESS,
951
                 &spr_read_generic, SPR_NOACCESS,
952
                 0x00000000);
953
    /* XXX : not implemented */
954
    spr_register(env, SPR_SDA, "SDA",
955
                 SPR_NOACCESS, SPR_NOACCESS,
956
                 &spr_read_generic, SPR_NOACCESS,
957
                 0x00000000);
958
    /* External access control */
959
    /* XXX : not implemented */
960
    spr_register(env, SPR_EAR, "EAR",
961
                 SPR_NOACCESS, SPR_NOACCESS,
962
                 &spr_read_generic, &spr_write_generic,
963
                 0x00000000);
964
}
965

    
966
/* SPR specific to PowerPC 603 implementation */
967
static void gen_spr_603 (CPUPPCState *env)
968
{
969
    /* External access control */
970
    /* XXX : not implemented */
971
    spr_register(env, SPR_EAR, "EAR",
972
                 SPR_NOACCESS, SPR_NOACCESS,
973
                 &spr_read_generic, &spr_write_generic,
974
                 0x00000000);
975
}
976

    
977
/* SPR specific to PowerPC G2 implementation */
978
static void gen_spr_G2 (CPUPPCState *env)
979
{
980
    /* Memory base address */
981
    /* MBAR */
982
    /* XXX : not implemented */
983
    spr_register(env, SPR_MBAR, "MBAR",
984
                 SPR_NOACCESS, SPR_NOACCESS,
985
                 &spr_read_generic, &spr_write_generic,
986
                 0x00000000);
987
    /* System version register */
988
    /* SVR */
989
    /* XXX : TODO: initialize it to an appropriate value */
990
    spr_register(env, SPR_SVR, "SVR",
991
                 SPR_NOACCESS, SPR_NOACCESS,
992
                 &spr_read_generic, SPR_NOACCESS,
993
                 0x00000000);
994
    /* Exception processing */
995
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
996
                 SPR_NOACCESS, SPR_NOACCESS,
997
                 &spr_read_generic, &spr_write_generic,
998
                 0x00000000);
999
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1000
                 SPR_NOACCESS, SPR_NOACCESS,
1001
                 &spr_read_generic, &spr_write_generic,
1002
                 0x00000000);
1003
    /* Breakpoints */
1004
    /* XXX : not implemented */
1005
    spr_register(env, SPR_DABR, "DABR",
1006
                 SPR_NOACCESS, SPR_NOACCESS,
1007
                 &spr_read_generic, &spr_write_generic,
1008
                 0x00000000);
1009
    /* XXX : not implemented */
1010
    spr_register(env, SPR_DABR2, "DABR2",
1011
                 SPR_NOACCESS, SPR_NOACCESS,
1012
                 &spr_read_generic, &spr_write_generic,
1013
                 0x00000000);
1014
    /* XXX : not implemented */
1015
    spr_register(env, SPR_IABR, "IABR",
1016
                 SPR_NOACCESS, SPR_NOACCESS,
1017
                 &spr_read_generic, &spr_write_generic,
1018
                 0x00000000);
1019
    /* XXX : not implemented */
1020
    spr_register(env, SPR_IABR2, "IABR2",
1021
                 SPR_NOACCESS, SPR_NOACCESS,
1022
                 &spr_read_generic, &spr_write_generic,
1023
                 0x00000000);
1024
    /* XXX : not implemented */
1025
    spr_register(env, SPR_IBCR, "IBCR",
1026
                 SPR_NOACCESS, SPR_NOACCESS,
1027
                 &spr_read_generic, &spr_write_generic,
1028
                 0x00000000);
1029
    /* XXX : not implemented */
1030
    spr_register(env, SPR_DBCR, "DBCR",
1031
                 SPR_NOACCESS, SPR_NOACCESS,
1032
                 &spr_read_generic, &spr_write_generic,
1033
                 0x00000000);
1034
}
1035

    
1036
/* SPR specific to PowerPC 602 implementation */
1037
static void gen_spr_602 (CPUPPCState *env)
1038
{
1039
    /* ESA registers */
1040
    /* XXX : not implemented */
1041
    spr_register(env, SPR_SER, "SER",
1042
                 SPR_NOACCESS, SPR_NOACCESS,
1043
                 &spr_read_generic, &spr_write_generic,
1044
                 0x00000000);
1045
    /* XXX : not implemented */
1046
    spr_register(env, SPR_SEBR, "SEBR",
1047
                 SPR_NOACCESS, SPR_NOACCESS,
1048
                 &spr_read_generic, &spr_write_generic,
1049
                 0x00000000);
1050
    /* XXX : not implemented */
1051
    spr_register(env, SPR_ESASRR, "ESASRR",
1052
                 SPR_NOACCESS, SPR_NOACCESS,
1053
                 &spr_read_generic, &spr_write_generic,
1054
                 0x00000000);
1055
    /* Floating point status */
1056
    /* XXX : not implemented */
1057
    spr_register(env, SPR_SP, "SP",
1058
                 SPR_NOACCESS, SPR_NOACCESS,
1059
                 &spr_read_generic, &spr_write_generic,
1060
                 0x00000000);
1061
    /* XXX : not implemented */
1062
    spr_register(env, SPR_LT, "LT",
1063
                 SPR_NOACCESS, SPR_NOACCESS,
1064
                 &spr_read_generic, &spr_write_generic,
1065
                 0x00000000);
1066
    /* Watchdog timer */
1067
    /* XXX : not implemented */
1068
    spr_register(env, SPR_TCR, "TCR",
1069
                 SPR_NOACCESS, SPR_NOACCESS,
1070
                 &spr_read_generic, &spr_write_generic,
1071
                 0x00000000);
1072
    /* Interrupt base */
1073
    spr_register(env, SPR_IBR, "IBR",
1074
                 SPR_NOACCESS, SPR_NOACCESS,
1075
                 &spr_read_generic, &spr_write_generic,
1076
                 0x00000000);
1077
    /* XXX : not implemented */
1078
    spr_register(env, SPR_IABR, "IABR",
1079
                 SPR_NOACCESS, SPR_NOACCESS,
1080
                 &spr_read_generic, &spr_write_generic,
1081
                 0x00000000);
1082
}
1083

    
1084
/* SPR specific to PowerPC 601 implementation */
1085
static void gen_spr_601 (CPUPPCState *env)
1086
{
1087
    /* Multiplication/division register */
1088
    /* MQ */
1089
    spr_register(env, SPR_MQ, "MQ",
1090
                 &spr_read_generic, &spr_write_generic,
1091
                 &spr_read_generic, &spr_write_generic,
1092
                 0x00000000);
1093
    /* RTC registers */
1094
    spr_register(env, SPR_601_RTCU, "RTCU",
1095
                 SPR_NOACCESS, SPR_NOACCESS,
1096
                 SPR_NOACCESS, &spr_write_601_rtcu,
1097
                 0x00000000);
1098
    spr_register(env, SPR_601_VRTCU, "RTCU",
1099
                 &spr_read_601_rtcu, SPR_NOACCESS,
1100
                 &spr_read_601_rtcu, SPR_NOACCESS,
1101
                 0x00000000);
1102
    spr_register(env, SPR_601_RTCL, "RTCL",
1103
                 SPR_NOACCESS, SPR_NOACCESS,
1104
                 SPR_NOACCESS, &spr_write_601_rtcl,
1105
                 0x00000000);
1106
    spr_register(env, SPR_601_VRTCL, "RTCL",
1107
                 &spr_read_601_rtcl, SPR_NOACCESS,
1108
                 &spr_read_601_rtcl, SPR_NOACCESS,
1109
                 0x00000000);
1110
    /* Timer */
1111
#if 0 /* ? */
1112
    spr_register(env, SPR_601_UDECR, "UDECR",
1113
                 &spr_read_decr, SPR_NOACCESS,
1114
                 &spr_read_decr, SPR_NOACCESS,
1115
                 0x00000000);
1116
#endif
1117
    /* External access control */
1118
    /* XXX : not implemented */
1119
    spr_register(env, SPR_EAR, "EAR",
1120
                 SPR_NOACCESS, SPR_NOACCESS,
1121
                 &spr_read_generic, &spr_write_generic,
1122
                 0x00000000);
1123
    /* Memory management */
1124
#if !defined(CONFIG_USER_ONLY)
1125
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1126
                 SPR_NOACCESS, SPR_NOACCESS,
1127
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1128
                 0x00000000);
1129
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1130
                 SPR_NOACCESS, SPR_NOACCESS,
1131
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1132
                 0x00000000);
1133
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1134
                 SPR_NOACCESS, SPR_NOACCESS,
1135
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1136
                 0x00000000);
1137
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1138
                 SPR_NOACCESS, SPR_NOACCESS,
1139
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1140
                 0x00000000);
1141
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1142
                 SPR_NOACCESS, SPR_NOACCESS,
1143
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1144
                 0x00000000);
1145
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1146
                 SPR_NOACCESS, SPR_NOACCESS,
1147
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1148
                 0x00000000);
1149
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1150
                 SPR_NOACCESS, SPR_NOACCESS,
1151
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1152
                 0x00000000);
1153
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1154
                 SPR_NOACCESS, SPR_NOACCESS,
1155
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1156
                 0x00000000);
1157
    env->nb_BATs = 4;
1158
#endif
1159
}
1160

    
1161
static void gen_spr_74xx (CPUPPCState *env)
1162
{
1163
    /* Processor identification */
1164
    spr_register(env, SPR_PIR, "PIR",
1165
                 SPR_NOACCESS, SPR_NOACCESS,
1166
                 &spr_read_generic, &spr_write_pir,
1167
                 0x00000000);
1168
    /* XXX : not implemented */
1169
    spr_register(env, SPR_MMCR2, "MMCR2",
1170
                 SPR_NOACCESS, SPR_NOACCESS,
1171
                 &spr_read_generic, &spr_write_generic,
1172
                 0x00000000);
1173
    /* XXX : not implemented */
1174
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1175
                 &spr_read_ureg, SPR_NOACCESS,
1176
                 &spr_read_ureg, SPR_NOACCESS,
1177
                 0x00000000);
1178
    /* XXX: not implemented */
1179
    spr_register(env, SPR_BAMR, "BAMR",
1180
                 SPR_NOACCESS, SPR_NOACCESS,
1181
                 &spr_read_generic, &spr_write_generic,
1182
                 0x00000000);
1183
    /* XXX : not implemented */
1184
    spr_register(env, SPR_UBAMR, "UBAMR",
1185
                 &spr_read_ureg, SPR_NOACCESS,
1186
                 &spr_read_ureg, SPR_NOACCESS,
1187
                 0x00000000);
1188
    /* XXX : not implemented */
1189
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1190
                 SPR_NOACCESS, SPR_NOACCESS,
1191
                 &spr_read_generic, &spr_write_generic,
1192
                 0x00000000);
1193
    /* Hardware implementation registers */
1194
    /* XXX : not implemented */
1195
    spr_register(env, SPR_HID0, "HID0",
1196
                 SPR_NOACCESS, SPR_NOACCESS,
1197
                 &spr_read_generic, &spr_write_generic,
1198
                 0x00000000);
1199
    /* XXX : not implemented */
1200
    spr_register(env, SPR_HID1, "HID1",
1201
                 SPR_NOACCESS, SPR_NOACCESS,
1202
                 &spr_read_generic, &spr_write_generic,
1203
                 0x00000000);
1204
    /* Altivec */
1205
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1206
                 &spr_read_generic, &spr_write_generic,
1207
                 &spr_read_generic, &spr_write_generic,
1208
                 0x00000000);
1209
}
1210

    
1211
static void gen_l3_ctrl (CPUPPCState *env)
1212
{
1213
    /* L3CR */
1214
    /* XXX : not implemented */
1215
    spr_register(env, SPR_L3CR, "L3CR",
1216
                 SPR_NOACCESS, SPR_NOACCESS,
1217
                 &spr_read_generic, &spr_write_generic,
1218
                 0x00000000);
1219
    /* L3ITCR0 */
1220
    /* XXX : not implemented */
1221
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1222
                 SPR_NOACCESS, SPR_NOACCESS,
1223
                 &spr_read_generic, &spr_write_generic,
1224
                 0x00000000);
1225
    /* L3ITCR1 */
1226
    /* XXX : not implemented */
1227
    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1228
                 SPR_NOACCESS, SPR_NOACCESS,
1229
                 &spr_read_generic, &spr_write_generic,
1230
                 0x00000000);
1231
    /* L3ITCR2 */
1232
    /* XXX : not implemented */
1233
    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1234
                 SPR_NOACCESS, SPR_NOACCESS,
1235
                 &spr_read_generic, &spr_write_generic,
1236
                 0x00000000);
1237
    /* L3ITCR3 */
1238
    /* XXX : not implemented */
1239
    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1240
                 SPR_NOACCESS, SPR_NOACCESS,
1241
                 &spr_read_generic, &spr_write_generic,
1242
                 0x00000000);
1243
    /* L3OHCR */
1244
    /* XXX : not implemented */
1245
    spr_register(env, SPR_L3OHCR, "L3OHCR",
1246
                 SPR_NOACCESS, SPR_NOACCESS,
1247
                 &spr_read_generic, &spr_write_generic,
1248
                 0x00000000);
1249
    /* L3PM */
1250
    /* XXX : not implemented */
1251
    spr_register(env, SPR_L3PM, "L3PM",
1252
                 SPR_NOACCESS, SPR_NOACCESS,
1253
                 &spr_read_generic, &spr_write_generic,
1254
                 0x00000000);
1255
}
1256

    
1257
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1258
{
1259
#if !defined(CONFIG_USER_ONLY)
1260
    env->nb_tlb = nb_tlbs;
1261
    env->nb_ways = nb_ways;
1262
    env->id_tlbs = 1;
1263
    /* XXX : not implemented */
1264
    spr_register(env, SPR_PTEHI, "PTEHI",
1265
                 SPR_NOACCESS, SPR_NOACCESS,
1266
                 &spr_read_generic, &spr_write_generic,
1267
                 0x00000000);
1268
    /* XXX : not implemented */
1269
    spr_register(env, SPR_PTELO, "PTELO",
1270
                 SPR_NOACCESS, SPR_NOACCESS,
1271
                 &spr_read_generic, &spr_write_generic,
1272
                 0x00000000);
1273
    /* XXX : not implemented */
1274
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1275
                 SPR_NOACCESS, SPR_NOACCESS,
1276
                 &spr_read_generic, &spr_write_generic,
1277
                 0x00000000);
1278
#endif
1279
}
1280

    
1281
/* PowerPC BookE SPR */
1282
static void gen_spr_BookE (CPUPPCState *env)
1283
{
1284
    /* Processor identification */
1285
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1286
                 SPR_NOACCESS, SPR_NOACCESS,
1287
                 &spr_read_generic, &spr_write_pir,
1288
                 0x00000000);
1289
    /* Interrupt processing */
1290
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1291
                 SPR_NOACCESS, SPR_NOACCESS,
1292
                 &spr_read_generic, &spr_write_generic,
1293
                 0x00000000);
1294
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1295
                 SPR_NOACCESS, SPR_NOACCESS,
1296
                 &spr_read_generic, &spr_write_generic,
1297
                 0x00000000);
1298
#if 0
1299
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1300
                 SPR_NOACCESS, SPR_NOACCESS,
1301
                 &spr_read_generic, &spr_write_generic,
1302
                 0x00000000);
1303
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1304
                 SPR_NOACCESS, SPR_NOACCESS,
1305
                 &spr_read_generic, &spr_write_generic,
1306
                 0x00000000);
1307
#endif
1308
    /* Debug */
1309
    /* XXX : not implemented */
1310
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1311
                 SPR_NOACCESS, SPR_NOACCESS,
1312
                 &spr_read_generic, &spr_write_generic,
1313
                 0x00000000);
1314
    /* XXX : not implemented */
1315
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1316
                 SPR_NOACCESS, SPR_NOACCESS,
1317
                 &spr_read_generic, &spr_write_generic,
1318
                 0x00000000);
1319
    /* XXX : not implemented */
1320
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1321
                 SPR_NOACCESS, SPR_NOACCESS,
1322
                 &spr_read_generic, &spr_write_generic,
1323
                 0x00000000);
1324
    /* XXX : not implemented */
1325
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1326
                 SPR_NOACCESS, SPR_NOACCESS,
1327
                 &spr_read_generic, &spr_write_generic,
1328
                 0x00000000);
1329
    /* XXX : not implemented */
1330
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1331
                 SPR_NOACCESS, SPR_NOACCESS,
1332
                 &spr_read_generic, &spr_write_generic,
1333
                 0x00000000);
1334
    /* XXX : not implemented */
1335
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1336
                 SPR_NOACCESS, SPR_NOACCESS,
1337
                 &spr_read_generic, &spr_write_generic,
1338
                 0x00000000);
1339
    /* XXX : not implemented */
1340
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1341
                 SPR_NOACCESS, SPR_NOACCESS,
1342
                 &spr_read_generic, &spr_write_generic,
1343
                 0x00000000);
1344
    /* XXX : not implemented */
1345
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1346
                 SPR_NOACCESS, SPR_NOACCESS,
1347
                 &spr_read_generic, &spr_write_generic,
1348
                 0x00000000);
1349
    /* XXX : not implemented */
1350
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1351
                 SPR_NOACCESS, SPR_NOACCESS,
1352
                 &spr_read_generic, &spr_write_generic,
1353
                 0x00000000);
1354
    /* XXX : not implemented */
1355
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1356
                 SPR_NOACCESS, SPR_NOACCESS,
1357
                 &spr_read_generic, &spr_write_generic,
1358
                 0x00000000);
1359
    /* XXX : not implemented */
1360
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1361
                 SPR_NOACCESS, SPR_NOACCESS,
1362
                 &spr_read_generic, &spr_write_generic,
1363
                 0x00000000);
1364
    /* XXX : not implemented */
1365
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1366
                 SPR_NOACCESS, SPR_NOACCESS,
1367
                 &spr_read_generic, &spr_write_clear,
1368
                 0x00000000);
1369
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1370
                 SPR_NOACCESS, SPR_NOACCESS,
1371
                 &spr_read_generic, &spr_write_generic,
1372
                 0x00000000);
1373
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1374
                 SPR_NOACCESS, SPR_NOACCESS,
1375
                 &spr_read_generic, &spr_write_generic,
1376
                 0x00000000);
1377
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1378
                 SPR_NOACCESS, SPR_NOACCESS,
1379
                 &spr_read_generic, &spr_write_excp_prefix,
1380
                 0x00000000);
1381
    /* Exception vectors */
1382
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1383
                 SPR_NOACCESS, SPR_NOACCESS,
1384
                 &spr_read_generic, &spr_write_excp_vector,
1385
                 0x00000000);
1386
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1387
                 SPR_NOACCESS, SPR_NOACCESS,
1388
                 &spr_read_generic, &spr_write_excp_vector,
1389
                 0x00000000);
1390
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1391
                 SPR_NOACCESS, SPR_NOACCESS,
1392
                 &spr_read_generic, &spr_write_excp_vector,
1393
                 0x00000000);
1394
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1395
                 SPR_NOACCESS, SPR_NOACCESS,
1396
                 &spr_read_generic, &spr_write_excp_vector,
1397
                 0x00000000);
1398
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1399
                 SPR_NOACCESS, SPR_NOACCESS,
1400
                 &spr_read_generic, &spr_write_excp_vector,
1401
                 0x00000000);
1402
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1403
                 SPR_NOACCESS, SPR_NOACCESS,
1404
                 &spr_read_generic, &spr_write_excp_vector,
1405
                 0x00000000);
1406
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1407
                 SPR_NOACCESS, SPR_NOACCESS,
1408
                 &spr_read_generic, &spr_write_excp_vector,
1409
                 0x00000000);
1410
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1411
                 SPR_NOACCESS, SPR_NOACCESS,
1412
                 &spr_read_generic, &spr_write_excp_vector,
1413
                 0x00000000);
1414
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1415
                 SPR_NOACCESS, SPR_NOACCESS,
1416
                 &spr_read_generic, &spr_write_excp_vector,
1417
                 0x00000000);
1418
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1419
                 SPR_NOACCESS, SPR_NOACCESS,
1420
                 &spr_read_generic, &spr_write_excp_vector,
1421
                 0x00000000);
1422
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1423
                 SPR_NOACCESS, SPR_NOACCESS,
1424
                 &spr_read_generic, &spr_write_excp_vector,
1425
                 0x00000000);
1426
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1427
                 SPR_NOACCESS, SPR_NOACCESS,
1428
                 &spr_read_generic, &spr_write_excp_vector,
1429
                 0x00000000);
1430
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1431
                 SPR_NOACCESS, SPR_NOACCESS,
1432
                 &spr_read_generic, &spr_write_excp_vector,
1433
                 0x00000000);
1434
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1435
                 SPR_NOACCESS, SPR_NOACCESS,
1436
                 &spr_read_generic, &spr_write_excp_vector,
1437
                 0x00000000);
1438
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1439
                 SPR_NOACCESS, SPR_NOACCESS,
1440
                 &spr_read_generic, &spr_write_excp_vector,
1441
                 0x00000000);
1442
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1443
                 SPR_NOACCESS, SPR_NOACCESS,
1444
                 &spr_read_generic, &spr_write_excp_vector,
1445
                 0x00000000);
1446
#if 0
1447
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1448
                 SPR_NOACCESS, SPR_NOACCESS,
1449
                 &spr_read_generic, &spr_write_excp_vector,
1450
                 0x00000000);
1451
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1452
                 SPR_NOACCESS, SPR_NOACCESS,
1453
                 &spr_read_generic, &spr_write_excp_vector,
1454
                 0x00000000);
1455
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1456
                 SPR_NOACCESS, SPR_NOACCESS,
1457
                 &spr_read_generic, &spr_write_excp_vector,
1458
                 0x00000000);
1459
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1460
                 SPR_NOACCESS, SPR_NOACCESS,
1461
                 &spr_read_generic, &spr_write_excp_vector,
1462
                 0x00000000);
1463
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1464
                 SPR_NOACCESS, SPR_NOACCESS,
1465
                 &spr_read_generic, &spr_write_excp_vector,
1466
                 0x00000000);
1467
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1468
                 SPR_NOACCESS, SPR_NOACCESS,
1469
                 &spr_read_generic, &spr_write_excp_vector,
1470
                 0x00000000);
1471
#endif
1472
    spr_register(env, SPR_BOOKE_PID, "PID",
1473
                 SPR_NOACCESS, SPR_NOACCESS,
1474
                 &spr_read_generic, &spr_write_generic,
1475
                 0x00000000);
1476
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1477
                 SPR_NOACCESS, SPR_NOACCESS,
1478
                 &spr_read_generic, &spr_write_booke_tcr,
1479
                 0x00000000);
1480
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1481
                 SPR_NOACCESS, SPR_NOACCESS,
1482
                 &spr_read_generic, &spr_write_booke_tsr,
1483
                 0x00000000);
1484
    /* Timer */
1485
    spr_register(env, SPR_DECR, "DECR",
1486
                 SPR_NOACCESS, SPR_NOACCESS,
1487
                 &spr_read_decr, &spr_write_decr,
1488
                 0x00000000);
1489
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1490
                 SPR_NOACCESS, SPR_NOACCESS,
1491
                 SPR_NOACCESS, &spr_write_generic,
1492
                 0x00000000);
1493
    /* SPRGs */
1494
    spr_register(env, SPR_USPRG0, "USPRG0",
1495
                 &spr_read_generic, &spr_write_generic,
1496
                 &spr_read_generic, &spr_write_generic,
1497
                 0x00000000);
1498
    spr_register(env, SPR_SPRG4, "SPRG4",
1499
                 SPR_NOACCESS, SPR_NOACCESS,
1500
                 &spr_read_generic, &spr_write_generic,
1501
                 0x00000000);
1502
    spr_register(env, SPR_USPRG4, "USPRG4",
1503
                 &spr_read_ureg, SPR_NOACCESS,
1504
                 &spr_read_ureg, SPR_NOACCESS,
1505
                 0x00000000);
1506
    spr_register(env, SPR_SPRG5, "SPRG5",
1507
                 SPR_NOACCESS, SPR_NOACCESS,
1508
                 &spr_read_generic, &spr_write_generic,
1509
                 0x00000000);
1510
    spr_register(env, SPR_USPRG5, "USPRG5",
1511
                 &spr_read_ureg, SPR_NOACCESS,
1512
                 &spr_read_ureg, SPR_NOACCESS,
1513
                 0x00000000);
1514
    spr_register(env, SPR_SPRG6, "SPRG6",
1515
                 SPR_NOACCESS, SPR_NOACCESS,
1516
                 &spr_read_generic, &spr_write_generic,
1517
                 0x00000000);
1518
    spr_register(env, SPR_USPRG6, "USPRG6",
1519
                 &spr_read_ureg, SPR_NOACCESS,
1520
                 &spr_read_ureg, SPR_NOACCESS,
1521
                 0x00000000);
1522
    spr_register(env, SPR_SPRG7, "SPRG7",
1523
                 SPR_NOACCESS, SPR_NOACCESS,
1524
                 &spr_read_generic, &spr_write_generic,
1525
                 0x00000000);
1526
    spr_register(env, SPR_USPRG7, "USPRG7",
1527
                 &spr_read_ureg, SPR_NOACCESS,
1528
                 &spr_read_ureg, SPR_NOACCESS,
1529
                 0x00000000);
1530
}
1531

    
1532
/* FSL storage control registers */
1533
static void gen_spr_BookE_FSL (CPUPPCState *env)
1534
{
1535
#if !defined(CONFIG_USER_ONLY)
1536
    /* TLB assist registers */
1537
    /* XXX : not implemented */
1538
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1539
                 SPR_NOACCESS, SPR_NOACCESS,
1540
                 &spr_read_generic, &spr_write_generic,
1541
                 0x00000000);
1542
    /* XXX : not implemented */
1543
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1544
                 SPR_NOACCESS, SPR_NOACCESS,
1545
                 &spr_read_generic, &spr_write_generic,
1546
                 0x00000000);
1547
    /* XXX : not implemented */
1548
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1549
                 SPR_NOACCESS, SPR_NOACCESS,
1550
                 &spr_read_generic, &spr_write_generic,
1551
                 0x00000000);
1552
    /* XXX : not implemented */
1553
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1554
                 SPR_NOACCESS, SPR_NOACCESS,
1555
                 &spr_read_generic, &spr_write_generic,
1556
                 0x00000000);
1557
    /* XXX : not implemented */
1558
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1559
                 SPR_NOACCESS, SPR_NOACCESS,
1560
                 &spr_read_generic, &spr_write_generic,
1561
                 0x00000000);
1562
    /* XXX : not implemented */
1563
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1564
                 SPR_NOACCESS, SPR_NOACCESS,
1565
                 &spr_read_generic, &spr_write_generic,
1566
                 0x00000000);
1567
    /* XXX : not implemented */
1568
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1569
                 SPR_NOACCESS, SPR_NOACCESS,
1570
                 &spr_read_generic, &spr_write_generic,
1571
                 0x00000000);
1572
    if (env->nb_pids > 1) {
1573
        /* XXX : not implemented */
1574
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1575
                     SPR_NOACCESS, SPR_NOACCESS,
1576
                     &spr_read_generic, &spr_write_generic,
1577
                     0x00000000);
1578
    }
1579
    if (env->nb_pids > 2) {
1580
        /* XXX : not implemented */
1581
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1582
                     SPR_NOACCESS, SPR_NOACCESS,
1583
                     &spr_read_generic, &spr_write_generic,
1584
                     0x00000000);
1585
    }
1586
    /* XXX : not implemented */
1587
    spr_register(env, SPR_MMUCFG, "MMUCFG",
1588
                 SPR_NOACCESS, SPR_NOACCESS,
1589
                 &spr_read_generic, SPR_NOACCESS,
1590
                 0x00000000); /* TOFIX */
1591
    /* XXX : not implemented */
1592
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1593
                 SPR_NOACCESS, SPR_NOACCESS,
1594
                 &spr_read_generic, &spr_write_generic,
1595
                 0x00000000); /* TOFIX */
1596
    switch (env->nb_ways) {
1597
    case 4:
1598
        /* XXX : not implemented */
1599
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1600
                     SPR_NOACCESS, SPR_NOACCESS,
1601
                     &spr_read_generic, SPR_NOACCESS,
1602
                     0x00000000); /* TOFIX */
1603
        /* Fallthru */
1604
    case 3:
1605
        /* XXX : not implemented */
1606
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1607
                     SPR_NOACCESS, SPR_NOACCESS,
1608
                     &spr_read_generic, SPR_NOACCESS,
1609
                     0x00000000); /* TOFIX */
1610
        /* Fallthru */
1611
    case 2:
1612
        /* XXX : not implemented */
1613
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1614
                     SPR_NOACCESS, SPR_NOACCESS,
1615
                     &spr_read_generic, SPR_NOACCESS,
1616
                     0x00000000); /* TOFIX */
1617
        /* Fallthru */
1618
    case 1:
1619
        /* XXX : not implemented */
1620
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1621
                     SPR_NOACCESS, SPR_NOACCESS,
1622
                     &spr_read_generic, SPR_NOACCESS,
1623
                     0x00000000); /* TOFIX */
1624
        /* Fallthru */
1625
    case 0:
1626
    default:
1627
        break;
1628
    }
1629
#endif
1630
}
1631

    
1632
/* SPR specific to PowerPC 440 implementation */
1633
static void gen_spr_440 (CPUPPCState *env)
1634
{
1635
    /* Cache control */
1636
    /* XXX : not implemented */
1637
    spr_register(env, SPR_440_DNV0, "DNV0",
1638
                 SPR_NOACCESS, SPR_NOACCESS,
1639
                 &spr_read_generic, &spr_write_generic,
1640
                 0x00000000);
1641
    /* XXX : not implemented */
1642
    spr_register(env, SPR_440_DNV1, "DNV1",
1643
                 SPR_NOACCESS, SPR_NOACCESS,
1644
                 &spr_read_generic, &spr_write_generic,
1645
                 0x00000000);
1646
    /* XXX : not implemented */
1647
    spr_register(env, SPR_440_DNV2, "DNV2",
1648
                 SPR_NOACCESS, SPR_NOACCESS,
1649
                 &spr_read_generic, &spr_write_generic,
1650
                 0x00000000);
1651
    /* XXX : not implemented */
1652
    spr_register(env, SPR_440_DNV3, "DNV3",
1653
                 SPR_NOACCESS, SPR_NOACCESS,
1654
                 &spr_read_generic, &spr_write_generic,
1655
                 0x00000000);
1656
    /* XXX : not implemented */
1657
    spr_register(env, SPR_440_DTV0, "DTV0",
1658
                 SPR_NOACCESS, SPR_NOACCESS,
1659
                 &spr_read_generic, &spr_write_generic,
1660
                 0x00000000);
1661
    /* XXX : not implemented */
1662
    spr_register(env, SPR_440_DTV1, "DTV1",
1663
                 SPR_NOACCESS, SPR_NOACCESS,
1664
                 &spr_read_generic, &spr_write_generic,
1665
                 0x00000000);
1666
    /* XXX : not implemented */
1667
    spr_register(env, SPR_440_DTV2, "DTV2",
1668
                 SPR_NOACCESS, SPR_NOACCESS,
1669
                 &spr_read_generic, &spr_write_generic,
1670
                 0x00000000);
1671
    /* XXX : not implemented */
1672
    spr_register(env, SPR_440_DTV3, "DTV3",
1673
                 SPR_NOACCESS, SPR_NOACCESS,
1674
                 &spr_read_generic, &spr_write_generic,
1675
                 0x00000000);
1676
    /* XXX : not implemented */
1677
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1678
                 SPR_NOACCESS, SPR_NOACCESS,
1679
                 &spr_read_generic, &spr_write_generic,
1680
                 0x00000000);
1681
    /* XXX : not implemented */
1682
    spr_register(env, SPR_440_INV0, "INV0",
1683
                 SPR_NOACCESS, SPR_NOACCESS,
1684
                 &spr_read_generic, &spr_write_generic,
1685
                 0x00000000);
1686
    /* XXX : not implemented */
1687
    spr_register(env, SPR_440_INV1, "INV1",
1688
                 SPR_NOACCESS, SPR_NOACCESS,
1689
                 &spr_read_generic, &spr_write_generic,
1690
                 0x00000000);
1691
    /* XXX : not implemented */
1692
    spr_register(env, SPR_440_INV2, "INV2",
1693
                 SPR_NOACCESS, SPR_NOACCESS,
1694
                 &spr_read_generic, &spr_write_generic,
1695
                 0x00000000);
1696
    /* XXX : not implemented */
1697
    spr_register(env, SPR_440_INV3, "INV3",
1698
                 SPR_NOACCESS, SPR_NOACCESS,
1699
                 &spr_read_generic, &spr_write_generic,
1700
                 0x00000000);
1701
    /* XXX : not implemented */
1702
    spr_register(env, SPR_440_ITV0, "ITV0",
1703
                 SPR_NOACCESS, SPR_NOACCESS,
1704
                 &spr_read_generic, &spr_write_generic,
1705
                 0x00000000);
1706
    /* XXX : not implemented */
1707
    spr_register(env, SPR_440_ITV1, "ITV1",
1708
                 SPR_NOACCESS, SPR_NOACCESS,
1709
                 &spr_read_generic, &spr_write_generic,
1710
                 0x00000000);
1711
    /* XXX : not implemented */
1712
    spr_register(env, SPR_440_ITV2, "ITV2",
1713
                 SPR_NOACCESS, SPR_NOACCESS,
1714
                 &spr_read_generic, &spr_write_generic,
1715
                 0x00000000);
1716
    /* XXX : not implemented */
1717
    spr_register(env, SPR_440_ITV3, "ITV3",
1718
                 SPR_NOACCESS, SPR_NOACCESS,
1719
                 &spr_read_generic, &spr_write_generic,
1720
                 0x00000000);
1721
    /* XXX : not implemented */
1722
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1723
                 SPR_NOACCESS, SPR_NOACCESS,
1724
                 &spr_read_generic, &spr_write_generic,
1725
                 0x00000000);
1726
    /* Cache debug */
1727
    /* XXX : not implemented */
1728
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1729
                 SPR_NOACCESS, SPR_NOACCESS,
1730
                 &spr_read_generic, SPR_NOACCESS,
1731
                 0x00000000);
1732
    /* XXX : not implemented */
1733
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1734
                 SPR_NOACCESS, SPR_NOACCESS,
1735
                 &spr_read_generic, SPR_NOACCESS,
1736
                 0x00000000);
1737
    /* XXX : not implemented */
1738
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1739
                 SPR_NOACCESS, SPR_NOACCESS,
1740
                 &spr_read_generic, SPR_NOACCESS,
1741
                 0x00000000);
1742
    /* XXX : not implemented */
1743
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1744
                 SPR_NOACCESS, SPR_NOACCESS,
1745
                 &spr_read_generic, SPR_NOACCESS,
1746
                 0x00000000);
1747
    /* XXX : not implemented */
1748
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1749
                 SPR_NOACCESS, SPR_NOACCESS,
1750
                 &spr_read_generic, SPR_NOACCESS,
1751
                 0x00000000);
1752
    /* XXX : not implemented */
1753
    spr_register(env, SPR_440_DBDR, "DBDR",
1754
                 SPR_NOACCESS, SPR_NOACCESS,
1755
                 &spr_read_generic, &spr_write_generic,
1756
                 0x00000000);
1757
    /* Processor control */
1758
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1759
                 SPR_NOACCESS, SPR_NOACCESS,
1760
                 &spr_read_generic, &spr_write_generic,
1761
                 0x00000000);
1762
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1763
                 SPR_NOACCESS, SPR_NOACCESS,
1764
                 &spr_read_generic, SPR_NOACCESS,
1765
                 0x00000000);
1766
    /* Storage control */
1767
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1768
                 SPR_NOACCESS, SPR_NOACCESS,
1769
                 &spr_read_generic, &spr_write_generic,
1770
                 0x00000000);
1771
}
1772

    
1773
/* SPR shared between PowerPC 40x implementations */
1774
static void gen_spr_40x (CPUPPCState *env)
1775
{
1776
    /* Cache */
1777
    /* not emulated, as Qemu do not emulate caches */
1778
    spr_register(env, SPR_40x_DCCR, "DCCR",
1779
                 SPR_NOACCESS, SPR_NOACCESS,
1780
                 &spr_read_generic, &spr_write_generic,
1781
                 0x00000000);
1782
    /* not emulated, as Qemu do not emulate caches */
1783
    spr_register(env, SPR_40x_ICCR, "ICCR",
1784
                 SPR_NOACCESS, SPR_NOACCESS,
1785
                 &spr_read_generic, &spr_write_generic,
1786
                 0x00000000);
1787
    /* not emulated, as Qemu do not emulate caches */
1788
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1789
                 SPR_NOACCESS, SPR_NOACCESS,
1790
                 &spr_read_generic, SPR_NOACCESS,
1791
                 0x00000000);
1792
    /* Exception */
1793
    spr_register(env, SPR_40x_DEAR, "DEAR",
1794
                 SPR_NOACCESS, SPR_NOACCESS,
1795
                 &spr_read_generic, &spr_write_generic,
1796
                 0x00000000);
1797
    spr_register(env, SPR_40x_ESR, "ESR",
1798
                 SPR_NOACCESS, SPR_NOACCESS,
1799
                 &spr_read_generic, &spr_write_generic,
1800
                 0x00000000);
1801
    spr_register(env, SPR_40x_EVPR, "EVPR",
1802
                 SPR_NOACCESS, SPR_NOACCESS,
1803
                 &spr_read_generic, &spr_write_excp_prefix,
1804
                 0x00000000);
1805
    spr_register(env, SPR_40x_SRR2, "SRR2",
1806
                 &spr_read_generic, &spr_write_generic,
1807
                 &spr_read_generic, &spr_write_generic,
1808
                 0x00000000);
1809
    spr_register(env, SPR_40x_SRR3, "SRR3",
1810
                 &spr_read_generic, &spr_write_generic,
1811
                 &spr_read_generic, &spr_write_generic,
1812
                 0x00000000);
1813
    /* Timers */
1814
    spr_register(env, SPR_40x_PIT, "PIT",
1815
                 SPR_NOACCESS, SPR_NOACCESS,
1816
                 &spr_read_40x_pit, &spr_write_40x_pit,
1817
                 0x00000000);
1818
    spr_register(env, SPR_40x_TCR, "TCR",
1819
                 SPR_NOACCESS, SPR_NOACCESS,
1820
                 &spr_read_generic, &spr_write_booke_tcr,
1821
                 0x00000000);
1822
    spr_register(env, SPR_40x_TSR, "TSR",
1823
                 SPR_NOACCESS, SPR_NOACCESS,
1824
                 &spr_read_generic, &spr_write_booke_tsr,
1825
                 0x00000000);
1826
}
1827

    
1828
/* SPR specific to PowerPC 405 implementation */
1829
static void gen_spr_405 (CPUPPCState *env)
1830
{
1831
    /* MMU */
1832
    spr_register(env, SPR_40x_PID, "PID",
1833
                 SPR_NOACCESS, SPR_NOACCESS,
1834
                 &spr_read_generic, &spr_write_generic,
1835
                 0x00000000);
1836
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1837
                 SPR_NOACCESS, SPR_NOACCESS,
1838
                 &spr_read_generic, &spr_write_generic,
1839
                 0x00700000);
1840
    /* Debug interface */
1841
    /* XXX : not implemented */
1842
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1843
                 SPR_NOACCESS, SPR_NOACCESS,
1844
                 &spr_read_generic, &spr_write_40x_dbcr0,
1845
                 0x00000000);
1846
    /* XXX : not implemented */
1847
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1848
                 SPR_NOACCESS, SPR_NOACCESS,
1849
                 &spr_read_generic, &spr_write_generic,
1850
                 0x00000000);
1851
    /* XXX : not implemented */
1852
    spr_register(env, SPR_40x_DBSR, "DBSR",
1853
                 SPR_NOACCESS, SPR_NOACCESS,
1854
                 &spr_read_generic, &spr_write_clear,
1855
                 /* Last reset was system reset */
1856
                 0x00000300);
1857
    /* XXX : not implemented */
1858
    spr_register(env, SPR_40x_DAC1, "DAC1",
1859
                 SPR_NOACCESS, SPR_NOACCESS,
1860
                 &spr_read_generic, &spr_write_generic,
1861
                 0x00000000);
1862
    spr_register(env, SPR_40x_DAC2, "DAC2",
1863
                 SPR_NOACCESS, SPR_NOACCESS,
1864
                 &spr_read_generic, &spr_write_generic,
1865
                 0x00000000);
1866
    /* XXX : not implemented */
1867
    spr_register(env, SPR_405_DVC1, "DVC1",
1868
                 SPR_NOACCESS, SPR_NOACCESS,
1869
                 &spr_read_generic, &spr_write_generic,
1870
                 0x00000000);
1871
    /* XXX : not implemented */
1872
    spr_register(env, SPR_405_DVC2, "DVC2",
1873
                 SPR_NOACCESS, SPR_NOACCESS,
1874
                 &spr_read_generic, &spr_write_generic,
1875
                 0x00000000);
1876
    /* XXX : not implemented */
1877
    spr_register(env, SPR_40x_IAC1, "IAC1",
1878
                 SPR_NOACCESS, SPR_NOACCESS,
1879
                 &spr_read_generic, &spr_write_generic,
1880
                 0x00000000);
1881
    spr_register(env, SPR_40x_IAC2, "IAC2",
1882
                 SPR_NOACCESS, SPR_NOACCESS,
1883
                 &spr_read_generic, &spr_write_generic,
1884
                 0x00000000);
1885
    /* XXX : not implemented */
1886
    spr_register(env, SPR_405_IAC3, "IAC3",
1887
                 SPR_NOACCESS, SPR_NOACCESS,
1888
                 &spr_read_generic, &spr_write_generic,
1889
                 0x00000000);
1890
    /* XXX : not implemented */
1891
    spr_register(env, SPR_405_IAC4, "IAC4",
1892
                 SPR_NOACCESS, SPR_NOACCESS,
1893
                 &spr_read_generic, &spr_write_generic,
1894
                 0x00000000);
1895
    /* Storage control */
1896
    /* XXX: TODO: not implemented */
1897
    spr_register(env, SPR_405_SLER, "SLER",
1898
                 SPR_NOACCESS, SPR_NOACCESS,
1899
                 &spr_read_generic, &spr_write_40x_sler,
1900
                 0x00000000);
1901
    spr_register(env, SPR_40x_ZPR, "ZPR",
1902
                 SPR_NOACCESS, SPR_NOACCESS,
1903
                 &spr_read_generic, &spr_write_generic,
1904
                 0x00000000);
1905
    /* XXX : not implemented */
1906
    spr_register(env, SPR_405_SU0R, "SU0R",
1907
                 SPR_NOACCESS, SPR_NOACCESS,
1908
                 &spr_read_generic, &spr_write_generic,
1909
                 0x00000000);
1910
    /* SPRG */
1911
    spr_register(env, SPR_USPRG0, "USPRG0",
1912
                 &spr_read_ureg, SPR_NOACCESS,
1913
                 &spr_read_ureg, SPR_NOACCESS,
1914
                 0x00000000);
1915
    spr_register(env, SPR_SPRG4, "SPRG4",
1916
                 SPR_NOACCESS, SPR_NOACCESS,
1917
                 &spr_read_generic, &spr_write_generic,
1918
                 0x00000000);
1919
    spr_register(env, SPR_USPRG4, "USPRG4",
1920
                 &spr_read_ureg, SPR_NOACCESS,
1921
                 &spr_read_ureg, SPR_NOACCESS,
1922
                 0x00000000);
1923
    spr_register(env, SPR_SPRG5, "SPRG5",
1924
                 SPR_NOACCESS, SPR_NOACCESS,
1925
                 spr_read_generic, &spr_write_generic,
1926
                 0x00000000);
1927
    spr_register(env, SPR_USPRG5, "USPRG5",
1928
                 &spr_read_ureg, SPR_NOACCESS,
1929
                 &spr_read_ureg, SPR_NOACCESS,
1930
                 0x00000000);
1931
    spr_register(env, SPR_SPRG6, "SPRG6",
1932
                 SPR_NOACCESS, SPR_NOACCESS,
1933
                 spr_read_generic, &spr_write_generic,
1934
                 0x00000000);
1935
    spr_register(env, SPR_USPRG6, "USPRG6",
1936
                 &spr_read_ureg, SPR_NOACCESS,
1937
                 &spr_read_ureg, SPR_NOACCESS,
1938
                 0x00000000);
1939
    spr_register(env, SPR_SPRG7, "SPRG7",
1940
                 SPR_NOACCESS, SPR_NOACCESS,
1941
                 spr_read_generic, &spr_write_generic,
1942
                 0x00000000);
1943
    spr_register(env, SPR_USPRG7, "USPRG7",
1944
                 &spr_read_ureg, SPR_NOACCESS,
1945
                 &spr_read_ureg, SPR_NOACCESS,
1946
                 0x00000000);
1947
}
1948

    
1949
/* SPR shared between PowerPC 401 & 403 implementations */
1950
static void gen_spr_401_403 (CPUPPCState *env)
1951
{
1952
    /* Time base */
1953
    spr_register(env, SPR_403_VTBL,  "TBL",
1954
                 &spr_read_tbl, SPR_NOACCESS,
1955
                 &spr_read_tbl, SPR_NOACCESS,
1956
                 0x00000000);
1957
    spr_register(env, SPR_403_TBL,   "TBL",
1958
                 SPR_NOACCESS, SPR_NOACCESS,
1959
                 SPR_NOACCESS, &spr_write_tbl,
1960
                 0x00000000);
1961
    spr_register(env, SPR_403_VTBU,  "TBU",
1962
                 &spr_read_tbu, SPR_NOACCESS,
1963
                 &spr_read_tbu, SPR_NOACCESS,
1964
                 0x00000000);
1965
    spr_register(env, SPR_403_TBU,   "TBU",
1966
                 SPR_NOACCESS, SPR_NOACCESS,
1967
                 SPR_NOACCESS, &spr_write_tbu,
1968
                 0x00000000);
1969
    /* Debug */
1970
    /* not emulated, as Qemu do not emulate caches */
1971
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1972
                 SPR_NOACCESS, SPR_NOACCESS,
1973
                 &spr_read_generic, &spr_write_generic,
1974
                 0x00000000);
1975
}
1976

    
1977
/* SPR specific to PowerPC 401 implementation */
1978
static void gen_spr_401 (CPUPPCState *env)
1979
{
1980
    /* Debug interface */
1981
    /* XXX : not implemented */
1982
    spr_register(env, SPR_40x_DBCR0, "DBCR",
1983
                 SPR_NOACCESS, SPR_NOACCESS,
1984
                 &spr_read_generic, &spr_write_40x_dbcr0,
1985
                 0x00000000);
1986
    /* XXX : not implemented */
1987
    spr_register(env, SPR_40x_DBSR, "DBSR",
1988
                 SPR_NOACCESS, SPR_NOACCESS,
1989
                 &spr_read_generic, &spr_write_clear,
1990
                 /* Last reset was system reset */
1991
                 0x00000300);
1992
    /* XXX : not implemented */
1993
    spr_register(env, SPR_40x_DAC1, "DAC",
1994
                 SPR_NOACCESS, SPR_NOACCESS,
1995
                 &spr_read_generic, &spr_write_generic,
1996
                 0x00000000);
1997
    /* XXX : not implemented */
1998
    spr_register(env, SPR_40x_IAC1, "IAC",
1999
                 SPR_NOACCESS, SPR_NOACCESS,
2000
                 &spr_read_generic, &spr_write_generic,
2001
                 0x00000000);
2002
    /* Storage control */
2003
    /* XXX: TODO: not implemented */
2004
    spr_register(env, SPR_405_SLER, "SLER",
2005
                 SPR_NOACCESS, SPR_NOACCESS,
2006
                 &spr_read_generic, &spr_write_40x_sler,
2007
                 0x00000000);
2008
    /* not emulated, as Qemu never does speculative access */
2009
    spr_register(env, SPR_40x_SGR, "SGR",
2010
                 SPR_NOACCESS, SPR_NOACCESS,
2011
                 &spr_read_generic, &spr_write_generic,
2012
                 0xFFFFFFFF);
2013
    /* not emulated, as Qemu do not emulate caches */
2014
    spr_register(env, SPR_40x_DCWR, "DCWR",
2015
                 SPR_NOACCESS, SPR_NOACCESS,
2016
                 &spr_read_generic, &spr_write_generic,
2017
                 0x00000000);
2018
}
2019

    
2020
static void gen_spr_401x2 (CPUPPCState *env)
2021
{
2022
    gen_spr_401(env);
2023
    spr_register(env, SPR_40x_PID, "PID",
2024
                 SPR_NOACCESS, SPR_NOACCESS,
2025
                 &spr_read_generic, &spr_write_generic,
2026
                 0x00000000);
2027
    spr_register(env, SPR_40x_ZPR, "ZPR",
2028
                 SPR_NOACCESS, SPR_NOACCESS,
2029
                 &spr_read_generic, &spr_write_generic,
2030
                 0x00000000);
2031
}
2032

    
2033
/* SPR specific to PowerPC 403 implementation */
2034
static void gen_spr_403 (CPUPPCState *env)
2035
{
2036
    /* Debug interface */
2037
    /* XXX : not implemented */
2038
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2039
                 SPR_NOACCESS, SPR_NOACCESS,
2040
                 &spr_read_generic, &spr_write_40x_dbcr0,
2041
                 0x00000000);
2042
    /* XXX : not implemented */
2043
    spr_register(env, SPR_40x_DBSR, "DBSR",
2044
                 SPR_NOACCESS, SPR_NOACCESS,
2045
                 &spr_read_generic, &spr_write_clear,
2046
                 /* Last reset was system reset */
2047
                 0x00000300);
2048
    /* XXX : not implemented */
2049
    spr_register(env, SPR_40x_DAC1, "DAC1",
2050
                 SPR_NOACCESS, SPR_NOACCESS,
2051
                 &spr_read_generic, &spr_write_generic,
2052
                 0x00000000);
2053
    /* XXX : not implemented */
2054
    spr_register(env, SPR_40x_DAC2, "DAC2",
2055
                 SPR_NOACCESS, SPR_NOACCESS,
2056
                 &spr_read_generic, &spr_write_generic,
2057
                 0x00000000);
2058
    /* XXX : not implemented */
2059
    spr_register(env, SPR_40x_IAC1, "IAC1",
2060
                 SPR_NOACCESS, SPR_NOACCESS,
2061
                 &spr_read_generic, &spr_write_generic,
2062
                 0x00000000);
2063
    /* XXX : not implemented */
2064
    spr_register(env, SPR_40x_IAC2, "IAC2",
2065
                 SPR_NOACCESS, SPR_NOACCESS,
2066
                 &spr_read_generic, &spr_write_generic,
2067
                 0x00000000);
2068
}
2069

    
2070
static void gen_spr_403_real (CPUPPCState *env)
2071
{
2072
    spr_register(env, SPR_403_PBL1,  "PBL1",
2073
                 SPR_NOACCESS, SPR_NOACCESS,
2074
                 &spr_read_403_pbr, &spr_write_403_pbr,
2075
                 0x00000000);
2076
    spr_register(env, SPR_403_PBU1,  "PBU1",
2077
                 SPR_NOACCESS, SPR_NOACCESS,
2078
                 &spr_read_403_pbr, &spr_write_403_pbr,
2079
                 0x00000000);
2080
    spr_register(env, SPR_403_PBL2,  "PBL2",
2081
                 SPR_NOACCESS, SPR_NOACCESS,
2082
                 &spr_read_403_pbr, &spr_write_403_pbr,
2083
                 0x00000000);
2084
    spr_register(env, SPR_403_PBU2,  "PBU2",
2085
                 SPR_NOACCESS, SPR_NOACCESS,
2086
                 &spr_read_403_pbr, &spr_write_403_pbr,
2087
                 0x00000000);
2088
}
2089

    
2090
static void gen_spr_403_mmu (CPUPPCState *env)
2091
{
2092
    /* MMU */
2093
    spr_register(env, SPR_40x_PID, "PID",
2094
                 SPR_NOACCESS, SPR_NOACCESS,
2095
                 &spr_read_generic, &spr_write_generic,
2096
                 0x00000000);
2097
    spr_register(env, SPR_40x_ZPR, "ZPR",
2098
                 SPR_NOACCESS, SPR_NOACCESS,
2099
                 &spr_read_generic, &spr_write_generic,
2100
                 0x00000000);
2101
}
2102

    
2103
/* SPR specific to PowerPC compression coprocessor extension */
2104
static void gen_spr_compress (CPUPPCState *env)
2105
{
2106
    /* XXX : not implemented */
2107
    spr_register(env, SPR_401_SKR, "SKR",
2108
                 SPR_NOACCESS, SPR_NOACCESS,
2109
                 &spr_read_generic, &spr_write_generic,
2110
                 0x00000000);
2111
}
2112

    
2113
#if defined (TARGET_PPC64)
2114
/* SPR specific to PowerPC 620 */
2115
static void gen_spr_620 (CPUPPCState *env)
2116
{
2117
    /* XXX : not implemented */
2118
    spr_register(env, SPR_620_PMR0, "PMR0",
2119
                 SPR_NOACCESS, SPR_NOACCESS,
2120
                 &spr_read_generic, &spr_write_generic,
2121
                 0x00000000);
2122
    /* XXX : not implemented */
2123
    spr_register(env, SPR_620_PMR1, "PMR1",
2124
                 SPR_NOACCESS, SPR_NOACCESS,
2125
                 &spr_read_generic, &spr_write_generic,
2126
                 0x00000000);
2127
    /* XXX : not implemented */
2128
    spr_register(env, SPR_620_PMR2, "PMR2",
2129
                 SPR_NOACCESS, SPR_NOACCESS,
2130
                 &spr_read_generic, &spr_write_generic,
2131
                 0x00000000);
2132
    /* XXX : not implemented */
2133
    spr_register(env, SPR_620_PMR3, "PMR3",
2134
                 SPR_NOACCESS, SPR_NOACCESS,
2135
                 &spr_read_generic, &spr_write_generic,
2136
                 0x00000000);
2137
    /* XXX : not implemented */
2138
    spr_register(env, SPR_620_PMR4, "PMR4",
2139
                 SPR_NOACCESS, SPR_NOACCESS,
2140
                 &spr_read_generic, &spr_write_generic,
2141
                 0x00000000);
2142
    /* XXX : not implemented */
2143
    spr_register(env, SPR_620_PMR5, "PMR5",
2144
                 SPR_NOACCESS, SPR_NOACCESS,
2145
                 &spr_read_generic, &spr_write_generic,
2146
                 0x00000000);
2147
    /* XXX : not implemented */
2148
    spr_register(env, SPR_620_PMR6, "PMR6",
2149
                 SPR_NOACCESS, SPR_NOACCESS,
2150
                 &spr_read_generic, &spr_write_generic,
2151
                 0x00000000);
2152
    /* XXX : not implemented */
2153
    spr_register(env, SPR_620_PMR7, "PMR7",
2154
                 SPR_NOACCESS, SPR_NOACCESS,
2155
                 &spr_read_generic, &spr_write_generic,
2156
                 0x00000000);
2157
    /* XXX : not implemented */
2158
    spr_register(env, SPR_620_PMR8, "PMR8",
2159
                 SPR_NOACCESS, SPR_NOACCESS,
2160
                 &spr_read_generic, &spr_write_generic,
2161
                 0x00000000);
2162
    /* XXX : not implemented */
2163
    spr_register(env, SPR_620_PMR9, "PMR9",
2164
                 SPR_NOACCESS, SPR_NOACCESS,
2165
                 &spr_read_generic, &spr_write_generic,
2166
                 0x00000000);
2167
    /* XXX : not implemented */
2168
    spr_register(env, SPR_620_PMRA, "PMR10",
2169
                 SPR_NOACCESS, SPR_NOACCESS,
2170
                 &spr_read_generic, &spr_write_generic,
2171
                 0x00000000);
2172
    /* XXX : not implemented */
2173
    spr_register(env, SPR_620_PMRB, "PMR11",
2174
                 SPR_NOACCESS, SPR_NOACCESS,
2175
                 &spr_read_generic, &spr_write_generic,
2176
                 0x00000000);
2177
    /* XXX : not implemented */
2178
    spr_register(env, SPR_620_PMRC, "PMR12",
2179
                 SPR_NOACCESS, SPR_NOACCESS,
2180
                 &spr_read_generic, &spr_write_generic,
2181
                 0x00000000);
2182
    /* XXX : not implemented */
2183
    spr_register(env, SPR_620_PMRD, "PMR13",
2184
                 SPR_NOACCESS, SPR_NOACCESS,
2185
                 &spr_read_generic, &spr_write_generic,
2186
                 0x00000000);
2187
    /* XXX : not implemented */
2188
    spr_register(env, SPR_620_PMRE, "PMR14",
2189
                 SPR_NOACCESS, SPR_NOACCESS,
2190
                 &spr_read_generic, &spr_write_generic,
2191
                 0x00000000);
2192
    /* XXX : not implemented */
2193
    spr_register(env, SPR_620_PMRF, "PMR15",
2194
                 SPR_NOACCESS, SPR_NOACCESS,
2195
                 &spr_read_generic, &spr_write_generic,
2196
                 0x00000000);
2197
    /* XXX : not implemented */
2198
    spr_register(env, SPR_620_HID8, "HID8",
2199
                 SPR_NOACCESS, SPR_NOACCESS,
2200
                 &spr_read_generic, &spr_write_generic,
2201
                 0x00000000);
2202
    /* XXX : not implemented */
2203
    spr_register(env, SPR_620_HID9, "HID9",
2204
                 SPR_NOACCESS, SPR_NOACCESS,
2205
                 &spr_read_generic, &spr_write_generic,
2206
                 0x00000000);
2207
}
2208
#endif /* defined (TARGET_PPC64) */
2209

    
2210
// XXX: TODO
2211
/*
2212
 * AMR     => SPR 29 (Power 2.04)
2213
 * CTRL    => SPR 136 (Power 2.04)
2214
 * CTRL    => SPR 152 (Power 2.04)
2215
 * SCOMC   => SPR 276 (64 bits ?)
2216
 * SCOMD   => SPR 277 (64 bits ?)
2217
 * TBU40   => SPR 286 (Power 2.04 hypv)
2218
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2219
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2220
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2221
 * HDAR    => SPR 307 (Power 2.04 hypv)
2222
 * PURR    => SPR 309 (Power 2.04 hypv)
2223
 * HDEC    => SPR 310 (Power 2.04 hypv)
2224
 * HIOR    => SPR 311 (hypv)
2225
 * RMOR    => SPR 312 (970)
2226
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2227
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2228
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2229
 * LPCR    => SPR 316 (970)
2230
 * LPIDR   => SPR 317 (970)
2231
 * SPEFSCR => SPR 512 (Power 2.04 emb)
2232
 * EPR     => SPR 702 (Power 2.04 emb)
2233
 * perf    => 768-783 (Power 2.04)
2234
 * perf    => 784-799 (Power 2.04)
2235
 * PPR     => SPR 896 (Power 2.04)
2236
 * EPLC    => SPR 947 (Power 2.04 emb)
2237
 * EPSC    => SPR 948 (Power 2.04 emb)
2238
 * DABRX   => 1015    (Power 2.04 hypv)
2239
 * FPECR   => SPR 1022 (?)
2240
 * ... and more (thermal management, performance counters, ...)
2241
 */
2242

    
2243
/*****************************************************************************/
2244
/* Exception vectors models                                                  */
2245
static void init_excp_4xx_real (CPUPPCState *env)
2246
{
2247
#if !defined(CONFIG_USER_ONLY)
2248
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2249
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2250
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2251
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2252
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2253
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2254
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2255
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2256
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2257
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2258
    env->excp_prefix = 0x00000000UL;
2259
    env->ivor_mask = 0x0000FFF0UL;
2260
    env->ivpr_mask = 0xFFFF0000UL;
2261
    /* Hardware reset vector */
2262
    env->hreset_vector = 0xFFFFFFFCUL;
2263
#endif
2264
}
2265

    
2266
static void init_excp_4xx_softmmu (CPUPPCState *env)
2267
{
2268
#if !defined(CONFIG_USER_ONLY)
2269
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2270
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2271
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2272
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2273
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2274
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2275
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2276
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2277
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2278
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2279
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2280
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2281
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2282
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2283
    env->excp_prefix = 0x00000000UL;
2284
    env->ivor_mask = 0x0000FFF0UL;
2285
    env->ivpr_mask = 0xFFFF0000UL;
2286
    /* Hardware reset vector */
2287
    env->hreset_vector = 0xFFFFFFFCUL;
2288
#endif
2289
}
2290

    
2291
static void init_excp_BookE (CPUPPCState *env)
2292
{
2293
#if !defined(CONFIG_USER_ONLY)
2294
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2295
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2296
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2297
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2298
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2299
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2300
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2301
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2302
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2303
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2304
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2305
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2306
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2307
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2308
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2309
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2310
    env->excp_prefix = 0x00000000UL;
2311
    env->ivor_mask = 0x0000FFE0UL;
2312
    env->ivpr_mask = 0xFFFF0000UL;
2313
    /* Hardware reset vector */
2314
    env->hreset_vector = 0xFFFFFFFCUL;
2315
#endif
2316
}
2317

    
2318
static void init_excp_601 (CPUPPCState *env)
2319
{
2320
#if !defined(CONFIG_USER_ONLY)
2321
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2322
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2323
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2324
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2325
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2326
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2327
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2328
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2329
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2330
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2331
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2332
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2333
    env->excp_prefix = 0xFFF00000UL;
2334
    /* Hardware reset vector */
2335
    env->hreset_vector = 0x00000100UL;
2336
#endif
2337
}
2338

    
2339
static void init_excp_602 (CPUPPCState *env)
2340
{
2341
#if !defined(CONFIG_USER_ONLY)
2342
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2343
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2344
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2345
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2346
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2347
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2348
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2349
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2350
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2351
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2352
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2353
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2354
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2355
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2356
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2357
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2358
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2359
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2360
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2361
    env->excp_prefix = 0xFFF00000UL;
2362
    /* Hardware reset vector */
2363
    env->hreset_vector = 0xFFFFFFFCUL;
2364
#endif
2365
}
2366

    
2367
static void init_excp_603 (CPUPPCState *env)
2368
{
2369
#if !defined(CONFIG_USER_ONLY)
2370
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2371
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2372
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2373
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2374
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2375
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2376
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2377
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2378
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2379
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2380
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2381
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2382
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2383
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2384
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2385
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2386
    env->excp_prefix = 0x00000000UL;
2387
    /* Hardware reset vector */
2388
    env->hreset_vector = 0xFFFFFFFCUL;
2389
#endif
2390
}
2391

    
2392
static void init_excp_G2 (CPUPPCState *env)
2393
{
2394
#if !defined(CONFIG_USER_ONLY)
2395
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2396
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2397
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2398
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2399
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2400
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2401
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2402
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2403
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2404
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2405
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2406
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2407
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2408
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2409
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2410
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2411
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2412
    env->excp_prefix = 0x00000000UL;
2413
    /* Hardware reset vector */
2414
    env->hreset_vector = 0xFFFFFFFCUL;
2415
#endif
2416
}
2417

    
2418
static void init_excp_604 (CPUPPCState *env)
2419
{
2420
#if !defined(CONFIG_USER_ONLY)
2421
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2422
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2423
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2424
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2425
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2426
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2427
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2428
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2429
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2430
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2431
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2432
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2433
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2434
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2435
    env->excp_prefix = 0x00000000UL;
2436
    /* Hardware reset vector */
2437
    env->hreset_vector = 0xFFFFFFFCUL;
2438
#endif
2439
}
2440

    
2441
#if defined(TARGET_PPC64)
2442
static void init_excp_620 (CPUPPCState *env)
2443
{
2444
#if !defined(CONFIG_USER_ONLY)
2445
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2446
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2447
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2448
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2449
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2450
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2451
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2452
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2453
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2454
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2455
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2456
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2457
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2458
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2459
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2460
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2461
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2462
    env->excp_prefix = 0xFFF00000UL;
2463
    /* Hardware reset vector */
2464
    env->hreset_vector = 0x0000000000000100ULL;
2465
#endif
2466
}
2467
#endif /* defined(TARGET_PPC64) */
2468

    
2469
static void init_excp_7x0 (CPUPPCState *env)
2470
{
2471
#if !defined(CONFIG_USER_ONLY)
2472
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2473
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2474
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2475
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2476
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2477
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2478
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2479
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2480
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2481
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2482
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2483
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2484
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2485
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2486
    env->excp_prefix = 0x00000000UL;
2487
    /* Hardware reset vector */
2488
    env->hreset_vector = 0xFFFFFFFCUL;
2489
#endif
2490
}
2491

    
2492
static void init_excp_750FX (CPUPPCState *env)
2493
{
2494
#if !defined(CONFIG_USER_ONLY)
2495
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2496
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2497
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2498
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2499
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2500
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2501
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2502
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2503
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2504
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2505
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2506
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2507
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2508
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2509
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2510
    env->excp_prefix = 0x00000000UL;
2511
    /* Hardware reset vector */
2512
    env->hreset_vector = 0xFFFFFFFCUL;
2513
#endif
2514
}
2515

    
2516
/* XXX: Check if this is correct */
2517
static void init_excp_7x5 (CPUPPCState *env)
2518
{
2519
#if !defined(CONFIG_USER_ONLY)
2520
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2521
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2522
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2523
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2524
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2525
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2526
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2527
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2528
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2529
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2530
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2531
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2532
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2533
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2534
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2535
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2536
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2537
    env->excp_prefix = 0x00000000UL;
2538
    /* Hardware reset vector */
2539
    env->hreset_vector = 0xFFFFFFFCUL;
2540
#endif
2541
}
2542

    
2543
static void init_excp_7400 (CPUPPCState *env)
2544
{
2545
#if !defined(CONFIG_USER_ONLY)
2546
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2547
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2548
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2549
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2550
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2551
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2552
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2553
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2554
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2555
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2556
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2557
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2558
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2559
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2560
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2561
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2562
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2563
    env->excp_prefix = 0x00000000UL;
2564
    /* Hardware reset vector */
2565
    env->hreset_vector = 0xFFFFFFFCUL;
2566
#endif
2567
}
2568

    
2569
static void init_excp_7450 (CPUPPCState *env)
2570
{
2571
#if !defined(CONFIG_USER_ONLY)
2572
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2573
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2574
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2575
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2576
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2577
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2578
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2579
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2580
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2581
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2582
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2583
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2584
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2585
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2586
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2587
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2588
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2589
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2590
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2591
    env->excp_prefix = 0x00000000UL;
2592
    /* Hardware reset vector */
2593
    env->hreset_vector = 0xFFFFFFFCUL;
2594
#endif
2595
}
2596

    
2597
#if defined (TARGET_PPC64)
2598
static void init_excp_970 (CPUPPCState *env)
2599
{
2600
#if !defined(CONFIG_USER_ONLY)
2601
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2602
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2603
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2604
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2605
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2606
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2607
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2608
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2609
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2610
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2611
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2612
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2613
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2614
#endif
2615
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2616
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2617
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2618
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2619
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2620
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2621
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2622
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2623
    env->excp_prefix   = 0x00000000FFF00000ULL;
2624
    /* Hardware reset vector */
2625
    env->hreset_vector = 0x0000000000000100ULL;
2626
#endif
2627
}
2628
#endif
2629

    
2630
/*****************************************************************************/
2631
/* Power management enable checks                                            */
2632
static int check_pow_none (CPUPPCState *env)
2633
{
2634
    return 0;
2635
}
2636

    
2637
static int check_pow_nocheck (CPUPPCState *env)
2638
{
2639
    return 1;
2640
}
2641

    
2642
static int check_pow_hid0 (CPUPPCState *env)
2643
{
2644
    if (env->spr[SPR_HID0] & 0x00E00000)
2645
        return 1;
2646

    
2647
    return 0;
2648
}
2649

    
2650
/*****************************************************************************/
2651
/* PowerPC implementations definitions                                       */
2652

    
2653
/* PowerPC 40x instruction set                                               */
2654
#define POWERPC_INSNS_EMB    (PPC_INSNS_BASE | PPC_EMB_COMMON |               \
2655
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
2656

    
2657
/* PowerPC 401                                                               */
2658
#define POWERPC_INSNS_401    (POWERPC_INSNS_EMB |                             \
2659
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2660
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2661
#define POWERPC_MSRM_401     (0x00000000000FD201ULL)
2662
#define POWERPC_MMU_401      (POWERPC_MMU_REAL_4xx)
2663
#define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
2664
#define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
2665
#define POWERPC_BFDM_401     (bfd_mach_ppc_403)
2666
#define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2667
#define check_pow_401        check_pow_nocheck
2668

    
2669
static void init_proc_401 (CPUPPCState *env)
2670
{
2671
    gen_spr_40x(env);
2672
    gen_spr_401_403(env);
2673
    gen_spr_401(env);
2674
    init_excp_4xx_real(env);
2675
    env->dcache_line_size = 32;
2676
    env->icache_line_size = 32;
2677
    /* Allocate hardware IRQ controller */
2678
    ppc40x_irq_init(env);
2679
}
2680

    
2681
/* PowerPC 401x2                                                             */
2682
#define POWERPC_INSNS_401x2  (POWERPC_INSNS_EMB |                             \
2683
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2684
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2685
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2686
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2687
#define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
2688
#define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
2689
#define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
2690
#define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
2691
#define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
2692
#define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2693
#define check_pow_401x2      check_pow_nocheck
2694

    
2695
static void init_proc_401x2 (CPUPPCState *env)
2696
{
2697
    gen_spr_40x(env);
2698
    gen_spr_401_403(env);
2699
    gen_spr_401x2(env);
2700
    gen_spr_compress(env);
2701
    /* Memory management */
2702
#if !defined(CONFIG_USER_ONLY)
2703
    env->nb_tlb = 64;
2704
    env->nb_ways = 1;
2705
    env->id_tlbs = 0;
2706
#endif
2707
    init_excp_4xx_softmmu(env);
2708
    env->dcache_line_size = 32;
2709
    env->icache_line_size = 32;
2710
    /* Allocate hardware IRQ controller */
2711
    ppc40x_irq_init(env);
2712
}
2713

    
2714
/* PowerPC 401x3                                                             */
2715
#define POWERPC_INSNS_401x3  (POWERPC_INSNS_EMB |                             \
2716
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2717
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2718
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2719
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2720
#define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
2721
#define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
2722
#define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
2723
#define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
2724
#define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
2725
#define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2726
#define check_pow_401x3      check_pow_nocheck
2727

    
2728
__attribute__ (( unused ))
2729
static void init_proc_401x3 (CPUPPCState *env)
2730
{
2731
    gen_spr_40x(env);
2732
    gen_spr_401_403(env);
2733
    gen_spr_401(env);
2734
    gen_spr_401x2(env);
2735
    gen_spr_compress(env);
2736
    init_excp_4xx_softmmu(env);
2737
    env->dcache_line_size = 32;
2738
    env->icache_line_size = 32;
2739
    /* Allocate hardware IRQ controller */
2740
    ppc40x_irq_init(env);
2741
}
2742

    
2743
/* IOP480                                                                    */
2744
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB |                             \
2745
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2746
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2747
                              PPC_CACHE_DCBA |                                \
2748
                              PPC_4xx_COMMON | PPC_40x_EXCP |  PPC_40x_ICBT)
2749
#define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
2750
#define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
2751
#define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
2752
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2753
#define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
2754
#define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2755
#define check_pow_IOP480     check_pow_nocheck
2756

    
2757
static void init_proc_IOP480 (CPUPPCState *env)
2758
{
2759
    gen_spr_40x(env);
2760
    gen_spr_401_403(env);
2761
    gen_spr_401x2(env);
2762
    gen_spr_compress(env);
2763
    /* Memory management */
2764
#if !defined(CONFIG_USER_ONLY)
2765
    env->nb_tlb = 64;
2766
    env->nb_ways = 1;
2767
    env->id_tlbs = 0;
2768
#endif
2769
    init_excp_4xx_softmmu(env);
2770
    env->dcache_line_size = 32;
2771
    env->icache_line_size = 32;
2772
    /* Allocate hardware IRQ controller */
2773
    ppc40x_irq_init(env);
2774
}
2775

    
2776
/* PowerPC 403                                                               */
2777
#define POWERPC_INSNS_403    (POWERPC_INSNS_EMB |                             \
2778
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2779
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2780
#define POWERPC_MSRM_403     (0x000000000007D00DULL)
2781
#define POWERPC_MMU_403      (POWERPC_MMU_REAL_4xx)
2782
#define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
2783
#define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
2784
#define POWERPC_BFDM_403     (bfd_mach_ppc_403)
2785
#define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2786
#define check_pow_403        check_pow_nocheck
2787

    
2788
static void init_proc_403 (CPUPPCState *env)
2789
{
2790
    gen_spr_40x(env);
2791
    gen_spr_401_403(env);
2792
    gen_spr_403(env);
2793
    gen_spr_403_real(env);
2794
    init_excp_4xx_real(env);
2795
    env->dcache_line_size = 32;
2796
    env->icache_line_size = 32;
2797
    /* Allocate hardware IRQ controller */
2798
    ppc40x_irq_init(env);
2799
#if !defined(CONFIG_USER_ONLY)
2800
    /* Hardware reset vector */
2801
    env->hreset_vector = 0xFFFFFFFCUL;
2802
#endif
2803
}
2804

    
2805
/* PowerPC 403 GCX                                                           */
2806
#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB |                             \
2807
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2808
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2809
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2810
#define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
2811
#define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
2812
#define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
2813
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2814
#define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
2815
#define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2816
#define check_pow_403GCX     check_pow_nocheck
2817

    
2818
static void init_proc_403GCX (CPUPPCState *env)
2819
{
2820
    gen_spr_40x(env);
2821
    gen_spr_401_403(env);
2822
    gen_spr_403(env);
2823
    gen_spr_403_real(env);
2824
    gen_spr_403_mmu(env);
2825
    /* Bus access control */
2826
    /* not emulated, as Qemu never does speculative access */
2827
    spr_register(env, SPR_40x_SGR, "SGR",
2828
                 SPR_NOACCESS, SPR_NOACCESS,
2829
                 &spr_read_generic, &spr_write_generic,
2830
                 0xFFFFFFFF);
2831
    /* not emulated, as Qemu do not emulate caches */
2832
    spr_register(env, SPR_40x_DCWR, "DCWR",
2833
                 SPR_NOACCESS, SPR_NOACCESS,
2834
                 &spr_read_generic, &spr_write_generic,
2835
                 0x00000000);
2836
    /* Memory management */
2837
#if !defined(CONFIG_USER_ONLY)
2838
    env->nb_tlb = 64;
2839
    env->nb_ways = 1;
2840
    env->id_tlbs = 0;
2841
#endif
2842
    init_excp_4xx_softmmu(env);
2843
    env->dcache_line_size = 32;
2844
    env->icache_line_size = 32;
2845
    /* Allocate hardware IRQ controller */
2846
    ppc40x_irq_init(env);
2847
}
2848

    
2849
/* PowerPC 405                                                               */
2850
#define POWERPC_INSNS_405    (POWERPC_INSNS_EMB | PPC_MFTB |                  \
2851
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2852
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2853
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT |  \
2854
                              PPC_405_MAC)
2855
#define POWERPC_MSRM_405     (0x000000000006E630ULL)
2856
#define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
2857
#define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
2858
#define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
2859
#define POWERPC_BFDM_405     (bfd_mach_ppc_403)
2860
#define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2861
                              POWERPC_FLAG_DE)
2862
#define check_pow_405        check_pow_nocheck
2863

    
2864
static void init_proc_405 (CPUPPCState *env)
2865
{
2866
    /* Time base */
2867
    gen_tbl(env);
2868
    gen_spr_40x(env);
2869
    gen_spr_405(env);
2870
    /* Bus access control */
2871
    /* not emulated, as Qemu never does speculative access */
2872
    spr_register(env, SPR_40x_SGR, "SGR",
2873
                 SPR_NOACCESS, SPR_NOACCESS,
2874
                 &spr_read_generic, &spr_write_generic,
2875
                 0xFFFFFFFF);
2876
    /* not emulated, as Qemu do not emulate caches */
2877
    spr_register(env, SPR_40x_DCWR, "DCWR",
2878
                 SPR_NOACCESS, SPR_NOACCESS,
2879
                 &spr_read_generic, &spr_write_generic,
2880
                 0x00000000);
2881
    /* Memory management */
2882
#if !defined(CONFIG_USER_ONLY)
2883
    env->nb_tlb = 64;
2884
    env->nb_ways = 1;
2885
    env->id_tlbs = 0;
2886
#endif
2887
    init_excp_4xx_softmmu(env);
2888
    env->dcache_line_size = 32;
2889
    env->icache_line_size = 32;
2890
    /* Allocate hardware IRQ controller */
2891
    ppc40x_irq_init(env);
2892
}
2893

    
2894
/* PowerPC 440 EP                                                            */
2895
#define POWERPC_INSNS_440EP  (POWERPC_INSNS_EMB |                             \
2896
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2897
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2898
                              PPC_440_SPEC | PPC_RFMCI)
2899
#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
2900
#define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
2901
#define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
2902
#define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
2903
#define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
2904
#define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2905
                              POWERPC_FLAG_DE)
2906
#define check_pow_440EP      check_pow_nocheck
2907

    
2908
static void init_proc_440EP (CPUPPCState *env)
2909
{
2910
    /* Time base */
2911
    gen_tbl(env);
2912
    gen_spr_BookE(env);
2913
    gen_spr_440(env);
2914
    /* XXX : not implemented */
2915
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2916
                 SPR_NOACCESS, SPR_NOACCESS,
2917
                 &spr_read_generic, &spr_write_generic,
2918
                 0x00000000);
2919
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2920
                 SPR_NOACCESS, SPR_NOACCESS,
2921
                 &spr_read_generic, &spr_write_generic,
2922
                 0x00000000);
2923
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2924
                 SPR_NOACCESS, SPR_NOACCESS,
2925
                 &spr_read_generic, &spr_write_generic,
2926
                 0x00000000);
2927
    /* XXX : not implemented */
2928
    spr_register(env, SPR_440_CCR1, "CCR1",
2929
                 SPR_NOACCESS, SPR_NOACCESS,
2930
                 &spr_read_generic, &spr_write_generic,
2931
                 0x00000000);
2932
    /* Memory management */
2933
#if !defined(CONFIG_USER_ONLY)
2934
    env->nb_tlb = 64;
2935
    env->nb_ways = 1;
2936
    env->id_tlbs = 0;
2937
#endif
2938
    init_excp_BookE(env);
2939
    env->dcache_line_size = 32;
2940
    env->icache_line_size = 32;
2941
    /* XXX: TODO: allocate internal IRQ controller */
2942
}
2943

    
2944
/* PowerPC 440 GP                                                            */
2945
#define POWERPC_INSNS_440GP  (POWERPC_INSNS_EMB |                             \
2946
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2947
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2948
                              PPC_405_MAC | PPC_440_SPEC)
2949
#define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
2950
#define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
2951
#define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
2952
#define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
2953
#define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
2954
#define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2955
                              POWERPC_FLAG_DE)
2956
#define check_pow_440GP      check_pow_nocheck
2957

    
2958
static void init_proc_440GP (CPUPPCState *env)
2959
{
2960
    /* Time base */
2961
    gen_tbl(env);
2962
    gen_spr_BookE(env);
2963
    gen_spr_440(env);
2964
    /* Memory management */
2965
#if !defined(CONFIG_USER_ONLY)
2966
    env->nb_tlb = 64;
2967
    env->nb_ways = 1;
2968
    env->id_tlbs = 0;
2969
#endif
2970
    init_excp_BookE(env);
2971
    env->dcache_line_size = 32;
2972
    env->icache_line_size = 32;
2973
    /* XXX: TODO: allocate internal IRQ controller */
2974
}
2975

    
2976
/* PowerPC 440x4                                                             */
2977
#define POWERPC_INSNS_440x4  (POWERPC_INSNS_EMB |                             \
2978
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2979
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2980
                              PPC_440_SPEC)
2981
#define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
2982
#define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
2983
#define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
2984
#define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
2985
#define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
2986
#define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2987
                              POWERPC_FLAG_DE)
2988
#define check_pow_440x4      check_pow_nocheck
2989

    
2990
__attribute__ (( unused ))
2991
static void init_proc_440x4 (CPUPPCState *env)
2992
{
2993
    /* Time base */
2994
    gen_tbl(env);
2995
    gen_spr_BookE(env);
2996
    gen_spr_440(env);
2997
    /* Memory management */
2998
#if !defined(CONFIG_USER_ONLY)
2999
    env->nb_tlb = 64;
3000
    env->nb_ways = 1;
3001
    env->id_tlbs = 0;
3002
#endif
3003
    init_excp_BookE(env);
3004
    env->dcache_line_size = 32;
3005
    env->icache_line_size = 32;
3006
    /* XXX: TODO: allocate internal IRQ controller */
3007
}
3008

    
3009
/* PowerPC 440x5                                                             */
3010
#define POWERPC_INSNS_440x5  (POWERPC_INSNS_EMB |                             \
3011
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3012
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3013
                              PPC_440_SPEC | PPC_RFMCI)
3014
#define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3015
#define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3016
#define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3017
#define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3018
#define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3019
#define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3020
                              POWERPC_FLAG_DE)
3021
#define check_pow_440x5      check_pow_nocheck
3022

    
3023
static void init_proc_440x5 (CPUPPCState *env)
3024
{
3025
    /* Time base */
3026
    gen_tbl(env);
3027
    gen_spr_BookE(env);
3028
    gen_spr_440(env);
3029
    /* XXX : not implemented */
3030
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3031
                 SPR_NOACCESS, SPR_NOACCESS,
3032
                 &spr_read_generic, &spr_write_generic,
3033
                 0x00000000);
3034
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3035
                 SPR_NOACCESS, SPR_NOACCESS,
3036
                 &spr_read_generic, &spr_write_generic,
3037
                 0x00000000);
3038
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3039
                 SPR_NOACCESS, SPR_NOACCESS,
3040
                 &spr_read_generic, &spr_write_generic,
3041
                 0x00000000);
3042
    /* XXX : not implemented */
3043
    spr_register(env, SPR_440_CCR1, "CCR1",
3044
                 SPR_NOACCESS, SPR_NOACCESS,
3045
                 &spr_read_generic, &spr_write_generic,
3046
                 0x00000000);
3047
    /* Memory management */
3048
#if !defined(CONFIG_USER_ONLY)
3049
    env->nb_tlb = 64;
3050
    env->nb_ways = 1;
3051
    env->id_tlbs = 0;
3052
#endif
3053
    init_excp_BookE(env);
3054
    env->dcache_line_size = 32;
3055
    env->icache_line_size = 32;
3056
    /* XXX: TODO: allocate internal IRQ controller */
3057
}
3058

    
3059
/* PowerPC 460 (guessed)                                                     */
3060
#define POWERPC_INSNS_460    (POWERPC_INSNS_EMB |                             \
3061
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3062
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
3063
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3064
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3065
#define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3066
#define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3067
#define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3068
#define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3069
#define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3070
                              POWERPC_FLAG_DE)
3071
#define check_pow_460        check_pow_nocheck
3072

    
3073
__attribute__ (( unused ))
3074
static void init_proc_460 (CPUPPCState *env)
3075
{
3076
    /* Time base */
3077
    gen_tbl(env);
3078
    gen_spr_BookE(env);
3079
    gen_spr_440(env);
3080
    /* XXX : not implemented */
3081
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3082
                 SPR_NOACCESS, SPR_NOACCESS,
3083
                 &spr_read_generic, &spr_write_generic,
3084
                 0x00000000);
3085
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3086
                 SPR_NOACCESS, SPR_NOACCESS,
3087
                 &spr_read_generic, &spr_write_generic,
3088
                 0x00000000);
3089
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3090
                 SPR_NOACCESS, SPR_NOACCESS,
3091
                 &spr_read_generic, &spr_write_generic,
3092
                 0x00000000);
3093
    /* XXX : not implemented */
3094
    spr_register(env, SPR_440_CCR1, "CCR1",
3095
                 SPR_NOACCESS, SPR_NOACCESS,
3096
                 &spr_read_generic, &spr_write_generic,
3097
                 0x00000000);
3098
    /* XXX : not implemented */
3099
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3100
                 &spr_read_generic, &spr_write_generic,
3101
                 &spr_read_generic, &spr_write_generic,
3102
                 0x00000000);
3103
    /* Memory management */
3104
#if !defined(CONFIG_USER_ONLY)
3105
    env->nb_tlb = 64;
3106
    env->nb_ways = 1;
3107
    env->id_tlbs = 0;
3108
#endif
3109
    init_excp_BookE(env);
3110
    env->dcache_line_size = 32;
3111
    env->icache_line_size = 32;
3112
    /* XXX: TODO: allocate internal IRQ controller */
3113
}
3114

    
3115
/* PowerPC 460F (guessed)                                                    */
3116
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
3117
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3118
                              PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES |  \
3119
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |            \
3120
                              PPC_FLOAT_STFIWX |                              \
3121
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
3122
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3123
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3124
#define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3125
#define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3126
#define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3127
#define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3128
#define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3129
                              POWERPC_FLAG_DE)
3130
#define check_pow_460F       check_pow_nocheck
3131

    
3132
__attribute__ (( unused ))
3133
static void init_proc_460F (CPUPPCState *env)
3134
{
3135
    /* Time base */
3136
    gen_tbl(env);
3137
    gen_spr_BookE(env);
3138
    gen_spr_440(env);
3139
    /* XXX : not implemented */
3140
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3141
                 SPR_NOACCESS, SPR_NOACCESS,
3142
                 &spr_read_generic, &spr_write_generic,
3143
                 0x00000000);
3144
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3145
                 SPR_NOACCESS, SPR_NOACCESS,
3146
                 &spr_read_generic, &spr_write_generic,
3147
                 0x00000000);
3148
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3149
                 SPR_NOACCESS, SPR_NOACCESS,
3150
                 &spr_read_generic, &spr_write_generic,
3151
                 0x00000000);
3152
    /* XXX : not implemented */
3153
    spr_register(env, SPR_440_CCR1, "CCR1",
3154
                 SPR_NOACCESS, SPR_NOACCESS,
3155
                 &spr_read_generic, &spr_write_generic,
3156
                 0x00000000);
3157
    /* XXX : not implemented */
3158
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3159
                 &spr_read_generic, &spr_write_generic,
3160
                 &spr_read_generic, &spr_write_generic,
3161
                 0x00000000);
3162
    /* Memory management */
3163
#if !defined(CONFIG_USER_ONLY)
3164
    env->nb_tlb = 64;
3165
    env->nb_ways = 1;
3166
    env->id_tlbs = 0;
3167
#endif
3168
    init_excp_BookE(env);
3169
    env->dcache_line_size = 32;
3170
    env->icache_line_size = 32;
3171
    /* XXX: TODO: allocate internal IRQ controller */
3172
}
3173

    
3174
/* Generic BookE PowerPC                                                     */
3175
#define POWERPC_INSNS_BookE  (POWERPC_INSNS_EMB |                             \
3176
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3177
                              PPC_CACHE_DCBA |                                \
3178
                              PPC_FLOAT | PPC_FLOAT_FSQRT |                   \
3179
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3180
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3181
                              PPC_BOOKE)
3182
#define POWERPC_MSRM_BookE   (0x000000000006D630ULL)
3183
#define POWERPC_MMU_BookE    (POWERPC_MMU_BOOKE)
3184
#define POWERPC_EXCP_BookE   (POWERPC_EXCP_BOOKE)
3185
#define POWERPC_INPUT_BookE  (PPC_FLAGS_INPUT_BookE)
3186
#define POWERPC_BFDM_BookE   (bfd_mach_ppc_403)
3187
#define POWERPC_FLAG_BookE   (POWERPC_FLAG_NONE)
3188
#define check_pow_BookE      check_pow_nocheck
3189

    
3190
__attribute__ (( unused ))
3191
static void init_proc_BookE (CPUPPCState *env)
3192
{
3193
    init_excp_BookE(env);
3194
    env->dcache_line_size = 32;
3195
    env->icache_line_size = 32;
3196
}
3197

    
3198
/* e200 core                                                                 */
3199

    
3200
/* e300 core                                                                 */
3201

    
3202
/* e500 core                                                                 */
3203
#define POWERPC_INSNS_e500   (POWERPC_INSNS_EMB |                             \
3204
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3205
                              PPC_CACHE_DCBA |                                \
3206
                              PPC_BOOKE | PPC_E500_VECTOR)
3207
#define POWERPC_MMU_e500     (POWERPC_MMU_SOFT_4xx)
3208
#define POWERPC_EXCP_e500    (POWERPC_EXCP_40x)
3209
#define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
3210
#define POWERPC_BFDM_e500    (bfd_mach_ppc_403)
3211
#define POWERPC_FLAG_e500    (POWERPC_FLAG_SPE)
3212
#define check_pow_e500       check_pow_hid0
3213

    
3214
__attribute__ (( unused ))
3215
static void init_proc_e500 (CPUPPCState *env)
3216
{
3217
    /* Time base */
3218
    gen_tbl(env);
3219
    gen_spr_BookE(env);
3220
    /* Memory management */
3221
    gen_spr_BookE_FSL(env);
3222
#if !defined(CONFIG_USER_ONLY)
3223
    env->nb_tlb = 64;
3224
    env->nb_ways = 1;
3225
    env->id_tlbs = 0;
3226
#endif
3227
    init_excp_BookE(env);
3228
    env->dcache_line_size = 32;
3229
    env->icache_line_size = 32;
3230
    /* XXX: TODO: allocate internal IRQ controller */
3231
}
3232

    
3233
/* e600 core                                                                 */
3234

    
3235
/* Non-embedded PowerPC                                                      */
3236
/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC                    */
3237
#define POWERPC_INSNS_6xx    (PPC_INSNS_BASE | PPC_FLOAT |                    \
3238
                              PPC_CACHE | PPC_CACHE_ICBI |                    \
3239
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3240
/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602      */
3241
#define POWERPC_INSNS_WORKS  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |           \
3242
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3243
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3244
                              PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB |   \
3245
                              PPC_SEGMENT)
3246

    
3247
/* POWER : same as 601, without mfmsr, mfsr                                  */
3248
#if defined(TODO)
3249
#define POWERPC_INSNS_POWER  (XXX_TODO)
3250
/* POWER RSC (from RAD6000) */
3251
#define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
3252
#endif /* TODO */
3253

    
3254
/* PowerPC 601                                                               */
3255
#define POWERPC_INSNS_601    (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ |            \
3256
                              PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3257
#define POWERPC_MSRM_601     (0x000000000000FD70ULL)
3258
//#define POWERPC_MMU_601      (POWERPC_MMU_601)
3259
//#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
3260
#define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
3261
#define POWERPC_BFDM_601     (bfd_mach_ppc_601)
3262
#define POWERPC_FLAG_601     (POWERPC_FLAG_SE)
3263
#define check_pow_601        check_pow_none
3264

    
3265
static void init_proc_601 (CPUPPCState *env)
3266
{
3267
    gen_spr_ne_601(env);
3268
    gen_spr_601(env);
3269
    /* Hardware implementation registers */
3270
    /* XXX : not implemented */
3271
    spr_register(env, SPR_HID0, "HID0",
3272
                 SPR_NOACCESS, SPR_NOACCESS,
3273
                 &spr_read_generic, &spr_write_hid0_601,
3274
                 0x80010080);
3275
    /* XXX : not implemented */
3276
    spr_register(env, SPR_HID1, "HID1",
3277
                 SPR_NOACCESS, SPR_NOACCESS,
3278
                 &spr_read_generic, &spr_write_generic,
3279
                 0x00000000);
3280
    /* XXX : not implemented */
3281
    spr_register(env, SPR_601_HID2, "HID2",
3282
                 SPR_NOACCESS, SPR_NOACCESS,
3283
                 &spr_read_generic, &spr_write_generic,
3284
                 0x00000000);
3285
    /* XXX : not implemented */
3286
    spr_register(env, SPR_601_HID5, "HID5",
3287
                 SPR_NOACCESS, SPR_NOACCESS,
3288
                 &spr_read_generic, &spr_write_generic,
3289
                 0x00000000);
3290
    /* XXX : not implemented */
3291
    spr_register(env, SPR_601_HID15, "HID15",
3292
                 SPR_NOACCESS, SPR_NOACCESS,
3293
                 &spr_read_generic, &spr_write_generic,
3294
                 0x00000000);
3295
    /* Memory management */
3296
#if !defined(CONFIG_USER_ONLY)
3297
    env->nb_tlb = 64;
3298
    env->nb_ways = 2;
3299
    env->id_tlbs = 0;
3300
#endif
3301
    init_excp_601(env);
3302
    env->dcache_line_size = 64;
3303
    env->icache_line_size = 64;
3304
    /* Allocate hardware IRQ controller */
3305
    ppc6xx_irq_init(env);
3306
}
3307

    
3308
/* PowerPC 602                                                               */
3309
#define POWERPC_INSNS_602    (POWERPC_INSNS_6xx | PPC_MFTB |                  \
3310
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3311
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3312
                              PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3313
                              PPC_SEGMENT | PPC_602_SPEC)
3314
#define POWERPC_MSRM_602     (0x000000000033FF73ULL)
3315
#define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
3316
//#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
3317
#define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
3318
#define POWERPC_BFDM_602     (bfd_mach_ppc_602)
3319
#define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3320
                              POWERPC_FLAG_BE)
3321
#define check_pow_602        check_pow_hid0
3322

    
3323
static void init_proc_602 (CPUPPCState *env)
3324
{
3325
    gen_spr_ne_601(env);
3326
    gen_spr_602(env);
3327
    /* Time base */
3328
    gen_tbl(env);
3329
    /* hardware implementation registers */
3330
    /* XXX : not implemented */
3331
    spr_register(env, SPR_HID0, "HID0",
3332
                 SPR_NOACCESS, SPR_NOACCESS,
3333
                 &spr_read_generic, &spr_write_generic,
3334
                 0x00000000);
3335
    /* XXX : not implemented */
3336
    spr_register(env, SPR_HID1, "HID1",
3337
                 SPR_NOACCESS, SPR_NOACCESS,
3338
                 &spr_read_generic, &spr_write_generic,
3339
                 0x00000000);
3340
    /* Memory management */
3341
    gen_low_BATs(env);
3342
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3343
    init_excp_602(env);
3344
    env->dcache_line_size = 32;
3345
    env->icache_line_size = 32;
3346
    /* Allocate hardware IRQ controller */
3347
    ppc6xx_irq_init(env);
3348
}
3349

    
3350
/* PowerPC 603                                                               */
3351
#define POWERPC_INSNS_603    (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3352
#define POWERPC_MSRM_603     (0x000000000007FF73ULL)
3353
#define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
3354
//#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
3355
#define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
3356
#define POWERPC_BFDM_603     (bfd_mach_ppc_603)
3357
#define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3358
                              POWERPC_FLAG_BE)
3359
#define check_pow_603        check_pow_hid0
3360

    
3361
static void init_proc_603 (CPUPPCState *env)
3362
{
3363
    gen_spr_ne_601(env);
3364
    gen_spr_603(env);
3365
    /* Time base */
3366
    gen_tbl(env);
3367
    /* hardware implementation registers */
3368
    /* XXX : not implemented */
3369
    spr_register(env, SPR_HID0, "HID0",
3370
                 SPR_NOACCESS, SPR_NOACCESS,
3371
                 &spr_read_generic, &spr_write_generic,
3372
                 0x00000000);
3373
    /* XXX : not implemented */
3374
    spr_register(env, SPR_HID1, "HID1",
3375
                 SPR_NOACCESS, SPR_NOACCESS,
3376
                 &spr_read_generic, &spr_write_generic,
3377
                 0x00000000);
3378
    /* Memory management */
3379
    gen_low_BATs(env);
3380
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3381
    init_excp_603(env);
3382
    env->dcache_line_size = 32;
3383
    env->icache_line_size = 32;
3384
    /* Allocate hardware IRQ controller */
3385
    ppc6xx_irq_init(env);
3386
}
3387

    
3388
/* PowerPC 603e                                                              */
3389
#define POWERPC_INSNS_603E   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3390
#define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
3391
#define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
3392
//#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
3393
#define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
3394
#define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
3395
#define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3396
                              POWERPC_FLAG_BE)
3397
#define check_pow_603E       check_pow_hid0
3398

    
3399
static void init_proc_603E (CPUPPCState *env)
3400
{
3401
    gen_spr_ne_601(env);
3402
    gen_spr_603(env);
3403
    /* Time base */
3404
    gen_tbl(env);
3405
    /* hardware implementation registers */
3406
    /* XXX : not implemented */
3407
    spr_register(env, SPR_HID0, "HID0",
3408
                 SPR_NOACCESS, SPR_NOACCESS,
3409
                 &spr_read_generic, &spr_write_generic,
3410
                 0x00000000);
3411
    /* XXX : not implemented */
3412
    spr_register(env, SPR_HID1, "HID1",
3413
                 SPR_NOACCESS, SPR_NOACCESS,
3414
                 &spr_read_generic, &spr_write_generic,
3415
                 0x00000000);
3416
    /* XXX : not implemented */
3417
    spr_register(env, SPR_IABR, "IABR",
3418
                 SPR_NOACCESS, SPR_NOACCESS,
3419
                 &spr_read_generic, &spr_write_generic,
3420
                 0x00000000);
3421
    /* Memory management */
3422
    gen_low_BATs(env);
3423
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3424
    init_excp_603(env);
3425
    env->dcache_line_size = 32;
3426
    env->icache_line_size = 32;
3427
    /* Allocate hardware IRQ controller */
3428
    ppc6xx_irq_init(env);
3429
}
3430

    
3431
/* PowerPC G2                                                                */
3432
#define POWERPC_INSNS_G2     (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3433
#define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3434
#define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3435
//#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3436
#define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3437
#define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3438
#define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3439
                              POWERPC_FLAG_BE)
3440
#define check_pow_G2         check_pow_hid0
3441

    
3442
static void init_proc_G2 (CPUPPCState *env)
3443
{
3444
    gen_spr_ne_601(env);
3445
    gen_spr_G2_755(env);
3446
    gen_spr_G2(env);
3447
    /* Time base */
3448
    gen_tbl(env);
3449
    /* Hardware implementation register */
3450
    /* XXX : not implemented */
3451
    spr_register(env, SPR_HID0, "HID0",
3452
                 SPR_NOACCESS, SPR_NOACCESS,
3453
                 &spr_read_generic, &spr_write_generic,
3454
                 0x00000000);
3455
    /* XXX : not implemented */
3456
    spr_register(env, SPR_HID1, "HID1",
3457
                 SPR_NOACCESS, SPR_NOACCESS,
3458
                 &spr_read_generic, &spr_write_generic,
3459
                 0x00000000);
3460
    /* XXX : not implemented */
3461
    spr_register(env, SPR_HID2, "HID2",
3462
                 SPR_NOACCESS, SPR_NOACCESS,
3463
                 &spr_read_generic, &spr_write_generic,
3464
                 0x00000000);
3465
    /* Memory management */
3466
    gen_low_BATs(env);
3467
    gen_high_BATs(env);
3468
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3469
    init_excp_G2(env);
3470
    env->dcache_line_size = 32;
3471
    env->icache_line_size = 32;
3472
    /* Allocate hardware IRQ controller */
3473
    ppc6xx_irq_init(env);
3474
}
3475

    
3476
/* PowerPC G2LE                                                              */
3477
#define POWERPC_INSNS_G2LE   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3478
#define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3479
#define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3480
#define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3481
#define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3482
#define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3483
#define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3484
                              POWERPC_FLAG_BE)
3485
#define check_pow_G2LE       check_pow_hid0
3486

    
3487
static void init_proc_G2LE (CPUPPCState *env)
3488
{
3489
    gen_spr_ne_601(env);
3490
    gen_spr_G2_755(env);
3491
    gen_spr_G2(env);
3492
    /* Time base */
3493
    gen_tbl(env);
3494
    /* Hardware implementation register */
3495
    /* XXX : not implemented */
3496
    spr_register(env, SPR_HID0, "HID0",
3497
                 SPR_NOACCESS, SPR_NOACCESS,
3498
                 &spr_read_generic, &spr_write_generic,
3499
                 0x00000000);
3500
    /* XXX : not implemented */
3501
    spr_register(env, SPR_HID1, "HID1",
3502
                 SPR_NOACCESS, SPR_NOACCESS,
3503
                 &spr_read_generic, &spr_write_generic,
3504
                 0x00000000);
3505
    /* XXX : not implemented */
3506
    spr_register(env, SPR_HID2, "HID2",
3507
                 SPR_NOACCESS, SPR_NOACCESS,
3508
                 &spr_read_generic, &spr_write_generic,
3509
                 0x00000000);
3510
    /* Memory management */
3511
    gen_low_BATs(env);
3512
    gen_high_BATs(env);
3513
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3514
    init_excp_G2(env);
3515
    env->dcache_line_size = 32;
3516
    env->icache_line_size = 32;
3517
    /* Allocate hardware IRQ controller */
3518
    ppc6xx_irq_init(env);
3519
}
3520

    
3521
/* PowerPC 604                                                               */
3522
#define POWERPC_INSNS_604    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3523
#define POWERPC_MSRM_604     (0x000000000005FF77ULL)
3524
#define POWERPC_MMU_604      (POWERPC_MMU_32B)
3525
//#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
3526
#define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
3527
#define POWERPC_BFDM_604     (bfd_mach_ppc_604)
3528
#define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3529
                              POWERPC_FLAG_PMM)
3530
#define check_pow_604        check_pow_nocheck
3531

    
3532
static void init_proc_604 (CPUPPCState *env)
3533
{
3534
    gen_spr_ne_601(env);
3535
    gen_spr_604(env);
3536
    /* Time base */
3537
    gen_tbl(env);
3538
    /* Hardware implementation registers */
3539
    /* XXX : not implemented */
3540
    spr_register(env, SPR_HID0, "HID0",
3541
                 SPR_NOACCESS, SPR_NOACCESS,
3542
                 &spr_read_generic, &spr_write_generic,
3543
                 0x00000000);
3544
    /* XXX : not implemented */
3545
    spr_register(env, SPR_HID1, "HID1",
3546
                 SPR_NOACCESS, SPR_NOACCESS,
3547
                 &spr_read_generic, &spr_write_generic,
3548
                 0x00000000);
3549
    /* Memory management */
3550
    gen_low_BATs(env);
3551
    init_excp_604(env);
3552
    env->dcache_line_size = 32;
3553
    env->icache_line_size = 32;
3554
    /* Allocate hardware IRQ controller */
3555
    ppc6xx_irq_init(env);
3556
}
3557

    
3558
/* PowerPC 740/750 (aka G3)                                                  */
3559
#define POWERPC_INSNS_7x0    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3560
#define POWERPC_MSRM_7x0     (0x000000000005FF77ULL)
3561
#define POWERPC_MMU_7x0      (POWERPC_MMU_32B)
3562
//#define POWERPC_EXCP_7x0     (POWERPC_EXCP_7x0)
3563
#define POWERPC_INPUT_7x0    (PPC_FLAGS_INPUT_6xx)
3564
#define POWERPC_BFDM_7x0     (bfd_mach_ppc_750)
3565
#define POWERPC_FLAG_7x0     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3566
                              POWERPC_FLAG_PMM)
3567
#define check_pow_7x0        check_pow_hid0
3568

    
3569
static void init_proc_7x0 (CPUPPCState *env)
3570
{
3571
    gen_spr_ne_601(env);
3572
    gen_spr_7xx(env);
3573
    /* Time base */
3574
    gen_tbl(env);
3575
    /* Thermal management */
3576
    gen_spr_thrm(env);
3577
    /* Hardware implementation registers */
3578
    /* XXX : not implemented */
3579
    spr_register(env, SPR_HID0, "HID0",
3580
                 SPR_NOACCESS, SPR_NOACCESS,
3581
                 &spr_read_generic, &spr_write_generic,
3582
                 0x00000000);
3583
    /* XXX : not implemented */
3584
    spr_register(env, SPR_HID1, "HID1",
3585
                 SPR_NOACCESS, SPR_NOACCESS,
3586
                 &spr_read_generic, &spr_write_generic,
3587
                 0x00000000);
3588
    /* Memory management */
3589
    gen_low_BATs(env);
3590
    init_excp_7x0(env);
3591
    env->dcache_line_size = 32;
3592
    env->icache_line_size = 32;
3593
    /* Allocate hardware IRQ controller */
3594
    ppc6xx_irq_init(env);
3595
}
3596

    
3597
/* PowerPC 750FX/GX                                                          */
3598
#define POWERPC_INSNS_750fx  (POWERPC_INSNS_WORKS | PPC_EXTERN)
3599
#define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
3600
#define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
3601
#define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
3602
#define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
3603
#define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
3604
#define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3605
                              POWERPC_FLAG_PMM)
3606
#define check_pow_750fx      check_pow_hid0
3607

    
3608
static void init_proc_750fx (CPUPPCState *env)
3609
{
3610
    gen_spr_ne_601(env);
3611
    gen_spr_7xx(env);
3612
    /* Time base */
3613
    gen_tbl(env);
3614
    /* Thermal management */
3615
    gen_spr_thrm(env);
3616
    /* Hardware implementation registers */
3617
    /* XXX : not implemented */
3618
    spr_register(env, SPR_HID0, "HID0",
3619
                 SPR_NOACCESS, SPR_NOACCESS,
3620
                 &spr_read_generic, &spr_write_generic,
3621
                 0x00000000);
3622
    /* XXX : not implemented */
3623
    spr_register(env, SPR_HID1, "HID1",
3624
                 SPR_NOACCESS, SPR_NOACCESS,
3625
                 &spr_read_generic, &spr_write_generic,
3626
                 0x00000000);
3627
    /* XXX : not implemented */
3628
    spr_register(env, SPR_750_HID2, "HID2",
3629
                 SPR_NOACCESS, SPR_NOACCESS,
3630
                 &spr_read_generic, &spr_write_generic,
3631
                 0x00000000);
3632
    /* Memory management */
3633
    gen_low_BATs(env);
3634
    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3635
    gen_high_BATs(env);
3636
    init_excp_750FX(env);
3637
    env->dcache_line_size = 32;
3638
    env->icache_line_size = 32;
3639
    /* Allocate hardware IRQ controller */
3640
    ppc6xx_irq_init(env);
3641
}
3642

    
3643
/* PowerPC 745/755                                                           */
3644
#define POWERPC_INSNS_7x5    (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3645
#define POWERPC_MSRM_7x5     (0x000000000005FF77ULL)
3646
#define POWERPC_MMU_7x5      (POWERPC_MMU_SOFT_6xx)
3647
//#define POWERPC_EXCP_7x5     (POWERPC_EXCP_7x5)
3648
#define POWERPC_INPUT_7x5    (PPC_FLAGS_INPUT_6xx)
3649
#define POWERPC_BFDM_7x5     (bfd_mach_ppc_750)
3650
#define POWERPC_FLAG_7x5     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3651
                              POWERPC_FLAG_PMM)
3652
#define check_pow_7x5        check_pow_hid0
3653

    
3654
static void init_proc_7x5 (CPUPPCState *env)
3655
{
3656
    gen_spr_ne_601(env);
3657
    gen_spr_G2_755(env);
3658
    /* Time base */
3659
    gen_tbl(env);
3660
    /* L2 cache control */
3661
    /* XXX : not implemented */
3662
    spr_register(env, SPR_ICTC, "ICTC",
3663
                 SPR_NOACCESS, SPR_NOACCESS,
3664
                 &spr_read_generic, &spr_write_generic,
3665
                 0x00000000);
3666
    /* XXX : not implemented */
3667
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3668
                 SPR_NOACCESS, SPR_NOACCESS,
3669
                 &spr_read_generic, &spr_write_generic,
3670
                 0x00000000);
3671
    /* Hardware implementation registers */
3672
    /* XXX : not implemented */
3673
    spr_register(env, SPR_HID0, "HID0",
3674
                 SPR_NOACCESS, SPR_NOACCESS,
3675
                 &spr_read_generic, &spr_write_generic,
3676
                 0x00000000);
3677
    /* XXX : not implemented */
3678
    spr_register(env, SPR_HID1, "HID1",
3679
                 SPR_NOACCESS, SPR_NOACCESS,
3680
                 &spr_read_generic, &spr_write_generic,
3681
                 0x00000000);
3682
    /* XXX : not implemented */
3683
    spr_register(env, SPR_HID2, "HID2",
3684
                 SPR_NOACCESS, SPR_NOACCESS,
3685
                 &spr_read_generic, &spr_write_generic,
3686
                 0x00000000);
3687
    /* Memory management */
3688
    gen_low_BATs(env);
3689
    gen_high_BATs(env);
3690
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3691
    init_excp_7x5(env);
3692
    env->dcache_line_size = 32;
3693
    env->icache_line_size = 32;
3694
    /* Allocate hardware IRQ controller */
3695
    ppc6xx_irq_init(env);
3696
#if !defined(CONFIG_USER_ONLY)
3697
    /* Hardware reset vector */
3698
    env->hreset_vector = 0xFFFFFFFCUL;
3699
#endif
3700
}
3701

    
3702
/* PowerPC 7400 (aka G4)                                                     */
3703
#define POWERPC_INSNS_7400   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3704
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3705
                              PPC_ALTIVEC)
3706
#define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
3707
#define POWERPC_MMU_7400     (POWERPC_MMU_32B)
3708
#define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
3709
#define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
3710
#define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
3711
#define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3712
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3713
#define check_pow_7400       check_pow_hid0
3714

    
3715
static void init_proc_7400 (CPUPPCState *env)
3716
{
3717
    gen_spr_ne_601(env);
3718
    gen_spr_7xx(env);
3719
    /* Time base */
3720
    gen_tbl(env);
3721
    /* 74xx specific SPR */
3722
    gen_spr_74xx(env);
3723
    /* Thermal management */
3724
    gen_spr_thrm(env);
3725
    /* Memory management */
3726
    gen_low_BATs(env);
3727
    init_excp_7400(env);
3728
    env->dcache_line_size = 32;
3729
    env->icache_line_size = 32;
3730
    /* Allocate hardware IRQ controller */
3731
    ppc6xx_irq_init(env);
3732
}
3733

    
3734
/* PowerPC 7410 (aka G4)                                                     */
3735
#define POWERPC_INSNS_7410   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3736
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3737
                              PPC_ALTIVEC)
3738
#define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
3739
#define POWERPC_MMU_7410     (POWERPC_MMU_32B)
3740
#define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
3741
#define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
3742
#define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
3743
#define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3744
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3745
#define check_pow_7410       check_pow_hid0
3746

    
3747
static void init_proc_7410 (CPUPPCState *env)
3748
{
3749
    gen_spr_ne_601(env);
3750
    gen_spr_7xx(env);
3751
    /* Time base */
3752
    gen_tbl(env);
3753
    /* 74xx specific SPR */
3754
    gen_spr_74xx(env);
3755
    /* Thermal management */
3756
    gen_spr_thrm(env);
3757
    /* L2PMCR */
3758
    /* XXX : not implemented */
3759
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3760
                 SPR_NOACCESS, SPR_NOACCESS,
3761
                 &spr_read_generic, &spr_write_generic,
3762
                 0x00000000);
3763
    /* LDSTDB */
3764
    /* XXX : not implemented */
3765
    spr_register(env, SPR_LDSTDB, "LDSTDB",
3766
                 SPR_NOACCESS, SPR_NOACCESS,
3767
                 &spr_read_generic, &spr_write_generic,
3768
                 0x00000000);
3769
    /* Memory management */
3770
    gen_low_BATs(env);
3771
    init_excp_7400(env);
3772
    env->dcache_line_size = 32;
3773
    env->icache_line_size = 32;
3774
    /* Allocate hardware IRQ controller */
3775
    ppc6xx_irq_init(env);
3776
}
3777

    
3778
/* PowerPC 7440 (aka G4)                                                     */
3779
#define POWERPC_INSNS_7440   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3780
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3781
                              PPC_ALTIVEC)
3782
#define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
3783
#define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
3784
#define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
3785
#define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
3786
#define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
3787
#define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3788
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3789
#define check_pow_7440       check_pow_hid0
3790

    
3791
__attribute__ (( unused ))
3792
static void init_proc_7440 (CPUPPCState *env)
3793
{
3794
    gen_spr_ne_601(env);
3795
    gen_spr_7xx(env);
3796
    /* Time base */
3797
    gen_tbl(env);
3798
    /* 74xx specific SPR */
3799
    gen_spr_74xx(env);
3800
    /* LDSTCR */
3801
    /* XXX : not implemented */
3802
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3803
                 SPR_NOACCESS, SPR_NOACCESS,
3804
                 &spr_read_generic, &spr_write_generic,
3805
                 0x00000000);
3806
    /* ICTRL */
3807
    /* XXX : not implemented */
3808
    spr_register(env, SPR_ICTRL, "ICTRL",
3809
                 SPR_NOACCESS, SPR_NOACCESS,
3810
                 &spr_read_generic, &spr_write_generic,
3811
                 0x00000000);
3812
    /* MSSSR0 */
3813
    /* XXX : not implemented */
3814
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3815
                 SPR_NOACCESS, SPR_NOACCESS,
3816
                 &spr_read_generic, &spr_write_generic,
3817
                 0x00000000);
3818
    /* PMC */
3819
    /* XXX : not implemented */
3820
    spr_register(env, SPR_PMC5, "PMC5",
3821
                 SPR_NOACCESS, SPR_NOACCESS,
3822
                 &spr_read_generic, &spr_write_generic,
3823
                 0x00000000);
3824
    /* XXX : not implemented */
3825
    spr_register(env, SPR_UPMC5, "UPMC5",
3826
                 &spr_read_ureg, SPR_NOACCESS,
3827
                 &spr_read_ureg, SPR_NOACCESS,
3828
                 0x00000000);
3829
    /* XXX : not implemented */
3830
    spr_register(env, SPR_PMC6, "PMC6",
3831
                 SPR_NOACCESS, SPR_NOACCESS,
3832
                 &spr_read_generic, &spr_write_generic,
3833
                 0x00000000);
3834
    /* XXX : not implemented */
3835
    spr_register(env, SPR_UPMC6, "UPMC6",
3836
                 &spr_read_ureg, SPR_NOACCESS,
3837
                 &spr_read_ureg, SPR_NOACCESS,
3838
                 0x00000000);
3839
    /* Memory management */
3840
    gen_low_BATs(env);
3841
    gen_74xx_soft_tlb(env, 128, 2);
3842
    init_excp_7450(env);
3843
    env->dcache_line_size = 32;
3844
    env->icache_line_size = 32;
3845
    /* Allocate hardware IRQ controller */
3846
    ppc6xx_irq_init(env);
3847
}
3848

    
3849
/* PowerPC 7450 (aka G4)                                                     */
3850
#define POWERPC_INSNS_7450   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3851
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3852
                              PPC_ALTIVEC)
3853
#define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
3854
#define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
3855
#define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
3856
#define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
3857
#define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
3858
#define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3859
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3860
#define check_pow_7450       check_pow_hid0
3861

    
3862
__attribute__ (( unused ))
3863
static void init_proc_7450 (CPUPPCState *env)
3864
{
3865
    gen_spr_ne_601(env);
3866
    gen_spr_7xx(env);
3867
    /* Time base */
3868
    gen_tbl(env);
3869
    /* 74xx specific SPR */
3870
    gen_spr_74xx(env);
3871
    /* Level 3 cache control */
3872
    gen_l3_ctrl(env);
3873
    /* LDSTCR */
3874
    /* XXX : not implemented */
3875
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3876
                 SPR_NOACCESS, SPR_NOACCESS,
3877
                 &spr_read_generic, &spr_write_generic,
3878
                 0x00000000);
3879
    /* ICTRL */
3880
    /* XXX : not implemented */
3881
    spr_register(env, SPR_ICTRL, "ICTRL",
3882
                 SPR_NOACCESS, SPR_NOACCESS,
3883
                 &spr_read_generic, &spr_write_generic,
3884
                 0x00000000);
3885
    /* MSSSR0 */
3886
    /* XXX : not implemented */
3887
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3888
                 SPR_NOACCESS, SPR_NOACCESS,
3889
                 &spr_read_generic, &spr_write_generic,
3890
                 0x00000000);
3891
    /* PMC */
3892
    /* XXX : not implemented */
3893
    spr_register(env, SPR_PMC5, "PMC5",
3894
                 SPR_NOACCESS, SPR_NOACCESS,
3895
                 &spr_read_generic, &spr_write_generic,
3896
                 0x00000000);
3897
    /* XXX : not implemented */
3898
    spr_register(env, SPR_UPMC5, "UPMC5",
3899
                 &spr_read_ureg, SPR_NOACCESS,
3900
                 &spr_read_ureg, SPR_NOACCESS,
3901
                 0x00000000);
3902
    /* XXX : not implemented */
3903
    spr_register(env, SPR_PMC6, "PMC6",
3904
                 SPR_NOACCESS, SPR_NOACCESS,
3905
                 &spr_read_generic, &spr_write_generic,
3906
                 0x00000000);
3907
    /* XXX : not implemented */
3908
    spr_register(env, SPR_UPMC6, "UPMC6",
3909
                 &spr_read_ureg, SPR_NOACCESS,
3910
                 &spr_read_ureg, SPR_NOACCESS,
3911
                 0x00000000);
3912
    /* Memory management */
3913
    gen_low_BATs(env);
3914
    gen_74xx_soft_tlb(env, 128, 2);
3915
    init_excp_7450(env);
3916
    env->dcache_line_size = 32;
3917
    env->icache_line_size = 32;
3918
    /* Allocate hardware IRQ controller */
3919
    ppc6xx_irq_init(env);
3920
}
3921

    
3922
/* PowerPC 7445 (aka G4)                                                     */
3923
#define POWERPC_INSNS_7445   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3924
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3925
                              PPC_ALTIVEC)
3926
#define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
3927
#define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
3928
#define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
3929
#define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
3930
#define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
3931
#define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3932
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3933
#define check_pow_7445       check_pow_hid0
3934

    
3935
__attribute__ (( unused ))
3936
static void init_proc_7445 (CPUPPCState *env)
3937
{
3938
    gen_spr_ne_601(env);
3939
    gen_spr_7xx(env);
3940
    /* Time base */
3941
    gen_tbl(env);
3942
    /* 74xx specific SPR */
3943
    gen_spr_74xx(env);
3944
    /* LDSTCR */
3945
    /* XXX : not implemented */
3946
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3947
                 SPR_NOACCESS, SPR_NOACCESS,
3948
                 &spr_read_generic, &spr_write_generic,
3949
                 0x00000000);
3950
    /* ICTRL */
3951
    /* XXX : not implemented */
3952
    spr_register(env, SPR_ICTRL, "ICTRL",
3953
                 SPR_NOACCESS, SPR_NOACCESS,
3954
                 &spr_read_generic, &spr_write_generic,
3955
                 0x00000000);
3956
    /* MSSSR0 */
3957
    /* XXX : not implemented */
3958
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3959
                 SPR_NOACCESS, SPR_NOACCESS,
3960
                 &spr_read_generic, &spr_write_generic,
3961
                 0x00000000);
3962
    /* PMC */
3963
    /* XXX : not implemented */
3964
    spr_register(env, SPR_PMC5, "PMC5",
3965
                 SPR_NOACCESS, SPR_NOACCESS,
3966
                 &spr_read_generic, &spr_write_generic,
3967
                 0x00000000);
3968
    /* XXX : not implemented */
3969
    spr_register(env, SPR_UPMC5, "UPMC5",
3970
                 &spr_read_ureg, SPR_NOACCESS,
3971
                 &spr_read_ureg, SPR_NOACCESS,
3972
                 0x00000000);
3973
    /* XXX : not implemented */
3974
    spr_register(env, SPR_PMC6, "PMC6",
3975
                 SPR_NOACCESS, SPR_NOACCESS,
3976
                 &spr_read_generic, &spr_write_generic,
3977
                 0x00000000);
3978
    /* XXX : not implemented */
3979
    spr_register(env, SPR_UPMC6, "UPMC6",
3980
                 &spr_read_ureg, SPR_NOACCESS,
3981
                 &spr_read_ureg, SPR_NOACCESS,
3982
                 0x00000000);
3983
    /* SPRGs */
3984
    spr_register(env, SPR_SPRG4, "SPRG4",
3985
                 SPR_NOACCESS, SPR_NOACCESS,
3986
                 &spr_read_generic, &spr_write_generic,
3987
                 0x00000000);
3988
    spr_register(env, SPR_USPRG4, "USPRG4",
3989
                 &spr_read_ureg, SPR_NOACCESS,
3990
                 &spr_read_ureg, SPR_NOACCESS,
3991
                 0x00000000);
3992
    spr_register(env, SPR_SPRG5, "SPRG5",
3993
                 SPR_NOACCESS, SPR_NOACCESS,
3994
                 &spr_read_generic, &spr_write_generic,
3995
                 0x00000000);
3996
    spr_register(env, SPR_USPRG5, "USPRG5",
3997
                 &spr_read_ureg, SPR_NOACCESS,
3998
                 &spr_read_ureg, SPR_NOACCESS,
3999
                 0x00000000);
4000
    spr_register(env, SPR_SPRG6, "SPRG6",
4001
                 SPR_NOACCESS, SPR_NOACCESS,
4002
                 &spr_read_generic, &spr_write_generic,
4003
                 0x00000000);
4004
    spr_register(env, SPR_USPRG6, "USPRG6",
4005
                 &spr_read_ureg, SPR_NOACCESS,
4006
                 &spr_read_ureg, SPR_NOACCESS,
4007
                 0x00000000);
4008
    spr_register(env, SPR_SPRG7, "SPRG7",
4009
                 SPR_NOACCESS, SPR_NOACCESS,
4010
                 &spr_read_generic, &spr_write_generic,
4011
                 0x00000000);
4012
    spr_register(env, SPR_USPRG7, "USPRG7",
4013
                 &spr_read_ureg, SPR_NOACCESS,
4014
                 &spr_read_ureg, SPR_NOACCESS,
4015
                 0x00000000);
4016
    /* Memory management */
4017
    gen_low_BATs(env);
4018
    gen_high_BATs(env);
4019
    gen_74xx_soft_tlb(env, 128, 2);
4020
    init_excp_7450(env);
4021
    env->dcache_line_size = 32;
4022
    env->icache_line_size = 32;
4023
    /* Allocate hardware IRQ controller */
4024
    ppc6xx_irq_init(env);
4025
}
4026

    
4027
/* PowerPC 7455 (aka G4)                                                     */
4028
#define POWERPC_INSNS_7455   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
4029
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
4030
                              PPC_ALTIVEC)
4031
#define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
4032
#define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
4033
#define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
4034
#define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
4035
#define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
4036
#define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4037
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4038
#define check_pow_7455       check_pow_hid0
4039

    
4040
__attribute__ (( unused ))
4041
static void init_proc_7455 (CPUPPCState *env)
4042
{
4043
    gen_spr_ne_601(env);
4044
    gen_spr_7xx(env);
4045
    /* Time base */
4046
    gen_tbl(env);
4047
    /* 74xx specific SPR */
4048
    gen_spr_74xx(env);
4049
    /* Level 3 cache control */
4050
    gen_l3_ctrl(env);
4051
    /* LDSTCR */
4052
    /* XXX : not implemented */
4053
    spr_register(env, SPR_LDSTCR, "LDSTCR",
4054
                 SPR_NOACCESS, SPR_NOACCESS,
4055
                 &spr_read_generic, &spr_write_generic,
4056
                 0x00000000);
4057
    /* ICTRL */
4058
    /* XXX : not implemented */
4059
    spr_register(env, SPR_ICTRL, "ICTRL",
4060
                 SPR_NOACCESS, SPR_NOACCESS,
4061
                 &spr_read_generic, &spr_write_generic,
4062
                 0x00000000);
4063
    /* MSSSR0 */
4064
    /* XXX : not implemented */
4065
    spr_register(env, SPR_MSSSR0, "MSSSR0",
4066
                 SPR_NOACCESS, SPR_NOACCESS,
4067
                 &spr_read_generic, &spr_write_generic,
4068
                 0x00000000);
4069
    /* PMC */
4070
    /* XXX : not implemented */
4071
    spr_register(env, SPR_PMC5, "PMC5",
4072
                 SPR_NOACCESS, SPR_NOACCESS,
4073
                 &spr_read_generic, &spr_write_generic,
4074
                 0x00000000);
4075
    /* XXX : not implemented */
4076
    spr_register(env, SPR_UPMC5, "UPMC5",
4077
                 &spr_read_ureg, SPR_NOACCESS,
4078
                 &spr_read_ureg, SPR_NOACCESS,
4079
                 0x00000000);
4080
    /* XXX : not implemented */
4081
    spr_register(env, SPR_PMC6, "PMC6",
4082
                 SPR_NOACCESS, SPR_NOACCESS,
4083
                 &spr_read_generic, &spr_write_generic,
4084
                 0x00000000);
4085
    /* XXX : not implemented */
4086
    spr_register(env, SPR_UPMC6, "UPMC6",
4087
                 &spr_read_ureg, SPR_NOACCESS,
4088
                 &spr_read_ureg, SPR_NOACCESS,
4089
                 0x00000000);
4090
    /* SPRGs */
4091
    spr_register(env, SPR_SPRG4, "SPRG4",
4092
                 SPR_NOACCESS, SPR_NOACCESS,
4093
                 &spr_read_generic, &spr_write_generic,
4094
                 0x00000000);
4095
    spr_register(env, SPR_USPRG4, "USPRG4",
4096
                 &spr_read_ureg, SPR_NOACCESS,
4097
                 &spr_read_ureg, SPR_NOACCESS,
4098
                 0x00000000);
4099
    spr_register(env, SPR_SPRG5, "SPRG5",
4100
                 SPR_NOACCESS, SPR_NOACCESS,
4101
                 &spr_read_generic, &spr_write_generic,
4102
                 0x00000000);
4103
    spr_register(env, SPR_USPRG5, "USPRG5",
4104
                 &spr_read_ureg, SPR_NOACCESS,
4105
                 &spr_read_ureg, SPR_NOACCESS,
4106
                 0x00000000);
4107
    spr_register(env, SPR_SPRG6, "SPRG6",
4108
                 SPR_NOACCESS, SPR_NOACCESS,
4109
                 &spr_read_generic, &spr_write_generic,
4110
                 0x00000000);
4111
    spr_register(env, SPR_USPRG6, "USPRG6",
4112
                 &spr_read_ureg, SPR_NOACCESS,
4113
                 &spr_read_ureg, SPR_NOACCESS,
4114
                 0x00000000);
4115
    spr_register(env, SPR_SPRG7, "SPRG7",
4116
                 SPR_NOACCESS, SPR_NOACCESS,
4117
                 &spr_read_generic, &spr_write_generic,
4118
                 0x00000000);
4119
    spr_register(env, SPR_USPRG7, "USPRG7",
4120
                 &spr_read_ureg, SPR_NOACCESS,
4121
                 &spr_read_ureg, SPR_NOACCESS,
4122
                 0x00000000);
4123
    /* Memory management */
4124
    gen_low_BATs(env);
4125
    gen_high_BATs(env);
4126
    gen_74xx_soft_tlb(env, 128, 2);
4127
    init_excp_7450(env);
4128
    env->dcache_line_size = 32;
4129
    env->icache_line_size = 32;
4130
    /* Allocate hardware IRQ controller */
4131
    ppc6xx_irq_init(env);
4132
}
4133

    
4134
#if defined (TARGET_PPC64)
4135
#define POWERPC_INSNS_WORK64  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |          \
4136
                               PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |           \
4137
                               PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |            \
4138
                               PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4139
/* PowerPC 970                                                               */
4140
#define POWERPC_INSNS_970    (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4141
                              PPC_64B | PPC_ALTIVEC |                         \
4142
                              PPC_SEGMENT_64B | PPC_SLBI)
4143
#define POWERPC_MSRM_970     (0x900000000204FF36ULL)
4144
#define POWERPC_MMU_970      (POWERPC_MMU_64B)
4145
//#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
4146
#define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
4147
#define POWERPC_BFDM_970     (bfd_mach_ppc64)
4148
#define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4149
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4150

    
4151
#if defined(CONFIG_USER_ONLY)
4152
#define POWERPC970_HID5_INIT 0x00000080
4153
#else
4154
#define POWERPC970_HID5_INIT 0x00000000
4155
#endif
4156

    
4157
static int check_pow_970 (CPUPPCState *env)
4158
{
4159
    if (env->spr[SPR_HID0] & 0x00600000)
4160
        return 1;
4161

    
4162
    return 0;
4163
}
4164

    
4165
static void init_proc_970 (CPUPPCState *env)
4166
{
4167
    gen_spr_ne_601(env);
4168
    gen_spr_7xx(env);
4169
    /* Time base */
4170
    gen_tbl(env);
4171
    /* Hardware implementation registers */
4172
    /* XXX : not implemented */
4173
    spr_register(env, SPR_HID0, "HID0",
4174
                 SPR_NOACCESS, SPR_NOACCESS,
4175
                 &spr_read_generic, &spr_write_clear,
4176
                 0x60000000);
4177
    /* XXX : not implemented */
4178
    spr_register(env, SPR_HID1, "HID1",
4179
                 SPR_NOACCESS, SPR_NOACCESS,
4180
                 &spr_read_generic, &spr_write_generic,
4181
                 0x00000000);
4182
    /* XXX : not implemented */
4183
    spr_register(env, SPR_750_HID2, "HID2",
4184
                 SPR_NOACCESS, SPR_NOACCESS,
4185
                 &spr_read_generic, &spr_write_generic,
4186
                 0x00000000);
4187
    /* XXX : not implemented */
4188
    spr_register(env, SPR_970_HID5, "HID5",
4189
                 SPR_NOACCESS, SPR_NOACCESS,
4190
                 &spr_read_generic, &spr_write_generic,
4191
                 POWERPC970_HID5_INIT);
4192
    /* Memory management */
4193
    /* XXX: not correct */
4194
    gen_low_BATs(env);
4195
    /* XXX : not implemented */
4196
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4197
                 SPR_NOACCESS, SPR_NOACCESS,
4198
                 &spr_read_generic, SPR_NOACCESS,
4199
                 0x00000000); /* TOFIX */
4200
    /* XXX : not implemented */
4201
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4202
                 SPR_NOACCESS, SPR_NOACCESS,
4203
                 &spr_read_generic, &spr_write_generic,
4204
                 0x00000000); /* TOFIX */
4205
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4206
                 SPR_NOACCESS, SPR_NOACCESS,
4207
                 &spr_read_generic, &spr_write_generic,
4208
                 0xFFF00000); /* XXX: This is a hack */
4209
#if !defined(CONFIG_USER_ONLY)
4210
    env->slb_nr = 32;
4211
#endif
4212
    init_excp_970(env);
4213
    env->dcache_line_size = 128;
4214
    env->icache_line_size = 128;
4215
    /* Allocate hardware IRQ controller */
4216
    ppc970_irq_init(env);
4217
}
4218

    
4219
/* PowerPC 970FX (aka G5)                                                    */
4220
#define POWERPC_INSNS_970FX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4221
                              PPC_64B | PPC_ALTIVEC |                         \
4222
                              PPC_SEGMENT_64B | PPC_SLBI)
4223
#define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
4224
#define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
4225
#define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
4226
#define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
4227
#define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
4228
#define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4229
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4230

    
4231
static int check_pow_970FX (CPUPPCState *env)
4232
{
4233
    if (env->spr[SPR_HID0] & 0x00600000)
4234
        return 1;
4235

    
4236
    return 0;
4237
}
4238

    
4239
static void init_proc_970FX (CPUPPCState *env)
4240
{
4241
    gen_spr_ne_601(env);
4242
    gen_spr_7xx(env);
4243
    /* Time base */
4244
    gen_tbl(env);
4245
    /* Hardware implementation registers */
4246
    /* XXX : not implemented */
4247
    spr_register(env, SPR_HID0, "HID0",
4248
                 SPR_NOACCESS, SPR_NOACCESS,
4249
                 &spr_read_generic, &spr_write_clear,
4250
                 0x60000000);
4251
    /* XXX : not implemented */
4252
    spr_register(env, SPR_HID1, "HID1",
4253
                 SPR_NOACCESS, SPR_NOACCESS,
4254
                 &spr_read_generic, &spr_write_generic,
4255
                 0x00000000);
4256
    /* XXX : not implemented */
4257
    spr_register(env, SPR_750_HID2, "HID2",
4258
                 SPR_NOACCESS, SPR_NOACCESS,
4259
                 &spr_read_generic, &spr_write_generic,
4260
                 0x00000000);
4261
    /* XXX : not implemented */
4262
    spr_register(env, SPR_970_HID5, "HID5",
4263
                 SPR_NOACCESS, SPR_NOACCESS,
4264
                 &spr_read_generic, &spr_write_generic,
4265
                 POWERPC970_HID5_INIT);
4266
    /* Memory management */
4267
    /* XXX: not correct */
4268
    gen_low_BATs(env);
4269
    /* XXX : not implemented */
4270
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4271
                 SPR_NOACCESS, SPR_NOACCESS,
4272
                 &spr_read_generic, SPR_NOACCESS,
4273
                 0x00000000); /* TOFIX */
4274
    /* XXX : not implemented */
4275
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4276
                 SPR_NOACCESS, SPR_NOACCESS,
4277
                 &spr_read_generic, &spr_write_generic,
4278
                 0x00000000); /* TOFIX */
4279
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4280
                 SPR_NOACCESS, SPR_NOACCESS,
4281
                 &spr_read_generic, &spr_write_generic,
4282
                 0xFFF00000); /* XXX: This is a hack */
4283
#if !defined(CONFIG_USER_ONLY)
4284
    env->slb_nr = 32;
4285
#endif
4286
    init_excp_970(env);
4287
    env->dcache_line_size = 128;
4288
    env->icache_line_size = 128;
4289
    /* Allocate hardware IRQ controller */
4290
    ppc970_irq_init(env);
4291
}
4292

    
4293
/* PowerPC 970 GX                                                            */
4294
#define POWERPC_INSNS_970GX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4295
                              PPC_64B | PPC_ALTIVEC |                         \
4296
                              PPC_SEGMENT_64B | PPC_SLBI)
4297
#define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
4298
#define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
4299
#define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
4300
#define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
4301
#define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
4302
#define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4303
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4304

    
4305
static int check_pow_970GX (CPUPPCState *env)
4306
{
4307
    if (env->spr[SPR_HID0] & 0x00600000)
4308
        return 1;
4309

    
4310
    return 0;
4311
}
4312

    
4313
static void init_proc_970GX (CPUPPCState *env)
4314
{
4315
    gen_spr_ne_601(env);
4316
    gen_spr_7xx(env);
4317
    /* Time base */
4318
    gen_tbl(env);
4319
    /* Hardware implementation registers */
4320
    /* XXX : not implemented */
4321
    spr_register(env, SPR_HID0, "HID0",
4322
                 SPR_NOACCESS, SPR_NOACCESS,
4323
                 &spr_read_generic, &spr_write_clear,
4324
                 0x60000000);
4325
    /* XXX : not implemented */
4326
    spr_register(env, SPR_HID1, "HID1",
4327
                 SPR_NOACCESS, SPR_NOACCESS,
4328
                 &spr_read_generic, &spr_write_generic,
4329
                 0x00000000);
4330
    /* XXX : not implemented */
4331
    spr_register(env, SPR_750_HID2, "HID2",
4332
                 SPR_NOACCESS, SPR_NOACCESS,
4333
                 &spr_read_generic, &spr_write_generic,
4334
                 0x00000000);
4335
    /* XXX : not implemented */
4336
    spr_register(env, SPR_970_HID5, "HID5",
4337
                 SPR_NOACCESS, SPR_NOACCESS,
4338
                 &spr_read_generic, &spr_write_generic,
4339
                 POWERPC970_HID5_INIT);
4340
    /* Memory management */
4341
    /* XXX: not correct */
4342
    gen_low_BATs(env);
4343
    /* XXX : not implemented */
4344
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4345
                 SPR_NOACCESS, SPR_NOACCESS,
4346
                 &spr_read_generic, SPR_NOACCESS,
4347
                 0x00000000); /* TOFIX */
4348
    /* XXX : not implemented */
4349
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4350
                 SPR_NOACCESS, SPR_NOACCESS,
4351
                 &spr_read_generic, &spr_write_generic,
4352
                 0x00000000); /* TOFIX */
4353
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4354
                 SPR_NOACCESS, SPR_NOACCESS,
4355
                 &spr_read_generic, &spr_write_generic,
4356
                 0xFFF00000); /* XXX: This is a hack */
4357
#if !defined(CONFIG_USER_ONLY)
4358
    env->slb_nr = 32;
4359
#endif
4360
    init_excp_970(env);
4361
    env->dcache_line_size = 128;
4362
    env->icache_line_size = 128;
4363
    /* Allocate hardware IRQ controller */
4364
    ppc970_irq_init(env);
4365
}
4366

    
4367
/* PowerPC 970 MP                                                            */
4368
#define POWERPC_INSNS_970MP  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4369
                              PPC_64B | PPC_ALTIVEC |                         \
4370
                              PPC_SEGMENT_64B | PPC_SLBI)
4371
#define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
4372
#define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
4373
#define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
4374
#define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
4375
#define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
4376
#define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4377
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4378

    
4379
static int check_pow_970MP (CPUPPCState *env)
4380
{
4381
    if (env->spr[SPR_HID0] & 0x01C00000)
4382
        return 1;
4383

    
4384
    return 0;
4385
}
4386

    
4387
static void init_proc_970MP (CPUPPCState *env)
4388
{
4389
    gen_spr_ne_601(env);
4390
    gen_spr_7xx(env);
4391
    /* Time base */
4392
    gen_tbl(env);
4393
    /* Hardware implementation registers */
4394
    /* XXX : not implemented */
4395
    spr_register(env, SPR_HID0, "HID0",
4396
                 SPR_NOACCESS, SPR_NOACCESS,
4397
                 &spr_read_generic, &spr_write_clear,
4398
                 0x60000000);
4399
    /* XXX : not implemented */
4400
    spr_register(env, SPR_HID1, "HID1",
4401
                 SPR_NOACCESS, SPR_NOACCESS,
4402
                 &spr_read_generic, &spr_write_generic,
4403
                 0x00000000);
4404
    /* XXX : not implemented */
4405
    spr_register(env, SPR_750_HID2, "HID2",
4406
                 SPR_NOACCESS, SPR_NOACCESS,
4407
                 &spr_read_generic, &spr_write_generic,
4408
                 0x00000000);
4409
    /* XXX : not implemented */
4410
    spr_register(env, SPR_970_HID5, "HID5",
4411
                 SPR_NOACCESS, SPR_NOACCESS,
4412
                 &spr_read_generic, &spr_write_generic,
4413
                 POWERPC970_HID5_INIT);
4414
    /* Memory management */
4415
    /* XXX: not correct */
4416
    gen_low_BATs(env);
4417
    /* XXX : not implemented */
4418
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4419
                 SPR_NOACCESS, SPR_NOACCESS,
4420
                 &spr_read_generic, SPR_NOACCESS,
4421
                 0x00000000); /* TOFIX */
4422
    /* XXX : not implemented */
4423
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4424
                 SPR_NOACCESS, SPR_NOACCESS,
4425
                 &spr_read_generic, &spr_write_generic,
4426
                 0x00000000); /* TOFIX */
4427
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4428
                 SPR_NOACCESS, SPR_NOACCESS,
4429
                 &spr_read_generic, &spr_write_generic,
4430
                 0xFFF00000); /* XXX: This is a hack */
4431
#if !defined(CONFIG_USER_ONLY)
4432
    env->slb_nr = 32;
4433
#endif
4434
    init_excp_970(env);
4435
    env->dcache_line_size = 128;
4436
    env->icache_line_size = 128;
4437
    /* Allocate hardware IRQ controller */
4438
    ppc970_irq_init(env);
4439
}
4440

    
4441
/* PowerPC 620                                                               */
4442
#define POWERPC_INSNS_620    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
4443
                              PPC_64B | PPC_SLBI)
4444
#define POWERPC_MSRM_620     (0x800000000005FF73ULL)
4445
#define POWERPC_MMU_620      (POWERPC_MMU_64B)
4446
#define POWERPC_EXCP_620     (POWERPC_EXCP_970)
4447
#define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
4448
#define POWERPC_BFDM_620     (bfd_mach_ppc64)
4449
#define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
4450
#define check_pow_620        check_pow_nocheck /* Check this */
4451

    
4452
__attribute__ (( unused ))
4453
static void init_proc_620 (CPUPPCState *env)
4454
{
4455
    gen_spr_ne_601(env);
4456
    gen_spr_620(env);
4457
    /* Time base */
4458
    gen_tbl(env);
4459
    /* Hardware implementation registers */
4460
    /* XXX : not implemented */
4461
    spr_register(env, SPR_HID0, "HID0",
4462
                 SPR_NOACCESS, SPR_NOACCESS,
4463
                 &spr_read_generic, &spr_write_generic,
4464
                 0x00000000);
4465
    /* Memory management */
4466
    gen_low_BATs(env);
4467
    gen_high_BATs(env);
4468
    init_excp_620(env);
4469
    env->dcache_line_size = 64;
4470
    env->icache_line_size = 64;
4471
    /* Allocate hardware IRQ controller */
4472
    ppc6xx_irq_init(env);
4473
}
4474
#endif /* defined (TARGET_PPC64) */
4475

    
4476
/* Default 32 bits PowerPC target will be 604 */
4477
#define CPU_POWERPC_PPC32     CPU_POWERPC_604
4478
#define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
4479
#define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
4480
#define POWERPC_MMU_PPC32     POWERPC_MMU_604
4481
#define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
4482
#define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
4483
#define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
4484
#define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
4485
#define check_pow_PPC32       check_pow_604
4486
#define init_proc_PPC32       init_proc_604
4487

    
4488
/* Default 64 bits PowerPC target will be 970 FX */
4489
#define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
4490
#define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
4491
#define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
4492
#define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
4493
#define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
4494
#define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
4495
#define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
4496
#define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
4497
#define check_pow_PPC64       check_pow_970FX
4498
#define init_proc_PPC64       init_proc_970FX
4499

    
4500
/* Default PowerPC target will be PowerPC 32 */
4501
#if defined (TARGET_PPC64) && 0 // XXX: TODO
4502
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
4503
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4504
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
4505
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
4506
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
4507
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4508
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
4509
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
4510
#define check_pow_DEFAULT     check_pow_PPC64
4511
#define init_proc_DEFAULT     init_proc_PPC64
4512
#else
4513
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
4514
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4515
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
4516
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
4517
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
4518
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4519
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
4520
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
4521
#define check_pow_DEFAULT     check_pow_PPC32
4522
#define init_proc_DEFAULT     init_proc_PPC32
4523
#endif
4524

    
4525
/*****************************************************************************/
4526
/* PVR definitions for most known PowerPC                                    */
4527
enum {
4528
    /* PowerPC 401 family */
4529
    /* Generic PowerPC 401 */
4530
#define CPU_POWERPC_401       CPU_POWERPC_401G2
4531
    /* PowerPC 401 cores */
4532
    CPU_POWERPC_401A1       = 0x00210000,
4533
    CPU_POWERPC_401B2       = 0x00220000,
4534
#if 0
4535
    CPU_POWERPC_401B3       = xxx,
4536
#endif
4537
    CPU_POWERPC_401C2       = 0x00230000,
4538
    CPU_POWERPC_401D2       = 0x00240000,
4539
    CPU_POWERPC_401E2       = 0x00250000,
4540
    CPU_POWERPC_401F2       = 0x00260000,
4541
    CPU_POWERPC_401G2       = 0x00270000,
4542
    /* PowerPC 401 microcontrolers */
4543
#if 0
4544
    CPU_POWERPC_401GF       = xxx,
4545
#endif
4546
#define CPU_POWERPC_IOP480    CPU_POWERPC_401B2
4547
    /* IBM Processor for Network Resources */
4548
    CPU_POWERPC_COBRA       = 0x10100000, /* XXX: 405 ? */
4549
#if 0
4550
    CPU_POWERPC_XIPCHIP     = xxx,
4551
#endif
4552
    /* PowerPC 403 family */
4553
    /* Generic PowerPC 403 */
4554
#define CPU_POWERPC_403       CPU_POWERPC_403GC
4555
    /* PowerPC 403 microcontrollers */
4556
    CPU_POWERPC_403GA       = 0x00200011,
4557
    CPU_POWERPC_403GB       = 0x00200100,
4558
    CPU_POWERPC_403GC       = 0x00200200,
4559
    CPU_POWERPC_403GCX      = 0x00201400,
4560
#if 0
4561
    CPU_POWERPC_403GP       = xxx,
4562
#endif
4563
    /* PowerPC 405 family */
4564
    /* Generic PowerPC 405 */
4565
#define CPU_POWERPC_405       CPU_POWERPC_405D4
4566
    /* PowerPC 405 cores */
4567
#if 0
4568
    CPU_POWERPC_405A3       = xxx,
4569
#endif
4570
#if 0
4571
    CPU_POWERPC_405A4       = xxx,
4572
#endif
4573
#if 0
4574
    CPU_POWERPC_405B3       = xxx,
4575
#endif
4576
#if 0
4577
    CPU_POWERPC_405B4       = xxx,
4578
#endif
4579
#if 0
4580
    CPU_POWERPC_405C3       = xxx,
4581
#endif
4582
#if 0
4583
    CPU_POWERPC_405C4       = xxx,
4584
#endif
4585
    CPU_POWERPC_405D2       = 0x20010000,
4586
#if 0
4587
    CPU_POWERPC_405D3       = xxx,
4588
#endif
4589
    CPU_POWERPC_405D4       = 0x41810000,
4590
#if 0
4591
    CPU_POWERPC_405D5       = xxx,
4592
#endif
4593
#if 0
4594
    CPU_POWERPC_405E4       = xxx,
4595
#endif
4596
#if 0
4597
    CPU_POWERPC_405F4       = xxx,
4598
#endif
4599
#if 0
4600
    CPU_POWERPC_405F5       = xxx,
4601
#endif
4602
#if 0
4603
    CPU_POWERPC_405F6       = xxx,
4604
#endif
4605
    /* PowerPC 405 microcontrolers */
4606
    /* XXX: missing 0x200108a0 */
4607
#define CPU_POWERPC_405CR     CPU_POWERPC_405CRc
4608
    CPU_POWERPC_405CRa      = 0x40110041,
4609
    CPU_POWERPC_405CRb      = 0x401100C5,
4610
    CPU_POWERPC_405CRc      = 0x40110145,
4611
    CPU_POWERPC_405EP       = 0x51210950,
4612
#if 0
4613
    CPU_POWERPC_405EXr      = xxx,
4614
#endif
4615
    CPU_POWERPC_405EZ       = 0x41511460, /* 0x51210950 ? */
4616
#if 0
4617
    CPU_POWERPC_405FX       = xxx,
4618
#endif
4619
#define CPU_POWERPC_405GP     CPU_POWERPC_405GPd
4620
    CPU_POWERPC_405GPa      = 0x40110000,
4621
    CPU_POWERPC_405GPb      = 0x40110040,
4622
    CPU_POWERPC_405GPc      = 0x40110082,
4623
    CPU_POWERPC_405GPd      = 0x401100C4,
4624
#define CPU_POWERPC_405GPe    CPU_POWERPC_405CRc
4625
    CPU_POWERPC_405GPR      = 0x50910951,
4626
#if 0
4627
    CPU_POWERPC_405H        = xxx,
4628
#endif
4629
#if 0
4630
    CPU_POWERPC_405L        = xxx,
4631
#endif
4632
    CPU_POWERPC_405LP       = 0x41F10000,
4633
#if 0
4634
    CPU_POWERPC_405PM       = xxx,
4635
#endif
4636
#if 0
4637
    CPU_POWERPC_405PS       = xxx,
4638
#endif
4639
#if 0
4640
    CPU_POWERPC_405S        = xxx,
4641
#endif
4642
    /* IBM network processors */
4643
    CPU_POWERPC_NPE405H     = 0x414100C0,
4644
    CPU_POWERPC_NPE405H2    = 0x41410140,
4645
    CPU_POWERPC_NPE405L     = 0x416100C0,
4646
    CPU_POWERPC_NPE4GS3     = 0x40B10000,
4647
#if 0
4648
    CPU_POWERPC_NPCxx1      = xxx,
4649
#endif
4650
#if 0
4651
    CPU_POWERPC_NPR161      = xxx,
4652
#endif
4653
#if 0
4654
    CPU_POWERPC_LC77700     = xxx,
4655
#endif
4656
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4657
#if 0
4658
    CPU_POWERPC_STB01000    = xxx,
4659
#endif
4660
#if 0
4661
    CPU_POWERPC_STB01010    = xxx,
4662
#endif
4663
#if 0
4664
    CPU_POWERPC_STB0210     = xxx, /* 401B3 */
4665
#endif
4666
    CPU_POWERPC_STB03       = 0x40310000, /* 0x40130000 ? */
4667
#if 0
4668
    CPU_POWERPC_STB043      = xxx,
4669
#endif
4670
#if 0
4671
    CPU_POWERPC_STB045      = xxx,
4672
#endif
4673
    CPU_POWERPC_STB04       = 0x41810000,
4674
    CPU_POWERPC_STB25       = 0x51510950,
4675
#if 0
4676
    CPU_POWERPC_STB130      = xxx,
4677
#endif
4678
    /* Xilinx cores */
4679
    CPU_POWERPC_X2VP4       = 0x20010820,
4680
#define CPU_POWERPC_X2VP7     CPU_POWERPC_X2VP4
4681
    CPU_POWERPC_X2VP20      = 0x20010860,
4682
#define CPU_POWERPC_X2VP50    CPU_POWERPC_X2VP20
4683
#if 0
4684
    CPU_POWERPC_ZL10310     = xxx,
4685
#endif
4686
#if 0
4687
    CPU_POWERPC_ZL10311     = xxx,
4688
#endif
4689
#if 0
4690
    CPU_POWERPC_ZL10320     = xxx,
4691
#endif
4692
#if 0
4693
    CPU_POWERPC_ZL10321     = xxx,
4694
#endif
4695
    /* PowerPC 440 family */
4696
    /* Generic PowerPC 440 */
4697
#define CPU_POWERPC_440       CPU_POWERPC_440GXf
4698
    /* PowerPC 440 cores */
4699
#if 0
4700
    CPU_POWERPC_440A4       = xxx,
4701
#endif
4702
#if 0
4703
    CPU_POWERPC_440A5       = xxx,
4704
#endif
4705
#if 0
4706
    CPU_POWERPC_440B4       = xxx,
4707
#endif
4708
#if 0
4709
    CPU_POWERPC_440F5       = xxx,
4710
#endif
4711
#if 0
4712
    CPU_POWERPC_440G5       = xxx,
4713
#endif
4714
#if 0
4715
    CPU_POWERPC_440H4       = xxx,
4716
#endif
4717
#if 0
4718
    CPU_POWERPC_440H6       = xxx,
4719
#endif
4720
    /* PowerPC 440 microcontrolers */
4721
#define CPU_POWERPC_440EP     CPU_POWERPC_440EPb
4722
    CPU_POWERPC_440EPa      = 0x42221850,
4723
    CPU_POWERPC_440EPb      = 0x422218D3,
4724
#define CPU_POWERPC_440GP     CPU_POWERPC_440GPc
4725
    CPU_POWERPC_440GPb      = 0x40120440,
4726
    CPU_POWERPC_440GPc      = 0x40120481,
4727
#define CPU_POWERPC_440GR     CPU_POWERPC_440GRa
4728
#define CPU_POWERPC_440GRa    CPU_POWERPC_440EPb
4729
    CPU_POWERPC_440GRX      = 0x200008D0,
4730
#define CPU_POWERPC_440EPX    CPU_POWERPC_440GRX
4731
#d