root / target-ppc / helper.c @ 1b9eb036
History | View | Annotate | Download (54.4 kB)
1 |
/*
|
---|---|
2 |
* PowerPC emulation helpers for qemu.
|
3 |
*
|
4 |
* Copyright (c) 2003-2007 Jocelyn Mayer
|
5 |
*
|
6 |
* This library is free software; you can redistribute it and/or
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
8 |
* License as published by the Free Software Foundation; either
|
9 |
* version 2 of the License, or (at your option) any later version.
|
10 |
*
|
11 |
* This library is distributed in the hope that it will be useful,
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
* Lesser General Public License for more details.
|
15 |
*
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
17 |
* License along with this library; if not, write to the Free Software
|
18 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 |
*/
|
20 |
#include <stdarg.h> |
21 |
#include <stdlib.h> |
22 |
#include <stdio.h> |
23 |
#include <string.h> |
24 |
#include <inttypes.h> |
25 |
#include <signal.h> |
26 |
#include <assert.h> |
27 |
|
28 |
#include "cpu.h" |
29 |
#include "exec-all.h" |
30 |
|
31 |
//#define DEBUG_MMU
|
32 |
//#define DEBUG_BATS
|
33 |
//#define DEBUG_SOFTWARE_TLB
|
34 |
//#define DEBUG_EXCEPTIONS
|
35 |
//#define FLUSH_ALL_TLBS
|
36 |
|
37 |
/*****************************************************************************/
|
38 |
/* PowerPC MMU emulation */
|
39 |
|
40 |
#if defined(CONFIG_USER_ONLY)
|
41 |
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
42 |
int is_user, int is_softmmu) |
43 |
{ |
44 |
int exception, error_code;
|
45 |
|
46 |
if (rw == 2) { |
47 |
exception = EXCP_ISI; |
48 |
error_code = 0;
|
49 |
} else {
|
50 |
exception = EXCP_DSI; |
51 |
error_code = 0;
|
52 |
if (rw)
|
53 |
error_code |= 0x02000000;
|
54 |
env->spr[SPR_DAR] = address; |
55 |
env->spr[SPR_DSISR] = error_code; |
56 |
} |
57 |
env->exception_index = exception; |
58 |
env->error_code = error_code; |
59 |
|
60 |
return 1; |
61 |
} |
62 |
|
63 |
target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
64 |
{ |
65 |
return addr;
|
66 |
} |
67 |
#else
|
68 |
/* Common routines used by software and hardware TLBs emulation */
|
69 |
static inline int pte_is_valid (target_ulong pte0) |
70 |
{ |
71 |
return pte0 & 0x80000000 ? 1 : 0; |
72 |
} |
73 |
|
74 |
static inline void pte_invalidate (target_ulong *pte0) |
75 |
{ |
76 |
*pte0 &= ~0x80000000;
|
77 |
} |
78 |
|
79 |
#define PTE_PTEM_MASK 0x7FFFFFBF |
80 |
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
81 |
|
82 |
static int pte_check (mmu_ctx_t *ctx, |
83 |
target_ulong pte0, target_ulong pte1, int h, int rw) |
84 |
{ |
85 |
int access, ret;
|
86 |
|
87 |
access = 0;
|
88 |
ret = -1;
|
89 |
/* Check validity and table match */
|
90 |
if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) { |
91 |
/* Check vsid & api */
|
92 |
if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
|
93 |
if (ctx->raddr != (target_ulong)-1) { |
94 |
/* all matches should have equal RPN, WIMG & PP */
|
95 |
if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
|
96 |
if (loglevel > 0) |
97 |
fprintf(logfile, "Bad RPN/WIMG/PP\n");
|
98 |
return -3; |
99 |
} |
100 |
} |
101 |
/* Compute access rights */
|
102 |
if (ctx->key == 0) { |
103 |
access = PAGE_READ; |
104 |
if ((pte1 & 0x00000003) != 0x3) |
105 |
access |= PAGE_WRITE; |
106 |
} else {
|
107 |
switch (pte1 & 0x00000003) { |
108 |
case 0x0: |
109 |
access = 0;
|
110 |
break;
|
111 |
case 0x1: |
112 |
case 0x3: |
113 |
access = PAGE_READ; |
114 |
break;
|
115 |
case 0x2: |
116 |
access = PAGE_READ | PAGE_WRITE; |
117 |
break;
|
118 |
} |
119 |
} |
120 |
/* Keep the matching PTE informations */
|
121 |
ctx->raddr = pte1; |
122 |
ctx->prot = access; |
123 |
if ((rw == 0 && (access & PAGE_READ)) || |
124 |
(rw == 1 && (access & PAGE_WRITE))) {
|
125 |
/* Access granted */
|
126 |
#if defined (DEBUG_MMU)
|
127 |
if (loglevel > 0) |
128 |
fprintf(logfile, "PTE access granted !\n");
|
129 |
#endif
|
130 |
ret = 0;
|
131 |
} else {
|
132 |
/* Access right violation */
|
133 |
#if defined (DEBUG_MMU)
|
134 |
if (loglevel > 0) |
135 |
fprintf(logfile, "PTE access rejected\n");
|
136 |
#endif
|
137 |
ret = -2;
|
138 |
} |
139 |
} |
140 |
} |
141 |
|
142 |
return ret;
|
143 |
} |
144 |
|
145 |
static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
146 |
int ret, int rw) |
147 |
{ |
148 |
int store = 0; |
149 |
|
150 |
/* Update page flags */
|
151 |
if (!(*pte1p & 0x00000100)) { |
152 |
/* Update accessed flag */
|
153 |
*pte1p |= 0x00000100;
|
154 |
store = 1;
|
155 |
} |
156 |
if (!(*pte1p & 0x00000080)) { |
157 |
if (rw == 1 && ret == 0) { |
158 |
/* Update changed flag */
|
159 |
*pte1p |= 0x00000080;
|
160 |
store = 1;
|
161 |
} else {
|
162 |
/* Force page fault for first write access */
|
163 |
ctx->prot &= ~PAGE_WRITE; |
164 |
} |
165 |
} |
166 |
|
167 |
return store;
|
168 |
} |
169 |
|
170 |
/* Software driven TLB helpers */
|
171 |
static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
172 |
int way, int is_code) |
173 |
{ |
174 |
int nr;
|
175 |
|
176 |
/* Select TLB num in a way from address */
|
177 |
nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
|
178 |
/* Select TLB way */
|
179 |
nr += env->tlb_per_way * way; |
180 |
/* 6xx have separate TLBs for instructions and data */
|
181 |
if (is_code && env->id_tlbs == 1) |
182 |
nr += env->nb_tlb; |
183 |
|
184 |
return nr;
|
185 |
} |
186 |
|
187 |
void ppc6xx_tlb_invalidate_all (CPUState *env)
|
188 |
{ |
189 |
ppc_tlb_t *tlb; |
190 |
int nr, max;
|
191 |
|
192 |
#if defined (DEBUG_SOFTWARE_TLB) && 0 |
193 |
if (loglevel != 0) { |
194 |
fprintf(logfile, "Invalidate all TLBs\n");
|
195 |
} |
196 |
#endif
|
197 |
/* Invalidate all defined software TLB */
|
198 |
max = env->nb_tlb; |
199 |
if (env->id_tlbs == 1) |
200 |
max *= 2;
|
201 |
for (nr = 0; nr < max; nr++) { |
202 |
tlb = &env->tlb[nr]; |
203 |
#if !defined(FLUSH_ALL_TLBS)
|
204 |
tlb_flush_page(env, tlb->EPN); |
205 |
#endif
|
206 |
pte_invalidate(&tlb->pte0); |
207 |
} |
208 |
#if defined(FLUSH_ALL_TLBS)
|
209 |
tlb_flush(env, 1);
|
210 |
#endif
|
211 |
} |
212 |
|
213 |
static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
214 |
target_ulong eaddr, |
215 |
int is_code, int match_epn) |
216 |
{ |
217 |
ppc_tlb_t *tlb; |
218 |
int way, nr;
|
219 |
|
220 |
#if !defined(FLUSH_ALL_TLBS)
|
221 |
/* Invalidate ITLB + DTLB, all ways */
|
222 |
for (way = 0; way < env->nb_ways; way++) { |
223 |
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
224 |
tlb = &env->tlb[nr]; |
225 |
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
226 |
#if defined (DEBUG_SOFTWARE_TLB)
|
227 |
if (loglevel != 0) { |
228 |
fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
229 |
nr, env->nb_tlb, eaddr); |
230 |
} |
231 |
#endif
|
232 |
pte_invalidate(&tlb->pte0); |
233 |
tlb_flush_page(env, tlb->EPN); |
234 |
} |
235 |
} |
236 |
#else
|
237 |
/* XXX: PowerPC specification say this is valid as well */
|
238 |
ppc6xx_tlb_invalidate_all(env); |
239 |
#endif
|
240 |
} |
241 |
|
242 |
void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
|
243 |
int is_code)
|
244 |
{ |
245 |
__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
246 |
} |
247 |
|
248 |
void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
249 |
target_ulong pte0, target_ulong pte1) |
250 |
{ |
251 |
ppc_tlb_t *tlb; |
252 |
int nr;
|
253 |
|
254 |
nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
255 |
tlb = &env->tlb[nr]; |
256 |
#if defined (DEBUG_SOFTWARE_TLB)
|
257 |
if (loglevel != 0) { |
258 |
fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
259 |
" PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
260 |
} |
261 |
#endif
|
262 |
/* Invalidate any pending reference in Qemu for this virtual address */
|
263 |
__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
264 |
tlb->pte0 = pte0; |
265 |
tlb->pte1 = pte1; |
266 |
tlb->EPN = EPN; |
267 |
tlb->PID = 0;
|
268 |
tlb->size = 1;
|
269 |
/* Store last way for LRU mechanism */
|
270 |
env->last_way = way; |
271 |
} |
272 |
|
273 |
static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
274 |
target_ulong eaddr, int rw, int access_type) |
275 |
{ |
276 |
ppc_tlb_t *tlb; |
277 |
int nr, best, way;
|
278 |
int ret;
|
279 |
|
280 |
best = -1;
|
281 |
ret = -1; /* No TLB found */ |
282 |
for (way = 0; way < env->nb_ways; way++) { |
283 |
nr = ppc6xx_tlb_getnum(env, eaddr, way, |
284 |
access_type == ACCESS_CODE ? 1 : 0); |
285 |
tlb = &env->tlb[nr]; |
286 |
/* This test "emulates" the PTE index match for hardware TLBs */
|
287 |
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
288 |
#if defined (DEBUG_SOFTWARE_TLB)
|
289 |
if (loglevel != 0) { |
290 |
fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
291 |
"] <> " ADDRX "\n", |
292 |
nr, env->nb_tlb, |
293 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
294 |
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
295 |
} |
296 |
#endif
|
297 |
continue;
|
298 |
} |
299 |
#if defined (DEBUG_SOFTWARE_TLB)
|
300 |
if (loglevel != 0) { |
301 |
fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
302 |
" %c %c\n",
|
303 |
nr, env->nb_tlb, |
304 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
305 |
tlb->EPN, eaddr, tlb->pte1, |
306 |
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
307 |
} |
308 |
#endif
|
309 |
switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) { |
310 |
case -3: |
311 |
/* TLB inconsistency */
|
312 |
return -1; |
313 |
case -2: |
314 |
/* Access violation */
|
315 |
ret = -2;
|
316 |
best = nr; |
317 |
break;
|
318 |
case -1: |
319 |
default:
|
320 |
/* No match */
|
321 |
break;
|
322 |
case 0: |
323 |
/* access granted */
|
324 |
/* XXX: we should go on looping to check all TLBs consistency
|
325 |
* but we can speed-up the whole thing as the
|
326 |
* result would be undefined if TLBs are not consistent.
|
327 |
*/
|
328 |
ret = 0;
|
329 |
best = nr; |
330 |
goto done;
|
331 |
} |
332 |
} |
333 |
if (best != -1) { |
334 |
done:
|
335 |
#if defined (DEBUG_SOFTWARE_TLB)
|
336 |
if (loglevel > 0) { |
337 |
fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
|
338 |
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
339 |
} |
340 |
#endif
|
341 |
/* Update page flags */
|
342 |
pte_update_flags(ctx, &env->tlb[best].pte1, ret, rw); |
343 |
} |
344 |
|
345 |
return ret;
|
346 |
} |
347 |
|
348 |
/* Perform BAT hit & translation */
|
349 |
static int get_bat (CPUState *env, mmu_ctx_t *ctx, |
350 |
target_ulong virtual, int rw, int type) |
351 |
{ |
352 |
target_ulong *BATlt, *BATut, *BATu, *BATl; |
353 |
target_ulong base, BEPIl, BEPIu, bl; |
354 |
int i;
|
355 |
int ret = -1; |
356 |
|
357 |
#if defined (DEBUG_BATS)
|
358 |
if (loglevel > 0) { |
359 |
fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
360 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
361 |
} |
362 |
#endif
|
363 |
switch (type) {
|
364 |
case ACCESS_CODE:
|
365 |
BATlt = env->IBAT[1];
|
366 |
BATut = env->IBAT[0];
|
367 |
break;
|
368 |
default:
|
369 |
BATlt = env->DBAT[1];
|
370 |
BATut = env->DBAT[0];
|
371 |
break;
|
372 |
} |
373 |
#if defined (DEBUG_BATS)
|
374 |
if (loglevel > 0) { |
375 |
fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
376 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
377 |
} |
378 |
#endif
|
379 |
base = virtual & 0xFFFC0000;
|
380 |
for (i = 0; i < 4; i++) { |
381 |
BATu = &BATut[i]; |
382 |
BATl = &BATlt[i]; |
383 |
BEPIu = *BATu & 0xF0000000;
|
384 |
BEPIl = *BATu & 0x0FFE0000;
|
385 |
bl = (*BATu & 0x00001FFC) << 15; |
386 |
#if defined (DEBUG_BATS)
|
387 |
if (loglevel > 0) { |
388 |
fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
389 |
" BATl 0x" ADDRX "\n", |
390 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
391 |
*BATu, *BATl); |
392 |
} |
393 |
#endif
|
394 |
if ((virtual & 0xF0000000) == BEPIu && |
395 |
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
396 |
/* BAT matches */
|
397 |
if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
398 |
(msr_pr == 1 && (*BATu & 0x00000001))) { |
399 |
/* Get physical address */
|
400 |
ctx->raddr = (*BATl & 0xF0000000) |
|
401 |
((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
402 |
(virtual & 0x0001F000);
|
403 |
if (*BATl & 0x00000001) |
404 |
ctx->prot = PAGE_READ; |
405 |
if (*BATl & 0x00000002) |
406 |
ctx->prot = PAGE_WRITE | PAGE_READ; |
407 |
#if defined (DEBUG_BATS)
|
408 |
if (loglevel > 0) { |
409 |
fprintf(logfile, "BAT %d match: r 0x" ADDRX
|
410 |
" prot=%c%c\n",
|
411 |
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
412 |
ctx->prot & PAGE_WRITE ? 'W' : '-'); |
413 |
} |
414 |
#endif
|
415 |
ret = 0;
|
416 |
break;
|
417 |
} |
418 |
} |
419 |
} |
420 |
if (ret < 0) { |
421 |
#if defined (DEBUG_BATS)
|
422 |
printf("no BAT match for 0x" ADDRX ":\n", virtual); |
423 |
for (i = 0; i < 4; i++) { |
424 |
BATu = &BATut[i]; |
425 |
BATl = &BATlt[i]; |
426 |
BEPIu = *BATu & 0xF0000000;
|
427 |
BEPIl = *BATu & 0x0FFE0000;
|
428 |
bl = (*BATu & 0x00001FFC) << 15; |
429 |
printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
430 |
" BATl 0x" ADDRX " \n\t" |
431 |
"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", |
432 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
433 |
*BATu, *BATl, BEPIu, BEPIl, bl); |
434 |
} |
435 |
#endif
|
436 |
} |
437 |
/* No hit */
|
438 |
return ret;
|
439 |
} |
440 |
|
441 |
/* PTE table lookup */
|
442 |
static int find_pte (mmu_ctx_t *ctx, int h, int rw) |
443 |
{ |
444 |
target_ulong base, pte0, pte1; |
445 |
int i, good = -1; |
446 |
int ret;
|
447 |
|
448 |
ret = -1; /* No entry found */ |
449 |
base = ctx->pg_addr[h]; |
450 |
for (i = 0; i < 8; i++) { |
451 |
pte0 = ldl_phys(base + (i * 8));
|
452 |
pte1 = ldl_phys(base + (i * 8) + 4); |
453 |
#if defined (DEBUG_MMU)
|
454 |
if (loglevel > 0) { |
455 |
fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
456 |
" 0x" ADDRX " %d %d %d 0x" ADDRX "\n", |
457 |
base + (i * 8), pte0, pte1,
|
458 |
pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem); |
459 |
} |
460 |
#endif
|
461 |
switch (pte_check(ctx, pte0, pte1, h, rw)) {
|
462 |
case -3: |
463 |
/* PTE inconsistency */
|
464 |
return -1; |
465 |
case -2: |
466 |
/* Access violation */
|
467 |
ret = -2;
|
468 |
good = i; |
469 |
break;
|
470 |
case -1: |
471 |
default:
|
472 |
/* No PTE match */
|
473 |
break;
|
474 |
case 0: |
475 |
/* access granted */
|
476 |
/* XXX: we should go on looping to check all PTEs consistency
|
477 |
* but if we can speed-up the whole thing as the
|
478 |
* result would be undefined if PTEs are not consistent.
|
479 |
*/
|
480 |
ret = 0;
|
481 |
good = i; |
482 |
goto done;
|
483 |
} |
484 |
} |
485 |
if (good != -1) { |
486 |
done:
|
487 |
#if defined (DEBUG_MMU)
|
488 |
if (loglevel > 0) { |
489 |
fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x " |
490 |
"ret=%d\n",
|
491 |
ctx->raddr, ctx->prot, ret); |
492 |
} |
493 |
#endif
|
494 |
/* Update page flags */
|
495 |
pte1 = ctx->raddr; |
496 |
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) |
497 |
stl_phys_notdirty(base + (good * 8) + 4, pte1); |
498 |
} |
499 |
|
500 |
return ret;
|
501 |
} |
502 |
|
503 |
static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1, |
504 |
target_phys_addr_t hash, |
505 |
target_phys_addr_t mask) |
506 |
{ |
507 |
return (sdr1 & 0xFFFF0000) | (hash & mask); |
508 |
} |
509 |
|
510 |
/* Perform segment based translation */
|
511 |
static int get_segment (CPUState *env, mmu_ctx_t *ctx, |
512 |
target_ulong eaddr, int rw, int type) |
513 |
{ |
514 |
target_phys_addr_t sdr, hash, mask; |
515 |
target_ulong sr, vsid, pgidx; |
516 |
int ret = -1, ret2; |
517 |
|
518 |
sr = env->sr[eaddr >> 28];
|
519 |
#if defined (DEBUG_MMU)
|
520 |
if (loglevel > 0) { |
521 |
fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x" |
522 |
ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n", |
523 |
eaddr, eaddr >> 28, sr, env->nip,
|
524 |
env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
525 |
} |
526 |
#endif
|
527 |
ctx->key = (((sr & 0x20000000) && msr_pr == 1) || |
528 |
((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
529 |
if ((sr & 0x80000000) == 0) { |
530 |
#if defined (DEBUG_MMU)
|
531 |
if (loglevel > 0) |
532 |
fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n", |
533 |
ctx->key, sr & 0x10000000);
|
534 |
#endif
|
535 |
/* Check if instruction fetch is allowed, if needed */
|
536 |
if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { |
537 |
/* Page address translation */
|
538 |
pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
|
539 |
vsid = sr & 0x00FFFFFF;
|
540 |
hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6; |
541 |
/* Primary table address */
|
542 |
sdr = env->sdr1; |
543 |
mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
544 |
ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
|
545 |
/* Secondary table address */
|
546 |
hash = (~hash) & 0x01FFFFC0;
|
547 |
ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
|
548 |
ctx->ptem = (vsid << 7) | (pgidx >> 10); |
549 |
/* Initialize real address with an invalid value */
|
550 |
ctx->raddr = (target_ulong)-1;
|
551 |
if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
|
552 |
/* Software TLB search */
|
553 |
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
554 |
} else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) { |
555 |
/* XXX: TODO */
|
556 |
} else {
|
557 |
#if defined (DEBUG_MMU)
|
558 |
if (loglevel > 0) { |
559 |
fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x " |
560 |
"api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n", |
561 |
sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
|
562 |
} |
563 |
#endif
|
564 |
/* Primary table lookup */
|
565 |
ret = find_pte(ctx, 0, rw);
|
566 |
if (ret < 0) { |
567 |
/* Secondary table lookup */
|
568 |
#if defined (DEBUG_MMU)
|
569 |
if (eaddr != 0xEFFFFFFF && loglevel > 0) { |
570 |
fprintf(logfile, |
571 |
"1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x " |
572 |
"hash=0x%05x pg_addr=0x" ADDRX "\n", |
573 |
sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
|
574 |
} |
575 |
#endif
|
576 |
ret2 = find_pte(ctx, 1, rw);
|
577 |
if (ret2 != -1) |
578 |
ret = ret2; |
579 |
} |
580 |
} |
581 |
} else {
|
582 |
#if defined (DEBUG_MMU)
|
583 |
if (loglevel > 0) |
584 |
fprintf(logfile, "No access allowed\n");
|
585 |
#endif
|
586 |
ret = -3;
|
587 |
} |
588 |
} else {
|
589 |
#if defined (DEBUG_MMU)
|
590 |
if (loglevel > 0) |
591 |
fprintf(logfile, "direct store...\n");
|
592 |
#endif
|
593 |
/* Direct-store segment : absolutely *BUGGY* for now */
|
594 |
switch (type) {
|
595 |
case ACCESS_INT:
|
596 |
/* Integer load/store : only access allowed */
|
597 |
break;
|
598 |
case ACCESS_CODE:
|
599 |
/* No code fetch is allowed in direct-store areas */
|
600 |
return -4; |
601 |
case ACCESS_FLOAT:
|
602 |
/* Floating point load/store */
|
603 |
return -4; |
604 |
case ACCESS_RES:
|
605 |
/* lwarx, ldarx or srwcx. */
|
606 |
return -4; |
607 |
case ACCESS_CACHE:
|
608 |
/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
609 |
/* Should make the instruction do no-op.
|
610 |
* As it already do no-op, it's quite easy :-)
|
611 |
*/
|
612 |
ctx->raddr = eaddr; |
613 |
return 0; |
614 |
case ACCESS_EXT:
|
615 |
/* eciwx or ecowx */
|
616 |
return -4; |
617 |
default:
|
618 |
if (logfile) {
|
619 |
fprintf(logfile, "ERROR: instruction should not need "
|
620 |
"address translation\n");
|
621 |
} |
622 |
printf("ERROR: instruction should not need "
|
623 |
"address translation\n");
|
624 |
return -4; |
625 |
} |
626 |
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
627 |
ctx->raddr = eaddr; |
628 |
ret = 2;
|
629 |
} else {
|
630 |
ret = -2;
|
631 |
} |
632 |
} |
633 |
|
634 |
return ret;
|
635 |
} |
636 |
|
637 |
static int check_physical (CPUState *env, mmu_ctx_t *ctx, |
638 |
target_ulong eaddr, int rw)
|
639 |
{ |
640 |
int in_plb, ret;
|
641 |
|
642 |
ctx->raddr = eaddr; |
643 |
ctx->prot = PAGE_READ; |
644 |
ret = 0;
|
645 |
if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) { |
646 |
/* 403 family add some particular protections,
|
647 |
* using PBL/PBU registers for accesses with no translation.
|
648 |
*/
|
649 |
in_plb = |
650 |
/* Check PLB validity */
|
651 |
(env->pb[0] < env->pb[1] && |
652 |
/* and address in plb area */
|
653 |
eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
654 |
(env->pb[2] < env->pb[3] && |
655 |
eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
656 |
if (in_plb ^ msr_px) {
|
657 |
/* Access in protected area */
|
658 |
if (rw == 1) { |
659 |
/* Access is not allowed */
|
660 |
ret = -2;
|
661 |
} |
662 |
} else {
|
663 |
/* Read-write access is allowed */
|
664 |
ctx->prot |= PAGE_WRITE; |
665 |
} |
666 |
} else {
|
667 |
ctx->prot |= PAGE_WRITE; |
668 |
} |
669 |
|
670 |
return ret;
|
671 |
} |
672 |
|
673 |
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
674 |
int rw, int access_type, int check_BATs) |
675 |
{ |
676 |
int ret;
|
677 |
#if 0
|
678 |
if (loglevel > 0) {
|
679 |
fprintf(logfile, "%s\n", __func__);
|
680 |
}
|
681 |
#endif
|
682 |
if ((access_type == ACCESS_CODE && msr_ir == 0) || |
683 |
(access_type != ACCESS_CODE && msr_dr == 0)) {
|
684 |
/* No address translation */
|
685 |
ret = check_physical(env, ctx, eaddr, rw); |
686 |
} else {
|
687 |
/* Try to find a BAT */
|
688 |
ret = -1;
|
689 |
if (check_BATs)
|
690 |
ret = get_bat(env, ctx, eaddr, rw, access_type); |
691 |
if (ret < 0) { |
692 |
/* We didn't match any BAT entry */
|
693 |
ret = get_segment(env, ctx, eaddr, rw, access_type); |
694 |
} |
695 |
} |
696 |
#if 0
|
697 |
if (loglevel > 0) {
|
698 |
fprintf(logfile, "%s address " ADDRX " => " ADDRX "\n",
|
699 |
__func__, eaddr, ctx->raddr);
|
700 |
}
|
701 |
#endif
|
702 |
|
703 |
return ret;
|
704 |
} |
705 |
|
706 |
target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
707 |
{ |
708 |
mmu_ctx_t ctx; |
709 |
|
710 |
if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0)) |
711 |
return -1; |
712 |
|
713 |
return ctx.raddr & TARGET_PAGE_MASK;
|
714 |
} |
715 |
|
716 |
/* Perform address translation */
|
717 |
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
718 |
int is_user, int is_softmmu) |
719 |
{ |
720 |
mmu_ctx_t ctx; |
721 |
int exception = 0, error_code = 0; |
722 |
int access_type;
|
723 |
int ret = 0; |
724 |
|
725 |
if (rw == 2) { |
726 |
/* code access */
|
727 |
rw = 0;
|
728 |
access_type = ACCESS_CODE; |
729 |
} else {
|
730 |
/* data access */
|
731 |
/* XXX: put correct access by using cpu_restore_state()
|
732 |
correctly */
|
733 |
access_type = ACCESS_INT; |
734 |
// access_type = env->access_type;
|
735 |
} |
736 |
ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
|
737 |
if (ret == 0) { |
738 |
ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
739 |
ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
740 |
is_user, is_softmmu); |
741 |
} else if (ret < 0) { |
742 |
#if defined (DEBUG_MMU)
|
743 |
if (loglevel > 0) |
744 |
cpu_dump_state(env, logfile, fprintf, 0);
|
745 |
#endif
|
746 |
if (access_type == ACCESS_CODE) {
|
747 |
exception = EXCP_ISI; |
748 |
switch (ret) {
|
749 |
case -1: |
750 |
/* No matches in page tables or TLB */
|
751 |
if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
|
752 |
exception = EXCP_I_TLBMISS; |
753 |
env->spr[SPR_IMISS] = address; |
754 |
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
755 |
error_code = 1 << 18; |
756 |
goto tlb_miss;
|
757 |
} else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) { |
758 |
/* XXX: TODO */
|
759 |
} else {
|
760 |
error_code = 0x40000000;
|
761 |
} |
762 |
break;
|
763 |
case -2: |
764 |
/* Access rights violation */
|
765 |
error_code = 0x08000000;
|
766 |
break;
|
767 |
case -3: |
768 |
/* No execute protection violation */
|
769 |
error_code = 0x10000000;
|
770 |
break;
|
771 |
case -4: |
772 |
/* Direct store exception */
|
773 |
/* No code fetch is allowed in direct-store areas */
|
774 |
error_code = 0x10000000;
|
775 |
break;
|
776 |
case -5: |
777 |
/* No match in segment table */
|
778 |
exception = EXCP_ISEG; |
779 |
error_code = 0;
|
780 |
break;
|
781 |
} |
782 |
} else {
|
783 |
exception = EXCP_DSI; |
784 |
switch (ret) {
|
785 |
case -1: |
786 |
/* No matches in page tables or TLB */
|
787 |
if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
|
788 |
if (rw == 1) { |
789 |
exception = EXCP_DS_TLBMISS; |
790 |
error_code = 1 << 16; |
791 |
} else {
|
792 |
exception = EXCP_DL_TLBMISS; |
793 |
error_code = 0;
|
794 |
} |
795 |
env->spr[SPR_DMISS] = address; |
796 |
env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
797 |
tlb_miss:
|
798 |
error_code |= ctx.key << 19;
|
799 |
env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
800 |
env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
801 |
/* Do not alter DAR nor DSISR */
|
802 |
goto out;
|
803 |
} else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) { |
804 |
/* XXX: TODO */
|
805 |
} else {
|
806 |
error_code = 0x40000000;
|
807 |
} |
808 |
break;
|
809 |
case -2: |
810 |
/* Access rights violation */
|
811 |
error_code = 0x08000000;
|
812 |
break;
|
813 |
case -4: |
814 |
/* Direct store exception */
|
815 |
switch (access_type) {
|
816 |
case ACCESS_FLOAT:
|
817 |
/* Floating point load/store */
|
818 |
exception = EXCP_ALIGN; |
819 |
error_code = EXCP_ALIGN_FP; |
820 |
break;
|
821 |
case ACCESS_RES:
|
822 |
/* lwarx, ldarx or srwcx. */
|
823 |
error_code = 0x04000000;
|
824 |
break;
|
825 |
case ACCESS_EXT:
|
826 |
/* eciwx or ecowx */
|
827 |
error_code = 0x04100000;
|
828 |
break;
|
829 |
default:
|
830 |
printf("DSI: invalid exception (%d)\n", ret);
|
831 |
exception = EXCP_PROGRAM; |
832 |
error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
833 |
break;
|
834 |
} |
835 |
break;
|
836 |
case -5: |
837 |
/* No match in segment table */
|
838 |
exception = EXCP_DSEG; |
839 |
error_code = 0;
|
840 |
break;
|
841 |
} |
842 |
if (exception == EXCP_DSI && rw == 1) |
843 |
error_code |= 0x02000000;
|
844 |
/* Store fault address */
|
845 |
env->spr[SPR_DAR] = address; |
846 |
env->spr[SPR_DSISR] = error_code; |
847 |
} |
848 |
out:
|
849 |
#if 0
|
850 |
printf("%s: set exception to %d %02x\n",
|
851 |
__func__, exception, error_code);
|
852 |
#endif
|
853 |
env->exception_index = exception; |
854 |
env->error_code = error_code; |
855 |
ret = 1;
|
856 |
} |
857 |
|
858 |
return ret;
|
859 |
} |
860 |
|
861 |
/*****************************************************************************/
|
862 |
/* BATs management */
|
863 |
#if !defined(FLUSH_ALL_TLBS)
|
864 |
static inline void do_invalidate_BAT (CPUPPCState *env, |
865 |
target_ulong BATu, target_ulong mask) |
866 |
{ |
867 |
target_ulong base, end, page; |
868 |
|
869 |
base = BATu & ~0x0001FFFF;
|
870 |
end = base + mask + 0x00020000;
|
871 |
#if defined (DEBUG_BATS)
|
872 |
if (loglevel != 0) { |
873 |
fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
874 |
base, end, mask); |
875 |
} |
876 |
#endif
|
877 |
for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
878 |
tlb_flush_page(env, page); |
879 |
#if defined (DEBUG_BATS)
|
880 |
if (loglevel != 0) |
881 |
fprintf(logfile, "Flush done\n");
|
882 |
#endif
|
883 |
} |
884 |
#endif
|
885 |
|
886 |
static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr, |
887 |
target_ulong value) |
888 |
{ |
889 |
#if defined (DEBUG_BATS)
|
890 |
if (loglevel != 0) { |
891 |
fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n", |
892 |
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
893 |
} |
894 |
#endif
|
895 |
} |
896 |
|
897 |
target_ulong do_load_ibatu (CPUPPCState *env, int nr)
|
898 |
{ |
899 |
return env->IBAT[0][nr]; |
900 |
} |
901 |
|
902 |
target_ulong do_load_ibatl (CPUPPCState *env, int nr)
|
903 |
{ |
904 |
return env->IBAT[1][nr]; |
905 |
} |
906 |
|
907 |
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
908 |
{ |
909 |
target_ulong mask; |
910 |
|
911 |
dump_store_bat(env, 'I', 0, nr, value); |
912 |
if (env->IBAT[0][nr] != value) { |
913 |
mask = (value << 15) & 0x0FFE0000UL; |
914 |
#if !defined(FLUSH_ALL_TLBS)
|
915 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
916 |
#endif
|
917 |
/* When storing valid upper BAT, mask BEPI and BRPN
|
918 |
* and invalidate all TLBs covered by this BAT
|
919 |
*/
|
920 |
mask = (value << 15) & 0x0FFE0000UL; |
921 |
env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
922 |
(value & ~0x0001FFFFUL & ~mask);
|
923 |
env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
924 |
(env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
925 |
#if !defined(FLUSH_ALL_TLBS)
|
926 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
927 |
#else
|
928 |
tlb_flush(env, 1);
|
929 |
#endif
|
930 |
} |
931 |
} |
932 |
|
933 |
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
934 |
{ |
935 |
dump_store_bat(env, 'I', 1, nr, value); |
936 |
env->IBAT[1][nr] = value;
|
937 |
} |
938 |
|
939 |
target_ulong do_load_dbatu (CPUPPCState *env, int nr)
|
940 |
{ |
941 |
return env->DBAT[0][nr]; |
942 |
} |
943 |
|
944 |
target_ulong do_load_dbatl (CPUPPCState *env, int nr)
|
945 |
{ |
946 |
return env->DBAT[1][nr]; |
947 |
} |
948 |
|
949 |
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
950 |
{ |
951 |
target_ulong mask; |
952 |
|
953 |
dump_store_bat(env, 'D', 0, nr, value); |
954 |
if (env->DBAT[0][nr] != value) { |
955 |
/* When storing valid upper BAT, mask BEPI and BRPN
|
956 |
* and invalidate all TLBs covered by this BAT
|
957 |
*/
|
958 |
mask = (value << 15) & 0x0FFE0000UL; |
959 |
#if !defined(FLUSH_ALL_TLBS)
|
960 |
do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
961 |
#endif
|
962 |
mask = (value << 15) & 0x0FFE0000UL; |
963 |
env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
964 |
(value & ~0x0001FFFFUL & ~mask);
|
965 |
env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
966 |
(env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
967 |
#if !defined(FLUSH_ALL_TLBS)
|
968 |
do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
969 |
#else
|
970 |
tlb_flush(env, 1);
|
971 |
#endif
|
972 |
} |
973 |
} |
974 |
|
975 |
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
976 |
{ |
977 |
dump_store_bat(env, 'D', 1, nr, value); |
978 |
env->DBAT[1][nr] = value;
|
979 |
} |
980 |
|
981 |
/*****************************************************************************/
|
982 |
/* Special registers manipulation */
|
983 |
#if defined(TARGET_PPC64)
|
984 |
target_ulong ppc_load_asr (CPUPPCState *env) |
985 |
{ |
986 |
return env->asr;
|
987 |
} |
988 |
|
989 |
void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
990 |
{ |
991 |
if (env->asr != value) {
|
992 |
env->asr = value; |
993 |
tlb_flush(env, 1);
|
994 |
} |
995 |
} |
996 |
#endif
|
997 |
|
998 |
target_ulong do_load_sdr1 (CPUPPCState *env) |
999 |
{ |
1000 |
return env->sdr1;
|
1001 |
} |
1002 |
|
1003 |
void do_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1004 |
{ |
1005 |
#if defined (DEBUG_MMU)
|
1006 |
if (loglevel != 0) { |
1007 |
fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value); |
1008 |
} |
1009 |
#endif
|
1010 |
if (env->sdr1 != value) {
|
1011 |
env->sdr1 = value; |
1012 |
tlb_flush(env, 1);
|
1013 |
} |
1014 |
} |
1015 |
|
1016 |
target_ulong do_load_sr (CPUPPCState *env, int srnum)
|
1017 |
{ |
1018 |
return env->sr[srnum];
|
1019 |
} |
1020 |
|
1021 |
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1022 |
{ |
1023 |
#if defined (DEBUG_MMU)
|
1024 |
if (loglevel != 0) { |
1025 |
fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n", |
1026 |
__func__, srnum, value, env->sr[srnum]); |
1027 |
} |
1028 |
#endif
|
1029 |
if (env->sr[srnum] != value) {
|
1030 |
env->sr[srnum] = value; |
1031 |
#if !defined(FLUSH_ALL_TLBS) && 0 |
1032 |
{ |
1033 |
target_ulong page, end; |
1034 |
/* Invalidate 256 MB of virtual memory */
|
1035 |
page = (16 << 20) * srnum; |
1036 |
end = page + (16 << 20); |
1037 |
for (; page != end; page += TARGET_PAGE_SIZE)
|
1038 |
tlb_flush_page(env, page); |
1039 |
} |
1040 |
#else
|
1041 |
tlb_flush(env, 1);
|
1042 |
#endif
|
1043 |
} |
1044 |
} |
1045 |
#endif /* !defined (CONFIG_USER_ONLY) */ |
1046 |
|
1047 |
uint32_t ppc_load_xer (CPUPPCState *env) |
1048 |
{ |
1049 |
return (xer_so << XER_SO) |
|
1050 |
(xer_ov << XER_OV) | |
1051 |
(xer_ca << XER_CA) | |
1052 |
(xer_bc << XER_BC) | |
1053 |
(xer_cmp << XER_CMP); |
1054 |
} |
1055 |
|
1056 |
void ppc_store_xer (CPUPPCState *env, uint32_t value)
|
1057 |
{ |
1058 |
xer_so = (value >> XER_SO) & 0x01;
|
1059 |
xer_ov = (value >> XER_OV) & 0x01;
|
1060 |
xer_ca = (value >> XER_CA) & 0x01;
|
1061 |
xer_cmp = (value >> XER_CMP) & 0xFF;
|
1062 |
xer_bc = (value >> XER_BC) & 0x7F;
|
1063 |
} |
1064 |
|
1065 |
/* Swap temporary saved registers with GPRs */
|
1066 |
static inline void swap_gpr_tgpr (CPUPPCState *env) |
1067 |
{ |
1068 |
ppc_gpr_t tmp; |
1069 |
|
1070 |
tmp = env->gpr[0];
|
1071 |
env->gpr[0] = env->tgpr[0]; |
1072 |
env->tgpr[0] = tmp;
|
1073 |
tmp = env->gpr[1];
|
1074 |
env->gpr[1] = env->tgpr[1]; |
1075 |
env->tgpr[1] = tmp;
|
1076 |
tmp = env->gpr[2];
|
1077 |
env->gpr[2] = env->tgpr[2]; |
1078 |
env->tgpr[2] = tmp;
|
1079 |
tmp = env->gpr[3];
|
1080 |
env->gpr[3] = env->tgpr[3]; |
1081 |
env->tgpr[3] = tmp;
|
1082 |
} |
1083 |
|
1084 |
/* GDBstub can read and write MSR... */
|
1085 |
target_ulong do_load_msr (CPUPPCState *env) |
1086 |
{ |
1087 |
return
|
1088 |
#if defined (TARGET_PPC64)
|
1089 |
((target_ulong)msr_sf << MSR_SF) | |
1090 |
((target_ulong)msr_isf << MSR_ISF) | |
1091 |
((target_ulong)msr_hv << MSR_HV) | |
1092 |
#endif
|
1093 |
((target_ulong)msr_ucle << MSR_UCLE) | |
1094 |
((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
|
1095 |
((target_ulong)msr_ap << MSR_AP) | |
1096 |
((target_ulong)msr_sa << MSR_SA) | |
1097 |
((target_ulong)msr_key << MSR_KEY) | |
1098 |
((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
|
1099 |
((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
|
1100 |
((target_ulong)msr_ile << MSR_ILE) | |
1101 |
((target_ulong)msr_ee << MSR_EE) | |
1102 |
((target_ulong)msr_pr << MSR_PR) | |
1103 |
((target_ulong)msr_fp << MSR_FP) | |
1104 |
((target_ulong)msr_me << MSR_ME) | |
1105 |
((target_ulong)msr_fe0 << MSR_FE0) | |
1106 |
((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
|
1107 |
((target_ulong)msr_be << MSR_BE) | /* BE / DE */
|
1108 |
((target_ulong)msr_fe1 << MSR_FE1) | |
1109 |
((target_ulong)msr_al << MSR_AL) | |
1110 |
((target_ulong)msr_ip << MSR_IP) | |
1111 |
((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
|
1112 |
((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
|
1113 |
((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
|
1114 |
((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
|
1115 |
((target_ulong)msr_ri << MSR_RI) | |
1116 |
((target_ulong)msr_le << MSR_LE); |
1117 |
} |
1118 |
|
1119 |
void do_store_msr (CPUPPCState *env, target_ulong value)
|
1120 |
{ |
1121 |
int enter_pm;
|
1122 |
|
1123 |
value &= env->msr_mask; |
1124 |
if (((value >> MSR_IR) & 1) != msr_ir || |
1125 |
((value >> MSR_DR) & 1) != msr_dr) {
|
1126 |
/* Flush all tlb when changing translation mode */
|
1127 |
tlb_flush(env, 1);
|
1128 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1129 |
} |
1130 |
#if 0
|
1131 |
if (loglevel != 0) {
|
1132 |
fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
|
1133 |
}
|
1134 |
#endif
|
1135 |
switch (PPC_EXCP(env)) {
|
1136 |
case PPC_FLAGS_EXCP_602:
|
1137 |
case PPC_FLAGS_EXCP_603:
|
1138 |
if (((value >> MSR_TGPR) & 1) != msr_tgpr) { |
1139 |
/* Swap temporary saved registers with GPRs */
|
1140 |
swap_gpr_tgpr(env); |
1141 |
} |
1142 |
break;
|
1143 |
default:
|
1144 |
break;
|
1145 |
} |
1146 |
#if defined (TARGET_PPC64)
|
1147 |
msr_sf = (value >> MSR_SF) & 1;
|
1148 |
msr_isf = (value >> MSR_ISF) & 1;
|
1149 |
msr_hv = (value >> MSR_HV) & 1;
|
1150 |
#endif
|
1151 |
msr_ucle = (value >> MSR_UCLE) & 1;
|
1152 |
msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */ |
1153 |
msr_ap = (value >> MSR_AP) & 1;
|
1154 |
msr_sa = (value >> MSR_SA) & 1;
|
1155 |
msr_key = (value >> MSR_KEY) & 1;
|
1156 |
msr_pow = (value >> MSR_POW) & 1; /* POW / WE */ |
1157 |
msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */ |
1158 |
msr_ile = (value >> MSR_ILE) & 1;
|
1159 |
msr_ee = (value >> MSR_EE) & 1;
|
1160 |
msr_pr = (value >> MSR_PR) & 1;
|
1161 |
msr_fp = (value >> MSR_FP) & 1;
|
1162 |
msr_me = (value >> MSR_ME) & 1;
|
1163 |
msr_fe0 = (value >> MSR_FE0) & 1;
|
1164 |
msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */ |
1165 |
msr_be = (value >> MSR_BE) & 1; /* BE / DE */ |
1166 |
msr_fe1 = (value >> MSR_FE1) & 1;
|
1167 |
msr_al = (value >> MSR_AL) & 1;
|
1168 |
msr_ip = (value >> MSR_IP) & 1;
|
1169 |
msr_ir = (value >> MSR_IR) & 1; /* IR / IS */ |
1170 |
msr_dr = (value >> MSR_DR) & 1; /* DR / DS */ |
1171 |
msr_pe = (value >> MSR_PE) & 1; /* PE / EP */ |
1172 |
msr_px = (value >> MSR_PX) & 1; /* PX / PMM */ |
1173 |
msr_ri = (value >> MSR_RI) & 1;
|
1174 |
msr_le = (value >> MSR_LE) & 1;
|
1175 |
do_compute_hflags(env); |
1176 |
|
1177 |
enter_pm = 0;
|
1178 |
switch (PPC_EXCP(env)) {
|
1179 |
case PPC_FLAGS_EXCP_603:
|
1180 |
/* Don't handle SLEEP mode: we should disable all clocks...
|
1181 |
* No dynamic power-management.
|
1182 |
*/
|
1183 |
if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0) |
1184 |
enter_pm = 1;
|
1185 |
break;
|
1186 |
case PPC_FLAGS_EXCP_604:
|
1187 |
if (msr_pow == 1) |
1188 |
enter_pm = 1;
|
1189 |
break;
|
1190 |
case PPC_FLAGS_EXCP_7x0:
|
1191 |
if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0) |
1192 |
enter_pm = 1;
|
1193 |
break;
|
1194 |
default:
|
1195 |
break;
|
1196 |
} |
1197 |
if (enter_pm) {
|
1198 |
/* power save: exit cpu loop */
|
1199 |
env->halted = 1;
|
1200 |
env->exception_index = EXCP_HLT; |
1201 |
cpu_loop_exit(); |
1202 |
} |
1203 |
} |
1204 |
|
1205 |
#if defined(TARGET_PPC64)
|
1206 |
void ppc_store_msr_32 (CPUPPCState *env, target_ulong value)
|
1207 |
{ |
1208 |
do_store_msr(env, (uint32_t)value); |
1209 |
} |
1210 |
#endif
|
1211 |
|
1212 |
void do_compute_hflags (CPUPPCState *env)
|
1213 |
{ |
1214 |
/* Compute current hflags */
|
1215 |
env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) | |
1216 |
(msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) | |
1217 |
(msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | |
1218 |
(msr_se << MSR_SE) | (msr_be << MSR_BE); |
1219 |
#if defined (TARGET_PPC64)
|
1220 |
env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32)); |
1221 |
#endif
|
1222 |
} |
1223 |
|
1224 |
/*****************************************************************************/
|
1225 |
/* Exception processing */
|
1226 |
#if defined (CONFIG_USER_ONLY)
|
1227 |
void do_interrupt (CPUState *env)
|
1228 |
{ |
1229 |
env->exception_index = -1;
|
1230 |
} |
1231 |
#else /* defined (CONFIG_USER_ONLY) */ |
1232 |
static void dump_syscall(CPUState *env) |
1233 |
{ |
1234 |
fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX |
1235 |
" r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n", |
1236 |
env->gpr[0], env->gpr[3], env->gpr[4], |
1237 |
env->gpr[5], env->gpr[6], env->nip); |
1238 |
} |
1239 |
|
1240 |
void do_interrupt (CPUState *env)
|
1241 |
{ |
1242 |
target_ulong msr, *srr_0, *srr_1; |
1243 |
int excp;
|
1244 |
|
1245 |
excp = env->exception_index; |
1246 |
msr = do_load_msr(env); |
1247 |
/* The default is to use SRR0 & SRR1 to save the exception context */
|
1248 |
srr_0 = &env->spr[SPR_SRR0]; |
1249 |
srr_1 = &env->spr[SPR_SRR1]; |
1250 |
#if defined (DEBUG_EXCEPTIONS)
|
1251 |
if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) { |
1252 |
if (loglevel != 0) { |
1253 |
fprintf(logfile, |
1254 |
"Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
1255 |
env->nip, excp, env->error_code); |
1256 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1257 |
} |
1258 |
} |
1259 |
#endif
|
1260 |
if (loglevel & CPU_LOG_INT) {
|
1261 |
fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
1262 |
env->nip, excp, env->error_code); |
1263 |
} |
1264 |
msr_pow = 0;
|
1265 |
/* Generate informations in save/restore registers */
|
1266 |
switch (excp) {
|
1267 |
/* Generic PowerPC exceptions */
|
1268 |
case EXCP_RESET: /* 0x0100 */ |
1269 |
if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
|
1270 |
if (msr_ip)
|
1271 |
excp += 0xFFC00;
|
1272 |
excp |= 0xFFC00000;
|
1273 |
} else {
|
1274 |
srr_0 = &env->spr[SPR_40x_SRR2]; |
1275 |
srr_1 = &env->spr[SPR_40x_SRR3]; |
1276 |
} |
1277 |
goto store_next;
|
1278 |
case EXCP_MACHINE_CHECK: /* 0x0200 */ |
1279 |
if (msr_me == 0) { |
1280 |
cpu_abort(env, "Machine check exception while not allowed\n");
|
1281 |
} |
1282 |
if (unlikely(PPC_EXCP(env) == PPC_FLAGS_EXCP_40x)) {
|
1283 |
srr_0 = &env->spr[SPR_40x_SRR2]; |
1284 |
srr_1 = &env->spr[SPR_40x_SRR3]; |
1285 |
} |
1286 |
msr_me = 0;
|
1287 |
break;
|
1288 |
case EXCP_DSI: /* 0x0300 */ |
1289 |
/* Store exception cause */
|
1290 |
/* data location address has been stored
|
1291 |
* when the fault has been detected
|
1292 |
*/
|
1293 |
msr &= ~0xFFFF0000;
|
1294 |
#if defined (DEBUG_EXCEPTIONS)
|
1295 |
if (loglevel) {
|
1296 |
fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
1297 |
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
1298 |
} else {
|
1299 |
printf("DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX "\n", |
1300 |
env->spr[SPR_DSISR], env->spr[SPR_DAR]); |
1301 |
} |
1302 |
#endif
|
1303 |
goto store_next;
|
1304 |
case EXCP_ISI: /* 0x0400 */ |
1305 |
/* Store exception cause */
|
1306 |
msr &= ~0xFFFF0000;
|
1307 |
msr |= env->error_code; |
1308 |
#if defined (DEBUG_EXCEPTIONS)
|
1309 |
if (loglevel != 0) { |
1310 |
fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX |
1311 |
"\n", msr, env->nip);
|
1312 |
} |
1313 |
#endif
|
1314 |
goto store_next;
|
1315 |
case EXCP_EXTERNAL: /* 0x0500 */ |
1316 |
if (msr_ee == 0) { |
1317 |
#if defined (DEBUG_EXCEPTIONS)
|
1318 |
if (loglevel > 0) { |
1319 |
fprintf(logfile, "Skipping hardware interrupt\n");
|
1320 |
} |
1321 |
#endif
|
1322 |
/* Requeue it */
|
1323 |
env->interrupt_request |= CPU_INTERRUPT_HARD; |
1324 |
return;
|
1325 |
} |
1326 |
goto store_next;
|
1327 |
case EXCP_ALIGN: /* 0x0600 */ |
1328 |
if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
|
1329 |
/* Store exception cause */
|
1330 |
/* Get rS/rD and rA from faulting opcode */
|
1331 |
env->spr[SPR_DSISR] |= |
1332 |
(ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
1333 |
/* data location address has been stored
|
1334 |
* when the fault has been detected
|
1335 |
*/
|
1336 |
} else {
|
1337 |
/* IO error exception on PowerPC 601 */
|
1338 |
/* XXX: TODO */
|
1339 |
cpu_abort(env, |
1340 |
"601 IO error exception is not implemented yet !\n");
|
1341 |
} |
1342 |
goto store_current;
|
1343 |
case EXCP_PROGRAM: /* 0x0700 */ |
1344 |
msr &= ~0xFFFF0000;
|
1345 |
switch (env->error_code & ~0xF) { |
1346 |
case EXCP_FP:
|
1347 |
if (msr_fe0 == 0 && msr_fe1 == 0) { |
1348 |
#if defined (DEBUG_EXCEPTIONS)
|
1349 |
printf("Ignore floating point exception\n");
|
1350 |
#endif
|
1351 |
return;
|
1352 |
} |
1353 |
msr |= 0x00100000;
|
1354 |
/* Set FX */
|
1355 |
env->fpscr[7] |= 0x8; |
1356 |
/* Finally, update FEX */
|
1357 |
if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
1358 |
((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
1359 |
env->fpscr[7] |= 0x4; |
1360 |
break;
|
1361 |
case EXCP_INVAL:
|
1362 |
// printf("Invalid instruction at 0x" ADDRX "\n", env->nip);
|
1363 |
msr |= 0x00080000;
|
1364 |
break;
|
1365 |
case EXCP_PRIV:
|
1366 |
msr |= 0x00040000;
|
1367 |
break;
|
1368 |
case EXCP_TRAP:
|
1369 |
msr |= 0x00020000;
|
1370 |
break;
|
1371 |
default:
|
1372 |
/* Should never occur */
|
1373 |
break;
|
1374 |
} |
1375 |
msr |= 0x00010000;
|
1376 |
goto store_current;
|
1377 |
case EXCP_NO_FP: /* 0x0800 */ |
1378 |
msr &= ~0xFFFF0000;
|
1379 |
goto store_current;
|
1380 |
case EXCP_DECR:
|
1381 |
if (msr_ee == 0) { |
1382 |
#if 1 |
1383 |
/* Requeue it */
|
1384 |
env->interrupt_request |= CPU_INTERRUPT_TIMER; |
1385 |
#endif
|
1386 |
return;
|
1387 |
} |
1388 |
goto store_next;
|
1389 |
case EXCP_SYSCALL: /* 0x0C00 */ |
1390 |
/* NOTE: this is a temporary hack to support graphics OSI
|
1391 |
calls from the MOL driver */
|
1392 |
if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
1393 |
env->osi_call) { |
1394 |
if (env->osi_call(env) != 0) |
1395 |
return;
|
1396 |
} |
1397 |
if (loglevel & CPU_LOG_INT) {
|
1398 |
dump_syscall(env); |
1399 |
} |
1400 |
goto store_next;
|
1401 |
case EXCP_TRACE: /* 0x0D00 */ |
1402 |
goto store_next;
|
1403 |
case EXCP_PERF: /* 0x0F00 */ |
1404 |
/* XXX: TODO */
|
1405 |
cpu_abort(env, |
1406 |
"Performance counter exception is not implemented yet !\n");
|
1407 |
goto store_next;
|
1408 |
/* 32 bits PowerPC specific exceptions */
|
1409 |
case EXCP_FP_ASSIST: /* 0x0E00 */ |
1410 |
/* XXX: TODO */
|
1411 |
cpu_abort(env, "Floating point assist exception "
|
1412 |
"is not implemented yet !\n");
|
1413 |
goto store_next;
|
1414 |
/* 64 bits PowerPC exceptions */
|
1415 |
case EXCP_DSEG: /* 0x0380 */ |
1416 |
/* XXX: TODO */
|
1417 |
cpu_abort(env, "Data segment exception is not implemented yet !\n");
|
1418 |
goto store_next;
|
1419 |
case EXCP_ISEG: /* 0x0480 */ |
1420 |
/* XXX: TODO */
|
1421 |
cpu_abort(env, |
1422 |
"Instruction segment exception is not implemented yet !\n");
|
1423 |
goto store_next;
|
1424 |
case EXCP_HDECR: /* 0x0980 */ |
1425 |
if (msr_ee == 0) { |
1426 |
#if 1 |
1427 |
/* Requeue it */
|
1428 |
env->interrupt_request |= CPU_INTERRUPT_TIMER; |
1429 |
#endif
|
1430 |
return;
|
1431 |
} |
1432 |
/* XXX: TODO */
|
1433 |
cpu_abort(env, "Hypervisor decrementer exception is not implemented "
|
1434 |
"yet !\n");
|
1435 |
goto store_next;
|
1436 |
/* Implementation specific exceptions */
|
1437 |
case 0x0A00: |
1438 |
if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
|
1439 |
env->spr[SPR_PVR] == CPU_PPC_G2LE)) { |
1440 |
/* Critical interrupt on G2 */
|
1441 |
/* XXX: TODO */
|
1442 |
cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
|
1443 |
goto store_next;
|
1444 |
} else {
|
1445 |
cpu_abort(env, "Invalid exception 0x0A00 !\n");
|
1446 |
} |
1447 |
return;
|
1448 |
case 0x0F20: |
1449 |
switch (PPC_EXCP(env)) {
|
1450 |
case PPC_FLAGS_EXCP_40x:
|
1451 |
/* APU unavailable on 405 */
|
1452 |
/* XXX: TODO */
|
1453 |
cpu_abort(env, |
1454 |
"APU unavailable exception is not implemented yet !\n");
|
1455 |
goto store_next;
|
1456 |
case PPC_FLAGS_EXCP_74xx:
|
1457 |
/* Altivec unavailable */
|
1458 |
/* XXX: TODO */
|
1459 |
cpu_abort(env, "Altivec unavailable exception "
|
1460 |
"is not implemented yet !\n");
|
1461 |
goto store_next;
|
1462 |
default:
|
1463 |
cpu_abort(env, "Invalid exception 0x0F20 !\n");
|
1464 |
break;
|
1465 |
} |
1466 |
return;
|
1467 |
case 0x1000: |
1468 |
switch (PPC_EXCP(env)) {
|
1469 |
case PPC_FLAGS_EXCP_40x:
|
1470 |
/* PIT on 4xx */
|
1471 |
/* XXX: TODO */
|
1472 |
cpu_abort(env, "40x PIT exception is not implemented yet !\n");
|
1473 |
goto store_next;
|
1474 |
case PPC_FLAGS_EXCP_602:
|
1475 |
case PPC_FLAGS_EXCP_603:
|
1476 |
/* ITLBMISS on 602/603 */
|
1477 |
goto store_gprs;
|
1478 |
case PPC_FLAGS_EXCP_7x5:
|
1479 |
/* ITLBMISS on 745/755 */
|
1480 |
goto tlb_miss;
|
1481 |
default:
|
1482 |
cpu_abort(env, "Invalid exception 0x1000 !\n");
|
1483 |
break;
|
1484 |
} |
1485 |
return;
|
1486 |
case 0x1010: |
1487 |
switch (PPC_EXCP(env)) {
|
1488 |
case PPC_FLAGS_EXCP_40x:
|
1489 |
/* FIT on 4xx */
|
1490 |
/* XXX: TODO */
|
1491 |
cpu_abort(env, "40x FIT exception is not implemented yet !\n");
|
1492 |
goto store_next;
|
1493 |
default:
|
1494 |
cpu_abort(env, "Invalid exception 0x1010 !\n");
|
1495 |
break;
|
1496 |
} |
1497 |
return;
|
1498 |
case 0x1020: |
1499 |
switch (PPC_EXCP(env)) {
|
1500 |
case PPC_FLAGS_EXCP_40x:
|
1501 |
/* Watchdog on 4xx */
|
1502 |
/* XXX: TODO */
|
1503 |
cpu_abort(env, |
1504 |
"40x watchdog exception is not implemented yet !\n");
|
1505 |
goto store_next;
|
1506 |
default:
|
1507 |
cpu_abort(env, "Invalid exception 0x1020 !\n");
|
1508 |
break;
|
1509 |
} |
1510 |
return;
|
1511 |
case 0x1100: |
1512 |
switch (PPC_EXCP(env)) {
|
1513 |
case PPC_FLAGS_EXCP_40x:
|
1514 |
/* DTLBMISS on 4xx */
|
1515 |
/* XXX: TODO */
|
1516 |
cpu_abort(env, |
1517 |
"40x DTLBMISS exception is not implemented yet !\n");
|
1518 |
goto store_next;
|
1519 |
case PPC_FLAGS_EXCP_602:
|
1520 |
case PPC_FLAGS_EXCP_603:
|
1521 |
/* DLTLBMISS on 602/603 */
|
1522 |
goto store_gprs;
|
1523 |
case PPC_FLAGS_EXCP_7x5:
|
1524 |
/* DLTLBMISS on 745/755 */
|
1525 |
goto tlb_miss;
|
1526 |
default:
|
1527 |
cpu_abort(env, "Invalid exception 0x1100 !\n");
|
1528 |
break;
|
1529 |
} |
1530 |
return;
|
1531 |
case 0x1200: |
1532 |
switch (PPC_EXCP(env)) {
|
1533 |
case PPC_FLAGS_EXCP_40x:
|
1534 |
/* ITLBMISS on 4xx */
|
1535 |
/* XXX: TODO */
|
1536 |
cpu_abort(env, |
1537 |
"40x ITLBMISS exception is not implemented yet !\n");
|
1538 |
goto store_next;
|
1539 |
case PPC_FLAGS_EXCP_602:
|
1540 |
case PPC_FLAGS_EXCP_603:
|
1541 |
/* DSTLBMISS on 602/603 */
|
1542 |
store_gprs:
|
1543 |
/* Swap temporary saved registers with GPRs */
|
1544 |
swap_gpr_tgpr(env); |
1545 |
msr_tgpr = 1;
|
1546 |
#if defined (DEBUG_SOFTWARE_TLB)
|
1547 |
if (loglevel != 0) { |
1548 |
const unsigned char *es; |
1549 |
target_ulong *miss, *cmp; |
1550 |
int en;
|
1551 |
if (excp == 0x1000) { |
1552 |
es = "I";
|
1553 |
en = 'I';
|
1554 |
miss = &env->spr[SPR_IMISS]; |
1555 |
cmp = &env->spr[SPR_ICMP]; |
1556 |
} else {
|
1557 |
if (excp == 0x1100) |
1558 |
es = "DL";
|
1559 |
else
|
1560 |
es = "DS";
|
1561 |
en = 'D';
|
1562 |
miss = &env->spr[SPR_DMISS]; |
1563 |
cmp = &env->spr[SPR_DCMP]; |
1564 |
} |
1565 |
fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
1566 |
" H1 " ADDRX " H2 " ADDRX " " ADDRX "\n", |
1567 |
es, en, *miss, en, *cmp, |
1568 |
env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
1569 |
env->error_code); |
1570 |
} |
1571 |
#endif
|
1572 |
goto tlb_miss;
|
1573 |
case PPC_FLAGS_EXCP_7x5:
|
1574 |
/* DSTLBMISS on 745/755 */
|
1575 |
tlb_miss:
|
1576 |
msr &= ~0xF83F0000;
|
1577 |
msr |= env->crf[0] << 28; |
1578 |
msr |= env->error_code; /* key, D/I, S/L bits */
|
1579 |
/* Set way using a LRU mechanism */
|
1580 |
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
1581 |
goto store_next;
|
1582 |
default:
|
1583 |
cpu_abort(env, "Invalid exception 0x1200 !\n");
|
1584 |
break;
|
1585 |
} |
1586 |
return;
|
1587 |
case 0x1300: |
1588 |
switch (PPC_EXCP(env)) {
|
1589 |
case PPC_FLAGS_EXCP_601:
|
1590 |
case PPC_FLAGS_EXCP_602:
|
1591 |
case PPC_FLAGS_EXCP_603:
|
1592 |
case PPC_FLAGS_EXCP_604:
|
1593 |
case PPC_FLAGS_EXCP_7x0:
|
1594 |
case PPC_FLAGS_EXCP_7x5:
|
1595 |
/* IABR on 6xx/7xx */
|
1596 |
/* XXX: TODO */
|
1597 |
cpu_abort(env, "IABR exception is not implemented yet !\n");
|
1598 |
goto store_next;
|
1599 |
default:
|
1600 |
cpu_abort(env, "Invalid exception 0x1300 !\n");
|
1601 |
break;
|
1602 |
} |
1603 |
return;
|
1604 |
case 0x1400: |
1605 |
switch (PPC_EXCP(env)) {
|
1606 |
case PPC_FLAGS_EXCP_601:
|
1607 |
case PPC_FLAGS_EXCP_602:
|
1608 |
case PPC_FLAGS_EXCP_603:
|
1609 |
case PPC_FLAGS_EXCP_604:
|
1610 |
case PPC_FLAGS_EXCP_7x0:
|
1611 |
case PPC_FLAGS_EXCP_7x5:
|
1612 |
/* SMI on 6xx/7xx */
|
1613 |
/* XXX: TODO */
|
1614 |
cpu_abort(env, "SMI exception is not implemented yet !\n");
|
1615 |
goto store_next;
|
1616 |
default:
|
1617 |
cpu_abort(env, "Invalid exception 0x1400 !\n");
|
1618 |
break;
|
1619 |
} |
1620 |
return;
|
1621 |
case 0x1500: |
1622 |
switch (PPC_EXCP(env)) {
|
1623 |
case PPC_FLAGS_EXCP_602:
|
1624 |
/* Watchdog on 602 */
|
1625 |
/* XXX: TODO */
|
1626 |
cpu_abort(env, |
1627 |
"602 watchdog exception is not implemented yet !\n");
|
1628 |
goto store_next;
|
1629 |
case PPC_FLAGS_EXCP_970:
|
1630 |
/* Soft patch exception on 970 */
|
1631 |
/* XXX: TODO */
|
1632 |
cpu_abort(env, |
1633 |
"970 soft-patch exception is not implemented yet !\n");
|
1634 |
goto store_next;
|
1635 |
case PPC_FLAGS_EXCP_74xx:
|
1636 |
/* VPU assist on 74xx */
|
1637 |
/* XXX: TODO */
|
1638 |
cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
1639 |
goto store_next;
|
1640 |
default:
|
1641 |
cpu_abort(env, "Invalid exception 0x1500 !\n");
|
1642 |
break;
|
1643 |
} |
1644 |
return;
|
1645 |
case 0x1600: |
1646 |
switch (PPC_EXCP(env)) {
|
1647 |
case PPC_FLAGS_EXCP_602:
|
1648 |
/* Emulation trap on 602 */
|
1649 |
/* XXX: TODO */
|
1650 |
cpu_abort(env, "602 emulation trap exception "
|
1651 |
"is not implemented yet !\n");
|
1652 |
goto store_next;
|
1653 |
case PPC_FLAGS_EXCP_970:
|
1654 |
/* Maintenance exception on 970 */
|
1655 |
/* XXX: TODO */
|
1656 |
cpu_abort(env, |
1657 |
"970 maintenance exception is not implemented yet !\n");
|
1658 |
goto store_next;
|
1659 |
default:
|
1660 |
cpu_abort(env, "Invalid exception 0x1600 !\n");
|
1661 |
break;
|
1662 |
} |
1663 |
return;
|
1664 |
case 0x1700: |
1665 |
switch (PPC_EXCP(env)) {
|
1666 |
case PPC_FLAGS_EXCP_7x0:
|
1667 |
case PPC_FLAGS_EXCP_7x5:
|
1668 |
/* Thermal management interrupt on G3 */
|
1669 |
/* XXX: TODO */
|
1670 |
cpu_abort(env, "G3 thermal management exception "
|
1671 |
"is not implemented yet !\n");
|
1672 |
goto store_next;
|
1673 |
case PPC_FLAGS_EXCP_970:
|
1674 |
/* VPU assist on 970 */
|
1675 |
/* XXX: TODO */
|
1676 |
cpu_abort(env, |
1677 |
"970 VPU assist exception is not implemented yet !\n");
|
1678 |
goto store_next;
|
1679 |
default:
|
1680 |
cpu_abort(env, "Invalid exception 0x1700 !\n");
|
1681 |
break;
|
1682 |
} |
1683 |
return;
|
1684 |
case 0x1800: |
1685 |
switch (PPC_EXCP(env)) {
|
1686 |
case PPC_FLAGS_EXCP_970:
|
1687 |
/* Thermal exception on 970 */
|
1688 |
/* XXX: TODO */
|
1689 |
cpu_abort(env, "970 thermal management exception "
|
1690 |
"is not implemented yet !\n");
|
1691 |
goto store_next;
|
1692 |
default:
|
1693 |
cpu_abort(env, "Invalid exception 0x1800 !\n");
|
1694 |
break;
|
1695 |
} |
1696 |
return;
|
1697 |
case 0x2000: |
1698 |
switch (PPC_EXCP(env)) {
|
1699 |
case PPC_FLAGS_EXCP_40x:
|
1700 |
/* DEBUG on 4xx */
|
1701 |
/* XXX: TODO */
|
1702 |
cpu_abort(env, "40x debug exception is not implemented yet !\n");
|
1703 |
goto store_next;
|
1704 |
case PPC_FLAGS_EXCP_601:
|
1705 |
/* Run mode exception on 601 */
|
1706 |
/* XXX: TODO */
|
1707 |
cpu_abort(env, |
1708 |
"601 run mode exception is not implemented yet !\n");
|
1709 |
goto store_next;
|
1710 |
default:
|
1711 |
cpu_abort(env, "Invalid exception 0x1800 !\n");
|
1712 |
break;
|
1713 |
} |
1714 |
return;
|
1715 |
/* Other exceptions */
|
1716 |
/* Qemu internal exceptions:
|
1717 |
* we should never come here with those values: abort execution
|
1718 |
*/
|
1719 |
default:
|
1720 |
cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
|
1721 |
return;
|
1722 |
store_current:
|
1723 |
/* save current instruction location */
|
1724 |
*srr_0 = (env->nip - 4) & 0xFFFFFFFFULL; |
1725 |
break;
|
1726 |
store_next:
|
1727 |
/* save next instruction location */
|
1728 |
*srr_0 = env->nip & 0xFFFFFFFFULL;
|
1729 |
break;
|
1730 |
} |
1731 |
/* Save msr */
|
1732 |
*srr_1 = msr; |
1733 |
/* If we disactivated any translation, flush TLBs */
|
1734 |
if (msr_ir || msr_dr) {
|
1735 |
tlb_flush(env, 1);
|
1736 |
} |
1737 |
/* reload MSR with correct bits */
|
1738 |
msr_ee = 0;
|
1739 |
msr_pr = 0;
|
1740 |
msr_fp = 0;
|
1741 |
msr_fe0 = 0;
|
1742 |
msr_se = 0;
|
1743 |
msr_be = 0;
|
1744 |
msr_fe1 = 0;
|
1745 |
msr_ir = 0;
|
1746 |
msr_dr = 0;
|
1747 |
msr_ri = 0;
|
1748 |
msr_le = msr_ile; |
1749 |
msr_sf = msr_isf; |
1750 |
do_compute_hflags(env); |
1751 |
/* Jump to handler */
|
1752 |
env->nip = excp; |
1753 |
env->exception_index = EXCP_NONE; |
1754 |
} |
1755 |
#endif /* !CONFIG_USER_ONLY */ |