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/*
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* QEMU ETRAX DMA Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <sys/time.h>
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#include "hw.h"
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#include "etraxfs_dma.h"
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#define D(x)
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#define RW_DATA 0x0
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#define RW_SAVED_DATA 0x58
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#define RW_SAVED_DATA_BUF 0x5c
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#define RW_GROUP 0x60
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#define RW_GROUP_DOWN 0x7c
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#define RW_CMD 0x80
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#define RW_CFG 0x84
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#define RW_STAT 0x88
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#define RW_INTR_MASK 0x8c
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#define RW_ACK_INTR 0x90
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#define R_INTR 0x94
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#define R_MASKED_INTR 0x98
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#define RW_STREAM_CMD 0x9c
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#define DMA_REG_MAX 0x100
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/* descriptors */
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// ------------------------------------------------------------ dma_descr_group
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typedef struct dma_descr_group {
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struct dma_descr_group *next;
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unsigned eol : 1;
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unsigned tol : 1;
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unsigned bol : 1;
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unsigned : 1;
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unsigned intr : 1;
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unsigned : 2;
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unsigned en : 1;
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unsigned : 7;
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unsigned dis : 1;
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unsigned md : 16;
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struct dma_descr_group *up;
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union {
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struct dma_descr_context *context;
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struct dma_descr_group *group;
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} down;
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} dma_descr_group;
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// ---------------------------------------------------------- dma_descr_context
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typedef struct dma_descr_context {
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struct dma_descr_context *next;
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unsigned eol : 1;
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unsigned : 3;
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unsigned intr : 1;
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unsigned : 1;
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unsigned store_mode : 1;
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unsigned en : 1;
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unsigned : 7;
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unsigned dis : 1;
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unsigned md0 : 16;
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unsigned md1;
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unsigned md2;
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unsigned md3;
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unsigned md4;
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struct dma_descr_data *saved_data;
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char *saved_data_buf;
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} dma_descr_context;
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// ------------------------------------------------------------- dma_descr_data
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typedef struct dma_descr_data {
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struct dma_descr_data *next;
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char *buf;
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unsigned eol : 1;
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unsigned : 2;
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unsigned out_eop : 1;
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unsigned intr : 1;
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unsigned wait : 1;
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unsigned : 2;
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unsigned : 3;
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unsigned in_eop : 1;
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unsigned : 4;
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unsigned md : 16;
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char *after;
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} dma_descr_data;
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/* Constants */
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enum {
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regk_dma_ack_pkt = 0x00000100,
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regk_dma_anytime = 0x00000001,
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regk_dma_array = 0x00000008,
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regk_dma_burst = 0x00000020,
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regk_dma_client = 0x00000002,
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regk_dma_copy_next = 0x00000010,
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regk_dma_copy_up = 0x00000020,
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regk_dma_data_at_eol = 0x00000001,
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regk_dma_dis_c = 0x00000010,
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regk_dma_dis_g = 0x00000020,
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regk_dma_idle = 0x00000001,
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regk_dma_intern = 0x00000004,
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regk_dma_load_c = 0x00000200,
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regk_dma_load_c_n = 0x00000280,
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regk_dma_load_c_next = 0x00000240,
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regk_dma_load_d = 0x00000140,
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regk_dma_load_g = 0x00000300,
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regk_dma_load_g_down = 0x000003c0,
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regk_dma_load_g_next = 0x00000340,
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regk_dma_load_g_up = 0x00000380,
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regk_dma_next_en = 0x00000010,
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regk_dma_next_pkt = 0x00000010,
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regk_dma_no = 0x00000000,
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regk_dma_only_at_wait = 0x00000000,
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regk_dma_restore = 0x00000020,
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regk_dma_rst = 0x00000001,
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regk_dma_running = 0x00000004,
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regk_dma_rw_cfg_default = 0x00000000,
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regk_dma_rw_cmd_default = 0x00000000,
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regk_dma_rw_intr_mask_default = 0x00000000,
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regk_dma_rw_stat_default = 0x00000101,
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regk_dma_rw_stream_cmd_default = 0x00000000,
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regk_dma_save_down = 0x00000020,
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regk_dma_save_up = 0x00000020,
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regk_dma_set_reg = 0x00000050,
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regk_dma_set_w_size1 = 0x00000190,
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regk_dma_set_w_size2 = 0x000001a0,
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regk_dma_set_w_size4 = 0x000001c0,
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regk_dma_stopped = 0x00000002,
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regk_dma_store_c = 0x00000002,
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regk_dma_store_descr = 0x00000000,
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regk_dma_store_g = 0x00000004,
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regk_dma_store_md = 0x00000001,
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regk_dma_sw = 0x00000008,
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regk_dma_update_down = 0x00000020,
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regk_dma_yes = 0x00000001
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};
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enum dma_ch_state
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{
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RST = 0,
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STOPPED = 2,
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RUNNING = 4
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};
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struct fs_dma_channel
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{
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int regmap;
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qemu_irq *irq;
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struct etraxfs_dma_client *client;
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/* Internal status. */
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int stream_cmd_src;
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enum dma_ch_state state;
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unsigned int input : 1;
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unsigned int eol : 1;
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struct dma_descr_group current_g;
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struct dma_descr_context current_c;
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struct dma_descr_data current_d;
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/* Controll registers. */
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uint32_t regs[DMA_REG_MAX];
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};
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struct fs_dma_ctrl
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{
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CPUState *env;
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target_phys_addr_t base;
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int nr_channels;
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struct fs_dma_channel *channels;
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};
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static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
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{
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return ctrl->channels[c].regs[reg];
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}
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static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
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{
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return channel_reg(ctrl, c, RW_CFG) & 2;
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}
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static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
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{
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return (channel_reg(ctrl, c, RW_CFG) & 1)
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&& ctrl->channels[c].client;
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}
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static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
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{
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/* Every channel has a 0x2000 ctrl register map. */
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return (addr - base) >> 13;
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}
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static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_g,
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sizeof ctrl->channels[c].current_g);
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}
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static void dump_c(int ch, struct dma_descr_context *c)
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{
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%x\n", (uint32_t) c->next);
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printf("saved_data=%x\n", (uint32_t) c->saved_data);
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printf("saved_data_buf=%x\n", (uint32_t) c->saved_data_buf);
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printf("eol=%x\n", (uint32_t) c->eol);
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}
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static void dump_d(int ch, struct dma_descr_data *d)
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{
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%x\n", (uint32_t) d->next);
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printf("buf=%x\n", (uint32_t) d->buf);
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printf("after=%x\n", (uint32_t) d->after);
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printf("intr=%x\n", (uint32_t) d->intr);
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printf("out_eop=%x\n", (uint32_t) d->out_eop);
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printf("in_eop=%x\n", (uint32_t) d->in_eop);
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printf("eol=%x\n", (uint32_t) d->eol);
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}
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static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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D(dump_c(c, &ctrl->channels[c].current_c));
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/* I guess this should update the current pos. */
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t)ctrl->channels[c].current_c.saved_data;
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
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(uint32_t)ctrl->channels[c].current_c.saved_data_buf;
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}
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static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s addr=%x\n", __func__, addr));
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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D(dump_d(c, &ctrl->channels[c].current_d));
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
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(uint32_t)ctrl->channels[c].current_d.buf;
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}
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s addr=%x\n", __func__, addr));
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cpu_physical_memory_write (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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}
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static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
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{
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/* FIXME: */
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}
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static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
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{
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if (ctrl->channels[c].client)
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{
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ctrl->channels[c].eol = 0;
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ctrl->channels[c].state = RUNNING;
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} else
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printf("WARNING: starting DMA ch %d with no client\n", c);
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}
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static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
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{
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if (!channel_en(ctrl, c)
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|| channel_stopped(ctrl, c)
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|| ctrl->channels[c].state != RUNNING
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/* Only reload the current data descriptor if it has eol set. */
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|| !ctrl->channels[c].current_d.eol) {
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D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
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c, ctrl->channels[c].state,
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channel_stopped(ctrl, c),
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channel_en(ctrl,c),
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ctrl->channels[c].eol));
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D(dump_d(c, &ctrl->channels[c].current_d));
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return;
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320 |
}
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/* Reload the current descriptor. */
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channel_load_d(ctrl, c);
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/* If the current descriptor cleared the eol flag and we had already
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reached eol state, do the continue. */
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if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
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D(printf("continue %d ok %x\n", c,
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ctrl->channels[c].current_d.next));
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t) ctrl->channels[c].current_d.next;
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channel_load_d(ctrl, c);
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channel_start(ctrl, c);
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}
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}
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336 |
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static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
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{
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unsigned int cmd = v & ((1 << 10) - 1);
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D(printf("%s cmd=%x\n", __func__, cmd));
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if (cmd & regk_dma_load_d) {
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channel_load_d(ctrl, c);
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344 |
if (cmd & regk_dma_burst)
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channel_start(ctrl, c);
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346 |
}
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347 |
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348 |
if (cmd & regk_dma_load_c) {
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channel_load_c(ctrl, c);
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350 |
}
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351 |
}
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352 |
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353 |
static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
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354 |
{
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D(printf("%s %d\n", __func__, c));
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ctrl->channels[c].regs[R_INTR] &=
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~(ctrl->channels[c].regs[RW_ACK_INTR]);
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358 |
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ctrl->channels[c].regs[R_MASKED_INTR] =
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ctrl->channels[c].regs[R_INTR]
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& ctrl->channels[c].regs[RW_INTR_MASK];
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362 |
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D(printf("%s: chan=%d masked_intr=%x\n", __func__,
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c,
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ctrl->channels[c].regs[R_MASKED_INTR]));
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366 |
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if (ctrl->channels[c].regs[R_MASKED_INTR])
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qemu_irq_raise(ctrl->channels[c].irq[0]);
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else
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370 |
qemu_irq_lower(ctrl->channels[c].irq[0]);
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371 |
}
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372 |
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373 |
static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
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374 |
{
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375 |
uint32_t len;
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376 |
uint32_t saved_data_buf;
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377 |
unsigned char buf[2 * 1024];
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378 |
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379 |
if (ctrl->channels[c].eol == 1)
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380 |
return;
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381 |
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382 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
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383 |
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384 |
D(printf("buf=%x after=%x saved_data_buf=%x\n",
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(uint32_t)ctrl->channels[c].current_d.buf,
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386 |
(uint32_t)ctrl->channels[c].current_d.after,
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saved_data_buf));
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388 |
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389 |
if (saved_data_buf == (uint32_t)ctrl->channels[c].current_d.after) {
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390 |
/* Done. Step to next. */
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|
391 |
if (ctrl->channels[c].current_d.out_eop) {
|
|
392 |
/* TODO: signal eop to the client. */
|
|
393 |
D(printf("signal eop\n"));
|
|
394 |
}
|
|
395 |
if (ctrl->channels[c].current_d.intr) {
|
|
396 |
/* TODO: signal eop to the client. */
|
|
397 |
/* data intr. */
|
|
398 |
D(printf("signal intr\n"));
|
|
399 |
ctrl->channels[c].regs[R_INTR] |= (1 << 2);
|
|
400 |
channel_update_irq(ctrl, c);
|
|
401 |
}
|
|
402 |
if (ctrl->channels[c].current_d.eol) {
|
|
403 |
D(printf("channel %d EOL\n", c));
|
|
404 |
ctrl->channels[c].eol = 1;
|
|
405 |
channel_stop(ctrl, c);
|
|
406 |
} else {
|
|
407 |
ctrl->channels[c].regs[RW_SAVED_DATA] =
|
|
408 |
(uint32_t) ctrl->channels[c].current_d.next;
|
|
409 |
/* Load new descriptor. */
|
|
410 |
channel_load_d(ctrl, c);
|
|
411 |
}
|
|
412 |
|
|
413 |
channel_store_d(ctrl, c);
|
|
414 |
D(dump_d(c, &ctrl->channels[c].current_d));
|
|
415 |
return;
|
|
416 |
}
|
|
417 |
|
|
418 |
len = (uint32_t) ctrl->channels[c].current_d.after;
|
|
419 |
len -= saved_data_buf;
|
|
420 |
|
|
421 |
if (len > sizeof buf)
|
|
422 |
len = sizeof buf;
|
|
423 |
cpu_physical_memory_read (saved_data_buf, buf, len);
|
|
424 |
|
|
425 |
D(printf("channel %d pushes %x %u bytes\n", c,
|
|
426 |
saved_data_buf, len));
|
|
427 |
/* TODO: Push content. */
|
|
428 |
if (ctrl->channels[c].client->client.push)
|
|
429 |
ctrl->channels[c].client->client.push(
|
|
430 |
ctrl->channels[c].client->client.opaque, buf, len);
|
|
431 |
else
|
|
432 |
printf("WARNING: DMA ch%d dataloss, no attached client.\n", c);
|
|
433 |
|
|
434 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] += len;
|
|
435 |
}
|
|
436 |
|
|
437 |
static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
|
|
438 |
unsigned char *buf, int buflen, int eop)
|
|
439 |
{
|
|
440 |
uint32_t len;
|
|
441 |
uint32_t saved_data_buf;
|
|
442 |
|
|
443 |
if (ctrl->channels[c].eol == 1)
|
|
444 |
return 0;
|
|
445 |
|
|
446 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
|
|
447 |
len = (uint32_t) ctrl->channels[c].current_d.after;
|
|
448 |
len -= saved_data_buf;
|
|
449 |
|
|
450 |
if (len > buflen)
|
|
451 |
len = buflen;
|
|
452 |
|
|
453 |
cpu_physical_memory_write (saved_data_buf, buf, len);
|
|
454 |
saved_data_buf += len;
|
|
455 |
|
|
456 |
if (saved_data_buf == (uint32_t)ctrl->channels[c].current_d.after
|
|
457 |
|| eop) {
|
|
458 |
uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
|
|
459 |
|
|
460 |
D(printf("in dscr end len=%d\n",
|
|
461 |
ctrl->channels[c].current_d.after
|
|
462 |
- ctrl->channels[c].current_d.buf));
|
|
463 |
ctrl->channels[c].current_d.after =
|
|
464 |
(void *) saved_data_buf;
|
|
465 |
|
|
466 |
/* Done. Step to next. */
|
|
467 |
if (ctrl->channels[c].current_d.intr) {
|
|
468 |
/* TODO: signal eop to the client. */
|
|
469 |
/* data intr. */
|
|
470 |
ctrl->channels[c].regs[R_INTR] |= 3;
|
|
471 |
}
|
|
472 |
if (eop) {
|
|
473 |
ctrl->channels[c].current_d.in_eop = 1;
|
|
474 |
ctrl->channels[c].regs[R_INTR] |= 8;
|
|
475 |
}
|
|
476 |
if (r_intr != ctrl->channels[c].regs[R_INTR])
|
|
477 |
channel_update_irq(ctrl, c);
|
|
478 |
|
|
479 |
channel_store_d(ctrl, c);
|
|
480 |
D(dump_d(c, &ctrl->channels[c].current_d));
|
|
481 |
|
|
482 |
if (ctrl->channels[c].current_d.eol) {
|
|
483 |
D(printf("channel %d EOL\n", c));
|
|
484 |
ctrl->channels[c].eol = 1;
|
|
485 |
channel_stop(ctrl, c);
|
|
486 |
} else {
|
|
487 |
ctrl->channels[c].regs[RW_SAVED_DATA] =
|
|
488 |
(uint32_t) ctrl->channels[c].current_d.next;
|
|
489 |
/* Load new descriptor. */
|
|
490 |
channel_load_d(ctrl, c);
|
|
491 |
saved_data_buf =
|
|
492 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF];
|
|
493 |
}
|
|
494 |
}
|
|
495 |
|
|
496 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
|
|
497 |
return len;
|
|
498 |
}
|
|
499 |
|
|
500 |
static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c)
|
|
501 |
{
|
|
502 |
if (ctrl->channels[c].client->client.pull)
|
|
503 |
ctrl->channels[c].client->client.pull(
|
|
504 |
ctrl->channels[c].client->client.opaque);
|
|
505 |
}
|
|
506 |
|
|
507 |
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
|
|
508 |
{
|
|
509 |
struct fs_dma_ctrl *ctrl = opaque;
|
|
510 |
CPUState *env = ctrl->env;
|
|
511 |
cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
|
|
512 |
addr, env->pc);
|
|
513 |
return 0;
|
|
514 |
}
|
|
515 |
|
|
516 |
static uint32_t
|
|
517 |
dma_readl (void *opaque, target_phys_addr_t addr)
|
|
518 |
{
|
|
519 |
struct fs_dma_ctrl *ctrl = opaque;
|
|
520 |
int c;
|
|
521 |
uint32_t r = 0;
|
|
522 |
|
|
523 |
/* Make addr relative to this instances base. */
|
|
524 |
c = fs_channel(ctrl->base, addr);
|
|
525 |
addr &= 0x1fff;
|
|
526 |
switch (addr)
|
|
527 |
{
|
|
528 |
case RW_STAT:
|
|
529 |
r = ctrl->channels[c].state & 7;
|
|
530 |
r |= ctrl->channels[c].eol << 5;
|
|
531 |
r |= ctrl->channels[c].stream_cmd_src << 8;
|
|
532 |
break;
|
|
533 |
|
|
534 |
default:
|
|
535 |
r = ctrl->channels[c].regs[addr];
|
|
536 |
D(printf ("%s c=%d addr=%x pc=%x\n",
|
|
537 |
__func__, c, addr, env->pc));
|
|
538 |
break;
|
|
539 |
}
|
|
540 |
return r;
|
|
541 |
}
|
|
542 |
|
|
543 |
static void
|
|
544 |
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
545 |
{
|
|
546 |
struct fs_dma_ctrl *ctrl = opaque;
|
|
547 |
CPUState *env = ctrl->env;
|
|
548 |
cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
|
|
549 |
addr, env->pc);
|
|
550 |
}
|
|
551 |
|
|
552 |
static void
|
|
553 |
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
554 |
{
|
|
555 |
struct fs_dma_ctrl *ctrl = opaque;
|
|
556 |
int c;
|
|
557 |
|
|
558 |
/* Make addr relative to this instances base. */
|
|
559 |
c = fs_channel(ctrl->base, addr);
|
|
560 |
addr &= 0x1fff;
|
|
561 |
switch (addr)
|
|
562 |
{
|
|
563 |
case RW_DATA:
|
|
564 |
printf("RW_DATA=%x\n", value);
|
|
565 |
break;
|
|
566 |
|
|
567 |
case RW_CFG:
|
|
568 |
ctrl->channels[c].regs[addr] = value;
|
|
569 |
break;
|
|
570 |
case RW_CMD:
|
|
571 |
/* continue. */
|
|
572 |
ctrl->channels[c].regs[addr] = value;
|
|
573 |
channel_continue(ctrl, c);
|
|
574 |
break;
|
|
575 |
|
|
576 |
case RW_SAVED_DATA:
|
|
577 |
case RW_SAVED_DATA_BUF:
|
|
578 |
case RW_GROUP:
|
|
579 |
case RW_GROUP_DOWN:
|
|
580 |
ctrl->channels[c].regs[addr] = value;
|
|
581 |
break;
|
|
582 |
|
|
583 |
case RW_ACK_INTR:
|
|
584 |
case RW_INTR_MASK:
|
|
585 |
ctrl->channels[c].regs[addr] = value;
|
|
586 |
channel_update_irq(ctrl, c);
|
|
587 |
if (addr == RW_ACK_INTR)
|
|
588 |
ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
|
589 |
break;
|
|
590 |
|
|
591 |
case RW_STREAM_CMD:
|
|
592 |
ctrl->channels[c].regs[addr] = value;
|
|
593 |
channel_stream_cmd(ctrl, c, value);
|
|
594 |
break;
|
|
595 |
|
|
596 |
default:
|
|
597 |
D(printf ("%s c=%d %x %x pc=%x\n",
|
|
598 |
__func__, c, addr, value, env->pc));
|
|
599 |
break;
|
|
600 |
}
|
|
601 |
}
|
|
602 |
|
|
603 |
static CPUReadMemoryFunc *dma_read[] = {
|
|
604 |
&dma_rinvalid,
|
|
605 |
&dma_rinvalid,
|
|
606 |
&dma_readl,
|
|
607 |
};
|
|
608 |
|
|
609 |
static CPUWriteMemoryFunc *dma_write[] = {
|
|
610 |
&dma_winvalid,
|
|
611 |
&dma_winvalid,
|
|
612 |
&dma_writel,
|
|
613 |
};
|
|
614 |
|
|
615 |
void etraxfs_dmac_run(void *opaque)
|
|
616 |
{
|
|
617 |
struct fs_dma_ctrl *ctrl = opaque;
|
|
618 |
int i;
|
|
619 |
int p = 0;
|
|
620 |
|
|
621 |
for (i = 0;
|
|
622 |
i < ctrl->nr_channels;
|
|
623 |
i++)
|
|
624 |
{
|
|
625 |
if (ctrl->channels[i].state == RUNNING)
|
|
626 |
{
|
|
627 |
p++;
|
|
628 |
if (ctrl->channels[i].input)
|
|
629 |
channel_in_run(ctrl, i);
|
|
630 |
else
|
|
631 |
channel_out_run(ctrl, i);
|
|
632 |
}
|
|
633 |
}
|
|
634 |
}
|
|
635 |
|
|
636 |
int etraxfs_dmac_input(struct etraxfs_dma_client *client,
|
|
637 |
void *buf, int len, int eop)
|
|
638 |
{
|
|
639 |
return channel_in_process(client->ctrl, client->channel,
|
|
640 |
buf, len, eop);
|
|
641 |
}
|
|
642 |
|
|
643 |
/* Connect an IRQ line with a channel. */
|
|
644 |
void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
|
|
645 |
{
|
|
646 |
struct fs_dma_ctrl *ctrl = opaque;
|
|
647 |
ctrl->channels[c].irq = line;
|
|
648 |
ctrl->channels[c].input = input;
|
|
649 |
}
|
|
650 |
|
|
651 |
void etraxfs_dmac_connect_client(void *opaque, int c,
|
|
652 |
struct etraxfs_dma_client *cl)
|
|
653 |
{
|
|
654 |
struct fs_dma_ctrl *ctrl = opaque;
|
|
655 |
cl->ctrl = ctrl;
|
|
656 |
cl->channel = c;
|
|
657 |
ctrl->channels[c].client = cl;
|
|
658 |
}
|
|
659 |
|
|
660 |
|
|
661 |
void *etraxfs_dmac_init(CPUState *env,
|
|
662 |
target_phys_addr_t base, int nr_channels)
|
|
663 |
{
|
|
664 |
struct fs_dma_ctrl *ctrl = NULL;
|
|
665 |
int i;
|
|
666 |
|
|
667 |
ctrl = qemu_mallocz(sizeof *ctrl);
|
|
668 |
if (!ctrl)
|
|
669 |
return NULL;
|
|
670 |
|
|
671 |
ctrl->base = base;
|
|
672 |
ctrl->env = env;
|
|
673 |
ctrl->nr_channels = nr_channels;
|
|
674 |
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
|
|
675 |
if (!ctrl->channels)
|
|
676 |
goto err;
|
|
677 |
|
|
678 |
for (i = 0; i < nr_channels; i++)
|
|
679 |
{
|
|
680 |
ctrl->channels[i].regmap = cpu_register_io_memory(0,
|
|
681 |
dma_read,
|
|
682 |
dma_write,
|
|
683 |
ctrl);
|
|
684 |
cpu_register_physical_memory (base + i * 0x2000,
|
|
685 |
sizeof ctrl->channels[i].regs,
|
|
686 |
ctrl->channels[i].regmap);
|
|
687 |
}
|
|
688 |
|
|
689 |
return ctrl;
|
|
690 |
err:
|
|
691 |
qemu_free(ctrl->channels);
|
|
692 |
qemu_free(ctrl);
|
|
693 |
return NULL;
|
|
694 |
}
|