root / target-mips / machine.c @ 1ba74fb8
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1 | 8dd3dca3 | aurel32 | #include "hw/hw.h" |
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2 | 8dd3dca3 | aurel32 | #include "hw/boards.h" |
3 | 8dd3dca3 | aurel32 | |
4 | 33a84765 | ths | #include "exec-all.h" |
5 | 33a84765 | ths | |
6 | 8dd3dca3 | aurel32 | void register_machines(void) |
7 | 8dd3dca3 | aurel32 | { |
8 | 8dd3dca3 | aurel32 | qemu_register_machine(&mips_malta_machine); |
9 | 63742cf8 | ths | qemu_register_machine(&mips_magnum_machine); |
10 | 8dd3dca3 | aurel32 | qemu_register_machine(&mips_pica61_machine); |
11 | 8dd3dca3 | aurel32 | qemu_register_machine(&mips_mipssim_machine); |
12 | 63742cf8 | ths | qemu_register_machine(&mips_machine); |
13 | 8dd3dca3 | aurel32 | } |
14 | 8dd3dca3 | aurel32 | |
15 | 33a84765 | ths | static void save_tc(QEMUFile *f, TCState *tc) |
16 | 33a84765 | ths | { |
17 | 33a84765 | ths | int i;
|
18 | 33a84765 | ths | |
19 | 33a84765 | ths | /* Save active TC */
|
20 | 33a84765 | ths | for(i = 0; i < 32; i++) |
21 | 33a84765 | ths | qemu_put_betls(f, &tc->gpr[i]); |
22 | 33a84765 | ths | qemu_put_betls(f, &tc->PC); |
23 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
24 | 33a84765 | ths | qemu_put_betls(f, &tc->HI[i]); |
25 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
26 | 33a84765 | ths | qemu_put_betls(f, &tc->LO[i]); |
27 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
28 | 33a84765 | ths | qemu_put_betls(f, &tc->ACX[i]); |
29 | 33a84765 | ths | qemu_put_betls(f, &tc->DSPControl); |
30 | 33a84765 | ths | qemu_put_sbe32s(f, &tc->CP0_TCStatus); |
31 | 33a84765 | ths | qemu_put_sbe32s(f, &tc->CP0_TCBind); |
32 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCHalt); |
33 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCContext); |
34 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCSchedule); |
35 | 33a84765 | ths | qemu_put_betls(f, &tc->CP0_TCScheFBack); |
36 | 33a84765 | ths | qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); |
37 | 33a84765 | ths | } |
38 | 33a84765 | ths | |
39 | 33a84765 | ths | static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) |
40 | 33a84765 | ths | { |
41 | 33a84765 | ths | int i;
|
42 | 33a84765 | ths | |
43 | 33a84765 | ths | for(i = 0; i < 32; i++) |
44 | 33a84765 | ths | qemu_put_be64s(f, &fpu->fpr[i].d); |
45 | 33a84765 | ths | qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess); |
46 | 33a84765 | ths | qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode); |
47 | 33a84765 | ths | qemu_put_s8s(f, &fpu->fp_status.float_exception_flags); |
48 | 33a84765 | ths | qemu_put_be32s(f, &fpu->fcr0); |
49 | 33a84765 | ths | qemu_put_be32s(f, &fpu->fcr31); |
50 | 33a84765 | ths | } |
51 | 33a84765 | ths | |
52 | 8dd3dca3 | aurel32 | void cpu_save(QEMUFile *f, void *opaque) |
53 | 8dd3dca3 | aurel32 | { |
54 | 33a84765 | ths | CPUState *env = opaque; |
55 | 33a84765 | ths | int i;
|
56 | 33a84765 | ths | |
57 | 33a84765 | ths | /* Save active TC */
|
58 | 33a84765 | ths | save_tc(f, &env->active_tc); |
59 | 33a84765 | ths | |
60 | 33a84765 | ths | /* Save active FPU */
|
61 | 33a84765 | ths | save_fpu(f, &env->active_fpu); |
62 | 33a84765 | ths | |
63 | 33a84765 | ths | /* Save MVP */
|
64 | 33a84765 | ths | qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl); |
65 | 33a84765 | ths | qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0); |
66 | 33a84765 | ths | qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1); |
67 | 33a84765 | ths | |
68 | 33a84765 | ths | /* Save TLB */
|
69 | 33a84765 | ths | qemu_put_be32s(f, &env->tlb->nb_tlb); |
70 | 33a84765 | ths | qemu_put_be32s(f, &env->tlb->tlb_in_use); |
71 | 33a84765 | ths | for(i = 0; i < MIPS_TLB_MAX; i++) { |
72 | 33a84765 | ths | uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
|
73 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].C0 << 7) |
|
74 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].C1 << 4) |
|
75 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].V0 << 3) |
|
76 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].V1 << 2) |
|
77 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
|
78 | 33a84765 | ths | (env->tlb->mmu.r4k.tlb[i].D1 << 0));
|
79 | 33a84765 | ths | |
80 | 33a84765 | ths | qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); |
81 | 33a84765 | ths | qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); |
82 | 33a84765 | ths | qemu_put_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID); |
83 | 33a84765 | ths | qemu_put_be16s(f, &flags); |
84 | 33a84765 | ths | qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
|
85 | 33a84765 | ths | qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
|
86 | 33a84765 | ths | } |
87 | 33a84765 | ths | |
88 | 33a84765 | ths | /* Save CPU metastate */
|
89 | 33a84765 | ths | qemu_put_be32s(f, &env->current_tc); |
90 | 33a84765 | ths | qemu_put_be32s(f, &env->current_fpu); |
91 | 33a84765 | ths | qemu_put_sbe32s(f, &env->error_code); |
92 | 33a84765 | ths | qemu_put_be32s(f, &env->hflags); |
93 | 33a84765 | ths | qemu_put_betls(f, &env->btarget); |
94 | 1ba74fb8 | aurel32 | i = env->bcond; |
95 | 1ba74fb8 | aurel32 | qemu_put_sbe32s(f, &i); |
96 | 33a84765 | ths | |
97 | 33a84765 | ths | /* Save remaining CP1 registers */
|
98 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Index); |
99 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Random); |
100 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEControl); |
101 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEConf0); |
102 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEConf1); |
103 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_YQMask); |
104 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_VPESchedule); |
105 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_VPEScheFBack); |
106 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_VPEOpt); |
107 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EntryLo0); |
108 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EntryLo1); |
109 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_Context); |
110 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_PageMask); |
111 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_PageGrain); |
112 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Wired); |
113 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf0); |
114 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf1); |
115 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf2); |
116 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf3); |
117 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSConf4); |
118 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_HWREna); |
119 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_BadVAddr); |
120 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Count); |
121 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EntryHi); |
122 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Compare); |
123 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Status); |
124 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_IntCtl); |
125 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSCtl); |
126 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_SRSMap); |
127 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Cause); |
128 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_EPC); |
129 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_PRid); |
130 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_EBase); |
131 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config0); |
132 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config1); |
133 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config2); |
134 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config3); |
135 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config6); |
136 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Config7); |
137 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_LLAddr); |
138 | 33a84765 | ths | for(i = 0; i < 8; i++) |
139 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_WatchLo[i]); |
140 | 33a84765 | ths | for(i = 0; i < 8; i++) |
141 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_WatchHi[i]); |
142 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_XContext); |
143 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Framemask); |
144 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Debug); |
145 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_DEPC); |
146 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_Performance0); |
147 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_TagLo); |
148 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_DataLo); |
149 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_TagHi); |
150 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_DataHi); |
151 | 33a84765 | ths | qemu_put_betls(f, &env->CP0_ErrorEPC); |
152 | 33a84765 | ths | qemu_put_sbe32s(f, &env->CP0_DESAVE); |
153 | 33a84765 | ths | |
154 | 33a84765 | ths | /* Save inactive TC state */
|
155 | 33a84765 | ths | for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) |
156 | 33a84765 | ths | save_tc(f, &env->tcs[i]); |
157 | 33a84765 | ths | for (i = 0; i < MIPS_FPU_MAX; i++) |
158 | 33a84765 | ths | save_fpu(f, &env->fpus[i]); |
159 | 33a84765 | ths | } |
160 | 33a84765 | ths | |
161 | 33a84765 | ths | static void load_tc(QEMUFile *f, TCState *tc) |
162 | 33a84765 | ths | { |
163 | 33a84765 | ths | int i;
|
164 | 33a84765 | ths | |
165 | 33a84765 | ths | /* Save active TC */
|
166 | 33a84765 | ths | for(i = 0; i < 32; i++) |
167 | 33a84765 | ths | qemu_get_betls(f, &tc->gpr[i]); |
168 | 33a84765 | ths | qemu_get_betls(f, &tc->PC); |
169 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
170 | 33a84765 | ths | qemu_get_betls(f, &tc->HI[i]); |
171 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
172 | 33a84765 | ths | qemu_get_betls(f, &tc->LO[i]); |
173 | 33a84765 | ths | for(i = 0; i < MIPS_DSP_ACC; i++) |
174 | 33a84765 | ths | qemu_get_betls(f, &tc->ACX[i]); |
175 | 33a84765 | ths | qemu_get_betls(f, &tc->DSPControl); |
176 | 33a84765 | ths | qemu_get_sbe32s(f, &tc->CP0_TCStatus); |
177 | 33a84765 | ths | qemu_get_sbe32s(f, &tc->CP0_TCBind); |
178 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCHalt); |
179 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCContext); |
180 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCSchedule); |
181 | 33a84765 | ths | qemu_get_betls(f, &tc->CP0_TCScheFBack); |
182 | 33a84765 | ths | qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); |
183 | 33a84765 | ths | } |
184 | 33a84765 | ths | |
185 | 33a84765 | ths | static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) |
186 | 33a84765 | ths | { |
187 | 33a84765 | ths | int i;
|
188 | 33a84765 | ths | |
189 | 33a84765 | ths | for(i = 0; i < 32; i++) |
190 | 33a84765 | ths | qemu_get_be64s(f, &fpu->fpr[i].d); |
191 | 33a84765 | ths | qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); |
192 | 33a84765 | ths | qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); |
193 | 33a84765 | ths | qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); |
194 | 33a84765 | ths | qemu_get_be32s(f, &fpu->fcr0); |
195 | 33a84765 | ths | qemu_get_be32s(f, &fpu->fcr31); |
196 | 8dd3dca3 | aurel32 | } |
197 | 8dd3dca3 | aurel32 | |
198 | 8dd3dca3 | aurel32 | int cpu_load(QEMUFile *f, void *opaque, int version_id) |
199 | 8dd3dca3 | aurel32 | { |
200 | 33a84765 | ths | CPUState *env = opaque; |
201 | 33a84765 | ths | int i;
|
202 | 33a84765 | ths | |
203 | 33a84765 | ths | if (version_id != 3) |
204 | 33a84765 | ths | return -EINVAL;
|
205 | 33a84765 | ths | |
206 | 33a84765 | ths | /* Load active TC */
|
207 | 33a84765 | ths | load_tc(f, &env->active_tc); |
208 | 33a84765 | ths | |
209 | 33a84765 | ths | /* Load active FPU */
|
210 | 33a84765 | ths | load_fpu(f, &env->active_fpu); |
211 | 33a84765 | ths | |
212 | 33a84765 | ths | /* Load MVP */
|
213 | 33a84765 | ths | qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); |
214 | 33a84765 | ths | qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); |
215 | 33a84765 | ths | qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); |
216 | 33a84765 | ths | |
217 | 33a84765 | ths | /* Load TLB */
|
218 | 33a84765 | ths | qemu_get_be32s(f, &env->tlb->nb_tlb); |
219 | 33a84765 | ths | qemu_get_be32s(f, &env->tlb->tlb_in_use); |
220 | 33a84765 | ths | for(i = 0; i < MIPS_TLB_MAX; i++) { |
221 | 33a84765 | ths | uint16_t flags; |
222 | 33a84765 | ths | |
223 | 33a84765 | ths | qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); |
224 | 33a84765 | ths | qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); |
225 | 33a84765 | ths | qemu_get_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID); |
226 | 33a84765 | ths | qemu_get_be16s(f, &flags); |
227 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1; |
228 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; |
229 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; |
230 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; |
231 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; |
232 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; |
233 | 33a84765 | ths | env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; |
234 | 33a84765 | ths | qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
|
235 | 33a84765 | ths | qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
|
236 | 33a84765 | ths | } |
237 | 33a84765 | ths | |
238 | 33a84765 | ths | /* Load CPU metastate */
|
239 | 33a84765 | ths | qemu_get_be32s(f, &env->current_tc); |
240 | 33a84765 | ths | qemu_get_be32s(f, &env->current_fpu); |
241 | 33a84765 | ths | qemu_get_sbe32s(f, &env->error_code); |
242 | 33a84765 | ths | qemu_get_be32s(f, &env->hflags); |
243 | 33a84765 | ths | qemu_get_betls(f, &env->btarget); |
244 | 1ba74fb8 | aurel32 | qemu_get_sbe32s(f, &i); |
245 | 1ba74fb8 | aurel32 | env->bcond = i; |
246 | 33a84765 | ths | |
247 | 33a84765 | ths | /* Load remaining CP1 registers */
|
248 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Index); |
249 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Random); |
250 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEControl); |
251 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEConf0); |
252 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEConf1); |
253 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_YQMask); |
254 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_VPESchedule); |
255 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_VPEScheFBack); |
256 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_VPEOpt); |
257 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EntryLo0); |
258 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EntryLo1); |
259 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_Context); |
260 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_PageMask); |
261 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_PageGrain); |
262 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Wired); |
263 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf0); |
264 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf1); |
265 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf2); |
266 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf3); |
267 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSConf4); |
268 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_HWREna); |
269 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_BadVAddr); |
270 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Count); |
271 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EntryHi); |
272 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Compare); |
273 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Status); |
274 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_IntCtl); |
275 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSCtl); |
276 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_SRSMap); |
277 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Cause); |
278 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_EPC); |
279 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_PRid); |
280 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_EBase); |
281 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config0); |
282 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config1); |
283 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config2); |
284 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config3); |
285 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config6); |
286 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Config7); |
287 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_LLAddr); |
288 | 33a84765 | ths | for(i = 0; i < 8; i++) |
289 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_WatchLo[i]); |
290 | 33a84765 | ths | for(i = 0; i < 8; i++) |
291 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); |
292 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_XContext); |
293 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Framemask); |
294 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Debug); |
295 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_DEPC); |
296 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_Performance0); |
297 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_TagLo); |
298 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_DataLo); |
299 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_TagHi); |
300 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_DataHi); |
301 | 33a84765 | ths | qemu_get_betls(f, &env->CP0_ErrorEPC); |
302 | 33a84765 | ths | qemu_get_sbe32s(f, &env->CP0_DESAVE); |
303 | 33a84765 | ths | |
304 | 33a84765 | ths | /* Load inactive TC state */
|
305 | 33a84765 | ths | for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) |
306 | 33a84765 | ths | load_tc(f, &env->tcs[i]); |
307 | 33a84765 | ths | for (i = 0; i < MIPS_FPU_MAX; i++) |
308 | 33a84765 | ths | load_fpu(f, &env->fpus[i]); |
309 | 33a84765 | ths | |
310 | 33a84765 | ths | /* XXX: ensure compatiblity for halted bit ? */
|
311 | 33a84765 | ths | tlb_flush(env, 1);
|
312 | 8dd3dca3 | aurel32 | return 0; |
313 | 8dd3dca3 | aurel32 | } |