Revision 1ba74fb8

b/target-mips/cpu.h
443 443
#define MIPS_HFLAG_BL     0x0C00 /* Likely branch                      */
444 444
#define MIPS_HFLAG_BR     0x1000 /* branch to register (can't link TB) */
445 445
    target_ulong btarget;        /* Jump / branch target               */
446
    int bcond;                   /* Branch condition (if needed)       */
446
    target_ulong bcond;          /* Branch condition (if needed)       */
447 447

  
448 448
    int SYNCI_Step; /* Address step size for SYNCI */
449 449
    int CCRes; /* Cycle count resolution/divisor */
b/target-mips/machine.c
91 91
    qemu_put_sbe32s(f, &env->error_code);
92 92
    qemu_put_be32s(f, &env->hflags);
93 93
    qemu_put_betls(f, &env->btarget);
94
    qemu_put_sbe32s(f, &env->bcond);
94
    i = env->bcond;
95
    qemu_put_sbe32s(f, &i);
95 96

  
96 97
    /* Save remaining CP1 registers */
97 98
    qemu_put_sbe32s(f, &env->CP0_Index);
......
240 241
    qemu_get_sbe32s(f, &env->error_code);
241 242
    qemu_get_be32s(f, &env->hflags);
242 243
    qemu_get_betls(f, &env->btarget);
243
    qemu_get_sbe32s(f, &env->bcond);
244
    qemu_get_sbe32s(f, &i);
245
    env->bcond = i;
244 246

  
245 247
    /* Load remaining CP1 registers */
246 248
    qemu_get_sbe32s(f, &env->CP0_Index);
b/target-mips/translate.c
430 430
static TCGv cpu_gpr[32], cpu_PC;
431 431
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
432 432
static TCGv cpu_dspctrl, btarget;
433
static TCGv_i32 bcond;
433
static TCGv bcond;
434 434
static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32];
435 435
static TCGv_i32 fpu_fcr0, fpu_fcr31;
436 436

  
......
2167 2167
{
2168 2168
    int cond;
2169 2169
    TCGv t0 = tcg_temp_local_new();
2170
    TCGv t1 = tcg_temp_local_new();
2170
    TCGv t1 = tcg_temp_new();
2171 2171

  
2172 2172
    cond = 0;
2173 2173
    /* Load needed operands */
......
2290 2290
    target_ulong btgt = -1;
2291 2291
    int blink = 0;
2292 2292
    int bcond_compute = 0;
2293
    TCGv t0 = tcg_temp_local_new();
2294
    TCGv t1 = tcg_temp_local_new();
2293
    TCGv t0 = tcg_temp_new();
2294
    TCGv t1 = tcg_temp_new();
2295 2295

  
2296 2296
    if (ctx->hflags & MIPS_HFLAG_BMASK) {
2297 2297
#ifdef MIPS_DEBUG_DISAS
......
2383 2383
            MIPS_DEBUG("bnever (NOP)");
2384 2384
            goto out;
2385 2385
        case OPC_BLTZAL:  /* 0 < 0           */
2386
            tcg_gen_movi_tl(t0, ctx->pc + 8);
2387
            gen_store_gpr(t0, 31);
2386
            tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
2388 2387
            MIPS_DEBUG("bnever and link");
2389 2388
            goto out;
2390 2389
        case OPC_BLTZALL: /* 0 < 0 likely */
2391
            tcg_gen_movi_tl(t0, ctx->pc + 8);
2392
            gen_store_gpr(t0, 31);
2390
            tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
2393 2391
            /* Skip the instruction in the delay slot */
2394 2392
            MIPS_DEBUG("bnever, link and skip");
2395 2393
            ctx->pc += 4;
......
2427 2425
    } else {
2428 2426
        switch (opc) {
2429 2427
        case OPC_BEQ:
2430
            gen_op_eq(t0, t0, t1);
2428
            gen_op_eq(bcond, t0, t1);
2431 2429
            MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2432 2430
                       regnames[rs], regnames[rt], btgt);
2433 2431
            goto not_likely;
2434 2432
        case OPC_BEQL:
2435
            gen_op_eq(t0, t0, t1);
2433
            gen_op_eq(bcond, t0, t1);
2436 2434
            MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2437 2435
                       regnames[rs], regnames[rt], btgt);
2438 2436
            goto likely;
2439 2437
        case OPC_BNE:
2440
            gen_op_ne(t0, t0, t1);
2438
            gen_op_ne(bcond, t0, t1);
2441 2439
            MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2442 2440
                       regnames[rs], regnames[rt], btgt);
2443 2441
            goto not_likely;
2444 2442
        case OPC_BNEL:
2445
            gen_op_ne(t0, t0, t1);
2443
            gen_op_ne(bcond, t0, t1);
2446 2444
            MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2447 2445
                       regnames[rs], regnames[rt], btgt);
2448 2446
            goto likely;
2449 2447
        case OPC_BGEZ:
2450
            gen_op_gez(t0, t0);
2448
            gen_op_gez(bcond, t0);
2451 2449
            MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2452 2450
            goto not_likely;
2453 2451
        case OPC_BGEZL:
2454
            gen_op_gez(t0, t0);
2452
            gen_op_gez(bcond, t0);
2455 2453
            MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2456 2454
            goto likely;
2457 2455
        case OPC_BGEZAL:
2458
            gen_op_gez(t0, t0);
2456
            gen_op_gez(bcond, t0);
2459 2457
            MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2460 2458
            blink = 31;
2461 2459
            goto not_likely;
2462 2460
        case OPC_BGEZALL:
2463
            gen_op_gez(t0, t0);
2461
            gen_op_gez(bcond, t0);
2464 2462
            blink = 31;
2465 2463
            MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2466 2464
            goto likely;
2467 2465
        case OPC_BGTZ:
2468
            gen_op_gtz(t0, t0);
2466
            gen_op_gtz(bcond, t0);
2469 2467
            MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2470 2468
            goto not_likely;
2471 2469
        case OPC_BGTZL:
2472
            gen_op_gtz(t0, t0);
2470
            gen_op_gtz(bcond, t0);
2473 2471
            MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2474 2472
            goto likely;
2475 2473
        case OPC_BLEZ:
2476
            gen_op_lez(t0, t0);
2474
            gen_op_lez(bcond, t0);
2477 2475
            MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2478 2476
            goto not_likely;
2479 2477
        case OPC_BLEZL:
2480
            gen_op_lez(t0, t0);
2478
            gen_op_lez(bcond, t0);
2481 2479
            MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2482 2480
            goto likely;
2483 2481
        case OPC_BLTZ:
2484
            gen_op_ltz(t0, t0);
2482
            gen_op_ltz(bcond, t0);
2485 2483
            MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2486 2484
            goto not_likely;
2487 2485
        case OPC_BLTZL:
2488
            gen_op_ltz(t0, t0);
2486
            gen_op_ltz(bcond, t0);
2489 2487
            MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2490 2488
            goto likely;
2491 2489
        case OPC_BLTZAL:
2492
            gen_op_ltz(t0, t0);
2490
            gen_op_ltz(bcond, t0);
2493 2491
            blink = 31;
2494 2492
            MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2495 2493
        not_likely:
2496 2494
            ctx->hflags |= MIPS_HFLAG_BC;
2497
            tcg_gen_trunc_tl_i32(bcond, t0);
2498 2495
            break;
2499 2496
        case OPC_BLTZALL:
2500
            gen_op_ltz(t0, t0);
2497
            gen_op_ltz(bcond, t0);
2501 2498
            blink = 31;
2502 2499
            MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2503 2500
        likely:
2504 2501
            ctx->hflags |= MIPS_HFLAG_BL;
2505
            tcg_gen_trunc_tl_i32(bcond, t0);
2506 2502
            break;
2507 2503
        default:
2508 2504
            MIPS_INVAL("conditional branch/jump");
......
2515 2511

  
2516 2512
    ctx->btarget = btgt;
2517 2513
    if (blink > 0) {
2518
        tcg_gen_movi_tl(t0, ctx->pc + 8);
2519
        gen_store_gpr(t0, blink);
2514
        tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + 8);
2520 2515
    }
2521 2516

  
2522 2517
 out:
......
5537 5532
            get_fp_cond(t0);
5538 5533
            tcg_gen_andi_i32(t0, t0, 0x1 << cc);
5539 5534
            tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
5540
            tcg_gen_movi_i32(bcond, 0);
5535
            tcg_gen_movi_tl(bcond, 0);
5541 5536
            tcg_gen_br(l2);
5542 5537
            gen_set_label(l1);
5543
            tcg_gen_movi_i32(bcond, 1);
5538
            tcg_gen_movi_tl(bcond, 1);
5544 5539
            gen_set_label(l2);
5545 5540
        }
5546 5541
        opn = "bc1f";
......
5553 5548
            get_fp_cond(t0);
5554 5549
            tcg_gen_andi_i32(t0, t0, 0x1 << cc);
5555 5550
            tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
5556
            tcg_gen_movi_i32(bcond, 0);
5551
            tcg_gen_movi_tl(bcond, 0);
5557 5552
            tcg_gen_br(l2);
5558 5553
            gen_set_label(l1);
5559
            tcg_gen_movi_i32(bcond, 1);
5554
            tcg_gen_movi_tl(bcond, 1);
5560 5555
            gen_set_label(l2);
5561 5556
        }
5562 5557
        opn = "bc1fl";
......
5569 5564
            get_fp_cond(t0);
5570 5565
            tcg_gen_andi_i32(t0, t0, 0x1 << cc);
5571 5566
            tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
5572
            tcg_gen_movi_i32(bcond, 0);
5567
            tcg_gen_movi_tl(bcond, 0);
5573 5568
            tcg_gen_br(l2);
5574 5569
            gen_set_label(l1);
5575
            tcg_gen_movi_i32(bcond, 1);
5570
            tcg_gen_movi_tl(bcond, 1);
5576 5571
            gen_set_label(l2);
5577 5572
        }
5578 5573
        opn = "bc1t";
......
5585 5580
            get_fp_cond(t0);
5586 5581
            tcg_gen_andi_i32(t0, t0, 0x1 << cc);
5587 5582
            tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
5588
            tcg_gen_movi_i32(bcond, 0);
5583
            tcg_gen_movi_tl(bcond, 0);
5589 5584
            tcg_gen_br(l2);
5590 5585
            gen_set_label(l1);
5591
            tcg_gen_movi_i32(bcond, 1);
5586
            tcg_gen_movi_tl(bcond, 1);
5592 5587
            gen_set_label(l2);
5593 5588
        }
5594 5589
        opn = "bc1tl";
......
5603 5598
            get_fp_cond(t0);
5604 5599
            tcg_gen_andi_i32(t0, t0, 0x3 << cc);
5605 5600
            tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
5606
            tcg_gen_movi_i32(bcond, 0);
5601
            tcg_gen_movi_tl(bcond, 0);
5607 5602
            tcg_gen_br(l2);
5608 5603
            gen_set_label(l1);
5609
            tcg_gen_movi_i32(bcond, 1);
5604
            tcg_gen_movi_tl(bcond, 1);
5610 5605
            gen_set_label(l2);
5611 5606
        }
5612 5607
        opn = "bc1any2f";
......
5619 5614
            get_fp_cond(t0);
5620 5615
            tcg_gen_andi_i32(t0, t0, 0x3 << cc);
5621 5616
            tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
5622
            tcg_gen_movi_i32(bcond, 0);
5617
            tcg_gen_movi_tl(bcond, 0);
5623 5618
            tcg_gen_br(l2);
5624 5619
            gen_set_label(l1);
5625
            tcg_gen_movi_i32(bcond, 1);
5620
            tcg_gen_movi_tl(bcond, 1);
5626 5621
            gen_set_label(l2);
5627 5622
        }
5628 5623
        opn = "bc1any2t";
......
5635 5630
            get_fp_cond(t0);
5636 5631
            tcg_gen_andi_i32(t0, t0, 0xf << cc);
5637 5632
            tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
5638
            tcg_gen_movi_i32(bcond, 0);
5633
            tcg_gen_movi_tl(bcond, 0);
5639 5634
            tcg_gen_br(l2);
5640 5635
            gen_set_label(l1);
5641
            tcg_gen_movi_i32(bcond, 1);
5636
            tcg_gen_movi_tl(bcond, 1);
5642 5637
            gen_set_label(l2);
5643 5638
        }
5644 5639
        opn = "bc1any4f";
......
5651 5646
            get_fp_cond(t0);
5652 5647
            tcg_gen_andi_i32(t0, t0, 0xf << cc);
5653 5648
            tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
5654
            tcg_gen_movi_i32(bcond, 0);
5649
            tcg_gen_movi_tl(bcond, 0);
5655 5650
            tcg_gen_br(l2);
5656 5651
            gen_set_label(l1);
5657
            tcg_gen_movi_i32(bcond, 1);
5652
            tcg_gen_movi_tl(bcond, 1);
5658 5653
            gen_set_label(l2);
5659 5654
        }
5660 5655
        opn = "bc1any4t";
......
7585 7580
        int l1 = gen_new_label();
7586 7581

  
7587 7582
        MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
7588
        tcg_gen_brcondi_i32(TCG_COND_NE, bcond, 0, l1);
7583
        tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
7589 7584
        {
7590 7585
            TCGv_i32 r_tmp = tcg_temp_new_i32();
7591 7586

  
......
8147 8142
            {
8148 8143
                int l1 = gen_new_label();
8149 8144

  
8150
                tcg_gen_brcondi_i32(TCG_COND_NE, bcond, 0, l1);
8145
                tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
8151 8146
                gen_goto_tb(ctx, 1, ctx->pc + 4);
8152 8147
                gen_set_label(l1);
8153 8148
                gen_goto_tb(ctx, 0, ctx->btarget);
......
8440 8435
    cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
8441 8436
                                     offsetof(CPUState, active_tc.DSPControl),
8442 8437
                                     "DSPControl");
8443
    bcond = tcg_global_mem_new_i32(TCG_AREG0,
8444
                                   offsetof(CPUState, bcond), "bcond");
8438
    bcond = tcg_global_mem_new(TCG_AREG0,
8439
                               offsetof(CPUState, bcond), "bcond");
8445 8440
    btarget = tcg_global_mem_new(TCG_AREG0,
8446 8441
                                 offsetof(CPUState, btarget), "btarget");
8447 8442
    for (i = 0; i < 32; i++)

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