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/*
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* QEMU ES1370 emulation
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*
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* Copyright (c) 2005 Vassili Karpov (malc)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* #define DEBUG_ES1370 */
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/* #define VERBOSE_ES1370 */
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#define SILENT_ES1370
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#include "vl.h" |
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/* Missing stuff:
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SCTRL_P[12](END|ST)INC
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SCTRL_P1SCTRLD
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SCTRL_P2DACSEN
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CTRL_DAC_SYNC
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MIDI
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non looped mode
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surely more
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*/
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/*
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Following macros and samplerate array were copied verbatim from
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Linux kernel 2.4.30: drivers/sound/es1370.c
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Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
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*/
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/* Start blatant GPL violation */
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#define ES1370_REG_CONTROL 0x00 |
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#define ES1370_REG_STATUS 0x04 |
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#define ES1370_REG_UART_DATA 0x08 |
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#define ES1370_REG_UART_STATUS 0x09 |
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#define ES1370_REG_UART_CONTROL 0x09 |
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#define ES1370_REG_UART_TEST 0x0a |
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#define ES1370_REG_MEMPAGE 0x0c |
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#define ES1370_REG_CODEC 0x10 |
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#define ES1370_REG_SERIAL_CONTROL 0x20 |
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#define ES1370_REG_DAC1_SCOUNT 0x24 |
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#define ES1370_REG_DAC2_SCOUNT 0x28 |
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#define ES1370_REG_ADC_SCOUNT 0x2c |
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|
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#define ES1370_REG_DAC1_FRAMEADR 0xc30 |
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#define ES1370_REG_DAC1_FRAMECNT 0xc34 |
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#define ES1370_REG_DAC2_FRAMEADR 0xc38 |
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#define ES1370_REG_DAC2_FRAMECNT 0xc3c |
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#define ES1370_REG_ADC_FRAMEADR 0xd30 |
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#define ES1370_REG_ADC_FRAMECNT 0xd34 |
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#define ES1370_REG_PHANTOM_FRAMEADR 0xd38 |
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#define ES1370_REG_PHANTOM_FRAMECNT 0xd3c |
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static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 }; |
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#define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2) |
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#define DAC2_DIVTOSR(x) (1411200/((x)+2)) |
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#define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */ |
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#define CTRL_XCTL1 0x40000000 /* electret mic bias */ |
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#define CTRL_OPEN 0x20000000 /* no function, can be read and written */ |
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#define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */ |
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#define CTRL_SH_PCLKDIV 16 |
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#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */ |
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#define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */ |
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#define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */ |
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#define CTRL_SH_WTSRSEL 12 |
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#define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */ |
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#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */ |
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#define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */ |
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#define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */ |
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#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */ |
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#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */ |
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#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */ |
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#define CTRL_ADC_EN 0x00000010 /* enable ADC */ |
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#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */ |
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#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */ |
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#define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */ |
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#define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */ |
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#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */ |
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#define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */ |
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#define STAT_CBUSY 0x00000200 /* 1 = codec busy */ |
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#define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */ |
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#define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */ |
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#define STAT_SH_VC 5 |
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#define STAT_MCCB 0x00000010 /* CCB int pending */ |
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#define STAT_UART 0x00000008 /* UART int pending */ |
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#define STAT_DAC1 0x00000004 /* DAC1 int pending */ |
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#define STAT_DAC2 0x00000002 /* DAC2 int pending */ |
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#define STAT_ADC 0x00000001 /* ADC int pending */ |
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#define USTAT_RXINT 0x80 /* UART rx int pending */ |
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#define USTAT_TXINT 0x04 /* UART tx int pending */ |
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#define USTAT_TXRDY 0x02 /* UART tx ready */ |
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#define USTAT_RXRDY 0x01 /* UART rx ready */ |
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#define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */ |
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#define UCTRL_TXINTEN 0x60 /* TX int enable field mask */ |
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#define UCTRL_ENA_TXINT 0x20 /* enable TX int */ |
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#define UCTRL_CNTRL 0x03 /* control field */ |
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#define UCTRL_CNTRL_SWR 0x03 /* software reset command */ |
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#define SCTRL_P2ENDINC 0x00380000 /* */ |
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#define SCTRL_SH_P2ENDINC 19 |
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#define SCTRL_P2STINC 0x00070000 /* */ |
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#define SCTRL_SH_P2STINC 16 |
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#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */ |
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#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */ |
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#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */ |
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#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */ |
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#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */ |
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#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */ |
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#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */ |
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#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */ |
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#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */ |
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#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */ |
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#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */ |
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#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */ |
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#define SCTRL_R1FMT 0x00000030 /* format mask */ |
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#define SCTRL_SH_R1FMT 4 |
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#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */ |
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#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */ |
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#define SCTRL_P2FMT 0x0000000c /* format mask */ |
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#define SCTRL_SH_P2FMT 2 |
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#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */ |
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#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */ |
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#define SCTRL_P1FMT 0x00000003 /* format mask */ |
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#define SCTRL_SH_P1FMT 0 |
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/* End blatant GPL violation */
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#define NB_CHANNELS 3 |
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#define DAC1_CHANNEL 0 |
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#define DAC2_CHANNEL 1 |
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#define ADC_CHANNEL 2 |
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#define IO_READ_PROTO(n) \
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static uint32_t n (void *opaque, uint32_t addr) |
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#define IO_WRITE_PROTO(n) \
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static void n (void *opaque, uint32_t addr, uint32_t val) |
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static void es1370_dac1_callback (void *opaque, int free); |
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static void es1370_dac2_callback (void *opaque, int free); |
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static void es1370_adc_callback (void *opaque, int avail); |
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#ifdef DEBUG_ES1370
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#define ldebug(...) AUD_log ("es1370", __VA_ARGS__) |
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static void print_ctl (uint32_t val) |
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{ |
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char buf[1024]; |
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buf[0] = '\0'; |
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#define a(n) if (val & CTRL_##n) strcat (buf, " "#n) |
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a (ADC_STOP); |
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a (XCTL1); |
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a (OPEN); |
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a (MSFMTSEL); |
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a (M_SBB); |
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a (DAC_SYNC); |
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a (CCB_INTRM); |
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a (M_CB); |
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a (XCTL0); |
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a (BREQ); |
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a (DAC1_EN); |
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a (DAC2_EN); |
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a (ADC_EN); |
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a (UART_EN); |
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a (JYSTK_EN); |
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a (CDC_EN); |
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a (SERR_DIS); |
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#undef a
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AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n", |
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(val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV, |
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DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV), |
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dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL], |
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buf); |
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} |
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static void print_sctl (uint32_t val) |
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{ |
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static const char *fmt_names[] = {"8M", "8S", "16M", "16S"}; |
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char buf[1024]; |
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buf[0] = '\0'; |
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#define a(n) if (val & SCTRL_##n) strcat (buf, " "#n) |
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#define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n) |
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b (R1LOOPSEL); |
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b (P2LOOPSEL); |
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b (P1LOOPSEL); |
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a (P2PAUSE); |
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a (P1PAUSE); |
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a (R1INTEN); |
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a (P2INTEN); |
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a (P1INTEN); |
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a (P1SCTRLD); |
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a (P2DACSEN); |
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if (buf[0]) { |
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strcat (buf, "\n ");
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} |
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else {
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buf[0] = ' '; |
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buf[1] = '\0'; |
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} |
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#undef b
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#undef a
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AUD_log ("es1370",
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"%s"
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"p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
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buf, |
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(val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC, |
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(val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC, |
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fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
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fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
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fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
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); |
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} |
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#else
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#define ldebug(...)
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#define print_ctl(...)
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#define print_sctl(...)
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#endif
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#ifdef VERBOSE_ES1370
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#define dolog(...) AUD_log ("es1370", __VA_ARGS__) |
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#else
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#define dolog(...)
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#endif
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#ifndef SILENT_ES1370
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#define lwarn(...) AUD_log ("es1370: warning:", __VA_ARGS__) |
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#else
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#define lwarn(...)
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#endif
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struct chan {
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uint32_t shift; |
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uint32_t leftover; |
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uint32_t scount; |
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uint32_t frame_addr; |
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uint32_t frame_cnt; |
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}; |
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typedef struct ES1370State { |
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PCIDevice *pci_dev; |
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struct chan chan[NB_CHANNELS];
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SWVoiceOut *dac_voice[2];
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SWVoiceIn *adc_voice; |
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uint32_t ctl; |
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uint32_t status; |
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uint32_t mempage; |
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uint32_t codec; |
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uint32_t sctl; |
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} ES1370State; |
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typedef struct PCIES1370State { |
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PCIDevice dev; |
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ES1370State es1370; |
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} PCIES1370State; |
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struct chan_bits {
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uint32_t ctl_en; |
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uint32_t stat_int; |
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uint32_t sctl_pause; |
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uint32_t sctl_inten; |
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uint32_t sctl_fmt; |
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uint32_t sctl_sh_fmt; |
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uint32_t sctl_loopsel; |
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void (*calc_freq) (ES1370State *s, uint32_t ctl,
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uint32_t *old_freq, uint32_t *new_freq); |
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}; |
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static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl, |
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uint32_t *old_freq, uint32_t *new_freq); |
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static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl, |
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uint32_t *old_freq, |
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uint32_t *new_freq); |
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static const struct chan_bits es1370_chan_bits[] = { |
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{CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN, |
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SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL, |
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es1370_dac1_calc_freq}, |
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{CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN, |
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SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL, |
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es1370_dac2_and_adc_calc_freq}, |
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{CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
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SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL, |
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es1370_dac2_and_adc_calc_freq} |
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}; |
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static void es1370_update_status (ES1370State *s, uint32_t new_status) |
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{ |
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uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC); |
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if (level) {
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s->status = new_status | STAT_INTR; |
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} |
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else {
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s->status = new_status & ~STAT_INTR; |
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} |
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pci_set_irq (s->pci_dev, 0, !!level);
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} |
328 |
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static void es1370_reset (ES1370State *s) |
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{ |
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size_t i; |
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s->ctl = 1;
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s->status = 0x60;
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s->mempage = 0;
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s->codec = 0;
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s->sctl = 0;
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for (i = 0; i < NB_CHANNELS; ++i) { |
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struct chan *d = &s->chan[i];
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d->scount = 0;
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d->leftover = 0;
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if (i == ADC_CHANNEL) {
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AUD_close_in (s->adc_voice); |
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s->adc_voice = NULL;
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} |
347 |
else {
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AUD_close_out (s->dac_voice[i]); |
349 |
s->dac_voice[i] = NULL;
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} |
351 |
} |
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pci_set_irq (s->pci_dev, 0, 0); |
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} |
354 |
|
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static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl) |
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{ |
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uint32_t new_status = s->status; |
358 |
|
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if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
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new_status &= ~STAT_DAC1; |
361 |
} |
362 |
|
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if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
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new_status &= ~STAT_DAC2; |
365 |
} |
366 |
|
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if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
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new_status &= ~STAT_ADC; |
369 |
} |
370 |
|
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if (new_status != s->status) {
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es1370_update_status (s, new_status); |
373 |
} |
374 |
} |
375 |
|
376 |
static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl, |
377 |
uint32_t *old_freq, uint32_t *new_freq) |
378 |
|
379 |
{ |
380 |
*old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL]; |
381 |
*new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL]; |
382 |
} |
383 |
|
384 |
static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl, |
385 |
uint32_t *old_freq, |
386 |
uint32_t *new_freq) |
387 |
|
388 |
{ |
389 |
uint32_t old_pclkdiv, new_pclkdiv; |
390 |
|
391 |
new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV; |
392 |
old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV; |
393 |
*new_freq = DAC2_DIVTOSR (new_pclkdiv); |
394 |
*old_freq = DAC2_DIVTOSR (old_pclkdiv); |
395 |
} |
396 |
|
397 |
static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl) |
398 |
{ |
399 |
size_t i; |
400 |
uint32_t old_freq, new_freq, old_fmt, new_fmt; |
401 |
|
402 |
for (i = 0; i < NB_CHANNELS; ++i) { |
403 |
struct chan *d = &s->chan[i];
|
404 |
const struct chan_bits *b = &es1370_chan_bits[i]; |
405 |
|
406 |
new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt; |
407 |
old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt; |
408 |
|
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b->calc_freq (s, ctl, &old_freq, &new_freq); |
410 |
|
411 |
if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
|
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d->shift = (new_fmt & 1) + (new_fmt >> 1); |
413 |
ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
|
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i, |
415 |
new_freq, |
416 |
1 << (new_fmt & 1), |
417 |
(new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
|
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d->shift); |
419 |
if (new_freq) {
|
420 |
if (i == ADC_CHANNEL) {
|
421 |
s->adc_voice = |
422 |
AUD_open_in ( |
423 |
s->adc_voice, |
424 |
"es1370.adc",
|
425 |
s, |
426 |
es1370_adc_callback, |
427 |
new_freq, |
428 |
1 << (new_fmt & 1), |
429 |
(new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8
|
430 |
); |
431 |
} |
432 |
else {
|
433 |
s->dac_voice[i] = |
434 |
AUD_open_out ( |
435 |
s->dac_voice[i], |
436 |
i ? "es1370.dac2" : "es1370.dac1", |
437 |
s, |
438 |
i ? es1370_dac2_callback : es1370_dac1_callback, |
439 |
new_freq, |
440 |
1 << (new_fmt & 1), |
441 |
(new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8
|
442 |
); |
443 |
} |
444 |
} |
445 |
} |
446 |
|
447 |
if (((ctl ^ s->ctl) & b->ctl_en)
|
448 |
|| ((sctl ^ s->sctl) & b->sctl_pause)) { |
449 |
int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
|
450 |
|
451 |
if (i == ADC_CHANNEL) {
|
452 |
AUD_set_active_in (s->adc_voice, on); |
453 |
} |
454 |
else {
|
455 |
AUD_set_active_out (s->dac_voice[i], on); |
456 |
} |
457 |
} |
458 |
} |
459 |
|
460 |
s->ctl = ctl; |
461 |
s->sctl = sctl; |
462 |
} |
463 |
|
464 |
static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr) |
465 |
{ |
466 |
addr &= 0xff;
|
467 |
if (addr >= 0x30 && addr <= 0x3f) |
468 |
addr |= s->mempage << 8;
|
469 |
return addr;
|
470 |
} |
471 |
|
472 |
IO_WRITE_PROTO (es1370_writeb) |
473 |
{ |
474 |
ES1370State *s = opaque; |
475 |
addr = es1370_fixup (s, addr); |
476 |
uint32_t shift, mask; |
477 |
|
478 |
switch (addr) {
|
479 |
case ES1370_REG_CONTROL:
|
480 |
case ES1370_REG_CONTROL + 1: |
481 |
case ES1370_REG_CONTROL + 2: |
482 |
case ES1370_REG_CONTROL + 3: |
483 |
shift = (addr - ES1370_REG_CONTROL) << 3;
|
484 |
mask = 0xff << shift;
|
485 |
val = (s->ctl & ~mask) | ((val & 0xff) << shift);
|
486 |
es1370_update_voices (s, val, s->sctl); |
487 |
print_ctl (val); |
488 |
break;
|
489 |
case ES1370_REG_MEMPAGE:
|
490 |
s->mempage = val; |
491 |
break;
|
492 |
case ES1370_REG_SERIAL_CONTROL:
|
493 |
case ES1370_REG_SERIAL_CONTROL + 1: |
494 |
case ES1370_REG_SERIAL_CONTROL + 2: |
495 |
case ES1370_REG_SERIAL_CONTROL + 3: |
496 |
shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
|
497 |
mask = 0xff << shift;
|
498 |
val = (s->sctl & ~mask) | ((val & 0xff) << shift);
|
499 |
es1370_maybe_lower_irq (s, val); |
500 |
es1370_update_voices (s, s->ctl, val); |
501 |
print_sctl (val); |
502 |
break;
|
503 |
default:
|
504 |
lwarn ("writeb %#x <- %#x\n", addr, val);
|
505 |
break;
|
506 |
} |
507 |
} |
508 |
|
509 |
IO_WRITE_PROTO (es1370_writew) |
510 |
{ |
511 |
ES1370State *s = opaque; |
512 |
addr = es1370_fixup (s, addr); |
513 |
uint32_t shift, mask; |
514 |
struct chan *d = &s->chan[0]; |
515 |
|
516 |
switch (addr) {
|
517 |
case ES1370_REG_CODEC:
|
518 |
dolog ("ignored codec write address %#x, data %#x\n",
|
519 |
(val >> 8) & 0xff, val & 0xff); |
520 |
s->codec = val; |
521 |
break;
|
522 |
|
523 |
case ES1370_REG_CONTROL:
|
524 |
case ES1370_REG_CONTROL + 2: |
525 |
shift = (addr != ES1370_REG_CONTROL) << 4;
|
526 |
mask = 0xffff << shift;
|
527 |
val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
|
528 |
es1370_update_voices (s, val, s->sctl); |
529 |
print_ctl (val); |
530 |
break;
|
531 |
|
532 |
case ES1370_REG_ADC_SCOUNT:
|
533 |
d++; |
534 |
case ES1370_REG_DAC2_SCOUNT:
|
535 |
d++; |
536 |
case ES1370_REG_DAC1_SCOUNT:
|
537 |
d->scount = (d->scount & ~0xffff) | (val & 0xffff); |
538 |
break;
|
539 |
|
540 |
default:
|
541 |
lwarn ("writew %#x <- %#x\n", addr, val);
|
542 |
break;
|
543 |
} |
544 |
} |
545 |
|
546 |
IO_WRITE_PROTO (es1370_writel) |
547 |
{ |
548 |
ES1370State *s = opaque; |
549 |
struct chan *d = &s->chan[0]; |
550 |
|
551 |
addr = es1370_fixup (s, addr); |
552 |
|
553 |
switch (addr) {
|
554 |
case ES1370_REG_CONTROL:
|
555 |
es1370_update_voices (s, val, s->sctl); |
556 |
print_ctl (val); |
557 |
break;
|
558 |
|
559 |
case ES1370_REG_MEMPAGE:
|
560 |
s->mempage = val & 0xf;
|
561 |
break;
|
562 |
|
563 |
case ES1370_REG_SERIAL_CONTROL:
|
564 |
es1370_maybe_lower_irq (s, val); |
565 |
es1370_update_voices (s, s->ctl, val); |
566 |
print_sctl (val); |
567 |
break;
|
568 |
|
569 |
case ES1370_REG_ADC_SCOUNT:
|
570 |
d++; |
571 |
case ES1370_REG_DAC2_SCOUNT:
|
572 |
d++; |
573 |
case ES1370_REG_DAC1_SCOUNT:
|
574 |
d->scount = (val & 0xffff) | (d->scount & ~0xffff); |
575 |
ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
|
576 |
d - &s->chan[0], val >> 16, (val & 0xffff)); |
577 |
break;
|
578 |
|
579 |
case ES1370_REG_ADC_FRAMEADR:
|
580 |
d++; |
581 |
case ES1370_REG_DAC2_FRAMEADR:
|
582 |
d++; |
583 |
case ES1370_REG_DAC1_FRAMEADR:
|
584 |
d->frame_addr = val; |
585 |
ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val); |
586 |
break;
|
587 |
|
588 |
case ES1370_REG_ADC_FRAMECNT:
|
589 |
d++; |
590 |
case ES1370_REG_DAC2_FRAMECNT:
|
591 |
d++; |
592 |
case ES1370_REG_DAC1_FRAMECNT:
|
593 |
d->frame_cnt = val; |
594 |
d->leftover = 0;
|
595 |
ldebug ("chan %d frame count %d, buffer size %d\n",
|
596 |
d - &s->chan[0], val >> 16, val & 0xffff); |
597 |
break;
|
598 |
|
599 |
default:
|
600 |
lwarn ("writel %#x <- %#x\n", addr, val);
|
601 |
break;
|
602 |
} |
603 |
} |
604 |
|
605 |
IO_READ_PROTO (es1370_readb) |
606 |
{ |
607 |
ES1370State *s = opaque; |
608 |
uint32_t val; |
609 |
|
610 |
addr = es1370_fixup (s, addr); |
611 |
|
612 |
switch (addr) {
|
613 |
case 0x1b: /* Legacy */ |
614 |
lwarn ("Attempt to read from legacy register\n");
|
615 |
val = 5;
|
616 |
break;
|
617 |
case ES1370_REG_MEMPAGE:
|
618 |
val = s->mempage; |
619 |
break;
|
620 |
case ES1370_REG_CONTROL + 0: |
621 |
case ES1370_REG_CONTROL + 1: |
622 |
case ES1370_REG_CONTROL + 2: |
623 |
case ES1370_REG_CONTROL + 3: |
624 |
val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
|
625 |
break;
|
626 |
case ES1370_REG_STATUS + 0: |
627 |
case ES1370_REG_STATUS + 1: |
628 |
case ES1370_REG_STATUS + 2: |
629 |
case ES1370_REG_STATUS + 3: |
630 |
val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
|
631 |
break;
|
632 |
default:
|
633 |
val = ~0;
|
634 |
lwarn ("readb %#x -> %#x\n", addr, val);
|
635 |
break;
|
636 |
} |
637 |
return val;
|
638 |
} |
639 |
|
640 |
IO_READ_PROTO (es1370_readw) |
641 |
{ |
642 |
ES1370State *s = opaque; |
643 |
struct chan *d = &s->chan[0]; |
644 |
uint32_t val; |
645 |
|
646 |
addr = es1370_fixup (s, addr); |
647 |
|
648 |
switch (addr) {
|
649 |
case ES1370_REG_ADC_SCOUNT + 2: |
650 |
d++; |
651 |
case ES1370_REG_DAC2_SCOUNT + 2: |
652 |
d++; |
653 |
case ES1370_REG_DAC1_SCOUNT + 2: |
654 |
val = d->scount >> 16;
|
655 |
break;
|
656 |
|
657 |
default:
|
658 |
val = ~0;
|
659 |
lwarn ("readw %#x -> %#x\n", addr, val);
|
660 |
break;
|
661 |
} |
662 |
|
663 |
return val;
|
664 |
} |
665 |
|
666 |
IO_READ_PROTO (es1370_readl) |
667 |
{ |
668 |
ES1370State *s = opaque; |
669 |
uint32_t val; |
670 |
struct chan *d = &s->chan[0]; |
671 |
|
672 |
addr = es1370_fixup (s, addr); |
673 |
|
674 |
switch (addr) {
|
675 |
case ES1370_REG_CONTROL:
|
676 |
val = s->ctl; |
677 |
break;
|
678 |
case ES1370_REG_STATUS:
|
679 |
val = s->status; |
680 |
break;
|
681 |
case ES1370_REG_MEMPAGE:
|
682 |
val = s->mempage; |
683 |
break;
|
684 |
case ES1370_REG_CODEC:
|
685 |
val = s->codec; |
686 |
break;
|
687 |
case ES1370_REG_SERIAL_CONTROL:
|
688 |
val = s->sctl; |
689 |
break;
|
690 |
|
691 |
case ES1370_REG_ADC_SCOUNT:
|
692 |
d++; |
693 |
case ES1370_REG_DAC2_SCOUNT:
|
694 |
d++; |
695 |
case ES1370_REG_DAC1_SCOUNT:
|
696 |
val = d->scount; |
697 |
#ifdef DEBUG_ES1370
|
698 |
{ |
699 |
uint32_t curr_count = d->scount >> 16;
|
700 |
uint32_t count = d->scount & 0xffff;
|
701 |
|
702 |
curr_count <<= d->shift; |
703 |
count <<= d->shift; |
704 |
dolog ("read scount curr %d, total %d\n", curr_count, count);
|
705 |
} |
706 |
#endif
|
707 |
break;
|
708 |
|
709 |
case ES1370_REG_ADC_FRAMECNT:
|
710 |
d++; |
711 |
case ES1370_REG_DAC2_FRAMECNT:
|
712 |
d++; |
713 |
case ES1370_REG_DAC1_FRAMECNT:
|
714 |
val = d->frame_cnt; |
715 |
#ifdef DEBUG_ES1370
|
716 |
{ |
717 |
uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2; |
718 |
uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2; |
719 |
if (curr > size)
|
720 |
dolog ("read framecnt curr %d, size %d %d\n", curr, size,
|
721 |
curr > size); |
722 |
} |
723 |
#endif
|
724 |
break;
|
725 |
|
726 |
case ES1370_REG_ADC_FRAMEADR:
|
727 |
d++; |
728 |
case ES1370_REG_DAC2_FRAMEADR:
|
729 |
d++; |
730 |
case ES1370_REG_DAC1_FRAMEADR:
|
731 |
val = d->frame_addr; |
732 |
break;
|
733 |
|
734 |
default:
|
735 |
val = ~0U;
|
736 |
lwarn ("readl %#x -> %#x\n", addr, val);
|
737 |
break;
|
738 |
} |
739 |
return val;
|
740 |
} |
741 |
|
742 |
|
743 |
static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel, |
744 |
int max, int *irq) |
745 |
{ |
746 |
uint8_t tmpbuf[4096];
|
747 |
uint32_t addr = d->frame_addr; |
748 |
int sc = d->scount & 0xffff; |
749 |
int csc = d->scount >> 16; |
750 |
int csc_bytes = (csc + 1) << d->shift; |
751 |
int cnt = d->frame_cnt >> 16; |
752 |
int size = d->frame_cnt & 0xffff; |
753 |
int left = ((size - cnt + 1) << 2) + d->leftover; |
754 |
int transfered = 0; |
755 |
int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
|
756 |
int index = d - &s->chan[0]; |
757 |
|
758 |
addr += (cnt << 2) + d->leftover;
|
759 |
|
760 |
if (index == ADC_CHANNEL) {
|
761 |
while (temp) {
|
762 |
int acquired, to_copy;
|
763 |
|
764 |
to_copy = audio_MIN (temp, sizeof (tmpbuf));
|
765 |
acquired = AUD_read (s->adc_voice, tmpbuf, to_copy); |
766 |
if (!acquired)
|
767 |
break;
|
768 |
|
769 |
cpu_physical_memory_write (addr, tmpbuf, acquired); |
770 |
|
771 |
temp -= acquired; |
772 |
addr += acquired; |
773 |
transfered += acquired; |
774 |
} |
775 |
} |
776 |
else {
|
777 |
SWVoiceOut *voice = s->dac_voice[index]; |
778 |
|
779 |
while (temp) {
|
780 |
int copied, to_copy;
|
781 |
|
782 |
to_copy = audio_MIN (temp, sizeof (tmpbuf));
|
783 |
cpu_physical_memory_read (addr, tmpbuf, to_copy); |
784 |
copied = AUD_write (voice, tmpbuf, to_copy); |
785 |
if (!copied)
|
786 |
break;
|
787 |
temp -= copied; |
788 |
addr += copied; |
789 |
transfered += copied; |
790 |
} |
791 |
} |
792 |
|
793 |
if (csc_bytes == transfered) {
|
794 |
*irq = 1;
|
795 |
d->scount = sc | (sc << 16);
|
796 |
ldebug ("sc = %d, rate = %f\n",
|
797 |
(sc + 1) << d->shift,
|
798 |
(sc + 1) / (double) 44100); |
799 |
} |
800 |
else {
|
801 |
*irq = 0;
|
802 |
d->scount = sc | (((csc_bytes - transfered - 1) >> d->shift) << 16); |
803 |
} |
804 |
|
805 |
cnt += (transfered + d->leftover) >> 2;
|
806 |
|
807 |
if (s->sctl & loop_sel) {
|
808 |
/* Bah, how stupid is that having a 0 represent true value?
|
809 |
i just spent few hours on this shit */
|
810 |
lwarn ("whoops non looping mode\n");
|
811 |
} |
812 |
else {
|
813 |
d->frame_cnt = size; |
814 |
|
815 |
if (cnt <= d->frame_cnt)
|
816 |
d->frame_cnt |= cnt << 16;
|
817 |
} |
818 |
|
819 |
d->leftover = (transfered + d->leftover) & 3;
|
820 |
} |
821 |
|
822 |
static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail) |
823 |
{ |
824 |
uint32_t new_status = s->status; |
825 |
int max_bytes, irq;
|
826 |
struct chan *d = &s->chan[chan];
|
827 |
const struct chan_bits *b = &es1370_chan_bits[chan]; |
828 |
|
829 |
if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
|
830 |
return;
|
831 |
} |
832 |
|
833 |
max_bytes = free_or_avail; |
834 |
max_bytes &= ~((1 << d->shift) - 1); |
835 |
if (!max_bytes) {
|
836 |
return;
|
837 |
} |
838 |
|
839 |
es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq); |
840 |
|
841 |
if (irq) {
|
842 |
if (s->sctl & b->sctl_inten) {
|
843 |
new_status |= b->stat_int; |
844 |
} |
845 |
} |
846 |
|
847 |
if (new_status != s->status) {
|
848 |
es1370_update_status (s, new_status); |
849 |
} |
850 |
} |
851 |
|
852 |
static void es1370_dac1_callback (void *opaque, int free) |
853 |
{ |
854 |
ES1370State *s = opaque; |
855 |
|
856 |
es1370_run_channel (s, DAC1_CHANNEL, free); |
857 |
} |
858 |
|
859 |
static void es1370_dac2_callback (void *opaque, int free) |
860 |
{ |
861 |
ES1370State *s = opaque; |
862 |
|
863 |
es1370_run_channel (s, DAC2_CHANNEL, free); |
864 |
} |
865 |
|
866 |
static void es1370_adc_callback (void *opaque, int avail) |
867 |
{ |
868 |
ES1370State *s = opaque; |
869 |
|
870 |
es1370_run_channel (s, ADC_CHANNEL, avail); |
871 |
} |
872 |
|
873 |
static void es1370_map (PCIDevice *pci_dev, int region_num, |
874 |
uint32_t addr, uint32_t size, int type)
|
875 |
{ |
876 |
PCIES1370State *d = (PCIES1370State *) pci_dev; |
877 |
ES1370State *s = &d->es1370; |
878 |
|
879 |
register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s); |
880 |
register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s); |
881 |
register_ioport_write (addr, 0x40, 4, es1370_writel, s); |
882 |
|
883 |
register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s); |
884 |
register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s); |
885 |
register_ioport_read (addr, 0x40, 4, es1370_readl, s); |
886 |
} |
887 |
|
888 |
static void es1370_save (QEMUFile *f, void *opaque) |
889 |
{ |
890 |
ES1370State *s = opaque; |
891 |
size_t i; |
892 |
|
893 |
for (i = 0; i < NB_CHANNELS; ++i) { |
894 |
struct chan *d = &s->chan[i];
|
895 |
qemu_put_be32s (f, &d->shift); |
896 |
qemu_put_be32s (f, &d->leftover); |
897 |
qemu_put_be32s (f, &d->scount); |
898 |
qemu_put_be32s (f, &d->frame_addr); |
899 |
qemu_put_be32s (f, &d->frame_cnt); |
900 |
} |
901 |
qemu_put_be32s (f, &s->ctl); |
902 |
qemu_put_be32s (f, &s->status); |
903 |
qemu_put_be32s (f, &s->mempage); |
904 |
qemu_put_be32s (f, &s->codec); |
905 |
qemu_put_be32s (f, &s->sctl); |
906 |
} |
907 |
|
908 |
static int es1370_load (QEMUFile *f, void *opaque, int version_id) |
909 |
{ |
910 |
uint32_t ctl, sctl; |
911 |
ES1370State *s = opaque; |
912 |
size_t i; |
913 |
|
914 |
if (version_id != 1) |
915 |
return -EINVAL;
|
916 |
|
917 |
for (i = 0; i < NB_CHANNELS; ++i) { |
918 |
struct chan *d = &s->chan[i];
|
919 |
qemu_get_be32s (f, &d->shift); |
920 |
qemu_get_be32s (f, &d->leftover); |
921 |
qemu_get_be32s (f, &d->scount); |
922 |
qemu_get_be32s (f, &d->frame_addr); |
923 |
qemu_get_be32s (f, &d->frame_cnt); |
924 |
if (i == ADC_CHANNEL) {
|
925 |
if (s->adc_voice) {
|
926 |
AUD_close_in (s->adc_voice); |
927 |
s->adc_voice = NULL;
|
928 |
} |
929 |
} |
930 |
else {
|
931 |
if (s->dac_voice[i]) {
|
932 |
AUD_close_out (s->dac_voice[i]); |
933 |
s->dac_voice[i] = NULL;
|
934 |
} |
935 |
} |
936 |
} |
937 |
|
938 |
qemu_get_be32s (f, &ctl); |
939 |
qemu_get_be32s (f, &s->status); |
940 |
qemu_get_be32s (f, &s->mempage); |
941 |
qemu_get_be32s (f, &s->codec); |
942 |
qemu_get_be32s (f, &sctl); |
943 |
|
944 |
s->ctl = 0;
|
945 |
s->sctl = 0;
|
946 |
es1370_update_voices (s, ctl, sctl); |
947 |
return 0; |
948 |
} |
949 |
|
950 |
static void es1370_on_reset (void *opaque) |
951 |
{ |
952 |
ES1370State *s = opaque; |
953 |
es1370_reset (s); |
954 |
} |
955 |
|
956 |
int es1370_init (PCIBus *bus)
|
957 |
{ |
958 |
PCIES1370State *d; |
959 |
ES1370State *s; |
960 |
uint8_t *c; |
961 |
|
962 |
d = (PCIES1370State *) pci_register_device (bus, "ES1370",
|
963 |
sizeof (PCIES1370State),
|
964 |
-1, NULL, NULL); |
965 |
|
966 |
if (!d) {
|
967 |
fprintf (stderr, "Failed to register PCI device for ES1370\n");
|
968 |
return -1; |
969 |
} |
970 |
|
971 |
c = d->dev.config; |
972 |
c[0x00] = 0x74; |
973 |
c[0x01] = 0x12; |
974 |
c[0x02] = 0x00; |
975 |
c[0x03] = 0x50; |
976 |
c[0x07] = 2 << 1; |
977 |
c[0x0a] = 0x01; |
978 |
c[0x0b] = 0x04; |
979 |
|
980 |
#if 1 |
981 |
c[0x2c] = 0x42; |
982 |
c[0x2d] = 0x49; |
983 |
c[0x2e] = 0x4c; |
984 |
c[0x2f] = 0x4c; |
985 |
#else
|
986 |
c[0x2c] = 0x74; |
987 |
c[0x2d] = 0x12; |
988 |
c[0x2e] = 0x71; |
989 |
c[0x2f] = 0x13; |
990 |
c[0x34] = 0xdc; |
991 |
c[0x3c] = 10; |
992 |
c[0xdc] = 0x00; |
993 |
#endif
|
994 |
|
995 |
c[0x3d] = 1; |
996 |
c[0x3e] = 0x0c; |
997 |
c[0x3f] = 0x80; |
998 |
|
999 |
s = &d->es1370; |
1000 |
s->pci_dev = &d->dev; |
1001 |
|
1002 |
pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map); |
1003 |
register_savevm ("es1370", 0, 1, es1370_save, es1370_load, s); |
1004 |
qemu_register_reset (es1370_on_reset, s); |
1005 |
es1370_reset (s); |
1006 |
return 0; |
1007 |
} |