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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%rax",
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    "%rcx",
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    "%rdx",
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    "%rbx",
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    "%rsp",
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    "%rbp",
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    "%rsi",
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    "%rdi",
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    "%r8",
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    "%r9",
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    "%r10",
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    "%r11",
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    "%r12",
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    "%r13",
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    "%r14",
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    "%r15",
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};
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#endif
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static const int tcg_target_reg_alloc_order[] = {
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    TCG_REG_RBP,
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    TCG_REG_RBX,
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    TCG_REG_R12,
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    TCG_REG_R13,
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    TCG_REG_R14,
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    TCG_REG_R15,
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    TCG_REG_R10,
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    TCG_REG_R11,
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    TCG_REG_R9,
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    TCG_REG_R8,
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    TCG_REG_RCX,
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    TCG_REG_RDX,
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    TCG_REG_RSI,
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    TCG_REG_RDI,
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    TCG_REG_RAX,
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};
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static const int tcg_target_call_iarg_regs[6] = {
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    TCG_REG_RDI,
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    TCG_REG_RSI,
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    TCG_REG_RDX,
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    TCG_REG_RCX,
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    TCG_REG_R8,
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    TCG_REG_R9,
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};
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static const int tcg_target_call_oarg_regs[2] = {
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    TCG_REG_RAX, 
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    TCG_REG_RDX 
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};
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type, 
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                        tcg_target_long value, tcg_target_long addend)
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{
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    value += addend;
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    switch(type) {
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    case R_X86_64_32:
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        if (value != (uint32_t)value)
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            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
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    case R_X86_64_32S:
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        if (value != (int32_t)value)
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            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
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    case R_386_PC32:
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        value -= (long)code_ptr;
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        if (value != (int32_t)value)
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            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
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    default:
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        tcg_abort();
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    }
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}
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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    return 6;
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}
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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    const char *ct_str;
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    ct_str = *pct_str;
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    switch(ct_str[0]) {
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    case 'a':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
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        break;
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    case 'b':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
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        break;
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    case 'c':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
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        break;
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    case 'd':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
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        break;
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    case 'S':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
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        break;
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    case 'D':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
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        break;
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    case 'q':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xf);
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        break;
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    case 'r':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xffff);
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        break;
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    case 'L': /* qemu_ld/st constraint */
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xffff);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
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        break;
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    case 'e':
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        ct->ct |= TCG_CT_CONST_S32;
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        break;
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    case 'Z':
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        ct->ct |= TCG_CT_CONST_U32;
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        break;
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    default:
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        return -1;
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    }
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    ct_str++;
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    *pct_str = ct_str;
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    return 0;
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}
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val,
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                                         const TCGArgConstraint *arg_ct)
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{
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    int ct;
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    ct = arg_ct->ct;
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    if (ct & TCG_CT_CONST)
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        return 1;
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    else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
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        return 1;
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    else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
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        return 1;
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    else
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        return 0;
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}
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#define ARITH_ADD 0
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#define ARITH_OR  1
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#define ARITH_ADC 2
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#define ARITH_SBB 3
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#define ARITH_AND 4
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#define ARITH_SUB 5
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#define ARITH_XOR 6
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#define ARITH_CMP 7
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#define SHIFT_ROL 0
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#define SHIFT_ROR 1
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#define SHIFT_SHL 4
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#define SHIFT_SHR 5
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#define SHIFT_SAR 7
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#define JCC_JMP (-1)
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#define JCC_JO  0x0
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#define JCC_JNO 0x1
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#define JCC_JB  0x2
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#define JCC_JAE 0x3
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#define JCC_JE  0x4
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#define JCC_JNE 0x5
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#define JCC_JBE 0x6
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#define JCC_JA  0x7
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#define JCC_JS  0x8
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#define JCC_JNS 0x9
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#define JCC_JP  0xa
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#define JCC_JNP 0xb
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#define JCC_JL  0xc
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#define JCC_JGE 0xd
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#define JCC_JLE 0xe
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#define JCC_JG  0xf
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#define P_EXT                0x100                /* 0x0f opcode prefix */
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#define P_REXW                0x200                /* set rex.w = 1 */
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#define P_REXB_R        0x400                /* REG field as byte register */
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#define P_REXB_RM        0x800                /* R/M field as byte register */
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static const uint8_t tcg_cond_to_jcc[10] = {
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    [TCG_COND_EQ] = JCC_JE,
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    [TCG_COND_NE] = JCC_JNE,
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    [TCG_COND_LT] = JCC_JL,
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    [TCG_COND_GE] = JCC_JGE,
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    [TCG_COND_LE] = JCC_JLE,
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    [TCG_COND_GT] = JCC_JG,
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    [TCG_COND_LTU] = JCC_JB,
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    [TCG_COND_GEU] = JCC_JAE,
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    [TCG_COND_LEU] = JCC_JBE,
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    [TCG_COND_GTU] = JCC_JA,
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};
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static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
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{
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    int rex = 0;
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    rex |= (opc & P_REXW) >> 6;                /* REX.W */
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    rex |= (r & 8) >> 1;                /* REX.R */
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    rex |= (x & 8) >> 2;                /* REX.X */
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    rex |= (rm & 8) >> 3;                /* REX.B */
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    /* P_REXB_{R,RM} indicates that the given register is the low byte.
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       For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
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       as otherwise the encoding indicates %[abcd]h.  Note that the values
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       that are ORed in merely indicate that the REX byte must be present;
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       those bits get discarded in output.  */
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    rex |= opc & (r >= 4 ? P_REXB_R : 0);
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    rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
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    if (rex) {
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        tcg_out8(s, (uint8_t)(rex | 0x40));
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    }
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    if (opc & P_EXT) {
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        tcg_out8(s, 0x0f);
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    }
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    tcg_out8(s, opc & 0xff);
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}
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static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
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{
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    tcg_out_opc(s, opc, r, rm, 0);
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    tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
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}
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/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, 
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                                        tcg_target_long offset)
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{
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    if (rm < 0) {
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        tcg_target_long val;
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        tcg_out_opc(s, opc, r, 0, 0);
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        val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
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        if (val == (int32_t)val) {
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            /* eip relative */
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            tcg_out8(s, 0x05 | ((r & 7) << 3));
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            tcg_out32(s, val);
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        } else if (offset == (int32_t)offset) {
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            tcg_out8(s, 0x04 | ((r & 7) << 3));
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            tcg_out8(s, 0x25); /* sib */
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            tcg_out32(s, offset);
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        } else {
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            tcg_abort();
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        }
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    } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, 0x04 | ((r & 7) << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
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        }
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    } else if ((int8_t)offset == offset) {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, 0x44 | ((r & 7) << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
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        }
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        tcg_out8(s, offset);
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    } else {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, 0x84 | ((r & 7) << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
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        }
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        tcg_out32(s, offset);
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    }
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}
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#if defined(CONFIG_SOFTMMU)
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/* XXX: incomplete. index must be different from ESP */
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static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, 
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                                  int index, int shift,
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                                  tcg_target_long offset)
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{
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    int mod;
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    if (rm == -1)
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        tcg_abort();
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    if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
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        mod = 0;
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    } else if (offset == (int8_t)offset) {
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        mod = 0x40;
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    } else if (offset == (int32_t)offset) {
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        mod = 0x80;
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    } else {
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        tcg_abort();
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    }
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    if (index == -1) {
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        tcg_out_opc(s, opc, r, rm, 0);
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        if ((rm & 7) == TCG_REG_RSP) {
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            tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
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            tcg_out8(s, 0x04 | (rm & 7));
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        } else {
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            tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
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        }
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    } else {
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        tcg_out_opc(s, opc, r, rm, index);
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        tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
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        tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
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    }
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    if (mod == 0x40) {
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        tcg_out8(s, offset);
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    } else if (mod == 0x80) {
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        tcg_out32(s, offset);
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    }
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}
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#endif
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
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{
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    tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
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}
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static inline void tcg_out_movi(TCGContext *s, TCGType type, 
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                                int ret, tcg_target_long arg)
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{
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    if (arg == 0) {
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        tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
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    } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
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        tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
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        tcg_out32(s, arg);
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    } else if (arg == (int32_t)arg) {
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        tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
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        tcg_out32(s, arg);
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    } else {
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        tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
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        tcg_out32(s, arg);
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        tcg_out32(s, arg >> 32);
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    }
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}
379 c896fe29 bellard
380 abb6ae2c malc
static void tcg_out_goto(TCGContext *s, int call, uint8_t *target)
381 abb6ae2c malc
{
382 abb6ae2c malc
    int32_t disp;
383 abb6ae2c malc
384 abb6ae2c malc
    disp = target - s->code_ptr - 5;
385 abb6ae2c malc
    if (disp == (target - s->code_ptr - 5)) {
386 abb6ae2c malc
        tcg_out8(s, call ? 0xe8 : 0xe9);
387 abb6ae2c malc
        tcg_out32(s, disp);
388 abb6ae2c malc
    } else {
389 abb6ae2c malc
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target);
390 abb6ae2c malc
        tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10);
391 abb6ae2c malc
    }
392 abb6ae2c malc
}
393 abb6ae2c malc
394 e4d5434c blueswir1
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
395 c896fe29 bellard
                              int arg1, tcg_target_long arg2)
396 c896fe29 bellard
{
397 e4d5434c blueswir1
    if (type == TCG_TYPE_I32)
398 e4d5434c blueswir1
        tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
399 e4d5434c blueswir1
    else
400 e4d5434c blueswir1
        tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
401 c896fe29 bellard
}
402 c896fe29 bellard
403 e4d5434c blueswir1
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
404 c896fe29 bellard
                              int arg1, tcg_target_long arg2)
405 c896fe29 bellard
{
406 e4d5434c blueswir1
    if (type == TCG_TYPE_I32)
407 e4d5434c blueswir1
        tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
408 e4d5434c blueswir1
    else
409 e4d5434c blueswir1
        tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
410 c896fe29 bellard
}
411 c896fe29 bellard
412 c896fe29 bellard
static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
413 c896fe29 bellard
{
414 a4b18c6d Aurelien Jarno
    if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
415 a4b18c6d Aurelien Jarno
        /* inc */
416 a4b18c6d Aurelien Jarno
        tcg_out_modrm(s, 0xff, 0, r0);
417 a4b18c6d Aurelien Jarno
    } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
418 a4b18c6d Aurelien Jarno
        /* dec */
419 a4b18c6d Aurelien Jarno
        tcg_out_modrm(s, 0xff, 1, r0);
420 a4b18c6d Aurelien Jarno
    } else if (val == (int8_t)val) {
421 c896fe29 bellard
        tcg_out_modrm(s, 0x83, c, r0);
422 c896fe29 bellard
        tcg_out8(s, val);
423 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffu) {
424 733fef0e pbrook
        /* movzbl */
425 09aac126 Richard Henderson
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, r0, r0);
426 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffffu) {
427 733fef0e pbrook
        /* movzwl */
428 733fef0e pbrook
        tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
429 c896fe29 bellard
    } else {
430 c896fe29 bellard
        tcg_out_modrm(s, 0x81, c, r0);
431 c896fe29 bellard
        tcg_out32(s, val);
432 c896fe29 bellard
    }
433 c896fe29 bellard
}
434 c896fe29 bellard
435 c896fe29 bellard
static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
436 c896fe29 bellard
{
437 a4b18c6d Aurelien Jarno
    if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
438 a4b18c6d Aurelien Jarno
        /* inc */
439 a4b18c6d Aurelien Jarno
        tcg_out_modrm(s, 0xff | P_REXW, 0, r0);
440 a4b18c6d Aurelien Jarno
    } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
441 a4b18c6d Aurelien Jarno
        /* dec */
442 a4b18c6d Aurelien Jarno
        tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
443 733fef0e pbrook
    } else if (c == ARITH_AND && val == 0xffffffffu) {
444 733fef0e pbrook
        /* 32-bit mov zero extends */
445 733fef0e pbrook
        tcg_out_modrm(s, 0x8b, r0, r0);
446 57169903 Richard Henderson
    } else if (c == ARITH_AND && val == (uint32_t)val) {
447 57169903 Richard Henderson
        /* AND with no high bits set can use a 32-bit operation.  */
448 57169903 Richard Henderson
        tgen_arithi32(s, c, r0, (uint32_t)val);
449 57169903 Richard Henderson
    } else if (val == (int8_t)val) {
450 57169903 Richard Henderson
        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
451 57169903 Richard Henderson
        tcg_out8(s, val);
452 c896fe29 bellard
    } else if (val == (int32_t)val) {
453 c896fe29 bellard
        tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
454 c896fe29 bellard
        tcg_out32(s, val);
455 c896fe29 bellard
    } else {
456 c896fe29 bellard
        tcg_abort();
457 c896fe29 bellard
    }
458 c896fe29 bellard
}
459 c896fe29 bellard
460 8fcd3692 blueswir1
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
461 c896fe29 bellard
{
462 c896fe29 bellard
    if (val != 0)
463 c896fe29 bellard
        tgen_arithi64(s, ARITH_ADD, reg, val);
464 c896fe29 bellard
}
465 c896fe29 bellard
466 c896fe29 bellard
static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
467 c896fe29 bellard
{
468 c896fe29 bellard
    int32_t val, val1;
469 c896fe29 bellard
    TCGLabel *l = &s->labels[label_index];
470 c896fe29 bellard
    
471 c896fe29 bellard
    if (l->has_value) {
472 c896fe29 bellard
        val = l->u.value - (tcg_target_long)s->code_ptr;
473 c896fe29 bellard
        val1 = val - 2;
474 c896fe29 bellard
        if ((int8_t)val1 == val1) {
475 c896fe29 bellard
            if (opc == -1)
476 c896fe29 bellard
                tcg_out8(s, 0xeb);
477 c896fe29 bellard
            else
478 c896fe29 bellard
                tcg_out8(s, 0x70 + opc);
479 c896fe29 bellard
            tcg_out8(s, val1);
480 c896fe29 bellard
        } else {
481 c896fe29 bellard
            if (opc == -1) {
482 c896fe29 bellard
                tcg_out8(s, 0xe9);
483 c896fe29 bellard
                tcg_out32(s, val - 5);
484 c896fe29 bellard
            } else {
485 c896fe29 bellard
                tcg_out8(s, 0x0f);
486 c896fe29 bellard
                tcg_out8(s, 0x80 + opc);
487 c896fe29 bellard
                tcg_out32(s, val - 6);
488 c896fe29 bellard
            }
489 c896fe29 bellard
        }
490 c896fe29 bellard
    } else {
491 c896fe29 bellard
        if (opc == -1) {
492 c896fe29 bellard
            tcg_out8(s, 0xe9);
493 c896fe29 bellard
        } else {
494 c896fe29 bellard
            tcg_out8(s, 0x0f);
495 c896fe29 bellard
            tcg_out8(s, 0x80 + opc);
496 c896fe29 bellard
        }
497 c896fe29 bellard
        tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
498 623e265c pbrook
        s->code_ptr += 4;
499 c896fe29 bellard
    }
500 c896fe29 bellard
}
501 c896fe29 bellard
502 8f9db67c Richard Henderson
static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
503 8f9db67c Richard Henderson
                        int const_arg2, int rexw)
504 c896fe29 bellard
{
505 c896fe29 bellard
    if (const_arg2) {
506 c896fe29 bellard
        if (arg2 == 0) {
507 c896fe29 bellard
            /* test r, r */
508 c896fe29 bellard
            tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
509 c896fe29 bellard
        } else {
510 8f9db67c Richard Henderson
            if (rexw) {
511 c896fe29 bellard
                tgen_arithi64(s, ARITH_CMP, arg1, arg2);
512 8f9db67c Richard Henderson
            } else {
513 c896fe29 bellard
                tgen_arithi32(s, ARITH_CMP, arg1, arg2);
514 8f9db67c Richard Henderson
            }
515 c896fe29 bellard
        }
516 c896fe29 bellard
    } else {
517 bb210e78 bellard
        tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
518 c896fe29 bellard
    }
519 8f9db67c Richard Henderson
}
520 8f9db67c Richard Henderson
521 8f9db67c Richard Henderson
static void tcg_out_brcond(TCGContext *s, int cond,
522 8f9db67c Richard Henderson
                           TCGArg arg1, TCGArg arg2, int const_arg2,
523 8f9db67c Richard Henderson
                           int label_index, int rexw)
524 8f9db67c Richard Henderson
{
525 8f9db67c Richard Henderson
    tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
526 560f92cc bellard
    tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
527 c896fe29 bellard
}
528 c896fe29 bellard
529 8f9db67c Richard Henderson
static void tcg_out_setcond(TCGContext *s, int cond, TCGArg dest,
530 8f9db67c Richard Henderson
                            TCGArg arg1, TCGArg arg2, int const_arg2, int rexw)
531 8f9db67c Richard Henderson
{
532 8f9db67c Richard Henderson
    tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
533 8f9db67c Richard Henderson
    /* setcc */
534 8f9db67c Richard Henderson
    tcg_out_modrm(s, 0x90 | tcg_cond_to_jcc[cond] | P_EXT | P_REXB_RM, 0, dest);
535 8f9db67c Richard Henderson
    tgen_arithi32(s, ARITH_AND, dest, 0xff);
536 8f9db67c Richard Henderson
}
537 8f9db67c Richard Henderson
538 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
539 c896fe29 bellard
540 79383c9c blueswir1
#include "../../softmmu_defs.h"
541 c896fe29 bellard
542 c896fe29 bellard
static void *qemu_ld_helpers[4] = {
543 c896fe29 bellard
    __ldb_mmu,
544 c896fe29 bellard
    __ldw_mmu,
545 c896fe29 bellard
    __ldl_mmu,
546 c896fe29 bellard
    __ldq_mmu,
547 c896fe29 bellard
};
548 c896fe29 bellard
549 c896fe29 bellard
static void *qemu_st_helpers[4] = {
550 c896fe29 bellard
    __stb_mmu,
551 c896fe29 bellard
    __stw_mmu,
552 c896fe29 bellard
    __stl_mmu,
553 c896fe29 bellard
    __stq_mmu,
554 c896fe29 bellard
};
555 c896fe29 bellard
#endif
556 c896fe29 bellard
557 c896fe29 bellard
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
558 c896fe29 bellard
                            int opc)
559 c896fe29 bellard
{
560 c896fe29 bellard
    int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
561 379f6698 Paul Brook
    int32_t offset;
562 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
563 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
564 c896fe29 bellard
#endif
565 c896fe29 bellard
566 c896fe29 bellard
    data_reg = *args++;
567 c896fe29 bellard
    addr_reg = *args++;
568 c896fe29 bellard
    mem_index = *args;
569 c896fe29 bellard
    s_bits = opc & 3;
570 c896fe29 bellard
571 c896fe29 bellard
    r0 = TCG_REG_RDI;
572 c896fe29 bellard
    r1 = TCG_REG_RSI;
573 c896fe29 bellard
574 c896fe29 bellard
#if TARGET_LONG_BITS == 32
575 c896fe29 bellard
    rexw = 0;
576 c896fe29 bellard
#else
577 c896fe29 bellard
    rexw = P_REXW;
578 c896fe29 bellard
#endif
579 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
580 c896fe29 bellard
    /* mov */
581 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
582 c896fe29 bellard
583 c896fe29 bellard
    /* mov */
584 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
585 c896fe29 bellard
 
586 c896fe29 bellard
    tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
587 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
588 c896fe29 bellard
    
589 c896fe29 bellard
    tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
590 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
591 c896fe29 bellard
    
592 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
593 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
594 c896fe29 bellard
595 c896fe29 bellard
    /* lea offset(r1, env), r1 */
596 c896fe29 bellard
    tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
597 c896fe29 bellard
                          offsetof(CPUState, tlb_table[mem_index][0].addr_read));
598 c896fe29 bellard
599 c896fe29 bellard
    /* cmp 0(r1), r0 */
600 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
601 c896fe29 bellard
    
602 c896fe29 bellard
    /* mov */
603 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
604 c896fe29 bellard
    
605 c896fe29 bellard
    /* je label1 */
606 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
607 c896fe29 bellard
    label1_ptr = s->code_ptr;
608 c896fe29 bellard
    s->code_ptr++;
609 c896fe29 bellard
610 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
611 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
612 abb6ae2c malc
    tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]);
613 c896fe29 bellard
614 c896fe29 bellard
    switch(opc) {
615 c896fe29 bellard
    case 0 | 4:
616 c896fe29 bellard
        /* movsbq */
617 c896fe29 bellard
        tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
618 c896fe29 bellard
        break;
619 c896fe29 bellard
    case 1 | 4:
620 c896fe29 bellard
        /* movswq */
621 c896fe29 bellard
        tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
622 c896fe29 bellard
        break;
623 c896fe29 bellard
    case 2 | 4:
624 c896fe29 bellard
        /* movslq */
625 c896fe29 bellard
        tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
626 c896fe29 bellard
        break;
627 c896fe29 bellard
    case 0:
628 9db3ba4d aurel32
        /* movzbq */
629 9db3ba4d aurel32
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
630 9db3ba4d aurel32
        break;
631 c896fe29 bellard
    case 1:
632 9db3ba4d aurel32
        /* movzwq */
633 9db3ba4d aurel32
        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
634 9db3ba4d aurel32
        break;
635 c896fe29 bellard
    case 2:
636 c896fe29 bellard
    default:
637 c896fe29 bellard
        /* movl */
638 c896fe29 bellard
        tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
639 c896fe29 bellard
        break;
640 c896fe29 bellard
    case 3:
641 c896fe29 bellard
        tcg_out_mov(s, data_reg, TCG_REG_RAX);
642 c896fe29 bellard
        break;
643 c896fe29 bellard
    }
644 c896fe29 bellard
645 c896fe29 bellard
    /* jmp label2 */
646 c896fe29 bellard
    tcg_out8(s, 0xeb);
647 c896fe29 bellard
    label2_ptr = s->code_ptr;
648 c896fe29 bellard
    s->code_ptr++;
649 c896fe29 bellard
    
650 c896fe29 bellard
    /* label1: */
651 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
652 c896fe29 bellard
653 c896fe29 bellard
    /* add x(r1), r0 */
654 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) - 
655 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_read));
656 379f6698 Paul Brook
    offset = 0;
657 c896fe29 bellard
#else
658 379f6698 Paul Brook
    if (GUEST_BASE == (int32_t)GUEST_BASE) {
659 379f6698 Paul Brook
        r0 = addr_reg;
660 379f6698 Paul Brook
        offset = GUEST_BASE;
661 379f6698 Paul Brook
    } else {
662 379f6698 Paul Brook
        offset = 0;
663 379f6698 Paul Brook
        /* movq $GUEST_BASE, r0 */
664 379f6698 Paul Brook
        tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
665 379f6698 Paul Brook
        tcg_out32(s, GUEST_BASE);
666 379f6698 Paul Brook
        tcg_out32(s, GUEST_BASE >> 32);
667 379f6698 Paul Brook
        /* addq addr_reg, r0 */
668 379f6698 Paul Brook
        tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
669 379f6698 Paul Brook
    }
670 c896fe29 bellard
#endif    
671 c896fe29 bellard
672 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
673 c896fe29 bellard
    bswap = 1;
674 c896fe29 bellard
#else
675 c896fe29 bellard
    bswap = 0;
676 c896fe29 bellard
#endif
677 c896fe29 bellard
    switch(opc) {
678 c896fe29 bellard
    case 0:
679 c896fe29 bellard
        /* movzbl */
680 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
681 c896fe29 bellard
        break;
682 c896fe29 bellard
    case 0 | 4:
683 c896fe29 bellard
        /* movsbX */
684 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
685 c896fe29 bellard
        break;
686 c896fe29 bellard
    case 1:
687 c896fe29 bellard
        /* movzwl */
688 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
689 c896fe29 bellard
        if (bswap) {
690 c896fe29 bellard
            /* rolw $8, data_reg */
691 c896fe29 bellard
            tcg_out8(s, 0x66); 
692 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
693 c896fe29 bellard
            tcg_out8(s, 8);
694 c896fe29 bellard
        }
695 c896fe29 bellard
        break;
696 c896fe29 bellard
    case 1 | 4:
697 c896fe29 bellard
        if (bswap) {
698 c896fe29 bellard
            /* movzwl */
699 379f6698 Paul Brook
            tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
700 c896fe29 bellard
            /* rolw $8, data_reg */
701 c896fe29 bellard
            tcg_out8(s, 0x66); 
702 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
703 c896fe29 bellard
            tcg_out8(s, 8);
704 c896fe29 bellard
705 c896fe29 bellard
            /* movswX data_reg, data_reg */
706 c896fe29 bellard
            tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
707 c896fe29 bellard
        } else {
708 c896fe29 bellard
            /* movswX */
709 379f6698 Paul Brook
            tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
710 c896fe29 bellard
        }
711 c896fe29 bellard
        break;
712 c896fe29 bellard
    case 2:
713 c896fe29 bellard
        /* movl (r0), data_reg */
714 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
715 c896fe29 bellard
        if (bswap) {
716 c896fe29 bellard
            /* bswap */
717 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
718 c896fe29 bellard
        }
719 c896fe29 bellard
        break;
720 c896fe29 bellard
    case 2 | 4:
721 c896fe29 bellard
        if (bswap) {
722 c896fe29 bellard
            /* movl (r0), data_reg */
723 379f6698 Paul Brook
            tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
724 c896fe29 bellard
            /* bswap */
725 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
726 c896fe29 bellard
            /* movslq */
727 c896fe29 bellard
            tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
728 c896fe29 bellard
        } else {
729 c896fe29 bellard
            /* movslq */
730 379f6698 Paul Brook
            tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
731 c896fe29 bellard
        }
732 c896fe29 bellard
        break;
733 c896fe29 bellard
    case 3:
734 c896fe29 bellard
        /* movq (r0), data_reg */
735 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
736 c896fe29 bellard
        if (bswap) {
737 c896fe29 bellard
            /* bswap */
738 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
739 c896fe29 bellard
        }
740 c896fe29 bellard
        break;
741 c896fe29 bellard
    default:
742 c896fe29 bellard
        tcg_abort();
743 c896fe29 bellard
    }
744 c896fe29 bellard
745 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
746 c896fe29 bellard
    /* label2: */
747 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
748 c896fe29 bellard
#endif
749 c896fe29 bellard
}
750 c896fe29 bellard
751 c896fe29 bellard
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
752 c896fe29 bellard
                            int opc)
753 c896fe29 bellard
{
754 c896fe29 bellard
    int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
755 379f6698 Paul Brook
    int32_t offset;
756 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
757 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
758 c896fe29 bellard
#endif
759 c896fe29 bellard
760 c896fe29 bellard
    data_reg = *args++;
761 c896fe29 bellard
    addr_reg = *args++;
762 c896fe29 bellard
    mem_index = *args;
763 c896fe29 bellard
764 c896fe29 bellard
    s_bits = opc;
765 c896fe29 bellard
766 c896fe29 bellard
    r0 = TCG_REG_RDI;
767 c896fe29 bellard
    r1 = TCG_REG_RSI;
768 c896fe29 bellard
769 c896fe29 bellard
#if TARGET_LONG_BITS == 32
770 c896fe29 bellard
    rexw = 0;
771 c896fe29 bellard
#else
772 c896fe29 bellard
    rexw = P_REXW;
773 c896fe29 bellard
#endif
774 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
775 c896fe29 bellard
    /* mov */
776 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
777 c896fe29 bellard
778 c896fe29 bellard
    /* mov */
779 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
780 c896fe29 bellard
 
781 c896fe29 bellard
    tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
782 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
783 c896fe29 bellard
    
784 c896fe29 bellard
    tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
785 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
786 c896fe29 bellard
    
787 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
788 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
789 c896fe29 bellard
790 c896fe29 bellard
    /* lea offset(r1, env), r1 */
791 c896fe29 bellard
    tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
792 c896fe29 bellard
                          offsetof(CPUState, tlb_table[mem_index][0].addr_write));
793 c896fe29 bellard
794 c896fe29 bellard
    /* cmp 0(r1), r0 */
795 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
796 c896fe29 bellard
    
797 c896fe29 bellard
    /* mov */
798 c896fe29 bellard
    tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
799 c896fe29 bellard
    
800 c896fe29 bellard
    /* je label1 */
801 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
802 c896fe29 bellard
    label1_ptr = s->code_ptr;
803 c896fe29 bellard
    s->code_ptr++;
804 c896fe29 bellard
805 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
806 c896fe29 bellard
    switch(opc) {
807 c896fe29 bellard
    case 0:
808 c896fe29 bellard
        /* movzbl */
809 09aac126 Richard Henderson
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, TCG_REG_RSI, data_reg);
810 c896fe29 bellard
        break;
811 c896fe29 bellard
    case 1:
812 c896fe29 bellard
        /* movzwl */
813 c896fe29 bellard
        tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
814 c896fe29 bellard
        break;
815 c896fe29 bellard
    case 2:
816 c896fe29 bellard
        /* movl */
817 c896fe29 bellard
        tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
818 c896fe29 bellard
        break;
819 c896fe29 bellard
    default:
820 c896fe29 bellard
    case 3:
821 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_RSI, data_reg);
822 c896fe29 bellard
        break;
823 c896fe29 bellard
    }
824 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
825 abb6ae2c malc
    tcg_out_goto(s, 1, qemu_st_helpers[s_bits]);
826 c896fe29 bellard
827 c896fe29 bellard
    /* jmp label2 */
828 c896fe29 bellard
    tcg_out8(s, 0xeb);
829 c896fe29 bellard
    label2_ptr = s->code_ptr;
830 c896fe29 bellard
    s->code_ptr++;
831 c896fe29 bellard
    
832 c896fe29 bellard
    /* label1: */
833 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
834 c896fe29 bellard
835 c896fe29 bellard
    /* add x(r1), r0 */
836 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) - 
837 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_write));
838 379f6698 Paul Brook
    offset = 0;
839 c896fe29 bellard
#else
840 379f6698 Paul Brook
    if (GUEST_BASE == (int32_t)GUEST_BASE) {
841 379f6698 Paul Brook
        r0 = addr_reg;
842 379f6698 Paul Brook
        offset = GUEST_BASE;
843 379f6698 Paul Brook
    } else {
844 379f6698 Paul Brook
        offset = 0;
845 379f6698 Paul Brook
        /* movq $GUEST_BASE, r0 */
846 379f6698 Paul Brook
        tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
847 379f6698 Paul Brook
        tcg_out32(s, GUEST_BASE);
848 379f6698 Paul Brook
        tcg_out32(s, GUEST_BASE >> 32);
849 379f6698 Paul Brook
        /* addq addr_reg, r0 */
850 379f6698 Paul Brook
        tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
851 379f6698 Paul Brook
    }
852 c896fe29 bellard
#endif
853 c896fe29 bellard
854 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
855 c896fe29 bellard
    bswap = 1;
856 c896fe29 bellard
#else
857 c896fe29 bellard
    bswap = 0;
858 c896fe29 bellard
#endif
859 c896fe29 bellard
    switch(opc) {
860 c896fe29 bellard
    case 0:
861 c896fe29 bellard
        /* movb */
862 09aac126 Richard Henderson
        tcg_out_modrm_offset(s, 0x88 | P_REXB_R, data_reg, r0, offset);
863 c896fe29 bellard
        break;
864 c896fe29 bellard
    case 1:
865 c896fe29 bellard
        if (bswap) {
866 c896fe29 bellard
            tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
867 c896fe29 bellard
            tcg_out8(s, 0x66); /* rolw $8, %ecx */
868 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, r1);
869 c896fe29 bellard
            tcg_out8(s, 8);
870 c896fe29 bellard
            data_reg = r1;
871 c896fe29 bellard
        }
872 c896fe29 bellard
        /* movw */
873 c896fe29 bellard
        tcg_out8(s, 0x66);
874 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
875 c896fe29 bellard
        break;
876 c896fe29 bellard
    case 2:
877 c896fe29 bellard
        if (bswap) {
878 c896fe29 bellard
            tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
879 c896fe29 bellard
            /* bswap data_reg */
880 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
881 c896fe29 bellard
            data_reg = r1;
882 c896fe29 bellard
        }
883 c896fe29 bellard
        /* movl */
884 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
885 c896fe29 bellard
        break;
886 c896fe29 bellard
    case 3:
887 c896fe29 bellard
        if (bswap) {
888 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
889 c896fe29 bellard
            /* bswap data_reg */
890 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
891 c896fe29 bellard
            data_reg = r1;
892 c896fe29 bellard
        }
893 c896fe29 bellard
        /* movq */
894 379f6698 Paul Brook
        tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
895 c896fe29 bellard
        break;
896 c896fe29 bellard
    default:
897 c896fe29 bellard
        tcg_abort();
898 c896fe29 bellard
    }
899 c896fe29 bellard
900 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
901 c896fe29 bellard
    /* label2: */
902 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
903 c896fe29 bellard
#endif
904 c896fe29 bellard
}
905 c896fe29 bellard
906 c896fe29 bellard
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
907 c896fe29 bellard
                              const int *const_args)
908 c896fe29 bellard
{
909 c896fe29 bellard
    int c;
910 c896fe29 bellard
    
911 c896fe29 bellard
    switch(opc) {
912 c896fe29 bellard
    case INDEX_op_exit_tb:
913 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
914 abb6ae2c malc
        tcg_out_goto(s, 0, tb_ret_addr);
915 c896fe29 bellard
        break;
916 c896fe29 bellard
    case INDEX_op_goto_tb:
917 c896fe29 bellard
        if (s->tb_jmp_offset) {
918 c896fe29 bellard
            /* direct jump method */
919 c896fe29 bellard
            tcg_out8(s, 0xe9); /* jmp im */
920 c896fe29 bellard
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
921 c896fe29 bellard
            tcg_out32(s, 0);
922 c896fe29 bellard
        } else {
923 c896fe29 bellard
            /* indirect jump method */
924 c896fe29 bellard
            /* jmp Ev */
925 c896fe29 bellard
            tcg_out_modrm_offset(s, 0xff, 4, -1, 
926 c896fe29 bellard
                                 (tcg_target_long)(s->tb_next + 
927 c896fe29 bellard
                                                   args[0]));
928 c896fe29 bellard
        }
929 c896fe29 bellard
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
930 c896fe29 bellard
        break;
931 c896fe29 bellard
    case INDEX_op_call:
932 c896fe29 bellard
        if (const_args[0]) {
933 abb6ae2c malc
            tcg_out_goto(s, 1, (void *) args[0]);
934 c896fe29 bellard
        } else {
935 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 2, args[0]);
936 c896fe29 bellard
        }
937 c896fe29 bellard
        break;
938 c896fe29 bellard
    case INDEX_op_jmp:
939 c896fe29 bellard
        if (const_args[0]) {
940 abb6ae2c malc
            tcg_out_goto(s, 0, (void *) args[0]);
941 c896fe29 bellard
        } else {
942 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 4, args[0]);
943 c896fe29 bellard
        }
944 c896fe29 bellard
        break;
945 c896fe29 bellard
    case INDEX_op_br:
946 c896fe29 bellard
        tcg_out_jxx(s, JCC_JMP, args[0]);
947 c896fe29 bellard
        break;
948 c896fe29 bellard
    case INDEX_op_movi_i32:
949 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
950 c896fe29 bellard
        break;
951 c896fe29 bellard
    case INDEX_op_movi_i64:
952 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
953 c896fe29 bellard
        break;
954 c896fe29 bellard
    case INDEX_op_ld8u_i32:
955 c896fe29 bellard
    case INDEX_op_ld8u_i64:
956 c896fe29 bellard
        /* movzbl */
957 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
958 c896fe29 bellard
        break;
959 c896fe29 bellard
    case INDEX_op_ld8s_i32:
960 c896fe29 bellard
        /* movsbl */
961 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
962 c896fe29 bellard
        break;
963 c896fe29 bellard
    case INDEX_op_ld8s_i64:
964 c896fe29 bellard
        /* movsbq */
965 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
966 c896fe29 bellard
        break;
967 c896fe29 bellard
    case INDEX_op_ld16u_i32:
968 c896fe29 bellard
    case INDEX_op_ld16u_i64:
969 c896fe29 bellard
        /* movzwl */
970 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
971 c896fe29 bellard
        break;
972 c896fe29 bellard
    case INDEX_op_ld16s_i32:
973 c896fe29 bellard
        /* movswl */
974 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
975 c896fe29 bellard
        break;
976 c896fe29 bellard
    case INDEX_op_ld16s_i64:
977 c896fe29 bellard
        /* movswq */
978 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
979 c896fe29 bellard
        break;
980 c896fe29 bellard
    case INDEX_op_ld_i32:
981 c896fe29 bellard
    case INDEX_op_ld32u_i64:
982 c896fe29 bellard
        /* movl */
983 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
984 c896fe29 bellard
        break;
985 c896fe29 bellard
    case INDEX_op_ld32s_i64:
986 c896fe29 bellard
        /* movslq */
987 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
988 c896fe29 bellard
        break;
989 c896fe29 bellard
    case INDEX_op_ld_i64:
990 c896fe29 bellard
        /* movq */
991 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
992 c896fe29 bellard
        break;
993 c896fe29 bellard
        
994 c896fe29 bellard
    case INDEX_op_st8_i32:
995 c896fe29 bellard
    case INDEX_op_st8_i64:
996 c896fe29 bellard
        /* movb */
997 09aac126 Richard Henderson
        tcg_out_modrm_offset(s, 0x88 | P_REXB_R, args[0], args[1], args[2]);
998 c896fe29 bellard
        break;
999 c896fe29 bellard
    case INDEX_op_st16_i32:
1000 c896fe29 bellard
    case INDEX_op_st16_i64:
1001 c896fe29 bellard
        /* movw */
1002 c896fe29 bellard
        tcg_out8(s, 0x66);
1003 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1004 c896fe29 bellard
        break;
1005 c896fe29 bellard
    case INDEX_op_st_i32:
1006 c896fe29 bellard
    case INDEX_op_st32_i64:
1007 c896fe29 bellard
        /* movl */
1008 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1009 c896fe29 bellard
        break;
1010 c896fe29 bellard
    case INDEX_op_st_i64:
1011 c896fe29 bellard
        /* movq */
1012 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
1013 c896fe29 bellard
        break;
1014 c896fe29 bellard
1015 c896fe29 bellard
    case INDEX_op_sub_i32:
1016 c896fe29 bellard
        c = ARITH_SUB;
1017 c896fe29 bellard
        goto gen_arith32;
1018 c896fe29 bellard
    case INDEX_op_and_i32:
1019 c896fe29 bellard
        c = ARITH_AND;
1020 c896fe29 bellard
        goto gen_arith32;
1021 c896fe29 bellard
    case INDEX_op_or_i32:
1022 c896fe29 bellard
        c = ARITH_OR;
1023 c896fe29 bellard
        goto gen_arith32;
1024 c896fe29 bellard
    case INDEX_op_xor_i32:
1025 c896fe29 bellard
        c = ARITH_XOR;
1026 c896fe29 bellard
        goto gen_arith32;
1027 c896fe29 bellard
    case INDEX_op_add_i32:
1028 c896fe29 bellard
        c = ARITH_ADD;
1029 c896fe29 bellard
    gen_arith32:
1030 c896fe29 bellard
        if (const_args[2]) {
1031 c896fe29 bellard
            tgen_arithi32(s, c, args[0], args[2]);
1032 c896fe29 bellard
        } else {
1033 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
1034 c896fe29 bellard
        }
1035 c896fe29 bellard
        break;
1036 c896fe29 bellard
1037 c896fe29 bellard
    case INDEX_op_sub_i64:
1038 c896fe29 bellard
        c = ARITH_SUB;
1039 c896fe29 bellard
        goto gen_arith64;
1040 c896fe29 bellard
    case INDEX_op_and_i64:
1041 c896fe29 bellard
        c = ARITH_AND;
1042 c896fe29 bellard
        goto gen_arith64;
1043 c896fe29 bellard
    case INDEX_op_or_i64:
1044 c896fe29 bellard
        c = ARITH_OR;
1045 c896fe29 bellard
        goto gen_arith64;
1046 c896fe29 bellard
    case INDEX_op_xor_i64:
1047 c896fe29 bellard
        c = ARITH_XOR;
1048 c896fe29 bellard
        goto gen_arith64;
1049 c896fe29 bellard
    case INDEX_op_add_i64:
1050 c896fe29 bellard
        c = ARITH_ADD;
1051 c896fe29 bellard
    gen_arith64:
1052 c896fe29 bellard
        if (const_args[2]) {
1053 c896fe29 bellard
            tgen_arithi64(s, c, args[0], args[2]);
1054 c896fe29 bellard
        } else {
1055 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
1056 c896fe29 bellard
        }
1057 c896fe29 bellard
        break;
1058 c896fe29 bellard
1059 c896fe29 bellard
    case INDEX_op_mul_i32:
1060 c896fe29 bellard
        if (const_args[2]) {
1061 c896fe29 bellard
            int32_t val;
1062 c896fe29 bellard
            val = args[2];
1063 c896fe29 bellard
            if (val == (int8_t)val) {
1064 c896fe29 bellard
                tcg_out_modrm(s, 0x6b, args[0], args[0]);
1065 c896fe29 bellard
                tcg_out8(s, val);
1066 c896fe29 bellard
            } else {
1067 c896fe29 bellard
                tcg_out_modrm(s, 0x69, args[0], args[0]);
1068 c896fe29 bellard
                tcg_out32(s, val);
1069 c896fe29 bellard
            }
1070 c896fe29 bellard
        } else {
1071 c896fe29 bellard
            tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1072 c896fe29 bellard
        }
1073 c896fe29 bellard
        break;
1074 c896fe29 bellard
    case INDEX_op_mul_i64:
1075 c896fe29 bellard
        if (const_args[2]) {
1076 c896fe29 bellard
            int32_t val;
1077 c896fe29 bellard
            val = args[2];
1078 c896fe29 bellard
            if (val == (int8_t)val) {
1079 c896fe29 bellard
                tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
1080 c896fe29 bellard
                tcg_out8(s, val);
1081 c896fe29 bellard
            } else {
1082 c896fe29 bellard
                tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
1083 c896fe29 bellard
                tcg_out32(s, val);
1084 c896fe29 bellard
            }
1085 c896fe29 bellard
        } else {
1086 c896fe29 bellard
            tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
1087 c896fe29 bellard
        }
1088 c896fe29 bellard
        break;
1089 c896fe29 bellard
    case INDEX_op_div2_i32:
1090 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 7, args[4]);
1091 c896fe29 bellard
        break;
1092 c896fe29 bellard
    case INDEX_op_divu2_i32:
1093 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 6, args[4]);
1094 c896fe29 bellard
        break;
1095 c896fe29 bellard
    case INDEX_op_div2_i64:
1096 c896fe29 bellard
        tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
1097 c896fe29 bellard
        break;
1098 c896fe29 bellard
    case INDEX_op_divu2_i64:
1099 c896fe29 bellard
        tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
1100 c896fe29 bellard
        break;
1101 c896fe29 bellard
1102 c896fe29 bellard
    case INDEX_op_shl_i32:
1103 c896fe29 bellard
        c = SHIFT_SHL;
1104 c896fe29 bellard
    gen_shift32:
1105 c896fe29 bellard
        if (const_args[2]) {
1106 c896fe29 bellard
            if (args[2] == 1) {
1107 c896fe29 bellard
                tcg_out_modrm(s, 0xd1, c, args[0]);
1108 c896fe29 bellard
            } else {
1109 c896fe29 bellard
                tcg_out_modrm(s, 0xc1, c, args[0]);
1110 c896fe29 bellard
                tcg_out8(s, args[2]);
1111 c896fe29 bellard
            }
1112 c896fe29 bellard
        } else {
1113 c896fe29 bellard
            tcg_out_modrm(s, 0xd3, c, args[0]);
1114 c896fe29 bellard
        }
1115 c896fe29 bellard
        break;
1116 c896fe29 bellard
    case INDEX_op_shr_i32:
1117 c896fe29 bellard
        c = SHIFT_SHR;
1118 c896fe29 bellard
        goto gen_shift32;
1119 c896fe29 bellard
    case INDEX_op_sar_i32:
1120 c896fe29 bellard
        c = SHIFT_SAR;
1121 c896fe29 bellard
        goto gen_shift32;
1122 d42f183c aurel32
    case INDEX_op_rotl_i32:
1123 d42f183c aurel32
        c = SHIFT_ROL;
1124 d42f183c aurel32
        goto gen_shift32;
1125 d42f183c aurel32
    case INDEX_op_rotr_i32:
1126 d42f183c aurel32
        c = SHIFT_ROR;
1127 d42f183c aurel32
        goto gen_shift32;
1128 d42f183c aurel32
1129 c896fe29 bellard
    case INDEX_op_shl_i64:
1130 c896fe29 bellard
        c = SHIFT_SHL;
1131 c896fe29 bellard
    gen_shift64:
1132 c896fe29 bellard
        if (const_args[2]) {
1133 c896fe29 bellard
            if (args[2] == 1) {
1134 c896fe29 bellard
                tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
1135 c896fe29 bellard
            } else {
1136 c896fe29 bellard
                tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
1137 c896fe29 bellard
                tcg_out8(s, args[2]);
1138 c896fe29 bellard
            }
1139 c896fe29 bellard
        } else {
1140 c896fe29 bellard
            tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
1141 c896fe29 bellard
        }
1142 c896fe29 bellard
        break;
1143 c896fe29 bellard
    case INDEX_op_shr_i64:
1144 c896fe29 bellard
        c = SHIFT_SHR;
1145 c896fe29 bellard
        goto gen_shift64;
1146 c896fe29 bellard
    case INDEX_op_sar_i64:
1147 c896fe29 bellard
        c = SHIFT_SAR;
1148 c896fe29 bellard
        goto gen_shift64;
1149 d42f183c aurel32
    case INDEX_op_rotl_i64:
1150 d42f183c aurel32
        c = SHIFT_ROL;
1151 d42f183c aurel32
        goto gen_shift64;
1152 d42f183c aurel32
    case INDEX_op_rotr_i64:
1153 d42f183c aurel32
        c = SHIFT_ROR;
1154 d42f183c aurel32
        goto gen_shift64;
1155 d42f183c aurel32
1156 c896fe29 bellard
    case INDEX_op_brcond_i32:
1157 c896fe29 bellard
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 
1158 c896fe29 bellard
                       args[3], 0);
1159 c896fe29 bellard
        break;
1160 c896fe29 bellard
    case INDEX_op_brcond_i64:
1161 c896fe29 bellard
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 
1162 c896fe29 bellard
                       args[3], P_REXW);
1163 c896fe29 bellard
        break;
1164 c896fe29 bellard
1165 86dbdd40 aurel32
    case INDEX_op_bswap16_i32:
1166 86dbdd40 aurel32
    case INDEX_op_bswap16_i64:
1167 86dbdd40 aurel32
        tcg_out8(s, 0x66);
1168 86dbdd40 aurel32
        tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
1169 86dbdd40 aurel32
        tcg_out8(s, 8);
1170 86dbdd40 aurel32
        break;
1171 66896cb8 aurel32
    case INDEX_op_bswap32_i32:
1172 86dbdd40 aurel32
    case INDEX_op_bswap32_i64:
1173 c896fe29 bellard
        tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1174 c896fe29 bellard
        break;
1175 66896cb8 aurel32
    case INDEX_op_bswap64_i64:
1176 c896fe29 bellard
        tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1177 c896fe29 bellard
        break;
1178 c896fe29 bellard
1179 390efc54 pbrook
    case INDEX_op_neg_i32:
1180 390efc54 pbrook
        tcg_out_modrm(s, 0xf7, 3, args[0]);
1181 390efc54 pbrook
        break;
1182 390efc54 pbrook
    case INDEX_op_neg_i64:
1183 390efc54 pbrook
        tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
1184 390efc54 pbrook
        break;
1185 390efc54 pbrook
1186 d2604285 aurel32
    case INDEX_op_not_i32:
1187 d2604285 aurel32
        tcg_out_modrm(s, 0xf7, 2, args[0]);
1188 d2604285 aurel32
        break;
1189 d2604285 aurel32
    case INDEX_op_not_i64:
1190 d2604285 aurel32
        tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
1191 d2604285 aurel32
        break;
1192 d2604285 aurel32
1193 b6d17150 pbrook
    case INDEX_op_ext8s_i32:
1194 09aac126 Richard Henderson
        tcg_out_modrm(s, 0xbe | P_EXT | P_REXB_RM, args[0], args[1]);
1195 b6d17150 pbrook
        break;
1196 b6d17150 pbrook
    case INDEX_op_ext16s_i32:
1197 b6d17150 pbrook
        tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
1198 b6d17150 pbrook
        break;
1199 b6d17150 pbrook
    case INDEX_op_ext8s_i64:
1200 b6d17150 pbrook
        tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
1201 b6d17150 pbrook
        break;
1202 b6d17150 pbrook
    case INDEX_op_ext16s_i64:
1203 b6d17150 pbrook
        tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
1204 b6d17150 pbrook
        break;
1205 b6d17150 pbrook
    case INDEX_op_ext32s_i64:
1206 b6d17150 pbrook
        tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
1207 b6d17150 pbrook
        break;
1208 64584218 Aurelien Jarno
    case INDEX_op_ext8u_i32:
1209 57169903 Richard Henderson
    case INDEX_op_ext8u_i64:
1210 09aac126 Richard Henderson
        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, args[0], args[1]);
1211 64584218 Aurelien Jarno
        break;
1212 64584218 Aurelien Jarno
    case INDEX_op_ext16u_i32:
1213 64584218 Aurelien Jarno
    case INDEX_op_ext16u_i64:
1214 57169903 Richard Henderson
        tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
1215 64584218 Aurelien Jarno
        break;
1216 64584218 Aurelien Jarno
    case INDEX_op_ext32u_i64:
1217 64584218 Aurelien Jarno
        tcg_out_modrm(s, 0x8b, args[0], args[1]);
1218 64584218 Aurelien Jarno
        break;
1219 b6d17150 pbrook
1220 8f9db67c Richard Henderson
    case INDEX_op_setcond_i32:
1221 8f9db67c Richard Henderson
        tcg_out_setcond(s, args[3], args[0], args[1], args[2],
1222 8f9db67c Richard Henderson
                        const_args[2], 0);
1223 8f9db67c Richard Henderson
        break;
1224 8f9db67c Richard Henderson
    case INDEX_op_setcond_i64:
1225 8f9db67c Richard Henderson
        tcg_out_setcond(s, args[3], args[0], args[1], args[2],
1226 8f9db67c Richard Henderson
                        const_args[2], P_REXW);
1227 8f9db67c Richard Henderson
        break;
1228 8f9db67c Richard Henderson
1229 c896fe29 bellard
    case INDEX_op_qemu_ld8u:
1230 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0);
1231 c896fe29 bellard
        break;
1232 c896fe29 bellard
    case INDEX_op_qemu_ld8s:
1233 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0 | 4);
1234 c896fe29 bellard
        break;
1235 c896fe29 bellard
    case INDEX_op_qemu_ld16u:
1236 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1);
1237 c896fe29 bellard
        break;
1238 c896fe29 bellard
    case INDEX_op_qemu_ld16s:
1239 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1 | 4);
1240 c896fe29 bellard
        break;
1241 c896fe29 bellard
    case INDEX_op_qemu_ld32u:
1242 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 2);
1243 c896fe29 bellard
        break;
1244 c896fe29 bellard
    case INDEX_op_qemu_ld32s:
1245 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 2 | 4);
1246 c896fe29 bellard
        break;
1247 c896fe29 bellard
    case INDEX_op_qemu_ld64:
1248 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 3);
1249 c896fe29 bellard
        break;
1250 c896fe29 bellard
        
1251 c896fe29 bellard
    case INDEX_op_qemu_st8:
1252 c896fe29 bellard
        tcg_out_qemu_st(s, args, 0);
1253 c896fe29 bellard
        break;
1254 c896fe29 bellard
    case INDEX_op_qemu_st16:
1255 c896fe29 bellard
        tcg_out_qemu_st(s, args, 1);
1256 c896fe29 bellard
        break;
1257 c896fe29 bellard
    case INDEX_op_qemu_st32:
1258 c896fe29 bellard
        tcg_out_qemu_st(s, args, 2);
1259 c896fe29 bellard
        break;
1260 c896fe29 bellard
    case INDEX_op_qemu_st64:
1261 c896fe29 bellard
        tcg_out_qemu_st(s, args, 3);
1262 c896fe29 bellard
        break;
1263 c896fe29 bellard
1264 c896fe29 bellard
    default:
1265 c896fe29 bellard
        tcg_abort();
1266 c896fe29 bellard
    }
1267 c896fe29 bellard
}
1268 c896fe29 bellard
1269 b03cce8e bellard
static int tcg_target_callee_save_regs[] = {
1270 b03cce8e bellard
    TCG_REG_RBP,
1271 b03cce8e bellard
    TCG_REG_RBX,
1272 b03cce8e bellard
    TCG_REG_R12,
1273 b03cce8e bellard
    TCG_REG_R13,
1274 b03cce8e bellard
    /*    TCG_REG_R14, */ /* currently used for the global env, so no
1275 b03cce8e bellard
                             need to save */
1276 b03cce8e bellard
    TCG_REG_R15,
1277 b03cce8e bellard
};
1278 b03cce8e bellard
1279 b03cce8e bellard
static inline void tcg_out_push(TCGContext *s, int reg)
1280 b03cce8e bellard
{
1281 b03cce8e bellard
    tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
1282 b03cce8e bellard
}
1283 b03cce8e bellard
1284 b03cce8e bellard
static inline void tcg_out_pop(TCGContext *s, int reg)
1285 b03cce8e bellard
{
1286 b03cce8e bellard
    tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
1287 b03cce8e bellard
}
1288 b03cce8e bellard
1289 b03cce8e bellard
/* Generate global QEMU prologue and epilogue code */
1290 b03cce8e bellard
void tcg_target_qemu_prologue(TCGContext *s)
1291 b03cce8e bellard
{
1292 b03cce8e bellard
    int i, frame_size, push_size, stack_addend;
1293 b03cce8e bellard
1294 b03cce8e bellard
    /* TB prologue */
1295 b03cce8e bellard
    /* save all callee saved registers */
1296 b03cce8e bellard
    for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1297 b03cce8e bellard
        tcg_out_push(s, tcg_target_callee_save_regs[i]);
1298 b03cce8e bellard
1299 b03cce8e bellard
    }
1300 b03cce8e bellard
    /* reserve some stack space */
1301 b03cce8e bellard
    push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
1302 b03cce8e bellard
    frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1303 b03cce8e bellard
    frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & 
1304 b03cce8e bellard
        ~(TCG_TARGET_STACK_ALIGN - 1);
1305 b03cce8e bellard
    stack_addend = frame_size - push_size;
1306 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
1307 b03cce8e bellard
1308 b03cce8e bellard
    tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
1309 b03cce8e bellard
    
1310 b03cce8e bellard
    /* TB epilogue */
1311 b03cce8e bellard
    tb_ret_addr = s->code_ptr;
1312 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_RSP, stack_addend);
1313 b03cce8e bellard
    for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1314 b03cce8e bellard
        tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1315 b03cce8e bellard
    }
1316 b03cce8e bellard
    tcg_out8(s, 0xc3); /* ret */
1317 b03cce8e bellard
}
1318 b03cce8e bellard
1319 c896fe29 bellard
static const TCGTargetOpDef x86_64_op_defs[] = {
1320 c896fe29 bellard
    { INDEX_op_exit_tb, { } },
1321 c896fe29 bellard
    { INDEX_op_goto_tb, { } },
1322 c896fe29 bellard
    { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
1323 c896fe29 bellard
    { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
1324 c896fe29 bellard
    { INDEX_op_br, { } },
1325 c896fe29 bellard
1326 c896fe29 bellard
    { INDEX_op_mov_i32, { "r", "r" } },
1327 c896fe29 bellard
    { INDEX_op_movi_i32, { "r" } },
1328 c896fe29 bellard
    { INDEX_op_ld8u_i32, { "r", "r" } },
1329 c896fe29 bellard
    { INDEX_op_ld8s_i32, { "r", "r" } },
1330 c896fe29 bellard
    { INDEX_op_ld16u_i32, { "r", "r" } },
1331 c896fe29 bellard
    { INDEX_op_ld16s_i32, { "r", "r" } },
1332 c896fe29 bellard
    { INDEX_op_ld_i32, { "r", "r" } },
1333 c896fe29 bellard
    { INDEX_op_st8_i32, { "r", "r" } },
1334 c896fe29 bellard
    { INDEX_op_st16_i32, { "r", "r" } },
1335 c896fe29 bellard
    { INDEX_op_st_i32, { "r", "r" } },
1336 c896fe29 bellard
1337 c896fe29 bellard
    { INDEX_op_add_i32, { "r", "0", "ri" } },
1338 c896fe29 bellard
    { INDEX_op_mul_i32, { "r", "0", "ri" } },
1339 c896fe29 bellard
    { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1340 c896fe29 bellard
    { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1341 c896fe29 bellard
    { INDEX_op_sub_i32, { "r", "0", "ri" } },
1342 c896fe29 bellard
    { INDEX_op_and_i32, { "r", "0", "ri" } },
1343 c896fe29 bellard
    { INDEX_op_or_i32, { "r", "0", "ri" } },
1344 c896fe29 bellard
    { INDEX_op_xor_i32, { "r", "0", "ri" } },
1345 c896fe29 bellard
1346 c896fe29 bellard
    { INDEX_op_shl_i32, { "r", "0", "ci" } },
1347 c896fe29 bellard
    { INDEX_op_shr_i32, { "r", "0", "ci" } },
1348 c896fe29 bellard
    { INDEX_op_sar_i32, { "r", "0", "ci" } },
1349 d42f183c aurel32
    { INDEX_op_rotl_i32, { "r", "0", "ci" } },
1350 d42f183c aurel32
    { INDEX_op_rotr_i32, { "r", "0", "ci" } },
1351 c896fe29 bellard
1352 c896fe29 bellard
    { INDEX_op_brcond_i32, { "r", "ri" } },
1353 c896fe29 bellard
1354 c896fe29 bellard
    { INDEX_op_mov_i64, { "r", "r" } },
1355 c896fe29 bellard
    { INDEX_op_movi_i64, { "r" } },
1356 c896fe29 bellard
    { INDEX_op_ld8u_i64, { "r", "r" } },
1357 c896fe29 bellard
    { INDEX_op_ld8s_i64, { "r", "r" } },
1358 c896fe29 bellard
    { INDEX_op_ld16u_i64, { "r", "r" } },
1359 c896fe29 bellard
    { INDEX_op_ld16s_i64, { "r", "r" } },
1360 c896fe29 bellard
    { INDEX_op_ld32u_i64, { "r", "r" } },
1361 c896fe29 bellard
    { INDEX_op_ld32s_i64, { "r", "r" } },
1362 c896fe29 bellard
    { INDEX_op_ld_i64, { "r", "r" } },
1363 c896fe29 bellard
    { INDEX_op_st8_i64, { "r", "r" } },
1364 c896fe29 bellard
    { INDEX_op_st16_i64, { "r", "r" } },
1365 c896fe29 bellard
    { INDEX_op_st32_i64, { "r", "r" } },
1366 c896fe29 bellard
    { INDEX_op_st_i64, { "r", "r" } },
1367 c896fe29 bellard
1368 c896fe29 bellard
    { INDEX_op_add_i64, { "r", "0", "re" } },
1369 c896fe29 bellard
    { INDEX_op_mul_i64, { "r", "0", "re" } },
1370 c896fe29 bellard
    { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
1371 c896fe29 bellard
    { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
1372 c896fe29 bellard
    { INDEX_op_sub_i64, { "r", "0", "re" } },
1373 c896fe29 bellard
    { INDEX_op_and_i64, { "r", "0", "reZ" } },
1374 c896fe29 bellard
    { INDEX_op_or_i64, { "r", "0", "re" } },
1375 c896fe29 bellard
    { INDEX_op_xor_i64, { "r", "0", "re" } },
1376 c896fe29 bellard
1377 c896fe29 bellard
    { INDEX_op_shl_i64, { "r", "0", "ci" } },
1378 c896fe29 bellard
    { INDEX_op_shr_i64, { "r", "0", "ci" } },
1379 c896fe29 bellard
    { INDEX_op_sar_i64, { "r", "0", "ci" } },
1380 d42f183c aurel32
    { INDEX_op_rotl_i64, { "r", "0", "ci" } },
1381 d42f183c aurel32
    { INDEX_op_rotr_i64, { "r", "0", "ci" } },
1382 c896fe29 bellard
1383 c896fe29 bellard
    { INDEX_op_brcond_i64, { "r", "re" } },
1384 c896fe29 bellard
1385 86dbdd40 aurel32
    { INDEX_op_bswap16_i32, { "r", "0" } },
1386 86dbdd40 aurel32
    { INDEX_op_bswap16_i64, { "r", "0" } },
1387 66896cb8 aurel32
    { INDEX_op_bswap32_i32, { "r", "0" } },
1388 86dbdd40 aurel32
    { INDEX_op_bswap32_i64, { "r", "0" } },
1389 66896cb8 aurel32
    { INDEX_op_bswap64_i64, { "r", "0" } },
1390 c896fe29 bellard
1391 390efc54 pbrook
    { INDEX_op_neg_i32, { "r", "0" } },
1392 390efc54 pbrook
    { INDEX_op_neg_i64, { "r", "0" } },
1393 390efc54 pbrook
1394 d2604285 aurel32
    { INDEX_op_not_i32, { "r", "0" } },
1395 d2604285 aurel32
    { INDEX_op_not_i64, { "r", "0" } },
1396 d2604285 aurel32
1397 b6d17150 pbrook
    { INDEX_op_ext8s_i32, { "r", "r"} },
1398 b6d17150 pbrook
    { INDEX_op_ext16s_i32, { "r", "r"} },
1399 b6d17150 pbrook
    { INDEX_op_ext8s_i64, { "r", "r"} },
1400 b6d17150 pbrook
    { INDEX_op_ext16s_i64, { "r", "r"} },
1401 b6d17150 pbrook
    { INDEX_op_ext32s_i64, { "r", "r"} },
1402 64584218 Aurelien Jarno
    { INDEX_op_ext8u_i32, { "r", "r"} },
1403 64584218 Aurelien Jarno
    { INDEX_op_ext16u_i32, { "r", "r"} },
1404 64584218 Aurelien Jarno
    { INDEX_op_ext8u_i64, { "r", "r"} },
1405 64584218 Aurelien Jarno
    { INDEX_op_ext16u_i64, { "r", "r"} },
1406 64584218 Aurelien Jarno
    { INDEX_op_ext32u_i64, { "r", "r"} },
1407 b6d17150 pbrook
1408 8f9db67c Richard Henderson
    { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1409 8f9db67c Richard Henderson
    { INDEX_op_setcond_i64, { "r", "r", "re" } },
1410 8f9db67c Richard Henderson
1411 c896fe29 bellard
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1412 c896fe29 bellard
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1413 c896fe29 bellard
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1414 c896fe29 bellard
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1415 c896fe29 bellard
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1416 c896fe29 bellard
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1417 c896fe29 bellard
    { INDEX_op_qemu_ld64, { "r", "L" } },
1418 c896fe29 bellard
1419 c896fe29 bellard
    { INDEX_op_qemu_st8, { "L", "L" } },
1420 c896fe29 bellard
    { INDEX_op_qemu_st16, { "L", "L" } },
1421 c896fe29 bellard
    { INDEX_op_qemu_st32, { "L", "L" } },
1422 016b2b28 Aurelien Jarno
    { INDEX_op_qemu_st64, { "L", "L" } },
1423 c896fe29 bellard
1424 c896fe29 bellard
    { -1 },
1425 c896fe29 bellard
};
1426 c896fe29 bellard
1427 c896fe29 bellard
void tcg_target_init(TCGContext *s)
1428 c896fe29 bellard
{
1429 b03cce8e bellard
    /* fail safe */
1430 b03cce8e bellard
    if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1431 b03cce8e bellard
        tcg_abort();
1432 b03cce8e bellard
1433 c896fe29 bellard
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1434 c896fe29 bellard
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
1435 c896fe29 bellard
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1436 c896fe29 bellard
                     (1 << TCG_REG_RDI) | 
1437 c896fe29 bellard
                     (1 << TCG_REG_RSI) | 
1438 c896fe29 bellard
                     (1 << TCG_REG_RDX) |
1439 c896fe29 bellard
                     (1 << TCG_REG_RCX) |
1440 c896fe29 bellard
                     (1 << TCG_REG_R8) |
1441 c896fe29 bellard
                     (1 << TCG_REG_R9) |
1442 c896fe29 bellard
                     (1 << TCG_REG_RAX) |
1443 c896fe29 bellard
                     (1 << TCG_REG_R10) |
1444 c896fe29 bellard
                     (1 << TCG_REG_R11));
1445 c896fe29 bellard
    
1446 c896fe29 bellard
    tcg_regset_clear(s->reserved_regs);
1447 c896fe29 bellard
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
1448 3c3a1d20 bellard
1449 c896fe29 bellard
    tcg_add_target_add_op_defs(x86_64_op_defs);
1450 c896fe29 bellard
}