Remove stray "i" from mul_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4933 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary PPC64/Linux host support
ppc64.ld from Heikki Lindholm's patchhttp://marc.info/?l=qemu-devel&m=114086179024634&w=2
Issues:x86_64 tripple faults shortly after decompressing the kernelNo immediate versions of most 64 bit operationsMore......
64 bit signed comparison fix (Juergen Lock)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4855 c046a42c-6fe2-441c-8c8c-71466251a162
Fix 64 bit constant generation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162
Fuse EQ and NE handling in tcg_out_brcond2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress bogus compiler warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4803 c046a42c-6fe2-441c-8c8c-71466251a162
According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
Shuffle contents of tcg_target_reg_alloc_order
Move reserved/volatile registers down. Currently qemu_ld/stXX aremarked with TCG_OPF_CALL_CLOBBER and since memory accesses arefrequent and R3 through R12 are volatile moving this down results inless spills and tighter generated code....
Save LR into proper place on callers stack frame
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4745 c046a42c-6fe2-441c-8c8c-71466251a162
Reimplement brcond2 and refactor brcond
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4738 c046a42c-6fe2-441c-8c8c-71466251a162
Allocate register pair for 64-bit registers on 32-bit host.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4730 c046a42c-6fe2-441c-8c8c-71466251a162
Remove stray variable
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4725 c046a42c-6fe2-441c-8c8c-71466251a162
Use rem/div[u]_i32 drop div[u]2_i32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4722 c046a42c-6fe2-441c-8c8c-71466251a162
Emit trampolines manually in prologue
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4715 c046a42c-6fe2-441c-8c8c-71466251a162
Fix test for signed div fast path
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4714 c046a42c-6fe2-441c-8c8c-71466251a162
Fix div[u]2.
Previous code assummed 32 by 32 bit divmod operation, and survivedx86_64 test only by sheer luck. MIPS wasn't so forgiving.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4705 c046a42c-6fe2-441c-8c8c-71466251a162
PPC TCG Fixes
Allocate a register pair instead of a single register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4688 c046a42c-6fe2-441c-8c8c-71466251a162
Spelling fixes, by Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4655 c046a42c-6fe2-441c-8c8c-71466251a162
support of long calls for PPC (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4629 c046a42c-6fe2-441c-8c8c-71466251a162
Fix signed/unsigned issues of immediate version of brcond (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4588 c046a42c-6fe2-441c-8c8c-71466251a162
ppc TCG target (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4584 c046a42c-6fe2-441c-8c8c-71466251a162
jump simplification
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4583 c046a42c-6fe2-441c-8c8c-71466251a162
jump optimizations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4582 c046a42c-6fe2-441c-8c8c-71466251a162
update
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4581 c046a42c-6fe2-441c-8c8c-71466251a162
suppressed unused macro handling
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4580 c046a42c-6fe2-441c-8c8c-71466251a162
added local temporaries
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4576 c046a42c-6fe2-441c-8c8c-71466251a162
Implement byte swapping accesses
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4574 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
Relax a constraint for qemu_ld64 on ARM host.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4567 c046a42c-6fe2-441c-8c8c-71466251a162
Fix a deadly typo, correct comments.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4566 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM host TLB.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4564 c046a42c-6fe2-441c-8c8c-71466251a162
Implement 64-bit constant loads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4561 c046a42c-6fe2-441c-8c8c-71466251a162
Use sethi and arith functions, fix comment
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4560 c046a42c-6fe2-441c-8c8c-71466251a162
Fix stack offsets and alignment
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4559 c046a42c-6fe2-441c-8c8c-71466251a162
Define stack offsets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4554 c046a42c-6fe2-441c-8c8c-71466251a162
More TCGv type fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4553 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM conditional branch bug.Add tcg_gen_brcondi.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
Comment non-obvious calculation. Don't clobber r3 in qemu_st64.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162
A branch insn must not overwrite the branch target before relocation.
When a branch to label is translated it generates a reloc that is filled inwhen the label is translated. However, when handling an exception andsearching for the pc we abort the translation early and we sometimes...
added tcg_temp_free() and improved the handling of constants
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4544 c046a42c-6fe2-441c-8c8c-71466251a162
Fix qemu_ld/st for mem_index > 0 on arm host.
offsetof(CPUState, tlb_table[mem_index][0].addr_read) with mem_index > 0was larger than max immediate offset for ldr and str (12-bit) so insert anadditional insn to add the mem_index offset.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4542 c046a42c-6fe2-441c-8c8c-71466251a162
Define TCG_TARGET_CALL_STACK_OFFSET on arm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
compilation fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4540 c046a42c-6fe2-441c-8c8c-71466251a162
profiler clean up
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4537 c046a42c-6fe2-441c-8c8c-71466251a162
added debug_insn_start debug instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4531 c046a42c-6fe2-441c-8c8c-71466251a162
debug output: write helper names
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4529 c046a42c-6fe2-441c-8c8c-71466251a162
more generic call codegen
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4528 c046a42c-6fe2-441c-8c8c-71466251a162
fixed zero shifts (64 bit case)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4527 c046a42c-6fe2-441c-8c8c-71466251a162
small shift opts
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4525 c046a42c-6fe2-441c-8c8c-71466251a162
fixed dead global variable update
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4512 c046a42c-6fe2-441c-8c8c-71466251a162
Fix 8-bit signed load/store and a typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4504 c046a42c-6fe2-441c-8c8c-71466251a162
Implement neg_i32, clean-up.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
Remove dyngen ARM code, which did't build.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4501 c046a42c-6fe2-441c-8c8c-71466251a162
ARM host support for TCG targets.
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162
Better solution for the alignment problem
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4498 c046a42c-6fe2-441c-8c8c-71466251a162
Switch most MIPS logical and arithmetic instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4496 c046a42c-6fe2-441c-8c8c-71466251a162
Fix constant checks on Sparc64 host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4486 c046a42c-6fe2-441c-8c8c-71466251a162
Fix TCG alignment problems on Sparc64 host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4485 c046a42c-6fe2-441c-8c8c-71466251a162
added 'pure' function attribute - fixed indirect function calls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4469 c046a42c-6fe2-441c-8c8c-71466251a162
added not pseudo op - more _tl macros
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4468 c046a42c-6fe2-441c-8c8c-71466251a162
Fix qemu_ld/st branches, constification, use orcc for tst synthetic op
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4466 c046a42c-6fe2-441c-8c8c-71466251a162
Implement qemu_ld/st, fix brcond, handle more corner cases
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4463 c046a42c-6fe2-441c-8c8c-71466251a162
Implement brcond, ldst with large offset; fix direct jump, prologue
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4461 c046a42c-6fe2-441c-8c8c-71466251a162
Fix bit fitting checks
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4460 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compilation on Sparc host, implement ld and st
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4457 c046a42c-6fe2-441c-8c8c-71466251a162
temporary hack to handle register shortage with dyngen for qemu_st64()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4438 c046a42c-6fe2-441c-8c8c-71466251a162
Add TCG native negation op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
Add zero extension (pseudo-)ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
REXB optimization cannot be done at this level
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4420 c046a42c-6fe2-441c-8c8c-71466251a162
fixed qemu_st8 insn - prologue saved too many registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4418 c046a42c-6fe2-441c-8c8c-71466251a162
Fix DEBUG_TCGV.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4415 c046a42c-6fe2-441c-8c8c-71466251a162
Rename CONFIG_NO_DYNGEN_OP to CONFIG_DYNGEN_OP to avoid double negatives
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4412 c046a42c-6fe2-441c-8c8c-71466251a162
fixed global variable handling with qemu load/stores - initial global prologue/epilogue implementation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4406 c046a42c-6fe2-441c-8c8c-71466251a162
Fix i64 remainder calculation copy-paste error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4357 c046a42c-6fe2-441c-8c8c-71466251a162
Add helpers and shorthands for mul and muli operations.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4319 c046a42c-6fe2-441c-8c8c-71466251a162
Skip register moves when the target and the source are the same
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4312 c046a42c-6fe2-441c-8c8c-71466251a162
HPPA (PA-RISC) host support
(Stuart Brady)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 9/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 7/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
Add TL variants of trunc and ext/extu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4099 c046a42c-6fe2-441c-8c8c-71466251a162
Prepare for op.c removal and zero legacy ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4095 c046a42c-6fe2-441c-8c8c-71466251a162
Make TCG br op available
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4093 c046a42c-6fe2-441c-8c8c-71466251a162
Increase max temps limit
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4074 c046a42c-6fe2-441c-8c8c-71466251a162
Add discard_ptr and discard_tl
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4072 c046a42c-6fe2-441c-8c8c-71466251a162
Add tcg_const_tl
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4053 c046a42c-6fe2-441c-8c8c-71466251a162
Fix i32 memory backed variables on 64-bit host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4044 c046a42c-6fe2-441c-8c8c-71466251a162
TCG README fixes (Stuart Brady)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4042 c046a42c-6fe2-441c-8c8c-71466251a162
Remove blank elements in tcg_target_reg_alloc_order[] (Stuart Brady)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4039 c046a42c-6fe2-441c-8c8c-71466251a162
Add function prologue, fix pointer load on Sparc64 host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4027 c046a42c-6fe2-441c-8c8c-71466251a162
Update based on Stuart Brady's comments
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4026 c046a42c-6fe2-441c-8c8c-71466251a162
32-bit host sign extension fix (Juergen Lock).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4017 c046a42c-6fe2-441c-8c8c-71466251a162
Add brcond_tl
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4008 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compiler warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4003 c046a42c-6fe2-441c-8c8c-71466251a162
Fix register references (Igor Kovalenko)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4002 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary Sparc TCG target
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3995 c046a42c-6fe2-441c-8c8c-71466251a162
Fix mixed defines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3992 c046a42c-6fe2-441c-8c8c-71466251a162
More helper types, rearrange generic definitions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3988 c046a42c-6fe2-441c-8c8c-71466251a162