Archipelago » qemu

*.tp

*.vr

*.d

#endif

#endif /* _A_OUT_H_ */

    NULL,

    cloop_close,

};

    NULL,

    dmg_close,

};

    print_direntry(NULL);

}

#endif

    return s->file;

}

    start &= qemu_host_page_mask;

    return msync((void *)start, end - start, flags);

}

    if (q != &k->info)

        free_sigqueue(q);

}

#undef GEN_HELPER

#endif

    return ( a0 != b0 ) || ( a1 != b1 );

}

    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));

    tcg_temp_free_i32(tmp);

}

                    "Advanced PCI Bus secondary bridge 2");

    return secondary;

}

void stellaris_enet_init(NICInfo *nd, uint32_t base, qemu_irq irq);

#endif /* !ARM_MISC_H */

    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    /* ??? Save/restore.  */

}

    /* This device has no state to save/restore.  The component timers will

       save themselves.  */

}

    return pic;

}

    cpu_to_be16wu((uint16_t *)buf, len - 2);

    return len;

}

#endif

    return s->bus;

}

    return s;

}

{

    *dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);

}

    m5206_mbar_reset(s);

    return pic;

}

#endif

    return val;

}

/* dscm1xxxx.c */

struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);

    }

    register_savevm("pl011_uart", -1, 1, pl011_save, pl011_load, s);

}

    pl022_reset(s);

    register_savevm("pl022_ssp", -1, 1, pl022_save, pl022_load, s);

}

        s->dev = ps2_kbd_init(pl050_update, s);

    /* ??? Save/restore.  */

}

    register_savevm("pl061_gpio", -1, 1, pl061_save, pl061_load, s);

    return qemu_allocate_irqs(pl061_set_irq, s, 8);

}

    /* ??? Save/restore.  */

    return s;

}

    return s->bus;

}

void ps2_queue(void *, int b);

void ps2_keyboard_set_translation(void *opaque, int mode);

void ps2_mouse_fake_event(void *opaque);

    s->timer = qemu_new_timer(vm_clock, ptimer_tick, s);

    return s;

}

        rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));

#endif /* RTL8139_ONBOARD_TIMER */

}

    return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),

                               1)[0];

}

    return p->bus;

}

    slavio_intctl_reset(s);

    return s;

}

#undef PIXEL_TYPE

#undef PIXEL_NAME

#undef BGR_FORMAT

/* smbus_eeprom.c */

void smbus_eeprom_device_init(i2c_bus *bus, uint8_t addr, uint8_t *buf);

    register_savevm("ssi_sd", -1, 1, ssi_sd_save, ssi_sd_load, s);

    return s;

}

    register_savevm("stellaris_gamepad", -1, 1,

                    stellaris_gamepad_save, stellaris_gamepad_load, s);

}

    sun4c_intctl_reset(s);

    return s;

}

    .nodisk_ok = 1,

    .use_scsi = 1,

};

#undef BITS

#undef SET_PIXEL

#endif

    return s->bus;

}

    return s;

}

    return s;

}

colon 0x34 shift

minus 0x35

underscore 0x35 shift

colon 0x34 shift

minus 0x35

underscore 0x35 shift

THORN 0x35 shift

dead_belowdot 0x35 altgr

dead_abovedot 0x35 shift altgr

bracketright 0x56

bracketleft 0x56 shift

brokenbar 0x56 altgr

colon 0x34 shift

minus 0x35

underscore 0x35 shift

#define TARGET_TIOCGICOUNT	0x545D	/* read serial port inline interrupt counts */

#define TARGET_TIOCGHAYESESP	0x545E  /* Get Hayes ESP configuration */

#define TARGET_TIOCSHAYESESP	0x545F  /* Set Hayes ESP configuration */

  }

}

#endif

#define TARGET_TIOCPKT_DOSTOP		32

#define TARGET_TIOCSER_TEMT    0x01	/* Transmitter physically empty */

        unsigned long exs;

        unsigned long eda;

};

#define TARGET_TIOCPKT_DOSTOP		32

#define TARGET_TIOCSER_TEMT    0x01	/* Transmitter physically empty */

/* for robust mutexes */

#define TARGET_EOWNERDEAD      130     /* Owner died */

#define TARGET_ENOTRECOVERABLE 131     /* State not recoverable */

#define TARGET_TIOCPKT_DOSTOP		32

#define TARGET_TIOCSER_TEMT    0x01	/* Transmitter physically empty */

#define TARGET_TIOCPKT_DOSTOP		32

#define TARGET_TIOCSER_TEMT    0x01	/* Transmitter physically empty */

#define TARGET_TIOCMIWAIT	0x545C	/* wait for a change on serial input line(s) */

#define TARGET_TIOCGICOUNT	0x545D	/* read serial port inline interrupt counts */

#define TARGET_TIOCSERSETMULTI 0x545B /* Set multiport config */

#define TARGET_TIOCMIWAIT	0x545C /* Wait input */

#define TARGET_TIOCGICOUNT	0x545D /* Read serial port inline interrupt counts */

#define TARGET_TIOCSERSETMULTI 0x545B /* Set multiport config */

#define TARGET_TIOCMIWAIT	0x545C /* Wait input */

#define TARGET_TIOCGICOUNT	0x545D /* Read serial port inline interrupt counts */

            break;

        }

}

 out:

    return ret;

}

}

#endif

clean:

	rm -f $(TARGETS) *.o *~

    return ret;

}

        return NULL;

    return term_history[index];

}

const int s390_num_opcodes =

  sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);

  .debug_typenames 0 : { *(.debug_typenames) }

  .debug_varnames  0 : { *(.debug_varnames) }

}

#endif

void debug_init _P((char *, int));

	return (struct mbuf *)0;

}

		   memcpy(to+off,sb->sb_data,len);

	}

}

	else

		sofcantsendmore(so);

}

    }

    cpu_fprintf(f, "\nlock     " TARGET_FMT_lx "\n", env->lock);

}

    return 0;

}

#undef DEFR

#undef DEFF64

};

    env->div2 = rem;

    env->cc_dest = flags;

}

{

    return 0;

}

Sun4v:

- A lot of unimplemented features

 - A lot of real machine types

    tlb_flush(env, 1);

    return 0;

}

#define tcg_gen_addi_ptr tcg_gen_addi_i64

#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64

#endif /* TCG_TARGET_REG_BITS != 32 */

{

    return arg1 % arg2;

}

display /x $r3

display /x $r4

display /t $ccs

Test-suite for the cris port. Heavily based on the test-suite for the CRIS port of sim by Hans-Peter Nilsson.

 checkr3 6712

 quit

 checkr3 d

 quit

 checkr3 ffffff00

 quit

  printf ("pass\n");

  exit (0);

}

  printf ("pass\n");

  exit (0);

}

    printf("\n");

    return 0;

}

#undef OP_SHIFTD

#undef OP_NOBYTE

#undef EXECSHIFT

    }

    return 0;

}