root / hw / ppc_prep.c @ 1d914fa0
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/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "nvram.h" |
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#include "pc.h" |
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#include "fdc.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "isa.h" |
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#include "pci.h" |
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#include "prep_pci.h" |
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#include "usb-ohci.h" |
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#include "ppc.h" |
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#include "boards.h" |
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#include "qemu-log.h" |
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#include "ide.h" |
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#include "loader.h" |
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#include "mc146818rtc.h" |
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//#define HARD_DEBUG_PPC_IO
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//#define DEBUG_PPC_IO
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1 |
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#define MAX_IDE_BUS 2 |
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#define BIOS_SIZE (1024 * 1024) |
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#define BIOS_FILENAME "ppc_rom.bin" |
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#define KERNEL_LOAD_ADDR 0x01000000 |
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#define INITRD_LOAD_ADDR 0x01800000 |
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#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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#define DEBUG_PPC_IO
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#endif
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#if defined (HARD_DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, ...) \
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do { \
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if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
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qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
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} else { \
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printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
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} \ |
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} while (0) |
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#elif defined (DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, ...) \
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qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) |
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#else
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#define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
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#endif
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
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static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
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static const int ide_irq[2] = { 13, 13 }; |
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#define NE2000_NB_MAX 6 |
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
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//static PITState *pit;
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000 |
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#if 0
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/* Speaker port 0x61 */
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static int speaker_data_on;
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static int dummy_refresh_clock;
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#endif
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static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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#if 0
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speaker_data_on = (val >> 1) & 1;
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pit_set_gate(pit, 2, val & 1);
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#endif
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} |
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static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
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{ |
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#if 0
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int out;
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out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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dummy_refresh_clock ^= 1;
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return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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(dummy_refresh_clock << 4);
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#endif
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return 0; |
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} |
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/* PCI intack register */
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/* Read-only register (?) */
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static void _PPC_intack_write (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#if 0
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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} |
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static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) |
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{ |
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uint32_t retval = 0;
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if ((addr & 0xf) == 0) |
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retval = pic_intack_read(isa_pic); |
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#if 0
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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#endif
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return retval;
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} |
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static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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return _PPC_intack_read(addr);
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} |
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static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap16(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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} |
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static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap32(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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} |
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static CPUWriteMemoryFunc * const PPC_intack_write[] = { |
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&_PPC_intack_write, |
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&_PPC_intack_write, |
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&_PPC_intack_write, |
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}; |
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static CPUReadMemoryFunc * const PPC_intack_read[] = { |
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&PPC_intack_readb, |
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&PPC_intack_readw, |
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&PPC_intack_readl, |
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}; |
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/* PowerPC control and status registers */
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#if 0 // Not used
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static struct {
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/* IDs */
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uint32_t veni_devi;
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uint32_t revi;
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/* Control and status */
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uint32_t gcsr;
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uint32_t xcfr;
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uint32_t ct32;
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uint32_t mcsr;
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/* General purpose registers */
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uint32_t gprg[6];
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/* Exceptions */
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uint32_t feen;
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uint32_t fest;
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uint32_t fema;
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uint32_t fecl;
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uint32_t eeen;
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uint32_t eest;
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uint32_t eecl;
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uint32_t eeint;
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uint32_t eemck0;
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uint32_t eemck1;
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/* Error diagnostic */
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} XCSR;
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static void PPC_XCSR_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static void PPC_XCSR_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
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value); |
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} |
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static void PPC_XCSR_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value); |
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#endif
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
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value); |
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} |
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static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
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retval); |
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return retval;
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} |
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static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
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retval); |
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap16(retval); |
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#endif
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return retval;
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} |
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static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
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retval); |
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap32(retval); |
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#endif
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return retval;
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} |
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static CPUWriteMemoryFunc * const PPC_XCSR_write[] = { |
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&PPC_XCSR_writeb, |
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&PPC_XCSR_writew, |
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&PPC_XCSR_writel, |
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}; |
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static CPUReadMemoryFunc * const PPC_XCSR_read[] = { |
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&PPC_XCSR_readb, |
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&PPC_XCSR_readw, |
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&PPC_XCSR_readl, |
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}; |
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#endif
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t { |
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qemu_irq reset_irq; |
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M48t59State *nvram; |
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uint8_t state; |
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uint8_t syscontrol; |
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uint8_t fake_io[2];
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int contiguous_map;
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int endian;
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} sysctrl_t; |
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enum {
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STATE_HARDFILE = 0x01,
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}; |
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static sysctrl_t *sysctrl;
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static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
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val); |
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sysctrl->fake_io[addr - 0x0398] = val;
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} |
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static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
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sysctrl->fake_io[addr - 0x0398]);
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return sysctrl->fake_io[addr - 0x0398]; |
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} |
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
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addr - PPC_IO_BASE, val); |
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switch (addr) {
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case 0x0092: |
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) { |
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qemu_irq_raise(sysctrl->reset_irq); |
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} else {
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qemu_irq_lower(sysctrl->reset_irq); |
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} |
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/* Check LE mode */
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if (val & 0x02) { |
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sysctrl->endian = 1;
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} else {
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sysctrl->endian = 0;
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} |
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break;
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case 0x0800: |
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802: |
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803: |
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/* Motorola base module status register : read-only */
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break;
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case 0x0808: |
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/* Hardfile light register */
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if (val & 1) |
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sysctrl->state |= STATE_HARDFILE; |
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else
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sysctrl->state &= ~STATE_HARDFILE; |
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break;
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case 0x0810: |
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL) |
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m48t59_toggle_lock(sysctrl->nvram, 1);
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break;
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case 0x0812: |
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL) |
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m48t59_toggle_lock(sysctrl->nvram, 2);
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break;
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case 0x0814: |
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/* L2 invalidate register */
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C: |
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
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case 0x0850: |
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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" => %02" PRIx32"\n", addr, val); |
376 |
break;
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} |
378 |
} |
379 |
|
380 |
static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
381 |
{ |
382 |
sysctrl_t *sysctrl = opaque; |
383 |
uint32_t retval = 0xFF;
|
384 |
|
385 |
switch (addr) {
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386 |
case 0x0092: |
387 |
/* Special port 92 */
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388 |
retval = 0x00;
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389 |
break;
|
390 |
case 0x0800: |
391 |
/* Motorola CPU configuration register */
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392 |
retval = 0xEF; /* MPC750 */ |
393 |
break;
|
394 |
case 0x0802: |
395 |
/* Motorola Base module feature register */
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396 |
retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
397 |
break;
|
398 |
case 0x0803: |
399 |
/* Motorola base module status register */
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400 |
retval = 0xE0; /* Standard MPC750 */ |
401 |
break;
|
402 |
case 0x080C: |
403 |
/* Equipment present register:
|
404 |
* no L2 cache
|
405 |
* no upgrade processor
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406 |
* no cards in PCI slots
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407 |
* SCSI fuse is bad
|
408 |
*/
|
409 |
retval = 0x3C;
|
410 |
break;
|
411 |
case 0x0810: |
412 |
/* Motorola base module extended feature register */
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413 |
retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
414 |
break;
|
415 |
case 0x0814: |
416 |
/* L2 invalidate: don't care */
|
417 |
break;
|
418 |
case 0x0818: |
419 |
/* Keylock */
|
420 |
retval = 0x00;
|
421 |
break;
|
422 |
case 0x081C: |
423 |
/* system control register
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424 |
* 7 - 6 / 1 - 0: L2 cache enable
|
425 |
*/
|
426 |
retval = sysctrl->syscontrol; |
427 |
break;
|
428 |
case 0x0823: |
429 |
/* */
|
430 |
retval = 0x03; /* no L2 cache */ |
431 |
break;
|
432 |
case 0x0850: |
433 |
/* I/O map type register */
|
434 |
retval = sysctrl->contiguous_map; |
435 |
break;
|
436 |
default:
|
437 |
printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
438 |
break;
|
439 |
} |
440 |
PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
441 |
addr - PPC_IO_BASE, retval); |
442 |
|
443 |
return retval;
|
444 |
} |
445 |
|
446 |
static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
447 |
target_phys_addr_t addr) |
448 |
{ |
449 |
if (sysctrl->contiguous_map == 0) { |
450 |
/* 64 KB contiguous space for IOs */
|
451 |
addr &= 0xFFFF;
|
452 |
} else {
|
453 |
/* 8 MB non-contiguous space for IOs */
|
454 |
addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
455 |
} |
456 |
|
457 |
return addr;
|
458 |
} |
459 |
|
460 |
static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
461 |
uint32_t value) |
462 |
{ |
463 |
sysctrl_t *sysctrl = opaque; |
464 |
|
465 |
addr = prep_IO_address(sysctrl, addr); |
466 |
cpu_outb(addr, value); |
467 |
} |
468 |
|
469 |
static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
470 |
{ |
471 |
sysctrl_t *sysctrl = opaque; |
472 |
uint32_t ret; |
473 |
|
474 |
addr = prep_IO_address(sysctrl, addr); |
475 |
ret = cpu_inb(addr); |
476 |
|
477 |
return ret;
|
478 |
} |
479 |
|
480 |
static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
481 |
uint32_t value) |
482 |
{ |
483 |
sysctrl_t *sysctrl = opaque; |
484 |
|
485 |
addr = prep_IO_address(sysctrl, addr); |
486 |
#ifdef TARGET_WORDS_BIGENDIAN
|
487 |
value = bswap16(value); |
488 |
#endif
|
489 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
490 |
cpu_outw(addr, value); |
491 |
} |
492 |
|
493 |
static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
494 |
{ |
495 |
sysctrl_t *sysctrl = opaque; |
496 |
uint32_t ret; |
497 |
|
498 |
addr = prep_IO_address(sysctrl, addr); |
499 |
ret = cpu_inw(addr); |
500 |
#ifdef TARGET_WORDS_BIGENDIAN
|
501 |
ret = bswap16(ret); |
502 |
#endif
|
503 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
504 |
|
505 |
return ret;
|
506 |
} |
507 |
|
508 |
static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
509 |
uint32_t value) |
510 |
{ |
511 |
sysctrl_t *sysctrl = opaque; |
512 |
|
513 |
addr = prep_IO_address(sysctrl, addr); |
514 |
#ifdef TARGET_WORDS_BIGENDIAN
|
515 |
value = bswap32(value); |
516 |
#endif
|
517 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
518 |
cpu_outl(addr, value); |
519 |
} |
520 |
|
521 |
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
522 |
{ |
523 |
sysctrl_t *sysctrl = opaque; |
524 |
uint32_t ret; |
525 |
|
526 |
addr = prep_IO_address(sysctrl, addr); |
527 |
ret = cpu_inl(addr); |
528 |
#ifdef TARGET_WORDS_BIGENDIAN
|
529 |
ret = bswap32(ret); |
530 |
#endif
|
531 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
532 |
|
533 |
return ret;
|
534 |
} |
535 |
|
536 |
static CPUWriteMemoryFunc * const PPC_prep_io_write[] = { |
537 |
&PPC_prep_io_writeb, |
538 |
&PPC_prep_io_writew, |
539 |
&PPC_prep_io_writel, |
540 |
}; |
541 |
|
542 |
static CPUReadMemoryFunc * const PPC_prep_io_read[] = { |
543 |
&PPC_prep_io_readb, |
544 |
&PPC_prep_io_readw, |
545 |
&PPC_prep_io_readl, |
546 |
}; |
547 |
|
548 |
#define NVRAM_SIZE 0x2000 |
549 |
|
550 |
/* PowerPC PREP hardware initialisation */
|
551 |
static void ppc_prep_init (ram_addr_t ram_size, |
552 |
const char *boot_device, |
553 |
const char *kernel_filename, |
554 |
const char *kernel_cmdline, |
555 |
const char *initrd_filename, |
556 |
const char *cpu_model) |
557 |
{ |
558 |
CPUState *env = NULL, *envs[MAX_CPUS];
|
559 |
char *filename;
|
560 |
nvram_t nvram; |
561 |
M48t59State *m48t59; |
562 |
int PPC_io_memory;
|
563 |
int linux_boot, i, nb_nics1, bios_size;
|
564 |
ram_addr_t ram_offset, bios_offset; |
565 |
uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
566 |
PCIBus *pci_bus; |
567 |
qemu_irq *i8259; |
568 |
int ppc_boot_device;
|
569 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
570 |
DriveInfo *fd[MAX_FD]; |
571 |
|
572 |
sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
573 |
|
574 |
linux_boot = (kernel_filename != NULL);
|
575 |
|
576 |
/* init CPUs */
|
577 |
if (cpu_model == NULL) |
578 |
cpu_model = "602";
|
579 |
for (i = 0; i < smp_cpus; i++) { |
580 |
env = cpu_init(cpu_model); |
581 |
if (!env) {
|
582 |
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
583 |
exit(1);
|
584 |
} |
585 |
if (env->flags & POWERPC_FLAG_RTC_CLK) {
|
586 |
/* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
|
587 |
cpu_ppc_tb_init(env, 7812500UL);
|
588 |
} else {
|
589 |
/* Set time-base frequency to 100 Mhz */
|
590 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
591 |
} |
592 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
593 |
envs[i] = env; |
594 |
} |
595 |
|
596 |
/* allocate RAM */
|
597 |
ram_offset = qemu_ram_alloc(ram_size); |
598 |
cpu_register_physical_memory(0, ram_size, ram_offset);
|
599 |
|
600 |
/* allocate and load BIOS */
|
601 |
bios_offset = qemu_ram_alloc(BIOS_SIZE); |
602 |
if (bios_name == NULL) |
603 |
bios_name = BIOS_FILENAME; |
604 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
605 |
if (filename) {
|
606 |
bios_size = get_image_size(filename); |
607 |
} else {
|
608 |
bios_size = -1;
|
609 |
} |
610 |
if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
611 |
target_phys_addr_t bios_addr; |
612 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
613 |
bios_addr = (uint32_t)(-bios_size); |
614 |
cpu_register_physical_memory(bios_addr, bios_size, |
615 |
bios_offset | IO_MEM_ROM); |
616 |
bios_size = load_image_targphys(filename, bios_addr, bios_size); |
617 |
} |
618 |
if (bios_size < 0 || bios_size > BIOS_SIZE) { |
619 |
hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
|
620 |
} |
621 |
if (filename) {
|
622 |
qemu_free(filename); |
623 |
} |
624 |
if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
625 |
hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
|
626 |
} |
627 |
|
628 |
if (linux_boot) {
|
629 |
kernel_base = KERNEL_LOAD_ADDR; |
630 |
/* now we can load the kernel */
|
631 |
kernel_size = load_image_targphys(kernel_filename, kernel_base, |
632 |
ram_size - kernel_base); |
633 |
if (kernel_size < 0) { |
634 |
hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
|
635 |
exit(1);
|
636 |
} |
637 |
/* load initrd */
|
638 |
if (initrd_filename) {
|
639 |
initrd_base = INITRD_LOAD_ADDR; |
640 |
initrd_size = load_image_targphys(initrd_filename, initrd_base, |
641 |
ram_size - initrd_base); |
642 |
if (initrd_size < 0) { |
643 |
hw_error("qemu: could not load initial ram disk '%s'\n",
|
644 |
initrd_filename); |
645 |
} |
646 |
} else {
|
647 |
initrd_base = 0;
|
648 |
initrd_size = 0;
|
649 |
} |
650 |
ppc_boot_device = 'm';
|
651 |
} else {
|
652 |
kernel_base = 0;
|
653 |
kernel_size = 0;
|
654 |
initrd_base = 0;
|
655 |
initrd_size = 0;
|
656 |
ppc_boot_device = '\0';
|
657 |
/* For now, OHW cannot boot from the network. */
|
658 |
for (i = 0; boot_device[i] != '\0'; i++) { |
659 |
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
660 |
ppc_boot_device = boot_device[i]; |
661 |
break;
|
662 |
} |
663 |
} |
664 |
if (ppc_boot_device == '\0') { |
665 |
fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
666 |
exit(1);
|
667 |
} |
668 |
} |
669 |
|
670 |
isa_mem_base = 0xc0000000;
|
671 |
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
672 |
hw_error("Only 6xx bus is supported on PREP machine\n");
|
673 |
} |
674 |
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
675 |
pci_bus = pci_prep_init(i8259); |
676 |
/* Hmm, prep has no pci-isa bridge ??? */
|
677 |
isa_bus_new(NULL);
|
678 |
isa_bus_irqs(i8259); |
679 |
// pci_bus = i440fx_init();
|
680 |
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
681 |
PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, |
682 |
PPC_prep_io_write, sysctrl); |
683 |
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
684 |
|
685 |
/* init basic PC hardware */
|
686 |
pci_vga_init(pci_bus, 0, 0); |
687 |
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
688 |
// pit = pit_init(0x40, i8259[0]);
|
689 |
rtc_init(2000);
|
690 |
|
691 |
if (serial_hds[0]) |
692 |
serial_isa_init(0, serial_hds[0]); |
693 |
nb_nics1 = nb_nics; |
694 |
if (nb_nics1 > NE2000_NB_MAX)
|
695 |
nb_nics1 = NE2000_NB_MAX; |
696 |
for(i = 0; i < nb_nics1; i++) { |
697 |
if (nd_table[i].model == NULL) { |
698 |
nd_table[i].model = qemu_strdup("ne2k_isa");
|
699 |
} |
700 |
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
701 |
isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
702 |
} else {
|
703 |
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
704 |
} |
705 |
} |
706 |
|
707 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
708 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
709 |
exit(1);
|
710 |
} |
711 |
|
712 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
713 |
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
714 |
} |
715 |
|
716 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
717 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
718 |
hd[2 * i],
|
719 |
hd[2 * i + 1]); |
720 |
} |
721 |
isa_create_simple("i8042");
|
722 |
DMA_init(1);
|
723 |
// SB16_init();
|
724 |
|
725 |
for(i = 0; i < MAX_FD; i++) { |
726 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
727 |
} |
728 |
fdctrl_init_isa(fd); |
729 |
|
730 |
/* Register speaker port */
|
731 |
register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
732 |
register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
733 |
/* Register fake IO ports for PREP */
|
734 |
sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
735 |
register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
736 |
register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
737 |
/* System control ports */
|
738 |
register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
739 |
register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
740 |
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
741 |
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
742 |
/* PCI intack location */
|
743 |
PPC_io_memory = cpu_register_io_memory(PPC_intack_read, |
744 |
PPC_intack_write, NULL);
|
745 |
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
746 |
/* PowerPC control and status register group */
|
747 |
#if 0
|
748 |
PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
|
749 |
NULL);
|
750 |
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
751 |
#endif
|
752 |
|
753 |
if (usb_enabled) {
|
754 |
usb_ohci_init_pci(pci_bus, -1);
|
755 |
} |
756 |
|
757 |
m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
758 |
if (m48t59 == NULL) |
759 |
return;
|
760 |
sysctrl->nvram = m48t59; |
761 |
|
762 |
/* Initialise NVRAM */
|
763 |
nvram.opaque = m48t59; |
764 |
nvram.read_fn = &m48t59_read; |
765 |
nvram.write_fn = &m48t59_write; |
766 |
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
767 |
kernel_base, kernel_size, |
768 |
kernel_cmdline, |
769 |
initrd_base, initrd_size, |
770 |
/* XXX: need an option to load a NVRAM image */
|
771 |
0,
|
772 |
graphic_width, graphic_height, graphic_depth); |
773 |
|
774 |
/* Special port to get debug messages from Open-Firmware */
|
775 |
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
776 |
} |
777 |
|
778 |
static QEMUMachine prep_machine = {
|
779 |
.name = "prep",
|
780 |
.desc = "PowerPC PREP platform",
|
781 |
.init = ppc_prep_init, |
782 |
.max_cpus = MAX_CPUS, |
783 |
}; |
784 |
|
785 |
static void prep_machine_init(void) |
786 |
{ |
787 |
qemu_register_machine(&prep_machine); |
788 |
} |
789 |
|
790 |
machine_init(prep_machine_init); |