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# Date Author Comment
fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

6fa724a3 01/03/2009 04:04 pm aurel32

Add vscr access macros.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6158 c046a42c-6fe2-441c-8c8c-71466251a162

2231ef10 12/19/2008 12:43 am aurel32

target-ppc: fix type of spe_acc.

ACC is a 64-bit register and needs to be specified as such regardless of
the target.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6090 c046a42c-6fe2-441c-8c8c-71466251a162

ab5f265d 12/15/2008 09:03 am aurel32

target-ppc: add signed fields to ppc_avr_t.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6042 c046a42c-6fe2-441c-8c8c-71466251a162

93220573 12/12/2008 12:42 am aurel32

target-ppc: remove remaining warnings

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162

45d827d2 12/07/2008 03:40 pm aurel32

target-ppc: convert SPR accesses to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162

8983da70 12/07/2008 12:01 am aurel32

target-ppc: remove dead code

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5896 c046a42c-6fe2-441c-8c8c-71466251a162

74d37793 12/06/2008 11:46 pm aurel32

target-ppc: convert SLB/TLB instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162

2cbd949d 11/30/2008 06:23 pm aurel32

Common cpu_loop_exit prototype

All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Aurelien Jarno <>...

01a4afeb 11/27/2008 09:30 pm aurel32

target-ppc: convert POWER2 load/store instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162

6a6ae23f 11/27/2008 09:30 pm aurel32

target-ppc: convert SPE load/store to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162

fe1e5c53 11/24/2008 10:47 am aurel32

target-ppc: convert altivec load/store to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162

af12906f 11/19/2008 06:10 pm aurel32

target-ppc: convert fp ops to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162

6b917547 11/18/2008 09:46 pm aliguori

Refactor translation block CPU state handling (Jan Kiszka)

This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()...

622ed360 11/18/2008 09:36 pm aliguori

Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)

as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162

57951c27 11/10/2008 01:10 pm aurel32

target-ppc: convert most SPE integer instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162

4870167d 11/08/2008 10:57 am aurel32

target-ppc: fix tcg fatal error on i386 host

It looks like the i386 runs out of registers for allocation due
to too many global registers allocated by the ppc target.

Here is a quick and dirty fix that seems to solve the problem.
This should be considered as temporary....

8d71247e 11/01/2008 02:53 am aurel32

target-ppc: xer access prototypes no more used & implemented

Revision 5500 of the qemu repository removed all code using
ppc_load_xer & ppc_store_xer as well as their implementation.

Another patch fixes it's usage in kvm-userspace for powerpc, but I think...

e1571908 10/21/2008 02:31 pm aurel32

target-ppc: convert crf related instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162

3d7b417e 10/21/2008 02:28 pm aurel32

target-ppc: Convert XER accesses to TCG

Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162

b55266b5 09/20/2008 11:07 am blueswir1

Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162

47e4661c 09/04/2008 08:06 pm aurel32

ppc: Convert CRF moves to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162

bd7d9a6d 09/04/2008 08:26 am aurel32

ppc: cleanup register types

- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162

f78fb44e 09/04/2008 08:25 am aurel32

ppc: Convert GPR moves to TCG

Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers...

9656f324 07/01/2008 11:01 pm pbrook

Move interrupt_request and user_mode_only to common cpu state.
Save and restore env->interrupt_request and env->halted.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162

b3c7724c 06/30/2008 07:31 pm pbrook

Move CPU save/load registration to common code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162

2e70f6ef 06/29/2008 04:03 am pbrook

Add instruction counter.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162

f8ed7070 05/30/2008 08:54 pm pbrook

Fix typo.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162

6e68e076 05/30/2008 08:22 pm pbrook

Move clone() register setup to target specific code. Handle fork-like clone.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162

9133e39b 05/29/2008 01:08 pm bellard

Push common interrupt variables to cpu-defs.h (Glauber Costa)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162

ce5232c5 05/28/2008 08:14 pm bellard

moved halted field to CPU_COMMON

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162

f9320410 05/06/2008 05:58 pm aurel32

PPC: fix definition of msr_spe

(Tristan Gingold)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4361 c046a42c-6fe2-441c-8c8c-71466251a162

e9b34b37 12/10/2007 10:13 am j_mayer

Cleanup: remove useless TARGET_GPR_BITS definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3799 c046a42c-6fe2-441c-8c8c-71466251a162

4e777442 12/10/2007 09:40 am j_mayer

Fix PowerPC 74xx definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162

6b542af7 11/24/2007 04:03 am j_mayer

Fix incorrect debug prints (reported by Paul Brook).
Remove obsolete / duplicated debug prints and improve output consistency.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162

69facb78 11/24/2007 12:16 am j_mayer

Revert foolish patch.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3724 c046a42c-6fe2-441c-8c8c-71466251a162

9b605b9e 11/23/2007 07:33 pm pbrook

Fix ppc32 register dumps on 64-bit hosts.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3723 c046a42c-6fe2-441c-8c8c-71466251a162

bd928eba 11/21/2007 03:08 pm j_mayer

Fix PowerPC 7xx definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162

082c6681 11/19/2007 03:22 pm j_mayer

Remove shared macro used to define PowerPC implementations instructions sets:
tend more to propagate bugged definition than simplify the code.
Check and fix PowerPC 6xx implementations definitions.
Misc fixes in PowerPC CPU list.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162

add78955 11/19/2007 01:41 pm j_mayer

PowerPC 620 MMU do not have the same exact behavior as standard
64 bits PowerPC ones.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162

4018bae9 11/19/2007 03:48 am j_mayer

New PowerPC CPU flag to define the decrementer and time-base source clock.
Use it to properly initialize the clock for the PreP target.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162

4c1b1bfe 11/18/2007 01:14 am j_mayer

Improve PowerPC instructions set dump.
Remove meaningless define from cpu.h
Misc cleanups.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162

80d11f44 11/18/2007 01:02 am j_mayer

Add definitions for Freescale PowerPC implementations,
ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
thus providing a way of testing their implementation specific instructions.

...

b4095fed 11/18/2007 12:42 am j_mayer

Define Freescale cores specific MMU model, exceptions and input bus.
(but do not provide any actual implementation).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162

a4f30719 11/17/2007 11:14 pm j_mayer

PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.
Remove TARGET_PPC64 dependency and add code provision to be able
to define a fake 32 bits CPU with hypervisor feature support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162

7820dbf3 11/17/2007 04:16 am j_mayer

Make the PowerPC MMU model, exception model and input bus model
typedefed enums.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162

7b62a955 11/17/2007 04:04 am j_mayer

Add missing definition for number of input pins for the PowerPC 970 bus.
Use proper INPUT_NB definitions to allocate PowerPC input pins structure,
fixing a buffer overflow in the 6xx bus case.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3659 c046a42c-6fe2-441c-8c8c-71466251a162

b172c56a 11/17/2007 03:37 am j_mayer

Always make all PowerPC exception definitions visible.
Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162

7863667f 11/16/2007 04:11 pm j_mayer

Always make PowerPC hypervisor mode memory accesses and instructions
available for full system emulation, then removing all #if TARGET_PPC64H
from micro-ops and code translator.
Add new macros to dramatically simplify memory access tables definitions
in target-ppc/translate.c....

57c26279 11/14/2007 08:45 pm j_mayer

Fix PowerPC targets compilation on 32 bits hosts:
now that the SPE extension is available for all targets,
we always need to have some 64 bits temporary registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162

65d6c0f3 11/13/2007 01:29 am j_mayer

PowerPC SPE extension fix: must always preserve GPR high bits when
running in 32 bits mode.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162

3cd7d1dd 11/12/2007 03:56 am j_mayer

Allow use of SPE extension by all PowerPC targets,
adding gprh registers to store GPR MSBs when GPRs are 32 bits.
Remove not-needed-anymore ppcemb-linux-user target.
Keep ppcemb-softmmu target, which provides 1kB pages support
and 36 bits physical address space....

ee4e83ed 11/11/2007 01:51 am j_mayer

Allow selection of PowerPC CPU giving a PVR.
Remove unused pvr_mask field from CPU definition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162

aaed909a 11/10/2007 05:15 pm bellard

added cpu_model parameter to cpu_init()

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162

056401ea 11/04/2007 04:55 am j_mayer

PowerPC 601 need specific callbacks for its BATs setup.
Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation....

faadf50e 11/03/2007 03:37 pm j_mayer PowerPC MMU and exception fixes:
  • PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than
    later PowerPC implementation.
  • Bugfix in BATs check: must not stop after 4 BATs when more are provided.
  • Enable POWER 'rac' instruction.
  • Fix exception prefix for all supported PowerPC implementations....
7c58044c 10/27/2007 08:54 pm j_mayer

Fix PowerPC FPSCR update and floating-point exception generation
in most useful cases.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162

cd346349 10/26/2007 02:27 am j_mayer

Add PowerPC power-management state check callback.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3441 c046a42c-6fe2-441c-8c8c-71466251a162

0411a972 10/26/2007 12:35 am j_mayer

Gprof prooved the PowerPC emulation spent too much time in MSR load and store
routines. Coming back to a raw MSR storage model then speed-up the emulation.
Improve fast MSR updates (wrtee wrteei and mtriee cases).
Share rfi family instructions helpers code to avoid bug in duplicated code....

b227a8e9 10/14/2007 01:21 pm j_mayer

Properly implement non-execute bit on PowerPC segments and PTEs.
Fix page protection bits for PowerPC 64 MMU.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3395 c046a42c-6fe2-441c-8c8c-71466251a162

d68f1306 10/14/2007 12:27 pm j_mayer

Merge PowerPC 620 input bus definitions with standard PowerPC 6xx.
Avoid hardcoding PowerPC interrupts definitions to ease updates.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3393 c046a42c-6fe2-441c-8c8c-71466251a162

a13d7523 10/14/2007 12:14 pm j_mayer

There is no need of a specific MMU model for PowerPC 601.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162

6ebbf390 10/14/2007 10:07 am j_mayer

Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions....

c732abe2 10/12/2007 09:47 am j_mayer

Unify '-cpu ?' option.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162

25ba3a68 10/08/2007 05:58 am j_mayer

Remove synonymous in PowerPC MSR bits definitions.
Fix MSR EP bit buggy definition.
Remove unuseful MSR flags.
Fix MSR bits and flags definitions for most supported PowerPC implementations.
Add MSR definitions/flags constistency checks and optional dump.
...

a9d9eb8f 10/07/2007 09:19 pm j_mayer

Implement PowerPC Altivec load & stores, used by Apple firmware for memcpy.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3349 c046a42c-6fe2-441c-8c8c-71466251a162

b33c17e1 10/07/2007 08:30 pm j_mayer

PowerPC target coding style fixes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162

f2e63a42 10/07/2007 06:43 pm j_mayer

Reorganize the CPUPPCState structure to group features.
Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets....

d26bfc9a 10/07/2007 05:41 pm j_mayer

Add MSR bits signification per PowerPC implementation flags (to be continued).
As a side effect, single step and branch step are available again.
Remove irrelevant MSR bits definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3342 c046a42c-6fe2-441c-8c8c-71466251a162

12de9a39 10/06/2007 01:06 am j_mayer

Full implementation of PowerPC 64 MMU, just missing support for 1 TB
memory segments.
Remove the PowerPC 64 "bridge" MMU model and implement segment registers
emulation using SLB entries instead.
Make SLB area size implementation dependant.
Improve TLB & SLB search debug traces....

65f9ee8d 10/05/2007 04:11 pm j_mayer

Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3333 c046a42c-6fe2-441c-8c8c-71466251a162

d63001d1 10/04/2007 03:51 am j_mayer

Make PowerPC cache line size implementation dependant.
Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162

00af685f 10/03/2007 04:05 am j_mayer

We never have to export ppc_set_irq.
Protect PowerPC 64 only features with #ifdef (TARGET_PPC64)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3316 c046a42c-6fe2-441c-8c8c-71466251a162

a97fed52 10/02/2007 12:49 am j_mayer

Fix reproductible crash: call cpu_loop_exit from micro-op, not from helper.c

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3311 c046a42c-6fe2-441c-8c8c-71466251a162

daf4f96e 10/01/2007 04:51 am j_mayer

Avoid op helpers that would just call helpers for TLB & SLB management:
call the helpers directly from the micro-ops.
Avoid duplicated code for tlbsx. implementation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3302 c046a42c-6fe2-441c-8c8c-71466251a162

4e290a0b 10/01/2007 04:27 am j_mayer

Share input pins and internal interrupt controller between all PowerPC 40x.
Fix critical input interrupt generation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3299 c046a42c-6fe2-441c-8c8c-71466251a162

be147d08 09/30/2007 04:03 pm j_mayer
  • Update OEA environment, following the PowerPC 2.04 specification:
    - New mtmsr/mtmsrd form that just update RI and EE bits
    - New hrfid, lq and stq instructions
    - Add support for supervisor and hypervisor modes process priority update
    - Code provision for hypervisor SPR accesses...
bfa1e5cf 09/30/2007 03:50 am j_mayer

XER is to be treated as a 64 bits register on 64 bits implementations,
according to the PowerPC 2.04 specification.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3279 c046a42c-6fe2-441c-8c8c-71466251a162

a062e36c 09/30/2007 03:38 am j_mayer

Implement the PowerPC alternate time-base, following the 2.04 specification.
Share most code with the time-base management routines.
Remove time-base write routines from user-mode emulation environments.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3277 c046a42c-6fe2-441c-8c8c-71466251a162

58a7d328 09/29/2007 04:21 pm j_mayer

Code provision for hypervisor timers resources,
as described in PowerPC 2.04 specification.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3264 c046a42c-6fe2-441c-8c8c-71466251a162

e1833e1f 09/29/2007 04:06 pm j_mayer Rework PowerPC exceptions model to make it more versatile:
  • don't use exception vectors as the exception number.
    Use vectors numbers as defined in the PowerPC embedded specification instead
    and extend this model to cover all emulated PowerPC variants exceptions....
237c0af0 09/29/2007 03:01 pm j_mayer

Define the proper bfd_mach to be used by the disassembler for each
PowerPC emulated CPU.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3257 c046a42c-6fe2-441c-8c8c-71466251a162

198a74de 09/27/2007 07:44 pm ths

Move get_sp_from_cpustate from cpu.h to target_signal.h.
Enable sigaltstack processing for more architectures.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162

a04e134a 09/27/2007 04:57 pm ths

linux-user sigaltstack() syscall, by Thayne Harbaugh.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162

a750fc0b 09/27/2007 02:54 am j_mayer Great rework and cleanups to ease PowerPC implementations definitions.
  • cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
  • add new flags to define instructions sets more precisely
  • various changes in MMU models definitions
  • add definitions for PowerPC 440/460 support (insns and SPRs)....
2662a059 09/21/2007 08:50 am j_mayer

More PowerPC definitions, from POWER 2.04 specifications and misc sources.
Check that at least instructions set and SPRs are correct for
PowerPC 401, 403, 405 and 440 cores.
Implement PowerPC 401 MMU model (real-mode only).
Improve INSNs and SPRs dump to ease parse with standard shell tools....

4296f459 09/21/2007 08:23 am j_mayer

Make CPU hflags be a masked version of the PowerPC MSR.
As a side effect, avoid potential bits shadowing in TB flags on 64 bits BookE.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3199 c046a42c-6fe2-441c-8c8c-71466251a162

cbecba26 09/20/2007 12:44 pm j_mayer

Move likely and unlikely macros in a common place (Aurelien Jarno).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3192 c046a42c-6fe2-441c-8c8c-71466251a162

71c8b8fd 09/19/2007 08:46 am j_mayer

TARGET_FMT_lu may also be useful.
Fix compilation warnings.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3190 c046a42c-6fe2-441c-8c8c-71466251a162

8b67546f 09/19/2007 07:34 am j_mayer

More PowerPC target cleanups:
- remove unuseful historical macros and definitions
- fix comments (bugs and cosmetics)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3185 c046a42c-6fe2-441c-8c8c-71466251a162

d9d7210c 09/18/2007 02:17 pm j_mayer

Fix PowerPC 32 emulation on 64 bits hosts:
we can use 64 bits registers but not pretend page is 1kB long
As it seems most Linux programs assume page-size is 4kB, never allow
1kB pages for user-mode only emulation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3182 c046a42c-6fe2-441c-8c8c-71466251a162

36081602 09/17/2007 11:21 am j_mayer

Coding style fixes in PowerPC related code (no functional change):
- avoid useless blanks at EOL.
- avoid tabs.
- fix wrapping lines on 80 chars terminals.
- add missing ';' at macros EOL to avoid confusing auto-identers.
- fix identation.
- Remove historical macros in micro-ops (PARAM, SPARAM, PPC_OP, regs)...

5fafdf24 09/17/2007 12:08 am ths

find -type f | xargs sed -i 's/[\t ]$//g' # on most files

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162

3c4c9f9f 07/11/2007 01:36 pm ths

Fix PPCEMB for 32bit hosts.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3059 c046a42c-6fe2-441c-8c8c-71466251a162

0cfec834 06/23/2007 07:02 pm ths

Spelling fixes, by Aurelien Jarno.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3009 c046a42c-6fe2-441c-8c8c-71466251a162

9467d44c 06/04/2007 12:02 am ths

Move target-specific defines to the target directories.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162

35cdaad6 04/24/2007 09:50 am j_mayer

Code provision for new PowerPC embedded target support with:
- 1 kB page size
- 64 bits GPR
- 64 bits physical address space
- SPE extension support.
Change TARGET_PPCSPE into TARGET_PPCEMB

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2718 c046a42c-6fe2-441c-8c8c-71466251a162

c294fc58 04/24/2007 09:44 am j_mayer

Improve PowerPC 405 MMU model / share more code for other embedded targets
support.
Fix PowerPC 405 MSR mask.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2717 c046a42c-6fe2-441c-8c8c-71466251a162

8ecc7913 04/16/2007 11:09 pm j_mayer

Add callbacks to allow dynamic change of PowerPC clocks (to be improved)
Fix embedded PowerPC watchdog and timers
Fix PowerPC 405 SPR
Add generic PowerPC 405 core instanciation code + resets support.
Implement simple peripherals shared by most PowerPC 405 implementations...

c55e9aef 04/16/2007 12:21 pm j_mayer

PowerPC 4xx software driven TLB fixes + debug traces.
Add code provision for more MMU models support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2683 c046a42c-6fe2-441c-8c8c-71466251a162