Statistics
| Branch: | Revision:

root / target-ppc / translate.c @ 1dd9ffb9

History | View | Annotate | Download (300.2 kB)

1
/*
2
 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
19
 */
20
#include <stdarg.h>
21
#include <stdlib.h>
22
#include <stdio.h>
23
#include <string.h>
24
#include <inttypes.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
28
#include "disas.h"
29
#include "tcg-op.h"
30
#include "qemu-common.h"
31

    
32
#include "helper.h"
33
#define GEN_HELPER 1
34
#include "helper.h"
35

    
36
#define CPU_SINGLE_STEP 0x1
37
#define CPU_BRANCH_STEP 0x2
38
#define GDBSTUB_SINGLE_STEP 0x4
39

    
40
/* Include definitions for instructions classes and implementations flags */
41
//#define DO_SINGLE_STEP
42
//#define PPC_DEBUG_DISAS
43
//#define DO_PPC_STATISTICS
44

    
45
/*****************************************************************************/
46
/* Code translation helpers                                                  */
47

    
48
/* global register indexes */
49
static TCGv_ptr cpu_env;
50
static char cpu_reg_names[10*3 + 22*4 /* GPR */
51
#if !defined(TARGET_PPC64)
52
    + 10*4 + 22*5 /* SPE GPRh */
53
#endif
54
    + 10*4 + 22*5 /* FPR */
55
    + 2*(10*6 + 22*7) /* AVRh, AVRl */
56
    + 8*5 /* CRF */];
57
static TCGv cpu_gpr[32];
58
#if !defined(TARGET_PPC64)
59
static TCGv cpu_gprh[32];
60
#endif
61
static TCGv_i64 cpu_fpr[32];
62
static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
63
static TCGv_i32 cpu_crf[8];
64
static TCGv cpu_nip;
65
static TCGv cpu_msr;
66
static TCGv cpu_ctr;
67
static TCGv cpu_lr;
68
static TCGv cpu_xer;
69
static TCGv cpu_reserve;
70
static TCGv_i32 cpu_fpscr;
71
static TCGv_i32 cpu_access_type;
72

    
73
#include "gen-icount.h"
74

    
75
void ppc_translate_init(void)
76
{
77
    int i;
78
    char* p;
79
    static int done_init = 0;
80

    
81
    if (done_init)
82
        return;
83

    
84
    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
85

    
86
    p = cpu_reg_names;
87

    
88
    for (i = 0; i < 8; i++) {
89
        sprintf(p, "crf%d", i);
90
        cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
91
                                            offsetof(CPUState, crf[i]), p);
92
        p += 5;
93
    }
94

    
95
    for (i = 0; i < 32; i++) {
96
        sprintf(p, "r%d", i);
97
        cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
98
                                        offsetof(CPUState, gpr[i]), p);
99
        p += (i < 10) ? 3 : 4;
100
#if !defined(TARGET_PPC64)
101
        sprintf(p, "r%dH", i);
102
        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
103
                                             offsetof(CPUState, gprh[i]), p);
104
        p += (i < 10) ? 4 : 5;
105
#endif
106

    
107
        sprintf(p, "fp%d", i);
108
        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
109
                                            offsetof(CPUState, fpr[i]), p);
110
        p += (i < 10) ? 4 : 5;
111

    
112
        sprintf(p, "avr%dH", i);
113
#ifdef WORDS_BIGENDIAN
114
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
115
                                             offsetof(CPUState, avr[i].u64[0]), p);
116
#else
117
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
118
                                             offsetof(CPUState, avr[i].u64[1]), p);
119
#endif
120
        p += (i < 10) ? 6 : 7;
121

    
122
        sprintf(p, "avr%dL", i);
123
#ifdef WORDS_BIGENDIAN
124
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
125
                                             offsetof(CPUState, avr[i].u64[1]), p);
126
#else
127
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
128
                                             offsetof(CPUState, avr[i].u64[0]), p);
129
#endif
130
        p += (i < 10) ? 6 : 7;
131
    }
132

    
133
    cpu_nip = tcg_global_mem_new(TCG_AREG0,
134
                                 offsetof(CPUState, nip), "nip");
135

    
136
    cpu_msr = tcg_global_mem_new(TCG_AREG0,
137
                                 offsetof(CPUState, msr), "msr");
138

    
139
    cpu_ctr = tcg_global_mem_new(TCG_AREG0,
140
                                 offsetof(CPUState, ctr), "ctr");
141

    
142
    cpu_lr = tcg_global_mem_new(TCG_AREG0,
143
                                offsetof(CPUState, lr), "lr");
144

    
145
    cpu_xer = tcg_global_mem_new(TCG_AREG0,
146
                                 offsetof(CPUState, xer), "xer");
147

    
148
    cpu_reserve = tcg_global_mem_new(TCG_AREG0,
149
                                     offsetof(CPUState, reserve), "reserve");
150

    
151
    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
152
                                       offsetof(CPUState, fpscr), "fpscr");
153

    
154
    cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
155
                                             offsetof(CPUState, access_type), "access_type");
156

    
157
    /* register helpers */
158
#define GEN_HELPER 2
159
#include "helper.h"
160

    
161
    done_init = 1;
162
}
163

    
164
/* internal defines */
165
typedef struct DisasContext {
166
    struct TranslationBlock *tb;
167
    target_ulong nip;
168
    uint32_t opcode;
169
    uint32_t exception;
170
    /* Routine used to access memory */
171
    int mem_idx;
172
    int access_type;
173
    /* Translation flags */
174
    int le_mode;
175
#if defined(TARGET_PPC64)
176
    int sf_mode;
177
#endif
178
    int fpu_enabled;
179
    int altivec_enabled;
180
    int spe_enabled;
181
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
182
    int singlestep_enabled;
183
} DisasContext;
184

    
185
struct opc_handler_t {
186
    /* invalid bits */
187
    uint32_t inval;
188
    /* instruction type */
189
    uint64_t type;
190
    /* handler */
191
    void (*handler)(DisasContext *ctx);
192
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
193
    const char *oname;
194
#endif
195
#if defined(DO_PPC_STATISTICS)
196
    uint64_t count;
197
#endif
198
};
199

    
200
static always_inline void gen_reset_fpstatus (void)
201
{
202
#ifdef CONFIG_SOFTFLOAT
203
    gen_helper_reset_fpstatus();
204
#endif
205
}
206

    
207
static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
208
{
209
    TCGv_i32 t0 = tcg_temp_new_i32();
210

    
211
    if (set_fprf != 0) {
212
        /* This case might be optimized later */
213
        tcg_gen_movi_i32(t0, 1);
214
        gen_helper_compute_fprf(t0, arg, t0);
215
        if (unlikely(set_rc)) {
216
            tcg_gen_mov_i32(cpu_crf[1], t0);
217
        }
218
        gen_helper_float_check_status();
219
    } else if (unlikely(set_rc)) {
220
        /* We always need to compute fpcc */
221
        tcg_gen_movi_i32(t0, 0);
222
        gen_helper_compute_fprf(t0, arg, t0);
223
        tcg_gen_mov_i32(cpu_crf[1], t0);
224
    }
225

    
226
    tcg_temp_free_i32(t0);
227
}
228

    
229
static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
230
{
231
    if (ctx->access_type != access_type) {
232
        tcg_gen_movi_i32(cpu_access_type, access_type);
233
        ctx->access_type = access_type;
234
    }
235
}
236

    
237
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
238
{
239
#if defined(TARGET_PPC64)
240
    if (ctx->sf_mode)
241
        tcg_gen_movi_tl(cpu_nip, nip);
242
    else
243
#endif
244
        tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
245
}
246

    
247
static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
248
{
249
    TCGv_i32 t0, t1;
250
    if (ctx->exception == POWERPC_EXCP_NONE) {
251
        gen_update_nip(ctx, ctx->nip);
252
    }
253
    t0 = tcg_const_i32(excp);
254
    t1 = tcg_const_i32(error);
255
    gen_helper_raise_exception_err(t0, t1);
256
    tcg_temp_free_i32(t0);
257
    tcg_temp_free_i32(t1);
258
    ctx->exception = (excp);
259
}
260

    
261
static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
262
{
263
    TCGv_i32 t0;
264
    if (ctx->exception == POWERPC_EXCP_NONE) {
265
        gen_update_nip(ctx, ctx->nip);
266
    }
267
    t0 = tcg_const_i32(excp);
268
    gen_helper_raise_exception(t0);
269
    tcg_temp_free_i32(t0);
270
    ctx->exception = (excp);
271
}
272

    
273
static always_inline void gen_debug_exception (DisasContext *ctx)
274
{
275
    TCGv_i32 t0;
276
    gen_update_nip(ctx, ctx->nip);
277
    t0 = tcg_const_i32(EXCP_DEBUG);
278
    gen_helper_raise_exception(t0);
279
    tcg_temp_free_i32(t0);
280
}
281

    
282
static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
283
{
284
    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
285
}
286

    
287
/* Stop translation */
288
static always_inline void gen_stop_exception (DisasContext *ctx)
289
{
290
    gen_update_nip(ctx, ctx->nip);
291
    ctx->exception = POWERPC_EXCP_STOP;
292
}
293

    
294
/* No need to update nip here, as execution flow will change */
295
static always_inline void gen_sync_exception (DisasContext *ctx)
296
{
297
    ctx->exception = POWERPC_EXCP_SYNC;
298
}
299

    
300
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
301
static void gen_##name (DisasContext *ctx);                                   \
302
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
303
static void gen_##name (DisasContext *ctx)
304

    
305
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
306
static void gen_##name (DisasContext *ctx);                                   \
307
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
308
static void gen_##name (DisasContext *ctx)
309

    
310
typedef struct opcode_t {
311
    unsigned char opc1, opc2, opc3;
312
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
313
    unsigned char pad[5];
314
#else
315
    unsigned char pad[1];
316
#endif
317
    opc_handler_t handler;
318
    const char *oname;
319
} opcode_t;
320

    
321
/*****************************************************************************/
322
/***                           Instruction decoding                        ***/
323
#define EXTRACT_HELPER(name, shift, nb)                                       \
324
static always_inline uint32_t name (uint32_t opcode)                          \
325
{                                                                             \
326
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
327
}
328

    
329
#define EXTRACT_SHELPER(name, shift, nb)                                      \
330
static always_inline int32_t name (uint32_t opcode)                           \
331
{                                                                             \
332
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
333
}
334

    
335
/* Opcode part 1 */
336
EXTRACT_HELPER(opc1, 26, 6);
337
/* Opcode part 2 */
338
EXTRACT_HELPER(opc2, 1, 5);
339
/* Opcode part 3 */
340
EXTRACT_HELPER(opc3, 6, 5);
341
/* Update Cr0 flags */
342
EXTRACT_HELPER(Rc, 0, 1);
343
/* Destination */
344
EXTRACT_HELPER(rD, 21, 5);
345
/* Source */
346
EXTRACT_HELPER(rS, 21, 5);
347
/* First operand */
348
EXTRACT_HELPER(rA, 16, 5);
349
/* Second operand */
350
EXTRACT_HELPER(rB, 11, 5);
351
/* Third operand */
352
EXTRACT_HELPER(rC, 6, 5);
353
/***                               Get CRn                                 ***/
354
EXTRACT_HELPER(crfD, 23, 3);
355
EXTRACT_HELPER(crfS, 18, 3);
356
EXTRACT_HELPER(crbD, 21, 5);
357
EXTRACT_HELPER(crbA, 16, 5);
358
EXTRACT_HELPER(crbB, 11, 5);
359
/* SPR / TBL */
360
EXTRACT_HELPER(_SPR, 11, 10);
361
static always_inline uint32_t SPR (uint32_t opcode)
362
{
363
    uint32_t sprn = _SPR(opcode);
364

    
365
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
366
}
367
/***                              Get constants                            ***/
368
EXTRACT_HELPER(IMM, 12, 8);
369
/* 16 bits signed immediate value */
370
EXTRACT_SHELPER(SIMM, 0, 16);
371
/* 16 bits unsigned immediate value */
372
EXTRACT_HELPER(UIMM, 0, 16);
373
/* 5 bits signed immediate value */
374
EXTRACT_HELPER(SIMM5, 16, 5);
375
/* 5 bits signed immediate value */
376
EXTRACT_HELPER(UIMM5, 16, 5);
377
/* Bit count */
378
EXTRACT_HELPER(NB, 11, 5);
379
/* Shift count */
380
EXTRACT_HELPER(SH, 11, 5);
381
/* Vector shift count */
382
EXTRACT_HELPER(VSH, 6, 4);
383
/* Mask start */
384
EXTRACT_HELPER(MB, 6, 5);
385
/* Mask end */
386
EXTRACT_HELPER(ME, 1, 5);
387
/* Trap operand */
388
EXTRACT_HELPER(TO, 21, 5);
389

    
390
EXTRACT_HELPER(CRM, 12, 8);
391
EXTRACT_HELPER(FM, 17, 8);
392
EXTRACT_HELPER(SR, 16, 4);
393
EXTRACT_HELPER(FPIMM, 12, 4);
394

    
395
/***                            Jump target decoding                       ***/
396
/* Displacement */
397
EXTRACT_SHELPER(d, 0, 16);
398
/* Immediate address */
399
static always_inline target_ulong LI (uint32_t opcode)
400
{
401
    return (opcode >> 0) & 0x03FFFFFC;
402
}
403

    
404
static always_inline uint32_t BD (uint32_t opcode)
405
{
406
    return (opcode >> 0) & 0xFFFC;
407
}
408

    
409
EXTRACT_HELPER(BO, 21, 5);
410
EXTRACT_HELPER(BI, 16, 5);
411
/* Absolute/relative address */
412
EXTRACT_HELPER(AA, 1, 1);
413
/* Link */
414
EXTRACT_HELPER(LK, 0, 1);
415

    
416
/* Create a mask between <start> and <end> bits */
417
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
418
{
419
    target_ulong ret;
420

    
421
#if defined(TARGET_PPC64)
422
    if (likely(start == 0)) {
423
        ret = UINT64_MAX << (63 - end);
424
    } else if (likely(end == 63)) {
425
        ret = UINT64_MAX >> start;
426
    }
427
#else
428
    if (likely(start == 0)) {
429
        ret = UINT32_MAX << (31  - end);
430
    } else if (likely(end == 31)) {
431
        ret = UINT32_MAX >> start;
432
    }
433
#endif
434
    else {
435
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
436
            (((target_ulong)(-1ULL) >> (end)) >> 1);
437
        if (unlikely(start > end))
438
            return ~ret;
439
    }
440

    
441
    return ret;
442
}
443

    
444
/*****************************************************************************/
445
/* PowerPC Instructions types definitions                                    */
446
enum {
447
    PPC_NONE           = 0x0000000000000000ULL,
448
    /* PowerPC base instructions set                                         */
449
    PPC_INSNS_BASE     = 0x0000000000000001ULL,
450
    /*   integer operations instructions                                     */
451
#define PPC_INTEGER PPC_INSNS_BASE
452
    /*   flow control instructions                                           */
453
#define PPC_FLOW    PPC_INSNS_BASE
454
    /*   virtual memory instructions                                         */
455
#define PPC_MEM     PPC_INSNS_BASE
456
    /*   ld/st with reservation instructions                                 */
457
#define PPC_RES     PPC_INSNS_BASE
458
    /*   spr/msr access instructions                                         */
459
#define PPC_MISC    PPC_INSNS_BASE
460
    /* Deprecated instruction sets                                           */
461
    /*   Original POWER instruction set                                      */
462
    PPC_POWER          = 0x0000000000000002ULL,
463
    /*   POWER2 instruction set extension                                    */
464
    PPC_POWER2         = 0x0000000000000004ULL,
465
    /*   Power RTC support                                                   */
466
    PPC_POWER_RTC      = 0x0000000000000008ULL,
467
    /*   Power-to-PowerPC bridge (601)                                       */
468
    PPC_POWER_BR       = 0x0000000000000010ULL,
469
    /* 64 bits PowerPC instruction set                                       */
470
    PPC_64B            = 0x0000000000000020ULL,
471
    /*   New 64 bits extensions (PowerPC 2.0x)                               */
472
    PPC_64BX           = 0x0000000000000040ULL,
473
    /*   64 bits hypervisor extensions                                       */
474
    PPC_64H            = 0x0000000000000080ULL,
475
    /*   New wait instruction (PowerPC 2.0x)                                 */
476
    PPC_WAIT           = 0x0000000000000100ULL,
477
    /*   Time base mftb instruction                                          */
478
    PPC_MFTB           = 0x0000000000000200ULL,
479

    
480
    /* Fixed-point unit extensions                                           */
481
    /*   PowerPC 602 specific                                                */
482
    PPC_602_SPEC       = 0x0000000000000400ULL,
483
    /*   isel instruction                                                    */
484
    PPC_ISEL           = 0x0000000000000800ULL,
485
    /*   popcntb instruction                                                 */
486
    PPC_POPCNTB        = 0x0000000000001000ULL,
487
    /*   string load / store                                                 */
488
    PPC_STRING         = 0x0000000000002000ULL,
489

    
490
    /* Floating-point unit extensions                                        */
491
    /*   Optional floating point instructions                                */
492
    PPC_FLOAT          = 0x0000000000010000ULL,
493
    /* New floating-point extensions (PowerPC 2.0x)                          */
494
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
495
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
496
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
497
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
498
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
499
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
500
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
501

    
502
    /* Vector/SIMD extensions                                                */
503
    /*   Altivec support                                                     */
504
    PPC_ALTIVEC        = 0x0000000001000000ULL,
505
    /*   PowerPC 2.03 SPE extension                                          */
506
    PPC_SPE            = 0x0000000002000000ULL,
507
    /*   PowerPC 2.03 SPE floating-point extension                           */
508
    PPC_SPEFPU         = 0x0000000004000000ULL,
509

    
510
    /* Optional memory control instructions                                  */
511
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
512
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
513
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
514
    /*   sync instruction                                                    */
515
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
516
    /*   eieio instruction                                                   */
517
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
518

    
519
    /* Cache control instructions                                            */
520
    PPC_CACHE          = 0x0000000200000000ULL,
521
    /*   icbi instruction                                                    */
522
    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
523
    /*   dcbz instruction with fixed cache line size                         */
524
    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
525
    /*   dcbz instruction with tunable cache line size                       */
526
    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
527
    /*   dcba instruction                                                    */
528
    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
529
    /*   Freescale cache locking instructions                                */
530
    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
531

    
532
    /* MMU related extensions                                                */
533
    /*   external control instructions                                       */
534
    PPC_EXTERN         = 0x0000010000000000ULL,
535
    /*   segment register access instructions                                */
536
    PPC_SEGMENT        = 0x0000020000000000ULL,
537
    /*   PowerPC 6xx TLB management instructions                             */
538
    PPC_6xx_TLB        = 0x0000040000000000ULL,
539
    /* PowerPC 74xx TLB management instructions                              */
540
    PPC_74xx_TLB       = 0x0000080000000000ULL,
541
    /*   PowerPC 40x TLB management instructions                             */
542
    PPC_40x_TLB        = 0x0000100000000000ULL,
543
    /*   segment register access instructions for PowerPC 64 "bridge"        */
544
    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
545
    /*   SLB management                                                      */
546
    PPC_SLBI           = 0x0000400000000000ULL,
547

    
548
    /* Embedded PowerPC dedicated instructions                               */
549
    PPC_WRTEE          = 0x0001000000000000ULL,
550
    /* PowerPC 40x exception model                                           */
551
    PPC_40x_EXCP       = 0x0002000000000000ULL,
552
    /* PowerPC 405 Mac instructions                                          */
553
    PPC_405_MAC        = 0x0004000000000000ULL,
554
    /* PowerPC 440 specific instructions                                     */
555
    PPC_440_SPEC       = 0x0008000000000000ULL,
556
    /* BookE (embedded) PowerPC specification                                */
557
    PPC_BOOKE          = 0x0010000000000000ULL,
558
    /* mfapidi instruction                                                   */
559
    PPC_MFAPIDI        = 0x0020000000000000ULL,
560
    /* tlbiva instruction                                                    */
561
    PPC_TLBIVA         = 0x0040000000000000ULL,
562
    /* tlbivax instruction                                                   */
563
    PPC_TLBIVAX        = 0x0080000000000000ULL,
564
    /* PowerPC 4xx dedicated instructions                                    */
565
    PPC_4xx_COMMON     = 0x0100000000000000ULL,
566
    /* PowerPC 40x ibct instructions                                         */
567
    PPC_40x_ICBT       = 0x0200000000000000ULL,
568
    /* rfmci is not implemented in all BookE PowerPC                         */
569
    PPC_RFMCI          = 0x0400000000000000ULL,
570
    /* rfdi instruction                                                      */
571
    PPC_RFDI           = 0x0800000000000000ULL,
572
    /* DCR accesses                                                          */
573
    PPC_DCR            = 0x1000000000000000ULL,
574
    /* DCR extended accesse                                                  */
575
    PPC_DCRX           = 0x2000000000000000ULL,
576
    /* user-mode DCR access, implemented in PowerPC 460                      */
577
    PPC_DCRUX          = 0x4000000000000000ULL,
578
};
579

    
580
/*****************************************************************************/
581
/* PowerPC instructions table                                                */
582
#if HOST_LONG_BITS == 64
583
#define OPC_ALIGN 8
584
#else
585
#define OPC_ALIGN 4
586
#endif
587
#if defined(__APPLE__)
588
#define OPCODES_SECTION                                                       \
589
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
590
#else
591
#define OPCODES_SECTION                                                       \
592
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
593
#endif
594

    
595
#if defined(DO_PPC_STATISTICS)
596
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
597
OPCODES_SECTION opcode_t opc_##name = {                                       \
598
    .opc1 = op1,                                                              \
599
    .opc2 = op2,                                                              \
600
    .opc3 = op3,                                                              \
601
    .pad  = { 0, },                                                           \
602
    .handler = {                                                              \
603
        .inval   = invl,                                                      \
604
        .type = _typ,                                                         \
605
        .handler = &gen_##name,                                               \
606
        .oname = stringify(name),                                             \
607
    },                                                                        \
608
    .oname = stringify(name),                                                 \
609
}
610
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
611
OPCODES_SECTION opcode_t opc_##name = {                                       \
612
    .opc1 = op1,                                                              \
613
    .opc2 = op2,                                                              \
614
    .opc3 = op3,                                                              \
615
    .pad  = { 0, },                                                           \
616
    .handler = {                                                              \
617
        .inval   = invl,                                                      \
618
        .type = _typ,                                                         \
619
        .handler = &gen_##name,                                               \
620
        .oname = onam,                                                        \
621
    },                                                                        \
622
    .oname = onam,                                                            \
623
}
624
#else
625
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
626
OPCODES_SECTION opcode_t opc_##name = {                                       \
627
    .opc1 = op1,                                                              \
628
    .opc2 = op2,                                                              \
629
    .opc3 = op3,                                                              \
630
    .pad  = { 0, },                                                           \
631
    .handler = {                                                              \
632
        .inval   = invl,                                                      \
633
        .type = _typ,                                                         \
634
        .handler = &gen_##name,                                               \
635
    },                                                                        \
636
    .oname = stringify(name),                                                 \
637
}
638
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
639
OPCODES_SECTION opcode_t opc_##name = {                                       \
640
    .opc1 = op1,                                                              \
641
    .opc2 = op2,                                                              \
642
    .opc3 = op3,                                                              \
643
    .pad  = { 0, },                                                           \
644
    .handler = {                                                              \
645
        .inval   = invl,                                                      \
646
        .type = _typ,                                                         \
647
        .handler = &gen_##name,                                               \
648
    },                                                                        \
649
    .oname = onam,                                                            \
650
}
651
#endif
652

    
653
#define GEN_OPCODE_MARK(name)                                                 \
654
OPCODES_SECTION opcode_t opc_##name = {                                       \
655
    .opc1 = 0xFF,                                                             \
656
    .opc2 = 0xFF,                                                             \
657
    .opc3 = 0xFF,                                                             \
658
    .pad  = { 0, },                                                           \
659
    .handler = {                                                              \
660
        .inval   = 0x00000000,                                                \
661
        .type = 0x00,                                                         \
662
        .handler = NULL,                                                      \
663
    },                                                                        \
664
    .oname = stringify(name),                                                 \
665
}
666

    
667
/* SPR load/store helpers */
668
static always_inline void gen_load_spr(TCGv t, int reg)
669
{
670
    tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
671
}
672

    
673
static always_inline void gen_store_spr(int reg, TCGv t)
674
{
675
    tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
676
}
677

    
678
/* Start opcode list */
679
GEN_OPCODE_MARK(start);
680

    
681
/* Invalid instruction */
682
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
683
{
684
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
685
}
686

    
687
static opc_handler_t invalid_handler = {
688
    .inval   = 0xFFFFFFFF,
689
    .type    = PPC_NONE,
690
    .handler = gen_invalid,
691
};
692

    
693
/***                           Integer comparison                          ***/
694

    
695
static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
696
{
697
    int l1, l2, l3;
698

    
699
    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
700
    tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
701
    tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
702

    
703
    l1 = gen_new_label();
704
    l2 = gen_new_label();
705
    l3 = gen_new_label();
706
    if (s) {
707
        tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
708
        tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
709
    } else {
710
        tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
711
        tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
712
    }
713
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
714
    tcg_gen_br(l3);
715
    gen_set_label(l1);
716
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
717
    tcg_gen_br(l3);
718
    gen_set_label(l2);
719
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
720
    gen_set_label(l3);
721
}
722

    
723
static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
724
{
725
    TCGv t0 = tcg_const_local_tl(arg1);
726
    gen_op_cmp(arg0, t0, s, crf);
727
    tcg_temp_free(t0);
728
}
729

    
730
#if defined(TARGET_PPC64)
731
static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
732
{
733
    TCGv t0, t1;
734
    t0 = tcg_temp_local_new();
735
    t1 = tcg_temp_local_new();
736
    if (s) {
737
        tcg_gen_ext32s_tl(t0, arg0);
738
        tcg_gen_ext32s_tl(t1, arg1);
739
    } else {
740
        tcg_gen_ext32u_tl(t0, arg0);
741
        tcg_gen_ext32u_tl(t1, arg1);
742
    }
743
    gen_op_cmp(t0, t1, s, crf);
744
    tcg_temp_free(t1);
745
    tcg_temp_free(t0);
746
}
747

    
748
static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
749
{
750
    TCGv t0 = tcg_const_local_tl(arg1);
751
    gen_op_cmp32(arg0, t0, s, crf);
752
    tcg_temp_free(t0);
753
}
754
#endif
755

    
756
static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
757
{
758
#if defined(TARGET_PPC64)
759
    if (!(ctx->sf_mode))
760
        gen_op_cmpi32(reg, 0, 1, 0);
761
    else
762
#endif
763
        gen_op_cmpi(reg, 0, 1, 0);
764
}
765

    
766
/* cmp */
767
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
768
{
769
#if defined(TARGET_PPC64)
770
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
771
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
772
                     1, crfD(ctx->opcode));
773
    else
774
#endif
775
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
776
                   1, crfD(ctx->opcode));
777
}
778

    
779
/* cmpi */
780
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
781
{
782
#if defined(TARGET_PPC64)
783
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
784
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
785
                      1, crfD(ctx->opcode));
786
    else
787
#endif
788
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
789
                    1, crfD(ctx->opcode));
790
}
791

    
792
/* cmpl */
793
GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
794
{
795
#if defined(TARGET_PPC64)
796
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
797
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
798
                     0, crfD(ctx->opcode));
799
    else
800
#endif
801
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
802
                   0, crfD(ctx->opcode));
803
}
804

    
805
/* cmpli */
806
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
807
{
808
#if defined(TARGET_PPC64)
809
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
810
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
811
                      0, crfD(ctx->opcode));
812
    else
813
#endif
814
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
815
                    0, crfD(ctx->opcode));
816
}
817

    
818
/* isel (PowerPC 2.03 specification) */
819
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
820
{
821
    int l1, l2;
822
    uint32_t bi = rC(ctx->opcode);
823
    uint32_t mask;
824
    TCGv_i32 t0;
825

    
826
    l1 = gen_new_label();
827
    l2 = gen_new_label();
828

    
829
    mask = 1 << (3 - (bi & 0x03));
830
    t0 = tcg_temp_new_i32();
831
    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
832
    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
833
    if (rA(ctx->opcode) == 0)
834
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
835
    else
836
        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
837
    tcg_gen_br(l2);
838
    gen_set_label(l1);
839
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
840
    gen_set_label(l2);
841
    tcg_temp_free_i32(t0);
842
}
843

    
844
/***                           Integer arithmetic                          ***/
845

    
846
static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
847
{
848
    int l1;
849
    TCGv t0;
850

    
851
    l1 = gen_new_label();
852
    /* Start with XER OV disabled, the most likely case */
853
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
854
    t0 = tcg_temp_local_new();
855
    tcg_gen_xor_tl(t0, arg0, arg1);
856
#if defined(TARGET_PPC64)
857
    if (!ctx->sf_mode)
858
        tcg_gen_ext32s_tl(t0, t0);
859
#endif
860
    if (sub)
861
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
862
    else
863
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
864
    tcg_gen_xor_tl(t0, arg1, arg2);
865
#if defined(TARGET_PPC64)
866
    if (!ctx->sf_mode)
867
        tcg_gen_ext32s_tl(t0, t0);
868
#endif
869
    if (sub)
870
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
871
    else
872
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
873
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
874
    gen_set_label(l1);
875
    tcg_temp_free(t0);
876
}
877

    
878
static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
879
{
880
    int l1 = gen_new_label();
881

    
882
#if defined(TARGET_PPC64)
883
    if (!(ctx->sf_mode)) {
884
        TCGv t0, t1;
885
        t0 = tcg_temp_new();
886
        t1 = tcg_temp_new();
887

    
888
        tcg_gen_ext32u_tl(t0, arg1);
889
        tcg_gen_ext32u_tl(t1, arg2);
890
        if (sub) {
891
            tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
892
        } else {
893
            tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
894
        }
895
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
896
        gen_set_label(l1);
897
        tcg_temp_free(t0);
898
        tcg_temp_free(t1);
899
    } else
900
#endif
901
    {
902
        if (sub) {
903
            tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
904
        } else {
905
            tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
906
        }
907
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
908
        gen_set_label(l1);
909
    }
910
}
911

    
912
/* Common add function */
913
static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
914
                                           int add_ca, int compute_ca, int compute_ov)
915
{
916
    TCGv t0, t1;
917

    
918
    if ((!compute_ca && !compute_ov) ||
919
        (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2)))  {
920
        t0 = ret;
921
    } else {
922
        t0 = tcg_temp_local_new();
923
    }
924

    
925
    if (add_ca) {
926
        t1 = tcg_temp_local_new();
927
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
928
        tcg_gen_shri_tl(t1, t1, XER_CA);
929
    }
930

    
931
    if (compute_ca && compute_ov) {
932
        /* Start with XER CA and OV disabled, the most likely case */
933
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
934
    } else if (compute_ca) {
935
        /* Start with XER CA disabled, the most likely case */
936
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
937
    } else if (compute_ov) {
938
        /* Start with XER OV disabled, the most likely case */
939
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
940
    }
941

    
942
    tcg_gen_add_tl(t0, arg1, arg2);
943

    
944
    if (compute_ca) {
945
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
946
    }
947
    if (add_ca) {
948
        tcg_gen_add_tl(t0, t0, t1);
949
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
950
        tcg_temp_free(t1);
951
    }
952
    if (compute_ov) {
953
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
954
    }
955

    
956
    if (unlikely(Rc(ctx->opcode) != 0))
957
        gen_set_Rc0(ctx, t0);
958

    
959
    if (!TCGV_EQUAL(t0, ret)) {
960
        tcg_gen_mov_tl(ret, t0);
961
        tcg_temp_free(t0);
962
    }
963
}
964
/* Add functions with two operands */
965
#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
966
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER)                  \
967
{                                                                             \
968
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
969
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
970
                     add_ca, compute_ca, compute_ov);                         \
971
}
972
/* Add functions with one operand and one immediate */
973
#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
974
                                add_ca, compute_ca, compute_ov)               \
975
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER)                  \
976
{                                                                             \
977
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
978
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
979
                     cpu_gpr[rA(ctx->opcode)], t0,                            \
980
                     add_ca, compute_ca, compute_ov);                         \
981
    tcg_temp_free(t0);                                                        \
982
}
983

    
984
/* add  add.  addo  addo. */
985
GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
986
GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
987
/* addc  addc.  addco  addco. */
988
GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
989
GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
990
/* adde  adde.  addeo  addeo. */
991
GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
992
GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
993
/* addme  addme.  addmeo  addmeo.  */
994
GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
995
GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
996
/* addze  addze.  addzeo  addzeo.*/
997
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
998
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
999
/* addi */
1000
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1001
{
1002
    target_long simm = SIMM(ctx->opcode);
1003

    
1004
    if (rA(ctx->opcode) == 0) {
1005
        /* li case */
1006
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1007
    } else {
1008
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1009
    }
1010
}
1011
/* addic  addic.*/
1012
static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1013
                                        int compute_Rc0)
1014
{
1015
    target_long simm = SIMM(ctx->opcode);
1016

    
1017
    /* Start with XER CA and OV disabled, the most likely case */
1018
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1019

    
1020
    if (likely(simm != 0)) {
1021
        TCGv t0 = tcg_temp_local_new();
1022
        tcg_gen_addi_tl(t0, arg1, simm);
1023
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1024
        tcg_gen_mov_tl(ret, t0);
1025
        tcg_temp_free(t0);
1026
    } else {
1027
        tcg_gen_mov_tl(ret, arg1);
1028
    }
1029
    if (compute_Rc0) {
1030
        gen_set_Rc0(ctx, ret);
1031
    }
1032
}
1033
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1034
{
1035
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1036
}
1037
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1038
{
1039
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1040
}
1041
/* addis */
1042
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1043
{
1044
    target_long simm = SIMM(ctx->opcode);
1045

    
1046
    if (rA(ctx->opcode) == 0) {
1047
        /* lis case */
1048
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1049
    } else {
1050
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1051
    }
1052
}
1053

    
1054
static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1055
                                             int sign, int compute_ov)
1056
{
1057
    int l1 = gen_new_label();
1058
    int l2 = gen_new_label();
1059
    TCGv_i32 t0 = tcg_temp_local_new_i32();
1060
    TCGv_i32 t1 = tcg_temp_local_new_i32();
1061

    
1062
    tcg_gen_trunc_tl_i32(t0, arg1);
1063
    tcg_gen_trunc_tl_i32(t1, arg2);
1064
    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1065
    if (sign) {
1066
        int l3 = gen_new_label();
1067
        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1068
        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1069
        gen_set_label(l3);
1070
        tcg_gen_div_i32(t0, t0, t1);
1071
    } else {
1072
        tcg_gen_divu_i32(t0, t0, t1);
1073
    }
1074
    if (compute_ov) {
1075
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1076
    }
1077
    tcg_gen_br(l2);
1078
    gen_set_label(l1);
1079
    if (sign) {
1080
        tcg_gen_sari_i32(t0, t0, 31);
1081
    } else {
1082
        tcg_gen_movi_i32(t0, 0);
1083
    }
1084
    if (compute_ov) {
1085
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1086
    }
1087
    gen_set_label(l2);
1088
    tcg_gen_extu_i32_tl(ret, t0);
1089
    tcg_temp_free_i32(t0);
1090
    tcg_temp_free_i32(t1);
1091
    if (unlikely(Rc(ctx->opcode) != 0))
1092
        gen_set_Rc0(ctx, ret);
1093
}
1094
/* Div functions */
1095
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
1096
GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)                  \
1097
{                                                                             \
1098
    gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1099
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1100
                     sign, compute_ov);                                       \
1101
}
1102
/* divwu  divwu.  divwuo  divwuo.   */
1103
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1104
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1105
/* divw  divw.  divwo  divwo.   */
1106
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1107
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1108
#if defined(TARGET_PPC64)
1109
static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1110
                                             int sign, int compute_ov)
1111
{
1112
    int l1 = gen_new_label();
1113
    int l2 = gen_new_label();
1114

    
1115
    tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1116
    if (sign) {
1117
        int l3 = gen_new_label();
1118
        tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1119
        tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1120
        gen_set_label(l3);
1121
        tcg_gen_div_i64(ret, arg1, arg2);
1122
    } else {
1123
        tcg_gen_divu_i64(ret, arg1, arg2);
1124
    }
1125
    if (compute_ov) {
1126
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1127
    }
1128
    tcg_gen_br(l2);
1129
    gen_set_label(l1);
1130
    if (sign) {
1131
        tcg_gen_sari_i64(ret, arg1, 63);
1132
    } else {
1133
        tcg_gen_movi_i64(ret, 0);
1134
    }
1135
    if (compute_ov) {
1136
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1137
    }
1138
    gen_set_label(l2);
1139
    if (unlikely(Rc(ctx->opcode) != 0))
1140
        gen_set_Rc0(ctx, ret);
1141
}
1142
#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
1143
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)                      \
1144
{                                                                             \
1145
    gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1146
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1147
                      sign, compute_ov);                                      \
1148
}
1149
/* divwu  divwu.  divwuo  divwuo.   */
1150
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1151
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1152
/* divw  divw.  divwo  divwo.   */
1153
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1154
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1155
#endif
1156

    
1157
/* mulhw  mulhw. */
1158
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1159
{
1160
    TCGv_i64 t0, t1;
1161

    
1162
    t0 = tcg_temp_new_i64();
1163
    t1 = tcg_temp_new_i64();
1164
#if defined(TARGET_PPC64)
1165
    tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1166
    tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1167
    tcg_gen_mul_i64(t0, t0, t1);
1168
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1169
#else
1170
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1171
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1172
    tcg_gen_mul_i64(t0, t0, t1);
1173
    tcg_gen_shri_i64(t0, t0, 32);
1174
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1175
#endif
1176
    tcg_temp_free_i64(t0);
1177
    tcg_temp_free_i64(t1);
1178
    if (unlikely(Rc(ctx->opcode) != 0))
1179
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1180
}
1181
/* mulhwu  mulhwu.  */
1182
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1183
{
1184
    TCGv_i64 t0, t1;
1185

    
1186
    t0 = tcg_temp_new_i64();
1187
    t1 = tcg_temp_new_i64();
1188
#if defined(TARGET_PPC64)
1189
    tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1190
    tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1191
    tcg_gen_mul_i64(t0, t0, t1);
1192
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1193
#else
1194
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1195
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1196
    tcg_gen_mul_i64(t0, t0, t1);
1197
    tcg_gen_shri_i64(t0, t0, 32);
1198
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1199
#endif
1200
    tcg_temp_free_i64(t0);
1201
    tcg_temp_free_i64(t1);
1202
    if (unlikely(Rc(ctx->opcode) != 0))
1203
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1204
}
1205
/* mullw  mullw. */
1206
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1207
{
1208
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1209
                   cpu_gpr[rB(ctx->opcode)]);
1210
    tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1211
    if (unlikely(Rc(ctx->opcode) != 0))
1212
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213
}
1214
/* mullwo  mullwo. */
1215
GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1216
{
1217
    int l1;
1218
    TCGv_i64 t0, t1;
1219

    
1220
    t0 = tcg_temp_new_i64();
1221
    t1 = tcg_temp_new_i64();
1222
    l1 = gen_new_label();
1223
    /* Start with XER OV disabled, the most likely case */
1224
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1225
#if defined(TARGET_PPC64)
1226
    tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1227
    tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1228
#else
1229
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1230
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1231
#endif
1232
    tcg_gen_mul_i64(t0, t0, t1);
1233
#if defined(TARGET_PPC64)
1234
    tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1235
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1236
#else
1237
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1238
    tcg_gen_ext32s_i64(t1, t0);
1239
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1240
#endif
1241
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1242
    gen_set_label(l1);
1243
    tcg_temp_free_i64(t0);
1244
    tcg_temp_free_i64(t1);
1245
    if (unlikely(Rc(ctx->opcode) != 0))
1246
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1247
}
1248
/* mulli */
1249
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1250
{
1251
    tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1252
                    SIMM(ctx->opcode));
1253
}
1254
#if defined(TARGET_PPC64)
1255
#define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
1256
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)                      \
1257
{                                                                             \
1258
    gen_helper_##name (cpu_gpr[rD(ctx->opcode)],                              \
1259
                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);   \
1260
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1261
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1262
}
1263
/* mulhd  mulhd. */
1264
GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1265
/* mulhdu  mulhdu. */
1266
GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1267
/* mulld  mulld. */
1268
GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1269
{
1270
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1271
                   cpu_gpr[rB(ctx->opcode)]);
1272
    if (unlikely(Rc(ctx->opcode) != 0))
1273
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1274
}
1275
/* mulldo  mulldo. */
1276
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1277
#endif
1278

    
1279
/* neg neg. nego nego. */
1280
static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1281
{
1282
    int l1 = gen_new_label();
1283
    int l2 = gen_new_label();
1284
    TCGv t0 = tcg_temp_local_new();
1285
#if defined(TARGET_PPC64)
1286
    if (ctx->sf_mode) {
1287
        tcg_gen_mov_tl(t0, arg1);
1288
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1289
    } else
1290
#endif
1291
    {
1292
        tcg_gen_ext32s_tl(t0, arg1);
1293
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1294
    }
1295
    tcg_gen_neg_tl(ret, arg1);
1296
    if (ov_check) {
1297
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1298
    }
1299
    tcg_gen_br(l2);
1300
    gen_set_label(l1);
1301
    tcg_gen_mov_tl(ret, t0);
1302
    if (ov_check) {
1303
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1304
    }
1305
    gen_set_label(l2);
1306
    tcg_temp_free(t0);
1307
    if (unlikely(Rc(ctx->opcode) != 0))
1308
        gen_set_Rc0(ctx, ret);
1309
}
1310
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1311
{
1312
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1313
}
1314
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1315
{
1316
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1317
}
1318

    
1319
/* Common subf function */
1320
static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1321
                                            int add_ca, int compute_ca, int compute_ov)
1322
{
1323
    TCGv t0, t1;
1324

    
1325
    if ((!compute_ca && !compute_ov) ||
1326
        (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2)))  {
1327
        t0 = ret;
1328
    } else {
1329
        t0 = tcg_temp_local_new();
1330
    }
1331

    
1332
    if (add_ca) {
1333
        t1 = tcg_temp_local_new();
1334
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1335
        tcg_gen_shri_tl(t1, t1, XER_CA);
1336
    }
1337

    
1338
    if (compute_ca && compute_ov) {
1339
        /* Start with XER CA and OV disabled, the most likely case */
1340
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1341
    } else if (compute_ca) {
1342
        /* Start with XER CA disabled, the most likely case */
1343
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1344
    } else if (compute_ov) {
1345
        /* Start with XER OV disabled, the most likely case */
1346
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1347
    }
1348

    
1349
    if (add_ca) {
1350
        tcg_gen_not_tl(t0, arg1);
1351
        tcg_gen_add_tl(t0, t0, arg2);
1352
        gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1353
        tcg_gen_add_tl(t0, t0, t1);
1354
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
1355
        tcg_temp_free(t1);
1356
    } else {
1357
        tcg_gen_sub_tl(t0, arg2, arg1);
1358
        if (compute_ca) {
1359
            gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1360
        }
1361
    }
1362
    if (compute_ov) {
1363
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1364
    }
1365

    
1366
    if (unlikely(Rc(ctx->opcode) != 0))
1367
        gen_set_Rc0(ctx, t0);
1368

    
1369
    if (!TCGV_EQUAL(t0, ret)) {
1370
        tcg_gen_mov_tl(ret, t0);
1371
        tcg_temp_free(t0);
1372
    }
1373
}
1374
/* Sub functions with Two operands functions */
1375
#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
1376
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER)                  \
1377
{                                                                             \
1378
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1379
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1380
                      add_ca, compute_ca, compute_ov);                        \
1381
}
1382
/* Sub functions with one operand and one immediate */
1383
#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
1384
                                add_ca, compute_ca, compute_ov)               \
1385
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER)                  \
1386
{                                                                             \
1387
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
1388
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1389
                      cpu_gpr[rA(ctx->opcode)], t0,                           \
1390
                      add_ca, compute_ca, compute_ov);                        \
1391
    tcg_temp_free(t0);                                                        \
1392
}
1393
/* subf  subf.  subfo  subfo. */
1394
GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1395
GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1396
/* subfc  subfc.  subfco  subfco. */
1397
GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1398
GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1399
/* subfe  subfe.  subfeo  subfo. */
1400
GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1401
GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1402
/* subfme  subfme.  subfmeo  subfmeo.  */
1403
GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1404
GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1405
/* subfze  subfze.  subfzeo  subfzeo.*/
1406
GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1407
GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1408
/* subfic */
1409
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1410
{
1411
    /* Start with XER CA and OV disabled, the most likely case */
1412
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1413
    TCGv t0 = tcg_temp_local_new();
1414
    TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1415
    tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1416
    gen_op_arith_compute_ca(ctx, t0, t1, 1);
1417
    tcg_temp_free(t1);
1418
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1419
    tcg_temp_free(t0);
1420
}
1421

    
1422
/***                            Integer logical                            ***/
1423
#define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
1424
GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)                          \
1425
{                                                                             \
1426
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
1427
       cpu_gpr[rB(ctx->opcode)]);                                             \
1428
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1429
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1430
}
1431

    
1432
#define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
1433
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
1434
{                                                                             \
1435
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
1436
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1437
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1438
}
1439

    
1440
/* and & and. */
1441
GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1442
/* andc & andc. */
1443
GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1444
/* andi. */
1445
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1446
{
1447
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1448
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1449
}
1450
/* andis. */
1451
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1452
{
1453
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1454
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1455
}
1456
/* cntlzw */
1457
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1458
{
1459
    gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460
    if (unlikely(Rc(ctx->opcode) != 0))
1461
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1462
}
1463
/* eqv & eqv. */
1464
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1465
/* extsb & extsb. */
1466
GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1467
/* extsh & extsh. */
1468
GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1469
/* nand & nand. */
1470
GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1471
/* nor & nor. */
1472
GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1473
/* or & or. */
1474
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1475
{
1476
    int rs, ra, rb;
1477

    
1478
    rs = rS(ctx->opcode);
1479
    ra = rA(ctx->opcode);
1480
    rb = rB(ctx->opcode);
1481
    /* Optimisation for mr. ri case */
1482
    if (rs != ra || rs != rb) {
1483
        if (rs != rb)
1484
            tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1485
        else
1486
            tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1487
        if (unlikely(Rc(ctx->opcode) != 0))
1488
            gen_set_Rc0(ctx, cpu_gpr[ra]);
1489
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1490
        gen_set_Rc0(ctx, cpu_gpr[rs]);
1491
#if defined(TARGET_PPC64)
1492
    } else {
1493
        int prio = 0;
1494

    
1495
        switch (rs) {
1496
        case 1:
1497
            /* Set process priority to low */
1498
            prio = 2;
1499
            break;
1500
        case 6:
1501
            /* Set process priority to medium-low */
1502
            prio = 3;
1503
            break;
1504
        case 2:
1505
            /* Set process priority to normal */
1506
            prio = 4;
1507
            break;
1508
#if !defined(CONFIG_USER_ONLY)
1509
        case 31:
1510
            if (ctx->mem_idx > 0) {
1511
                /* Set process priority to very low */
1512
                prio = 1;
1513
            }
1514
            break;
1515
        case 5:
1516
            if (ctx->mem_idx > 0) {
1517
                /* Set process priority to medium-hight */
1518
                prio = 5;
1519
            }
1520
            break;
1521
        case 3:
1522
            if (ctx->mem_idx > 0) {
1523
                /* Set process priority to high */
1524
                prio = 6;
1525
            }
1526
            break;
1527
        case 7:
1528
            if (ctx->mem_idx > 1) {
1529
                /* Set process priority to very high */
1530
                prio = 7;
1531
            }
1532
            break;
1533
#endif
1534
        default:
1535
            /* nop */
1536
            break;
1537
        }
1538
        if (prio) {
1539
            TCGv t0 = tcg_temp_new();
1540
            gen_load_spr(t0, SPR_PPR);
1541
            tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1542
            tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1543
            gen_store_spr(SPR_PPR, t0);
1544
            tcg_temp_free(t0);
1545
        }
1546
#endif
1547
    }
1548
}
1549
/* orc & orc. */
1550
GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1551
/* xor & xor. */
1552
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1553
{
1554
    /* Optimisation for "set to zero" case */
1555
    if (rS(ctx->opcode) != rB(ctx->opcode))
1556
        tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1557
    else
1558
        tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1559
    if (unlikely(Rc(ctx->opcode) != 0))
1560
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1561
}
1562
/* ori */
1563
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1564
{
1565
    target_ulong uimm = UIMM(ctx->opcode);
1566

    
1567
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1568
        /* NOP */
1569
        /* XXX: should handle special NOPs for POWER series */
1570
        return;
1571
    }
1572
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1573
}
1574
/* oris */
1575
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1576
{
1577
    target_ulong uimm = UIMM(ctx->opcode);
1578

    
1579
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1580
        /* NOP */
1581
        return;
1582
    }
1583
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1584
}
1585
/* xori */
1586
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1587
{
1588
    target_ulong uimm = UIMM(ctx->opcode);
1589

    
1590
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1591
        /* NOP */
1592
        return;
1593
    }
1594
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1595
}
1596
/* xoris */
1597
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1598
{
1599
    target_ulong uimm = UIMM(ctx->opcode);
1600

    
1601
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1602
        /* NOP */
1603
        return;
1604
    }
1605
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1606
}
1607
/* popcntb : PowerPC 2.03 specification */
1608
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1609
{
1610
#if defined(TARGET_PPC64)
1611
    if (ctx->sf_mode)
1612
        gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1613
    else
1614
#endif
1615
        gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1616
}
1617

    
1618
#if defined(TARGET_PPC64)
1619
/* extsw & extsw. */
1620
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1621
/* cntlzd */
1622
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1623
{
1624
    gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1625
    if (unlikely(Rc(ctx->opcode) != 0))
1626
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1627
}
1628
#endif
1629

    
1630
/***                             Integer rotate                            ***/
1631
/* rlwimi & rlwimi. */
1632
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1633
{
1634
    uint32_t mb, me, sh;
1635

    
1636
    mb = MB(ctx->opcode);
1637
    me = ME(ctx->opcode);
1638
    sh = SH(ctx->opcode);
1639
    if (likely(sh == 0 && mb == 0 && me == 31)) {
1640
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1641
    } else {
1642
        target_ulong mask;
1643
        TCGv t1;
1644
        TCGv t0 = tcg_temp_new();
1645
#if defined(TARGET_PPC64)
1646
        TCGv_i32 t2 = tcg_temp_new_i32();
1647
        tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1648
        tcg_gen_rotli_i32(t2, t2, sh);
1649
        tcg_gen_extu_i32_i64(t0, t2);
1650
        tcg_temp_free_i32(t2);
1651
#else
1652
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1653
#endif
1654
#if defined(TARGET_PPC64)
1655
        mb += 32;
1656
        me += 32;
1657
#endif
1658
        mask = MASK(mb, me);
1659
        t1 = tcg_temp_new();
1660
        tcg_gen_andi_tl(t0, t0, mask);
1661
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1662
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1663
        tcg_temp_free(t0);
1664
        tcg_temp_free(t1);
1665
    }
1666
    if (unlikely(Rc(ctx->opcode) != 0))
1667
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1668
}
1669
/* rlwinm & rlwinm. */
1670
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1671
{
1672
    uint32_t mb, me, sh;
1673

    
1674
    sh = SH(ctx->opcode);
1675
    mb = MB(ctx->opcode);
1676
    me = ME(ctx->opcode);
1677

    
1678
    if (likely(mb == 0 && me == (31 - sh))) {
1679
        if (likely(sh == 0)) {
1680
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1681
        } else {
1682
            TCGv t0 = tcg_temp_new();
1683
            tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1684
            tcg_gen_shli_tl(t0, t0, sh);
1685
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686
            tcg_temp_free(t0);
1687
        }
1688
    } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1689
        TCGv t0 = tcg_temp_new();
1690
        tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1691
        tcg_gen_shri_tl(t0, t0, mb);
1692
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1693
        tcg_temp_free(t0);
1694
    } else {
1695
        TCGv t0 = tcg_temp_new();
1696
#if defined(TARGET_PPC64)
1697
        TCGv_i32 t1 = tcg_temp_new_i32();
1698
        tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1699
        tcg_gen_rotli_i32(t1, t1, sh);
1700
        tcg_gen_extu_i32_i64(t0, t1);
1701
        tcg_temp_free_i32(t1);
1702
#else
1703
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1704
#endif
1705
#if defined(TARGET_PPC64)
1706
        mb += 32;
1707
        me += 32;
1708
#endif
1709
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1710
        tcg_temp_free(t0);
1711
    }
1712
    if (unlikely(Rc(ctx->opcode) != 0))
1713
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1714
}
1715
/* rlwnm & rlwnm. */
1716
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1717
{
1718
    uint32_t mb, me;
1719
    TCGv t0;
1720
#if defined(TARGET_PPC64)
1721
    TCGv_i32 t1, t2;
1722
#endif
1723

    
1724
    mb = MB(ctx->opcode);
1725
    me = ME(ctx->opcode);
1726
    t0 = tcg_temp_new();
1727
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1728
#if defined(TARGET_PPC64)
1729
    t1 = tcg_temp_new_i32();
1730
    t2 = tcg_temp_new_i32();
1731
    tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1732
    tcg_gen_trunc_i64_i32(t2, t0);
1733
    tcg_gen_rotl_i32(t1, t1, t2);
1734
    tcg_gen_extu_i32_i64(t0, t1);
1735
    tcg_temp_free_i32(t1);
1736
    tcg_temp_free_i32(t2);
1737
#else
1738
    tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1739
#endif
1740
    if (unlikely(mb != 0 || me != 31)) {
1741
#if defined(TARGET_PPC64)
1742
        mb += 32;
1743
        me += 32;
1744
#endif
1745
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746
    } else {
1747
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1748
    }
1749
    tcg_temp_free(t0);
1750
    if (unlikely(Rc(ctx->opcode) != 0))
1751
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1752
}
1753

    
1754
#if defined(TARGET_PPC64)
1755
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1756
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1757
{                                                                             \
1758
    gen_##name(ctx, 0);                                                       \
1759
}                                                                             \
1760
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1761
             PPC_64B)                                                         \
1762
{                                                                             \
1763
    gen_##name(ctx, 1);                                                       \
1764
}
1765
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1766
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1767
{                                                                             \
1768
    gen_##name(ctx, 0, 0);                                                    \
1769
}                                                                             \
1770
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
1771
             PPC_64B)                                                         \
1772
{                                                                             \
1773
    gen_##name(ctx, 0, 1);                                                    \
1774
}                                                                             \
1775
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1776
             PPC_64B)                                                         \
1777
{                                                                             \
1778
    gen_##name(ctx, 1, 0);                                                    \
1779
}                                                                             \
1780
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
1781
             PPC_64B)                                                         \
1782
{                                                                             \
1783
    gen_##name(ctx, 1, 1);                                                    \
1784
}
1785

    
1786
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1787
                                      uint32_t me, uint32_t sh)
1788
{
1789
    if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1790
        tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1791
    } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1792
        tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1793
    } else {
1794
        TCGv t0 = tcg_temp_new();
1795
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1796
        if (likely(mb == 0 && me == 63)) {
1797
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1798
        } else {
1799
            tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1800
        }
1801
        tcg_temp_free(t0);
1802
    }
1803
    if (unlikely(Rc(ctx->opcode) != 0))
1804
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1805
}
1806
/* rldicl - rldicl. */
1807
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1808
{
1809
    uint32_t sh, mb;
1810

    
1811
    sh = SH(ctx->opcode) | (shn << 5);
1812
    mb = MB(ctx->opcode) | (mbn << 5);
1813
    gen_rldinm(ctx, mb, 63, sh);
1814
}
1815
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1816
/* rldicr - rldicr. */
1817
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1818
{
1819
    uint32_t sh, me;
1820

    
1821
    sh = SH(ctx->opcode) | (shn << 5);
1822
    me = MB(ctx->opcode) | (men << 5);
1823
    gen_rldinm(ctx, 0, me, sh);
1824
}
1825
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1826
/* rldic - rldic. */
1827
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1828
{
1829
    uint32_t sh, mb;
1830

    
1831
    sh = SH(ctx->opcode) | (shn << 5);
1832
    mb = MB(ctx->opcode) | (mbn << 5);
1833
    gen_rldinm(ctx, mb, 63 - sh, sh);
1834
}
1835
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1836

    
1837
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1838
                                     uint32_t me)
1839
{
1840
    TCGv t0;
1841

    
1842
    mb = MB(ctx->opcode);
1843
    me = ME(ctx->opcode);
1844
    t0 = tcg_temp_new();
1845
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1846
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1847
    if (unlikely(mb != 0 || me != 63)) {
1848
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1849
    } else {
1850
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1851
    }
1852
    tcg_temp_free(t0);
1853
    if (unlikely(Rc(ctx->opcode) != 0))
1854
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1855
}
1856

    
1857
/* rldcl - rldcl. */
1858
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1859
{
1860
    uint32_t mb;
1861

    
1862
    mb = MB(ctx->opcode) | (mbn << 5);
1863
    gen_rldnm(ctx, mb, 63);
1864
}
1865
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1866
/* rldcr - rldcr. */
1867
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1868
{
1869
    uint32_t me;
1870

    
1871
    me = MB(ctx->opcode) | (men << 5);
1872
    gen_rldnm(ctx, 0, me);
1873
}
1874
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1875
/* rldimi - rldimi. */
1876
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1877
{
1878
    uint32_t sh, mb, me;
1879

    
1880
    sh = SH(ctx->opcode) | (shn << 5);
1881
    mb = MB(ctx->opcode) | (mbn << 5);
1882
    me = 63 - sh;
1883
    if (unlikely(sh == 0 && mb == 0)) {
1884
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1885
    } else {
1886
        TCGv t0, t1;
1887
        target_ulong mask;
1888

    
1889
        t0 = tcg_temp_new();
1890
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1891
        t1 = tcg_temp_new();
1892
        mask = MASK(mb, me);
1893
        tcg_gen_andi_tl(t0, t0, mask);
1894
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1895
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1896
        tcg_temp_free(t0);
1897
        tcg_temp_free(t1);
1898
    }
1899
    if (unlikely(Rc(ctx->opcode) != 0))
1900
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1901
}
1902
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1903
#endif
1904

    
1905
/***                             Integer shift                             ***/
1906
/* slw & slw. */
1907
GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1908
{
1909
    TCGv t0;
1910
    int l1, l2;
1911
    l1 = gen_new_label();
1912
    l2 = gen_new_label();
1913

    
1914
    t0 = tcg_temp_local_new();
1915
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1916
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1917
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1918
    tcg_gen_br(l2);
1919
    gen_set_label(l1);
1920
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1921
    tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1922
    gen_set_label(l2);
1923
    tcg_temp_free(t0);
1924
    if (unlikely(Rc(ctx->opcode) != 0))
1925
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1926
}
1927
/* sraw & sraw. */
1928
GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1929
{
1930
    gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1931
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1932
    if (unlikely(Rc(ctx->opcode) != 0))
1933
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1934
}
1935
/* srawi & srawi. */
1936
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1937
{
1938
    int sh = SH(ctx->opcode);
1939
    if (sh != 0) {
1940
        int l1, l2;
1941
        TCGv t0;
1942
        l1 = gen_new_label();
1943
        l2 = gen_new_label();
1944
        t0 = tcg_temp_local_new();
1945
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1946
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1947
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1948
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1949
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1950
        tcg_gen_br(l2);
1951
        gen_set_label(l1);
1952
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1953
        gen_set_label(l2);
1954
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1955
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1956
        tcg_temp_free(t0);
1957
    } else {
1958
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1959
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1960
    }
1961
    if (unlikely(Rc(ctx->opcode) != 0))
1962
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1963
}
1964
/* srw & srw. */
1965
GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1966
{
1967
    TCGv t0, t1;
1968
    int l1, l2;
1969
    l1 = gen_new_label();
1970
    l2 = gen_new_label();
1971

    
1972
    t0 = tcg_temp_local_new();
1973
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1974
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1975
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1976
    tcg_gen_br(l2);
1977
    gen_set_label(l1);
1978
    t1 = tcg_temp_new();
1979
    tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1980
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1981
    tcg_temp_free(t1);
1982
    gen_set_label(l2);
1983
    tcg_temp_free(t0);
1984
    if (unlikely(Rc(ctx->opcode) != 0))
1985
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986
}
1987
#if defined(TARGET_PPC64)
1988
/* sld & sld. */
1989
GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1990
{
1991
    TCGv t0;
1992
    int l1, l2;
1993
    l1 = gen_new_label();
1994
    l2 = gen_new_label();
1995

    
1996
    t0 = tcg_temp_local_new();
1997
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1998
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1999
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2000
    tcg_gen_br(l2);
2001
    gen_set_label(l1);
2002
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2003
    gen_set_label(l2);
2004
    tcg_temp_free(t0);
2005
    if (unlikely(Rc(ctx->opcode) != 0))
2006
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2007
}
2008
/* srad & srad. */
2009
GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2010
{
2011
    gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2012
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2013
    if (unlikely(Rc(ctx->opcode) != 0))
2014
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2015
}
2016
/* sradi & sradi. */
2017
static always_inline void gen_sradi (DisasContext *ctx, int n)
2018
{
2019
    int sh = SH(ctx->opcode) + (n << 5);
2020
    if (sh != 0) {
2021
        int l1, l2;
2022
        TCGv t0;
2023
        l1 = gen_new_label();
2024
        l2 = gen_new_label();
2025
        t0 = tcg_temp_local_new();
2026
        tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2027
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2028
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2029
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2030
        tcg_gen_br(l2);
2031
        gen_set_label(l1);
2032
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2033
        gen_set_label(l2);
2034
        tcg_temp_free(t0);
2035
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2036
    } else {
2037
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2038
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2039
    }
2040
    if (unlikely(Rc(ctx->opcode) != 0))
2041
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2042
}
2043
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2044
{
2045
    gen_sradi(ctx, 0);
2046
}
2047
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2048
{
2049
    gen_sradi(ctx, 1);
2050
}
2051
/* srd & srd. */
2052
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2053
{
2054
    TCGv t0;
2055
    int l1, l2;
2056
    l1 = gen_new_label();
2057
    l2 = gen_new_label();
2058

    
2059
    t0 = tcg_temp_local_new();
2060
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2061
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2062
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2063
    tcg_gen_br(l2);
2064
    gen_set_label(l1);
2065
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2066
    gen_set_label(l2);
2067
    tcg_temp_free(t0);
2068
    if (unlikely(Rc(ctx->opcode) != 0))
2069
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2070
}
2071
#endif
2072

    
2073
/***                       Floating-Point arithmetic                       ***/
2074
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
2075
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
2076
{                                                                             \
2077
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2078
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2079
        return;                                                               \
2080
    }                                                                         \
2081
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2082
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2083
    gen_reset_fpstatus();                                                     \
2084
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2085
                     cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);     \
2086
    if (isfloat) {                                                            \
2087
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2088
    }                                                                         \
2089
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf,                      \
2090
                     Rc(ctx->opcode) != 0);                                   \
2091
}
2092

    
2093
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
2094
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
2095
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2096

    
2097
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2098
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
2099
{                                                                             \
2100
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2101
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2102
        return;                                                               \
2103
    }                                                                         \
2104
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2105
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2106
    gen_reset_fpstatus();                                                     \
2107
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2108
                     cpu_fpr[rB(ctx->opcode)]);                               \
2109
    if (isfloat) {                                                            \
2110
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2111
    }                                                                         \
2112
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2113
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2114
}
2115
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
2116
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2117
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2118

    
2119
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2120
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
2121
{                                                                             \
2122
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2123
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2124
        return;                                                               \
2125
    }                                                                         \
2126
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2127
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2128
    gen_reset_fpstatus();                                                     \
2129
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2130
                       cpu_fpr[rC(ctx->opcode)]);                             \
2131
    if (isfloat) {                                                            \
2132
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2133
    }                                                                         \
2134
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2135
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2136
}
2137
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
2138
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2139
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2140

    
2141
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
2142
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
2143
{                                                                             \
2144
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2145
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2146
        return;                                                               \
2147
    }                                                                         \
2148
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2149
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2150
    gen_reset_fpstatus();                                                     \
2151
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2152
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2153
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2154
}
2155

    
2156
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
2157
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
2158
{                                                                             \
2159
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2160
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2161
        return;                                                               \
2162
    }                                                                         \
2163
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2164
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2165
    gen_reset_fpstatus();                                                     \
2166
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2167
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2168
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2169
}
2170

    
2171
/* fadd - fadds */
2172
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2173
/* fdiv - fdivs */
2174
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2175
/* fmul - fmuls */
2176
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2177

    
2178
/* fre */
2179
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2180

    
2181
/* fres */
2182
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2183

    
2184
/* frsqrte */
2185
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2186

    
2187
/* frsqrtes */
2188
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2189
{
2190
    if (unlikely(!ctx->fpu_enabled)) {
2191
        gen_exception(ctx, POWERPC_EXCP_FPU);
2192
        return;
2193
    }
2194
    /* NIP cannot be restored if the memory exception comes from an helper */
2195
    gen_update_nip(ctx, ctx->nip - 4);
2196
    gen_reset_fpstatus();
2197
    gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2198
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2199
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2200
}
2201

    
2202
/* fsel */
2203
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2204
/* fsub - fsubs */
2205
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2206
/* Optional: */
2207
/* fsqrt */
2208
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2209
{
2210
    if (unlikely(!ctx->fpu_enabled)) {
2211
        gen_exception(ctx, POWERPC_EXCP_FPU);
2212
        return;
2213
    }
2214
    /* NIP cannot be restored if the memory exception comes from an helper */
2215
    gen_update_nip(ctx, ctx->nip - 4);
2216
    gen_reset_fpstatus();
2217
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2218
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2219
}
2220

    
2221
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2222
{
2223
    if (unlikely(!ctx->fpu_enabled)) {
2224
        gen_exception(ctx, POWERPC_EXCP_FPU);
2225
        return;
2226
    }
2227
    /* NIP cannot be restored if the memory exception comes from an helper */
2228
    gen_update_nip(ctx, ctx->nip - 4);
2229
    gen_reset_fpstatus();
2230
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2231
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2232
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2233
}
2234

    
2235
/***                     Floating-Point multiply-and-add                   ***/
2236
/* fmadd - fmadds */
2237
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2238
/* fmsub - fmsubs */
2239
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2240
/* fnmadd - fnmadds */
2241
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2242
/* fnmsub - fnmsubs */
2243
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2244

    
2245
/***                     Floating-Point round & convert                    ***/
2246
/* fctiw */
2247
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2248
/* fctiwz */
2249
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2250
/* frsp */
2251
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2252
#if defined(TARGET_PPC64)
2253
/* fcfid */
2254
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2255
/* fctid */
2256
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2257
/* fctidz */
2258
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2259
#endif
2260

    
2261
/* frin */
2262
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2263
/* friz */
2264
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2265
/* frip */
2266
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2267
/* frim */
2268
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2269

    
2270
/***                         Floating-Point compare                        ***/
2271
/* fcmpo */
2272
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2273
{
2274
    TCGv_i32 crf;
2275
    if (unlikely(!ctx->fpu_enabled)) {
2276
        gen_exception(ctx, POWERPC_EXCP_FPU);
2277
        return;
2278
    }
2279
    /* NIP cannot be restored if the memory exception comes from an helper */
2280
    gen_update_nip(ctx, ctx->nip - 4);
2281
    gen_reset_fpstatus();
2282
    crf = tcg_const_i32(crfD(ctx->opcode));
2283
    gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2284
    tcg_temp_free_i32(crf);
2285
    gen_helper_float_check_status();
2286
}
2287

    
2288
/* fcmpu */
2289
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2290
{
2291
    TCGv_i32 crf;
2292
    if (unlikely(!ctx->fpu_enabled)) {
2293
        gen_exception(ctx, POWERPC_EXCP_FPU);
2294
        return;
2295
    }
2296
    /* NIP cannot be restored if the memory exception comes from an helper */
2297
    gen_update_nip(ctx, ctx->nip - 4);
2298
    gen_reset_fpstatus();
2299
    crf = tcg_const_i32(crfD(ctx->opcode));
2300
    gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2301
    tcg_temp_free_i32(crf);
2302
    gen_helper_float_check_status();
2303
}
2304

    
2305
/***                         Floating-point move                           ***/
2306
/* fabs */
2307
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2308
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2309

    
2310
/* fmr  - fmr. */
2311
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2312
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2313
{
2314
    if (unlikely(!ctx->fpu_enabled)) {
2315
        gen_exception(ctx, POWERPC_EXCP_FPU);
2316
        return;
2317
    }
2318
    tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2319
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2320
}
2321

    
2322
/* fnabs */
2323
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2324
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2325
/* fneg */
2326
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2327
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2328

    
2329
/***                  Floating-Point status & ctrl register                ***/
2330
/* mcrfs */
2331
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2332
{
2333
    int bfa;
2334

    
2335
    if (unlikely(!ctx->fpu_enabled)) {
2336
        gen_exception(ctx, POWERPC_EXCP_FPU);
2337
        return;
2338
    }
2339
    bfa = 4 * (7 - crfS(ctx->opcode));
2340
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2341
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2342
    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2343
}
2344

    
2345
/* mffs */
2346
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2347
{
2348
    if (unlikely(!ctx->fpu_enabled)) {
2349
        gen_exception(ctx, POWERPC_EXCP_FPU);
2350
        return;
2351
    }
2352
    gen_reset_fpstatus();
2353
    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2354
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2355
}
2356

    
2357
/* mtfsb0 */
2358
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2359
{
2360
    uint8_t crb;
2361

    
2362
    if (unlikely(!ctx->fpu_enabled)) {
2363
        gen_exception(ctx, POWERPC_EXCP_FPU);
2364
        return;
2365
    }
2366
    crb = 31 - crbD(ctx->opcode);
2367
    gen_reset_fpstatus();
2368
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2369
        TCGv_i32 t0;
2370
        /* NIP cannot be restored if the memory exception comes from an helper */
2371
        gen_update_nip(ctx, ctx->nip - 4);
2372
        t0 = tcg_const_i32(crb);
2373
        gen_helper_fpscr_clrbit(t0);
2374
        tcg_temp_free_i32(t0);
2375
    }
2376
    if (unlikely(Rc(ctx->opcode) != 0)) {
2377
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2378
    }
2379
}
2380

    
2381
/* mtfsb1 */
2382
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2383
{
2384
    uint8_t crb;
2385

    
2386
    if (unlikely(!ctx->fpu_enabled)) {
2387
        gen_exception(ctx, POWERPC_EXCP_FPU);
2388
        return;
2389
    }
2390
    crb = 31 - crbD(ctx->opcode);
2391
    gen_reset_fpstatus();
2392
    /* XXX: we pretend we can only do IEEE floating-point computations */
2393
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2394
        TCGv_i32 t0;
2395
        /* NIP cannot be restored if the memory exception comes from an helper */
2396
        gen_update_nip(ctx, ctx->nip - 4);
2397
        t0 = tcg_const_i32(crb);
2398
        gen_helper_fpscr_setbit(t0);
2399
        tcg_temp_free_i32(t0);
2400
    }
2401
    if (unlikely(Rc(ctx->opcode) != 0)) {
2402
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2403
    }
2404
    /* We can raise a differed exception */
2405
    gen_helper_float_check_status();
2406
}
2407

    
2408
/* mtfsf */
2409
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2410
{
2411
    TCGv_i32 t0;
2412

    
2413
    if (unlikely(!ctx->fpu_enabled)) {
2414
        gen_exception(ctx, POWERPC_EXCP_FPU);
2415
        return;
2416
    }
2417
    /* NIP cannot be restored if the memory exception comes from an helper */
2418
    gen_update_nip(ctx, ctx->nip - 4);
2419
    gen_reset_fpstatus();
2420
    t0 = tcg_const_i32(FM(ctx->opcode));
2421
    gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2422
    tcg_temp_free_i32(t0);
2423
    if (unlikely(Rc(ctx->opcode) != 0)) {
2424
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2425
    }
2426
    /* We can raise a differed exception */
2427
    gen_helper_float_check_status();
2428
}
2429

    
2430
/* mtfsfi */
2431
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2432
{
2433
    int bf, sh;
2434
    TCGv_i64 t0;
2435
    TCGv_i32 t1;
2436

    
2437
    if (unlikely(!ctx->fpu_enabled)) {
2438
        gen_exception(ctx, POWERPC_EXCP_FPU);
2439
        return;
2440
    }
2441
    bf = crbD(ctx->opcode) >> 2;
2442
    sh = 7 - bf;
2443
    /* NIP cannot be restored if the memory exception comes from an helper */
2444
    gen_update_nip(ctx, ctx->nip - 4);
2445
    gen_reset_fpstatus();
2446
    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2447
    t1 = tcg_const_i32(1 << sh);
2448
    gen_helper_store_fpscr(t0, t1);
2449
    tcg_temp_free_i64(t0);
2450
    tcg_temp_free_i32(t1);
2451
    if (unlikely(Rc(ctx->opcode) != 0)) {
2452
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2453
    }
2454
    /* We can raise a differed exception */
2455
    gen_helper_float_check_status();
2456
}
2457

    
2458
/***                           Addressing modes                            ***/
2459
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2460
static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2461
{
2462
    target_long simm = SIMM(ctx->opcode);
2463

    
2464
    simm &= ~maskl;
2465
    if (rA(ctx->opcode) == 0) {
2466
#if defined(TARGET_PPC64)
2467
        if (!ctx->sf_mode) {
2468
            tcg_gen_movi_tl(EA, (uint32_t)simm);
2469
        } else
2470
#endif
2471
        tcg_gen_movi_tl(EA, simm);
2472
    } else if (likely(simm != 0)) {
2473
        tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2474
#if defined(TARGET_PPC64)
2475
        if (!ctx->sf_mode) {
2476
            tcg_gen_ext32u_tl(EA, EA);
2477
        }
2478
#endif
2479
    } else {
2480
#if defined(TARGET_PPC64)
2481
        if (!ctx->sf_mode) {
2482
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2483
        } else
2484
#endif
2485
        tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2486
    }
2487
}
2488

    
2489
static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2490
{
2491
    if (rA(ctx->opcode) == 0) {
2492
#if defined(TARGET_PPC64)
2493
        if (!ctx->sf_mode) {
2494
            tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2495
        } else
2496
#endif
2497
        tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2498
    } else {
2499
        tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2500
#if defined(TARGET_PPC64)
2501
        if (!ctx->sf_mode) {
2502
            tcg_gen_ext32u_tl(EA, EA);
2503
        }
2504
#endif
2505
    }
2506
}
2507

    
2508
static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2509
{
2510
    if (rA(ctx->opcode) == 0) {
2511
        tcg_gen_movi_tl(EA, 0);
2512
    } else {
2513
#if defined(TARGET_PPC64)
2514
        if (!ctx->sf_mode) {
2515
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2516
        } else
2517
#endif
2518
            tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2519
    }
2520
}
2521

    
2522
static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2523
{
2524
    tcg_gen_addi_tl(ret, arg1, val);
2525
#if defined(TARGET_PPC64)
2526
    if (!ctx->sf_mode) {
2527
        tcg_gen_ext32u_tl(ret, ret);
2528
    }
2529
#endif
2530
}
2531

    
2532
static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2533
{
2534
    int l1 = gen_new_label();
2535
    TCGv t0 = tcg_temp_new();
2536
    TCGv_i32 t1, t2;
2537
    /* NIP cannot be restored if the memory exception comes from an helper */
2538
    gen_update_nip(ctx, ctx->nip - 4);
2539
    tcg_gen_andi_tl(t0, EA, mask);
2540
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2541
    t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2542
    t2 = tcg_const_i32(0);
2543
    gen_helper_raise_exception_err(t1, t2);
2544
    tcg_temp_free_i32(t1);
2545
    tcg_temp_free_i32(t2);
2546
    gen_set_label(l1);
2547
    tcg_temp_free(t0);
2548
}
2549

    
2550
/***                             Integer load                              ***/
2551
static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552
{
2553
    tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2554
}
2555

    
2556
static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2557
{
2558
    tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2559
}
2560

    
2561
static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2562
{
2563
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2564
    if (unlikely(ctx->le_mode)) {
2565
#if defined(TARGET_PPC64)
2566
        TCGv_i32 t0 = tcg_temp_new_i32();
2567
        tcg_gen_trunc_tl_i32(t0, arg1);
2568
        tcg_gen_bswap16_i32(t0, t0);
2569
        tcg_gen_extu_i32_tl(arg1, t0);
2570
        tcg_temp_free_i32(t0);
2571
#else
2572
        tcg_gen_bswap16_i32(arg1, arg1);
2573
#endif
2574
    }
2575
}
2576

    
2577
static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2578
{
2579
    if (unlikely(ctx->le_mode)) {
2580
#if defined(TARGET_PPC64)
2581
        TCGv_i32 t0;
2582
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2583
        t0 = tcg_temp_new_i32();
2584
        tcg_gen_trunc_tl_i32(t0, arg1);
2585
        tcg_gen_bswap16_i32(t0, t0);
2586
        tcg_gen_extu_i32_tl(arg1, t0);
2587
        tcg_gen_ext16s_tl(arg1, arg1);
2588
        tcg_temp_free_i32(t0);
2589
#else
2590
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2591
        tcg_gen_bswap16_i32(arg1, arg1);
2592
        tcg_gen_ext16s_i32(arg1, arg1);
2593
#endif
2594
    } else {
2595
        tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2596
    }
2597
}
2598

    
2599
static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2600
{
2601
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2602
    if (unlikely(ctx->le_mode)) {
2603
#if defined(TARGET_PPC64)
2604
        TCGv_i32 t0 = tcg_temp_new_i32();
2605
        tcg_gen_trunc_tl_i32(t0, arg1);
2606
        tcg_gen_bswap_i32(t0, t0);
2607
        tcg_gen_extu_i32_tl(arg1, t0);
2608
        tcg_temp_free_i32(t0);
2609
#else
2610
        tcg_gen_bswap_i32(arg1, arg1);
2611
#endif
2612
    }
2613
}
2614

    
2615
#if defined(TARGET_PPC64)
2616
static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2617
{
2618
    if (unlikely(ctx->mem_idx)) {
2619
        TCGv_i32 t0;
2620
        tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2621
        t0 = tcg_temp_new_i32();
2622
        tcg_gen_trunc_tl_i32(t0, arg1);
2623
        tcg_gen_bswap_i32(t0, t0);
2624
        tcg_gen_ext_i32_tl(arg1, t0);
2625
        tcg_temp_free_i32(t0);
2626
    } else
2627
        tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2628
}
2629
#endif
2630

    
2631
static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2632
{
2633
    tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2634
    if (unlikely(ctx->le_mode)) {
2635
        tcg_gen_bswap_i64(arg1, arg1);
2636
    }
2637
}
2638

    
2639
static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2640
{
2641
    tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2642
}
2643

    
2644
static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2645
{
2646
    if (unlikely(ctx->le_mode)) {
2647
#if defined(TARGET_PPC64)
2648
        TCGv_i32 t0;
2649
        TCGv t1;
2650
        t0 = tcg_temp_new_i32();
2651
        tcg_gen_trunc_tl_i32(t0, arg1);
2652
        tcg_gen_ext16u_i32(t0, t0);
2653
        tcg_gen_bswap16_i32(t0, t0);
2654
        t1 = tcg_temp_new();
2655
        tcg_gen_extu_i32_tl(t1, t0);
2656
        tcg_temp_free_i32(t0);
2657
        tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2658
        tcg_temp_free(t1);
2659
#else
2660
        TCGv t0 = tcg_temp_new();
2661
        tcg_gen_ext16u_tl(t0, arg1);
2662
        tcg_gen_bswap16_i32(t0, t0);
2663
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2664
        tcg_temp_free(t0);
2665
#endif
2666
    } else {
2667
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2668
    }
2669
}
2670

    
2671
static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2672
{
2673
    if (unlikely(ctx->le_mode)) {
2674
#if defined(TARGET_PPC64)
2675
        TCGv_i32 t0;
2676
        TCGv t1;
2677
        t0 = tcg_temp_new_i32();
2678
        tcg_gen_trunc_tl_i32(t0, arg1);
2679
        tcg_gen_bswap_i32(t0, t0);
2680
        t1 = tcg_temp_new();
2681
        tcg_gen_extu_i32_tl(t1, t0);
2682
        tcg_temp_free_i32(t0);
2683
        tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2684
        tcg_temp_free(t1);
2685
#else
2686
        TCGv t0 = tcg_temp_new_i32();
2687
        tcg_gen_bswap_i32(t0, arg1);
2688
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2689
        tcg_temp_free(t0);
2690
#endif
2691
    } else {
2692
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2693
    }
2694
}
2695

    
2696
static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2697
{
2698
    if (unlikely(ctx->le_mode)) {
2699
        TCGv_i64 t0 = tcg_temp_new_i64();
2700
        tcg_gen_bswap_i64(t0, arg1);
2701
        tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2702
        tcg_temp_free_i64(t0);
2703
    } else
2704
        tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2705
}
2706

    
2707
#define GEN_LD(name, ldop, opc, type)                                         \
2708
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
2709
{                                                                             \
2710
    TCGv EA;                                                                  \
2711
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2712
    EA = tcg_temp_new();                                                      \
2713
    gen_addr_imm_index(ctx, EA, 0);                                           \
2714
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2715
    tcg_temp_free(EA);                                                        \
2716
}
2717

    
2718
#define GEN_LDU(name, ldop, opc, type)                                        \
2719
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
2720
{                                                                             \
2721
    TCGv EA;                                                                  \
2722
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2723
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2724
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2725
        return;                                                               \
2726
    }                                                                         \
2727
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2728
    EA = tcg_temp_new();                                                      \
2729
    if (type == PPC_64B)                                                      \
2730
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2731
    else                                                                      \
2732
        gen_addr_imm_index(ctx, EA, 0);                                       \
2733
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2734
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2735
    tcg_temp_free(EA);                                                        \
2736
}
2737

    
2738
#define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
2739
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type)                     \
2740
{                                                                             \
2741
    TCGv EA;                                                                  \
2742
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2743
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2744
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2745
        return;                                                               \
2746
    }                                                                         \
2747
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2748
    EA = tcg_temp_new();                                                      \
2749
    gen_addr_reg_index(ctx, EA);                                              \
2750
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2751
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2752
    tcg_temp_free(EA);                                                        \
2753
}
2754

    
2755
#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
2756
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
2757
{                                                                             \
2758
    TCGv EA;                                                                  \
2759
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2760
    EA = tcg_temp_new();                                                      \
2761
    gen_addr_reg_index(ctx, EA);                                              \
2762
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2763
    tcg_temp_free(EA);                                                        \
2764
}
2765

    
2766
#define GEN_LDS(name, ldop, op, type)                                         \
2767
GEN_LD(name, ldop, op | 0x20, type);                                          \
2768
GEN_LDU(name, ldop, op | 0x21, type);                                         \
2769
GEN_LDUX(name, ldop, 0x17, op | 0x01, type);                                  \
2770
GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2771

    
2772
/* lbz lbzu lbzux lbzx */
2773
GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2774
/* lha lhau lhaux lhax */
2775
GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2776
/* lhz lhzu lhzux lhzx */
2777
GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2778
/* lwz lwzu lwzux lwzx */
2779
GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2780
#if defined(TARGET_PPC64)
2781
/* lwaux */
2782
GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2783
/* lwax */
2784
GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2785
/* ldux */
2786
GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2787
/* ldx */
2788
GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2789
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2790
{
2791
    TCGv EA;
2792
    if (Rc(ctx->opcode)) {
2793
        if (unlikely(rA(ctx->opcode) == 0 ||
2794
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2795
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2796
            return;
2797
        }
2798
    }
2799
    gen_set_access_type(ctx, ACCESS_INT);
2800
    EA = tcg_temp_new();
2801
    gen_addr_imm_index(ctx, EA, 0x03);
2802
    if (ctx->opcode & 0x02) {
2803
        /* lwa (lwau is undefined) */
2804
        gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2805
    } else {
2806
        /* ld - ldu */
2807
        gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2808
    }
2809
    if (Rc(ctx->opcode))
2810
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2811
    tcg_temp_free(EA);
2812
}
2813
/* lq */
2814
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2815
{
2816
#if defined(CONFIG_USER_ONLY)
2817
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2818
#else
2819
    int ra, rd;
2820
    TCGv EA;
2821

    
2822
    /* Restore CPU state */
2823
    if (unlikely(ctx->mem_idx == 0)) {
2824
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2825
        return;
2826
    }
2827
    ra = rA(ctx->opcode);
2828
    rd = rD(ctx->opcode);
2829
    if (unlikely((rd & 1) || rd == ra)) {
2830
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2831
        return;
2832
    }
2833
    if (unlikely(ctx->le_mode)) {
2834
        /* Little-endian mode is not handled */
2835
        gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2836
        return;
2837
    }
2838
    gen_set_access_type(ctx, ACCESS_INT);
2839
    EA = tcg_temp_new();
2840
    gen_addr_imm_index(ctx, EA, 0x0F);
2841
    gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2842
    gen_addr_add(ctx, EA, EA, 8);
2843
    gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2844
    tcg_temp_free(EA);
2845
#endif
2846
}
2847
#endif
2848

    
2849
/***                              Integer store                            ***/
2850
#define GEN_ST(name, stop, opc, type)                                         \
2851
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
2852
{                                                                             \
2853
    TCGv EA;                                                                  \
2854
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2855
    EA = tcg_temp_new();                                                      \
2856
    gen_addr_imm_index(ctx, EA, 0);                                           \
2857
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2858
    tcg_temp_free(EA);                                                        \
2859
}
2860

    
2861
#define GEN_STU(name, stop, opc, type)                                        \
2862
GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
2863
{                                                                             \
2864
    TCGv EA;                                                                  \
2865
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2866
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2867
        return;                                                               \
2868
    }                                                                         \
2869
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2870
    EA = tcg_temp_new();                                                      \
2871
    if (type == PPC_64B)                                                      \
2872
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2873
    else                                                                      \
2874
        gen_addr_imm_index(ctx, EA, 0);                                       \
2875
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2876
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2877
    tcg_temp_free(EA);                                                        \
2878
}
2879

    
2880
#define GEN_STUX(name, stop, opc2, opc3, type)                                \
2881
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type)                     \
2882
{                                                                             \
2883
    TCGv EA;                                                                  \
2884
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2885
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2886
        return;                                                               \
2887
    }                                                                         \
2888
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2889
    EA = tcg_temp_new();                                                      \
2890
    gen_addr_reg_index(ctx, EA);                                              \
2891
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2892
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2893
    tcg_temp_free(EA);                                                        \
2894
}
2895

    
2896
#define GEN_STX(name, stop, opc2, opc3, type)                                 \
2897
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
2898
{                                                                             \
2899
    TCGv EA;                                                                  \
2900
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2901
    EA = tcg_temp_new();                                                      \
2902
    gen_addr_reg_index(ctx, EA);                                              \
2903
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2904
    tcg_temp_free(EA);                                                        \
2905
}
2906

    
2907
#define GEN_STS(name, stop, op, type)                                         \
2908
GEN_ST(name, stop, op | 0x20, type);                                          \
2909
GEN_STU(name, stop, op | 0x21, type);                                         \
2910
GEN_STUX(name, stop, 0x17, op | 0x01, type);                                  \
2911
GEN_STX(name, stop, 0x17, op | 0x00, type)
2912

    
2913
/* stb stbu stbux stbx */
2914
GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2915
/* sth sthu sthux sthx */
2916
GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2917
/* stw stwu stwux stwx */
2918
GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2919
#if defined(TARGET_PPC64)
2920
GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2921
GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2922
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2923
{
2924
    int rs;
2925
    TCGv EA;
2926

    
2927
    rs = rS(ctx->opcode);
2928
    if ((ctx->opcode & 0x3) == 0x2) {
2929
#if defined(CONFIG_USER_ONLY)
2930
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2931
#else
2932
        /* stq */
2933
        if (unlikely(ctx->mem_idx == 0)) {
2934
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2935
            return;
2936
        }
2937
        if (unlikely(rs & 1)) {
2938
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2939
            return;
2940
        }
2941
        if (unlikely(ctx->le_mode)) {
2942
            /* Little-endian mode is not handled */
2943
            gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2944
            return;
2945
        }
2946
        gen_set_access_type(ctx, ACCESS_INT);
2947
        EA = tcg_temp_new();
2948
        gen_addr_imm_index(ctx, EA, 0x03);
2949
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2950
        gen_addr_add(ctx, EA, EA, 8);
2951
        gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2952
        tcg_temp_free(EA);
2953
#endif
2954
    } else {
2955
        /* std / stdu */
2956
        if (Rc(ctx->opcode)) {
2957
            if (unlikely(rA(ctx->opcode) == 0)) {
2958
                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2959
                return;
2960
            }
2961
        }
2962
        gen_set_access_type(ctx, ACCESS_INT);
2963
        EA = tcg_temp_new();
2964
        gen_addr_imm_index(ctx, EA, 0x03);
2965
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2966
        if (Rc(ctx->opcode))
2967
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2968
        tcg_temp_free(EA);
2969
    }
2970
}
2971
#endif
2972
/***                Integer load and store with byte reverse               ***/
2973
/* lhbrx */
2974
static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2975
{
2976
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2977
    if (likely(!ctx->le_mode)) {
2978
#if defined(TARGET_PPC64)
2979
        TCGv_i32 t0 = tcg_temp_new_i32();
2980
        tcg_gen_trunc_tl_i32(t0, arg1);
2981
        tcg_gen_bswap16_i32(t0, t0);
2982
        tcg_gen_extu_i32_tl(arg1, t0);
2983
        tcg_temp_free_i32(t0);
2984
#else
2985
        tcg_gen_bswap16_i32(arg1, arg1);
2986
#endif
2987
    }
2988
}
2989
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2990

    
2991
/* lwbrx */
2992
static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2993
{
2994
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2995
    if (likely(!ctx->le_mode)) {
2996
#if defined(TARGET_PPC64)
2997
        TCGv_i32 t0 = tcg_temp_new_i32();
2998
        tcg_gen_trunc_tl_i32(t0, arg1);
2999
        tcg_gen_bswap_i32(t0, t0);
3000
        tcg_gen_extu_i32_tl(arg1, t0);
3001
        tcg_temp_free_i32(t0);
3002
#else
3003
        tcg_gen_bswap_i32(arg1, arg1);
3004
#endif
3005
    }
3006
}
3007
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3008

    
3009
/* sthbrx */
3010
static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3011
{
3012
    if (likely(!ctx->le_mode)) {
3013
#if defined(TARGET_PPC64)
3014
        TCGv_i32 t0;
3015
        TCGv t1;
3016
        t0 = tcg_temp_new_i32();
3017
        tcg_gen_trunc_tl_i32(t0, arg1);
3018
        tcg_gen_ext16u_i32(t0, t0);
3019
        tcg_gen_bswap16_i32(t0, t0);
3020
        t1 = tcg_temp_new();
3021
        tcg_gen_extu_i32_tl(t1, t0);
3022
        tcg_temp_free_i32(t0);
3023
        tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3024
        tcg_temp_free(t1);
3025
#else
3026
        TCGv t0 = tcg_temp_new();
3027
        tcg_gen_ext16u_tl(t0, arg1);
3028
        tcg_gen_bswap16_i32(t0, t0);
3029
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3030
        tcg_temp_free(t0);
3031
#endif
3032
    } else {
3033
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3034
    }
3035
}
3036
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3037

    
3038
/* stwbrx */
3039
static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3040
{
3041
    if (likely(!ctx->le_mode)) {
3042
#if defined(TARGET_PPC64)
3043
        TCGv_i32 t0;
3044
        TCGv t1;
3045
        t0 = tcg_temp_new_i32();
3046
        tcg_gen_trunc_tl_i32(t0, arg1);
3047
        tcg_gen_bswap_i32(t0, t0);
3048
        t1 = tcg_temp_new();
3049
        tcg_gen_extu_i32_tl(t1, t0);
3050
        tcg_temp_free_i32(t0);
3051
        tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3052
        tcg_temp_free(t1);
3053
#else
3054
        TCGv t0 = tcg_temp_new_i32();
3055
        tcg_gen_bswap_i32(t0, arg1);
3056
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3057
        tcg_temp_free(t0);
3058
#endif
3059
    } else {
3060
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3061
    }
3062
}
3063
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3064

    
3065
/***                    Integer load and store multiple                    ***/
3066
/* lmw */
3067
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3068
{
3069
    TCGv t0;
3070
    TCGv_i32 t1;
3071
    gen_set_access_type(ctx, ACCESS_INT);
3072
    /* NIP cannot be restored if the memory exception comes from an helper */
3073
    gen_update_nip(ctx, ctx->nip - 4);
3074
    t0 = tcg_temp_new();
3075
    t1 = tcg_const_i32(rD(ctx->opcode));
3076
    gen_addr_imm_index(ctx, t0, 0);
3077
    gen_helper_lmw(t0, t1);
3078
    tcg_temp_free(t0);
3079
    tcg_temp_free_i32(t1);
3080
}
3081

    
3082
/* stmw */
3083
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3084
{
3085
    TCGv t0;
3086
    TCGv_i32 t1;
3087
    gen_set_access_type(ctx, ACCESS_INT);
3088
    /* NIP cannot be restored if the memory exception comes from an helper */
3089
    gen_update_nip(ctx, ctx->nip - 4);
3090
    t0 = tcg_temp_new();
3091
    t1 = tcg_const_i32(rS(ctx->opcode));
3092
    gen_addr_imm_index(ctx, t0, 0);
3093
    gen_helper_stmw(t0, t1);
3094
    tcg_temp_free(t0);
3095
    tcg_temp_free_i32(t1);
3096
}
3097

    
3098
/***                    Integer load and store strings                     ***/
3099
/* lswi */
3100
/* PowerPC32 specification says we must generate an exception if
3101
 * rA is in the range of registers to be loaded.
3102
 * In an other hand, IBM says this is valid, but rA won't be loaded.
3103
 * For now, I'll follow the spec...
3104
 */
3105
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3106
{
3107
    TCGv t0;
3108
    TCGv_i32 t1, t2;
3109
    int nb = NB(ctx->opcode);
3110
    int start = rD(ctx->opcode);
3111
    int ra = rA(ctx->opcode);
3112
    int nr;
3113

    
3114
    if (nb == 0)
3115
        nb = 32;
3116
    nr = nb / 4;
3117
    if (unlikely(((start + nr) > 32  &&
3118
                  start <= ra && (start + nr - 32) > ra) ||
3119
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3120
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3121
        return;
3122
    }
3123
    gen_set_access_type(ctx, ACCESS_INT);
3124
    /* NIP cannot be restored if the memory exception comes from an helper */
3125
    gen_update_nip(ctx, ctx->nip - 4);
3126
    t0 = tcg_temp_new();
3127
    gen_addr_register(ctx, t0);
3128
    t1 = tcg_const_i32(nb);
3129
    t2 = tcg_const_i32(start);
3130
    gen_helper_lsw(t0, t1, t2);
3131
    tcg_temp_free(t0);
3132
    tcg_temp_free_i32(t1);
3133
    tcg_temp_free_i32(t2);
3134
}
3135

    
3136
/* lswx */
3137
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3138
{
3139
    TCGv t0;
3140
    TCGv_i32 t1, t2, t3;
3141
    gen_set_access_type(ctx, ACCESS_INT);
3142
    /* NIP cannot be restored if the memory exception comes from an helper */
3143
    gen_update_nip(ctx, ctx->nip - 4);
3144
    t0 = tcg_temp_new();
3145
    gen_addr_reg_index(ctx, t0);
3146
    t1 = tcg_const_i32(rD(ctx->opcode));
3147
    t2 = tcg_const_i32(rA(ctx->opcode));
3148
    t3 = tcg_const_i32(rB(ctx->opcode));
3149
    gen_helper_lswx(t0, t1, t2, t3);
3150
    tcg_temp_free(t0);
3151
    tcg_temp_free_i32(t1);
3152
    tcg_temp_free_i32(t2);
3153
    tcg_temp_free_i32(t3);
3154
}
3155

    
3156
/* stswi */
3157
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3158
{
3159
    TCGv t0;
3160
    TCGv_i32 t1, t2;
3161
    int nb = NB(ctx->opcode);
3162
    gen_set_access_type(ctx, ACCESS_INT);
3163
    /* NIP cannot be restored if the memory exception comes from an helper */
3164
    gen_update_nip(ctx, ctx->nip - 4);
3165
    t0 = tcg_temp_new();
3166
    gen_addr_register(ctx, t0);
3167
    if (nb == 0)
3168
        nb = 32;
3169
    t1 = tcg_const_i32(nb);
3170
    t2 = tcg_const_i32(rS(ctx->opcode));
3171
    gen_helper_stsw(t0, t1, t2);
3172
    tcg_temp_free(t0);
3173
    tcg_temp_free_i32(t1);
3174
    tcg_temp_free_i32(t2);
3175
}
3176

    
3177
/* stswx */
3178
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3179
{
3180
    TCGv t0;
3181
    TCGv_i32 t1, t2;
3182
    gen_set_access_type(ctx, ACCESS_INT);
3183
    /* NIP cannot be restored if the memory exception comes from an helper */
3184
    gen_update_nip(ctx, ctx->nip - 4);
3185
    t0 = tcg_temp_new();
3186
    gen_addr_reg_index(ctx, t0);
3187
    t1 = tcg_temp_new_i32();
3188
    tcg_gen_trunc_tl_i32(t1, cpu_xer);
3189
    tcg_gen_andi_i32(t1, t1, 0x7F);
3190
    t2 = tcg_const_i32(rS(ctx->opcode));
3191
    gen_helper_stsw(t0, t1, t2);
3192
    tcg_temp_free(t0);
3193
    tcg_temp_free_i32(t1);
3194
    tcg_temp_free_i32(t2);
3195
}
3196

    
3197
/***                        Memory synchronisation                         ***/
3198
/* eieio */
3199
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3200
{
3201
}
3202

    
3203
/* isync */
3204
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3205
{
3206
    gen_stop_exception(ctx);
3207
}
3208

    
3209
/* lwarx */
3210
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3211
{
3212
    TCGv t0;
3213
    gen_set_access_type(ctx, ACCESS_RES);
3214
    t0 = tcg_temp_local_new();
3215
    gen_addr_reg_index(ctx, t0);
3216
    gen_check_align(ctx, t0, 0x03);
3217
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3218
    tcg_gen_mov_tl(cpu_reserve, t0);
3219
    tcg_temp_free(t0);
3220
}
3221

    
3222
/* stwcx. */
3223
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3224
{
3225
    int l1;
3226
    TCGv t0;
3227
    gen_set_access_type(ctx, ACCESS_RES);
3228
    t0 = tcg_temp_local_new();
3229
    gen_addr_reg_index(ctx, t0);
3230
    gen_check_align(ctx, t0, 0x03);
3231
    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3232
    tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3233
    tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3234
    l1 = gen_new_label();
3235
    tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3236
    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3237
    gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3238
    gen_set_label(l1);
3239
    tcg_gen_movi_tl(cpu_reserve, -1);
3240
    tcg_temp_free(t0);
3241
}
3242

    
3243
#if defined(TARGET_PPC64)
3244
/* ldarx */
3245
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3246
{
3247
    TCGv t0;
3248
    gen_set_access_type(ctx, ACCESS_RES);
3249
    t0 = tcg_temp_local_new();
3250
    gen_addr_reg_index(ctx, t0);
3251
    gen_check_align(ctx, t0, 0x07);
3252
    gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3253
    tcg_gen_mov_tl(cpu_reserve, t0);
3254
    tcg_temp_free(t0);
3255
}
3256

    
3257
/* stdcx. */
3258
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3259
{
3260
    int l1;
3261
    TCGv t0;
3262
    gen_set_access_type(ctx, ACCESS_RES);
3263
    t0 = tcg_temp_local_new();
3264
    gen_addr_reg_index(ctx, t0);
3265
    gen_check_align(ctx, t0, 0x07);
3266
    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3267
    tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3268
    tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3269
    l1 = gen_new_label();
3270
    tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3271
    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3272
    gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3273
    gen_set_label(l1);
3274
    tcg_gen_movi_tl(cpu_reserve, -1);
3275
    tcg_temp_free(t0);
3276
}
3277
#endif /* defined(TARGET_PPC64) */
3278

    
3279
/* sync */
3280
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3281
{
3282
}
3283

    
3284
/* wait */
3285
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3286
{
3287
    TCGv_i32 t0 = tcg_temp_new_i32();
3288
    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3289
    tcg_temp_free_i32(t0);
3290
    /* Stop translation, as the CPU is supposed to sleep from now */
3291
    gen_exception_err(ctx, EXCP_HLT, 1);
3292
}
3293

    
3294
/***                         Floating-point load                           ***/
3295
#define GEN_LDF(name, ldop, opc, type)                                        \
3296
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
3297
{                                                                             \
3298
    TCGv EA;                                                                  \
3299
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3300
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3301
        return;                                                               \
3302
    }                                                                         \
3303
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3304
    EA = tcg_temp_new();                                                      \
3305
    gen_addr_imm_index(ctx, EA, 0);                                           \
3306
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3307
    tcg_temp_free(EA);                                                        \
3308
}
3309

    
3310
#define GEN_LDUF(name, ldop, opc, type)                                       \
3311
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
3312
{                                                                             \
3313
    TCGv EA;                                                                  \
3314
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3315
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3316
        return;                                                               \
3317
    }                                                                         \
3318
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3319
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3320
        return;                                                               \
3321
    }                                                                         \
3322
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3323
    EA = tcg_temp_new();                                                      \
3324
    gen_addr_imm_index(ctx, EA, 0);                                           \
3325
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3326
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3327
    tcg_temp_free(EA);                                                        \
3328
}
3329

    
3330
#define GEN_LDUXF(name, ldop, opc, type)                                      \
3331
GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type)                      \
3332
{                                                                             \
3333
    TCGv EA;                                                                  \
3334
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3335
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3336
        return;                                                               \
3337
    }                                                                         \
3338
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3339
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3340
        return;                                                               \
3341
    }                                                                         \
3342
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3343
    EA = tcg_temp_new();                                                      \
3344
    gen_addr_reg_index(ctx, EA);                                              \
3345
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3346
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3347
    tcg_temp_free(EA);                                                        \
3348
}
3349

    
3350
#define GEN_LDXF(name, ldop, opc2, opc3, type)                                \
3351
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
3352
{                                                                             \
3353
    TCGv EA;                                                                  \
3354
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3355
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3356
        return;                                                               \
3357
    }                                                                         \
3358
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3359
    EA = tcg_temp_new();                                                      \
3360
    gen_addr_reg_index(ctx, EA);                                              \
3361
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3362
    tcg_temp_free(EA);                                                        \
3363
}
3364

    
3365
#define GEN_LDFS(name, ldop, op, type)                                        \
3366
GEN_LDF(name, ldop, op | 0x20, type);                                         \
3367
GEN_LDUF(name, ldop, op | 0x21, type);                                        \
3368
GEN_LDUXF(name, ldop, op | 0x01, type);                                       \
3369
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3370

    
3371
static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3372
{
3373
    TCGv t0 = tcg_temp_new();
3374
    TCGv_i32 t1 = tcg_temp_new_i32();
3375
    gen_qemu_ld32u(ctx, t0, arg2);
3376
    tcg_gen_trunc_tl_i32(t1, t0);
3377
    tcg_temp_free(t0);
3378
    gen_helper_float32_to_float64(arg1, t1);
3379
    tcg_temp_free_i32(t1);
3380
}
3381

    
3382
 /* lfd lfdu lfdux lfdx */
3383
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3384
 /* lfs lfsu lfsux lfsx */
3385
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3386

    
3387
/***                         Floating-point store                          ***/
3388
#define GEN_STF(name, stop, opc, type)                                        \
3389
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
3390
{                                                                             \
3391
    TCGv EA;                                                                  \
3392
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3393
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3394
        return;                                                               \
3395
    }                                                                         \
3396
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3397
    EA = tcg_temp_new();                                                      \
3398
    gen_addr_imm_index(ctx, EA, 0);                                           \
3399
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3400
    tcg_temp_free(EA);                                                        \
3401
}
3402

    
3403
#define GEN_STUF(name, stop, opc, type)                                       \
3404
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
3405
{                                                                             \
3406
    TCGv EA;                                                                  \
3407
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3408
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3409
        return;                                                               \
3410
    }                                                                         \
3411
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3412
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3413
        return;                                                               \
3414
    }                                                                         \
3415
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3416
    EA = tcg_temp_new();                                                      \
3417
    gen_addr_imm_index(ctx, EA, 0);                                           \
3418
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3419
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3420
    tcg_temp_free(EA);                                                        \
3421
}
3422

    
3423
#define GEN_STUXF(name, stop, opc, type)                                      \
3424
GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type)                      \
3425
{                                                                             \
3426
    TCGv EA;                                                                  \
3427
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3428
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3429
        return;                                                               \
3430
    }                                                                         \
3431
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3432
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3433
        return;                                                               \
3434
    }                                                                         \
3435
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3436
    EA = tcg_temp_new();                                                      \
3437
    gen_addr_reg_index(ctx, EA);                                              \
3438
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3439
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3440
    tcg_temp_free(EA);                                                        \
3441
}
3442

    
3443
#define GEN_STXF(name, stop, opc2, opc3, type)                                \
3444
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
3445
{                                                                             \
3446
    TCGv EA;                                                                  \
3447
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3448
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3449
        return;                                                               \
3450
    }                                                                         \
3451
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3452
    EA = tcg_temp_new();                                                      \
3453
    gen_addr_reg_index(ctx, EA);                                              \
3454
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3455
    tcg_temp_free(EA);                                                        \
3456
}
3457

    
3458
#define GEN_STFS(name, stop, op, type)                                        \
3459
GEN_STF(name, stop, op | 0x20, type);                                         \
3460
GEN_STUF(name, stop, op | 0x21, type);                                        \
3461
GEN_STUXF(name, stop, op | 0x01, type);                                       \
3462
GEN_STXF(name, stop, 0x17, op | 0x00, type)
3463

    
3464
static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3465
{
3466
    TCGv_i32 t0 = tcg_temp_new_i32();
3467
    TCGv t1 = tcg_temp_new();
3468
    gen_helper_float64_to_float32(t0, arg1);
3469
    tcg_gen_extu_i32_tl(t1, t0);
3470
    tcg_temp_free_i32(t0);
3471
    gen_qemu_st32(ctx, t1, arg2);
3472
    tcg_temp_free(t1);
3473
}
3474

    
3475
/* stfd stfdu stfdux stfdx */
3476
GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3477
/* stfs stfsu stfsux stfsx */
3478
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3479

    
3480
/* Optional: */
3481
static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3482
{
3483
    TCGv t0 = tcg_temp_new();
3484
    tcg_gen_trunc_i64_tl(t0, arg1),
3485
    gen_qemu_st32(ctx, t0, arg2);
3486
    tcg_temp_free(t0);
3487
}
3488
/* stfiwx */
3489
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3490

    
3491
/***                                Branch                                 ***/
3492
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3493
                                       target_ulong dest)
3494
{
3495
    TranslationBlock *tb;
3496
    tb = ctx->tb;
3497
#if defined(TARGET_PPC64)
3498
    if (!ctx->sf_mode)
3499
        dest = (uint32_t) dest;
3500
#endif
3501
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3502
        likely(!ctx->singlestep_enabled)) {
3503
        tcg_gen_goto_tb(n);
3504
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3505
        tcg_gen_exit_tb((long)tb + n);
3506
    } else {
3507
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3508
        if (unlikely(ctx->singlestep_enabled)) {
3509
            if ((ctx->singlestep_enabled &
3510
                (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3511
                ctx->exception == POWERPC_EXCP_BRANCH) {
3512
                target_ulong tmp = ctx->nip;
3513
                ctx->nip = dest;
3514
                gen_exception(ctx, POWERPC_EXCP_TRACE);
3515
                ctx->nip = tmp;
3516
            }
3517
            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3518
                gen_debug_exception(ctx);
3519
            }
3520
        }
3521
        tcg_gen_exit_tb(0);
3522
    }
3523
}
3524

    
3525
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3526
{
3527
#if defined(TARGET_PPC64)
3528
    if (ctx->sf_mode == 0)
3529
        tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3530
    else
3531
#endif
3532
        tcg_gen_movi_tl(cpu_lr, nip);
3533
}
3534

    
3535
/* b ba bl bla */
3536
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3537
{
3538
    target_ulong li, target;
3539

    
3540
    ctx->exception = POWERPC_EXCP_BRANCH;
3541
    /* sign extend LI */
3542
#if defined(TARGET_PPC64)
3543
    if (ctx->sf_mode)
3544
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3545
    else
3546
#endif
3547
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3548
    if (likely(AA(ctx->opcode) == 0))
3549
        target = ctx->nip + li - 4;
3550
    else
3551
        target = li;
3552
    if (LK(ctx->opcode))
3553
        gen_setlr(ctx, ctx->nip);
3554
    gen_goto_tb(ctx, 0, target);
3555
}
3556

    
3557
#define BCOND_IM  0
3558
#define BCOND_LR  1
3559
#define BCOND_CTR 2
3560

    
3561
static always_inline void gen_bcond (DisasContext *ctx, int type)
3562
{
3563
    uint32_t bo = BO(ctx->opcode);
3564
    int l1 = gen_new_label();
3565
    TCGv target;
3566

    
3567
    ctx->exception = POWERPC_EXCP_BRANCH;
3568
    if (type == BCOND_LR || type == BCOND_CTR) {
3569
        target = tcg_temp_local_new();
3570
        if (type == BCOND_CTR)
3571
            tcg_gen_mov_tl(target, cpu_ctr);
3572
        else
3573
            tcg_gen_mov_tl(target, cpu_lr);
3574
    }
3575
    if (LK(ctx->opcode))
3576
        gen_setlr(ctx, ctx->nip);
3577
    l1 = gen_new_label();
3578
    if ((bo & 0x4) == 0) {
3579
        /* Decrement and test CTR */
3580
        TCGv temp = tcg_temp_new();
3581
        if (unlikely(type == BCOND_CTR)) {
3582
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3583
            return;
3584
        }
3585
        tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3586
#if defined(TARGET_PPC64)
3587
        if (!ctx->sf_mode)
3588
            tcg_gen_ext32u_tl(temp, cpu_ctr);
3589
        else
3590
#endif
3591
            tcg_gen_mov_tl(temp, cpu_ctr);
3592
        if (bo & 0x2) {
3593
            tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3594
        } else {
3595
            tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3596
        }
3597
        tcg_temp_free(temp);
3598
    }
3599
    if ((bo & 0x10) == 0) {
3600
        /* Test CR */
3601
        uint32_t bi = BI(ctx->opcode);
3602
        uint32_t mask = 1 << (3 - (bi & 0x03));
3603
        TCGv_i32 temp = tcg_temp_new_i32();
3604

    
3605
        if (bo & 0x8) {
3606
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3607
            tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3608
        } else {
3609
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3610
            tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3611
        }
3612
        tcg_temp_free_i32(temp);
3613
    }
3614
    if (type == BCOND_IM) {
3615
        target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3616
        if (likely(AA(ctx->opcode) == 0)) {
3617
            gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3618
        } else {
3619
            gen_goto_tb(ctx, 0, li);
3620
        }
3621
        gen_set_label(l1);
3622
        gen_goto_tb(ctx, 1, ctx->nip);
3623
    } else {
3624
#if defined(TARGET_PPC64)
3625
        if (!(ctx->sf_mode))
3626
            tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3627
        else
3628
#endif
3629
            tcg_gen_andi_tl(cpu_nip, target, ~3);
3630
        tcg_gen_exit_tb(0);
3631
        gen_set_label(l1);
3632
#if defined(TARGET_PPC64)
3633
        if (!(ctx->sf_mode))
3634
            tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3635
        else
3636
#endif
3637
            tcg_gen_movi_tl(cpu_nip, ctx->nip);
3638
        tcg_gen_exit_tb(0);
3639
    }
3640
}
3641

    
3642
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3643
{
3644
    gen_bcond(ctx, BCOND_IM);
3645
}
3646

    
3647
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3648
{
3649
    gen_bcond(ctx, BCOND_CTR);
3650
}
3651

    
3652
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3653
{
3654
    gen_bcond(ctx, BCOND_LR);
3655
}
3656

    
3657
/***                      Condition register logical                       ***/
3658
#define GEN_CRLOGIC(name, tcg_op, opc)                                        \
3659
GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                   \
3660
{                                                                             \
3661
    uint8_t bitmask;                                                          \
3662
    int sh;                                                                   \
3663
    TCGv_i32 t0, t1;                                                          \
3664
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3665
    t0 = tcg_temp_new_i32();                                                  \
3666
    if (sh > 0)                                                               \
3667
        tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
3668
    else if (sh < 0)                                                          \
3669
        tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
3670
    else                                                                      \
3671
        tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
3672
    t1 = tcg_temp_new_i32();                                                  \
3673
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3674
    if (sh > 0)                                                               \
3675
        tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
3676
    else if (sh < 0)                                                          \
3677
        tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
3678
    else                                                                      \
3679
        tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
3680
    tcg_op(t0, t0, t1);                                                       \
3681
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3682
    tcg_gen_andi_i32(t0, t0, bitmask);                                        \
3683
    tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
3684
    tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
3685
    tcg_temp_free_i32(t0);                                                    \
3686
    tcg_temp_free_i32(t1);                                                    \
3687
}
3688

    
3689
/* crand */
3690
GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3691
/* crandc */
3692
GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3693
/* creqv */
3694
GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3695
/* crnand */
3696
GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3697
/* crnor */
3698
GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3699
/* cror */
3700
GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3701
/* crorc */
3702
GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3703
/* crxor */
3704
GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3705
/* mcrf */
3706
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3707
{
3708
    tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3709
}
3710

    
3711
/***                           System linkage                              ***/
3712
/* rfi (mem_idx only) */
3713
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3714
{
3715
#if defined(CONFIG_USER_ONLY)
3716
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3717
#else
3718
    /* Restore CPU state */
3719
    if (unlikely(!ctx->mem_idx)) {
3720
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3721
        return;
3722
    }
3723
    gen_helper_rfi();
3724
    gen_sync_exception(ctx);
3725
#endif
3726
}
3727

    
3728
#if defined(TARGET_PPC64)
3729
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3730
{
3731
#if defined(CONFIG_USER_ONLY)
3732
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3733
#else
3734
    /* Restore CPU state */
3735
    if (unlikely(!ctx->mem_idx)) {
3736
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3737
        return;
3738
    }
3739
    gen_helper_rfid();
3740
    gen_sync_exception(ctx);
3741
#endif
3742
}
3743

    
3744
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3745
{
3746
#if defined(CONFIG_USER_ONLY)
3747
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3748
#else
3749
    /* Restore CPU state */
3750
    if (unlikely(ctx->mem_idx <= 1)) {
3751
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3752
        return;
3753
    }
3754
    gen_helper_hrfid();
3755
    gen_sync_exception(ctx);
3756
#endif
3757
}
3758
#endif
3759

    
3760
/* sc */
3761
#if defined(CONFIG_USER_ONLY)
3762
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3763
#else
3764
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3765
#endif
3766
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3767
{
3768
    uint32_t lev;
3769

    
3770
    lev = (ctx->opcode >> 5) & 0x7F;
3771
    gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3772
}
3773

    
3774
/***                                Trap                                   ***/
3775
/* tw */
3776
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3777
{
3778
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3779
    /* Update the nip since this might generate a trap exception */
3780
    gen_update_nip(ctx, ctx->nip);
3781
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3782
    tcg_temp_free_i32(t0);
3783
}
3784

    
3785
/* twi */
3786
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3787
{
3788
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3789
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3790
    /* Update the nip since this might generate a trap exception */
3791
    gen_update_nip(ctx, ctx->nip);
3792
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3793
    tcg_temp_free(t0);
3794
    tcg_temp_free_i32(t1);
3795
}
3796

    
3797
#if defined(TARGET_PPC64)
3798
/* td */
3799
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3800
{
3801
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3802
    /* Update the nip since this might generate a trap exception */
3803
    gen_update_nip(ctx, ctx->nip);
3804
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3805
    tcg_temp_free_i32(t0);
3806
}
3807

    
3808
/* tdi */
3809
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3810
{
3811
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3812
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3813
    /* Update the nip since this might generate a trap exception */
3814
    gen_update_nip(ctx, ctx->nip);
3815
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3816
    tcg_temp_free(t0);
3817
    tcg_temp_free_i32(t1);
3818
}
3819
#endif
3820

    
3821
/***                          Processor control                            ***/
3822
/* mcrxr */
3823
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3824
{
3825
    tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3826
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3827
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3828
}
3829

    
3830
/* mfcr */
3831
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3832
{
3833
    uint32_t crm, crn;
3834

    
3835
    if (likely(ctx->opcode & 0x00100000)) {
3836
        crm = CRM(ctx->opcode);
3837
        if (likely((crm ^ (crm - 1)) == 0)) {
3838
            crn = ffs(crm);
3839
            tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3840
        }
3841
    } else {
3842
        gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3843
    }
3844
}
3845

    
3846
/* mfmsr */
3847
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3848
{
3849
#if defined(CONFIG_USER_ONLY)
3850
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3851
#else
3852
    if (unlikely(!ctx->mem_idx)) {
3853
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3854
        return;
3855
    }
3856
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3857
#endif
3858
}
3859

    
3860
#if 1
3861
#define SPR_NOACCESS ((void *)(-1UL))
3862
#else
3863
static void spr_noaccess (void *opaque, int sprn)
3864
{
3865
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3866
    printf("ERROR: try to access SPR %d !\n", sprn);
3867
}
3868
#define SPR_NOACCESS (&spr_noaccess)
3869
#endif
3870

    
3871
/* mfspr */
3872
static always_inline void gen_op_mfspr (DisasContext *ctx)
3873
{
3874
    void (*read_cb)(void *opaque, int gprn, int sprn);
3875
    uint32_t sprn = SPR(ctx->opcode);
3876

    
3877
#if !defined(CONFIG_USER_ONLY)
3878
    if (ctx->mem_idx == 2)
3879
        read_cb = ctx->spr_cb[sprn].hea_read;
3880
    else if (ctx->mem_idx)
3881
        read_cb = ctx->spr_cb[sprn].oea_read;
3882
    else
3883
#endif
3884
        read_cb = ctx->spr_cb[sprn].uea_read;
3885
    if (likely(read_cb != NULL)) {
3886
        if (likely(read_cb != SPR_NOACCESS)) {
3887
            (*read_cb)(ctx, rD(ctx->opcode), sprn);
3888
        } else {
3889
            /* Privilege exception */
3890
            /* This is a hack to avoid warnings when running Linux:
3891
             * this OS breaks the PowerPC virtualisation model,
3892
             * allowing userland application to read the PVR
3893
             */
3894
            if (sprn != SPR_PVR) {
3895
                if (loglevel != 0) {
3896
                    fprintf(logfile, "Trying to read privileged spr %d %03x at "
3897
                            ADDRX "\n", sprn, sprn, ctx->nip);
3898
                }
3899
                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3900
                       sprn, sprn, ctx->nip);
3901
            }
3902
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3903
        }
3904
    } else {
3905
        /* Not defined */
3906
        if (loglevel != 0) {
3907
            fprintf(logfile, "Trying to read invalid spr %d %03x at "
3908
                    ADDRX "\n", sprn, sprn, ctx->nip);
3909
        }
3910
        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3911
               sprn, sprn, ctx->nip);
3912
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3913
    }
3914
}
3915

    
3916
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3917
{
3918
    gen_op_mfspr(ctx);
3919
}
3920

    
3921
/* mftb */
3922
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3923
{
3924
    gen_op_mfspr(ctx);
3925
}
3926

    
3927
/* mtcrf */
3928
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3929
{
3930
    uint32_t crm, crn;
3931

    
3932
    crm = CRM(ctx->opcode);
3933
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3934
        TCGv_i32 temp = tcg_temp_new_i32();
3935
        crn = ffs(crm);
3936
        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3937
        tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3938
        tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3939
        tcg_temp_free_i32(temp);
3940
    } else {
3941
        TCGv_i32 temp = tcg_const_i32(crm);
3942
        gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3943
        tcg_temp_free_i32(temp);
3944
    }
3945
}
3946

    
3947
/* mtmsr */
3948
#if defined(TARGET_PPC64)
3949
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3950
{
3951
#if defined(CONFIG_USER_ONLY)
3952
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3953
#else
3954
    if (unlikely(!ctx->mem_idx)) {
3955
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3956
        return;
3957
    }
3958
    if (ctx->opcode & 0x00010000) {
3959
        /* Special form that does not need any synchronisation */
3960
        TCGv t0 = tcg_temp_new();
3961
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3962
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3963
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3964
        tcg_temp_free(t0);
3965
    } else {
3966
        /* XXX: we need to update nip before the store
3967
         *      if we enter power saving mode, we will exit the loop
3968
         *      directly from ppc_store_msr
3969
         */
3970
        gen_update_nip(ctx, ctx->nip);
3971
        gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3972
        /* Must stop the translation as machine state (may have) changed */
3973
        /* Note that mtmsr is not always defined as context-synchronizing */
3974
        gen_stop_exception(ctx);
3975
    }
3976
#endif
3977
}
3978
#endif
3979

    
3980
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3981
{
3982
#if defined(CONFIG_USER_ONLY)
3983
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3984
#else
3985
    if (unlikely(!ctx->mem_idx)) {
3986
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3987
        return;
3988
    }
3989
    if (ctx->opcode & 0x00010000) {
3990
        /* Special form that does not need any synchronisation */
3991
        TCGv t0 = tcg_temp_new();
3992
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3993
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3994
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3995
        tcg_temp_free(t0);
3996
    } else {
3997
        /* XXX: we need to update nip before the store
3998
         *      if we enter power saving mode, we will exit the loop
3999
         *      directly from ppc_store_msr
4000
         */
4001
        gen_update_nip(ctx, ctx->nip);
4002
#if defined(TARGET_PPC64)
4003
        if (!ctx->sf_mode) {
4004
            TCGv t0 = tcg_temp_new();
4005
            TCGv t1 = tcg_temp_new();
4006
            tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4007
            tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4008
            tcg_gen_or_tl(t0, t0, t1);
4009
            tcg_temp_free(t1);
4010
            gen_helper_store_msr(t0);
4011
            tcg_temp_free(t0);
4012
        } else
4013
#endif
4014
            gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4015
        /* Must stop the translation as machine state (may have) changed */
4016
        /* Note that mtmsr is not always defined as context-synchronizing */
4017
        gen_stop_exception(ctx);
4018
    }
4019
#endif
4020
}
4021

    
4022
/* mtspr */
4023
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4024
{
4025
    void (*write_cb)(void *opaque, int sprn, int gprn);
4026
    uint32_t sprn = SPR(ctx->opcode);
4027

    
4028
#if !defined(CONFIG_USER_ONLY)
4029
    if (ctx->mem_idx == 2)
4030
        write_cb = ctx->spr_cb[sprn].hea_write;
4031
    else if (ctx->mem_idx)
4032
        write_cb = ctx->spr_cb[sprn].oea_write;
4033
    else
4034
#endif
4035
        write_cb = ctx->spr_cb[sprn].uea_write;
4036
    if (likely(write_cb != NULL)) {
4037
        if (likely(write_cb != SPR_NOACCESS)) {
4038
            (*write_cb)(ctx, sprn, rS(ctx->opcode));
4039
        } else {
4040
            /* Privilege exception */
4041
            if (loglevel != 0) {
4042
                fprintf(logfile, "Trying to write privileged spr %d %03x at "
4043
                        ADDRX "\n", sprn, sprn, ctx->nip);
4044
            }
4045
            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4046
                   sprn, sprn, ctx->nip);
4047
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4048
        }
4049
    } else {
4050
        /* Not defined */
4051
        if (loglevel != 0) {
4052
            fprintf(logfile, "Trying to write invalid spr %d %03x at "
4053
                    ADDRX "\n", sprn, sprn, ctx->nip);
4054
        }
4055
        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4056
               sprn, sprn, ctx->nip);
4057
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4058
    }
4059
}
4060

    
4061
/***                         Cache management                              ***/
4062
/* dcbf */
4063
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4064
{
4065
    /* XXX: specification says this is treated as a load by the MMU */
4066
    TCGv t0;
4067
    gen_set_access_type(ctx, ACCESS_CACHE);
4068
    t0 = tcg_temp_new();
4069
    gen_addr_reg_index(ctx, t0);
4070
    gen_qemu_ld8u(ctx, t0, t0);
4071
    tcg_temp_free(t0);
4072
}
4073

    
4074
/* dcbi (Supervisor only) */
4075
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4076
{
4077
#if defined(CONFIG_USER_ONLY)
4078
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4079
#else
4080
    TCGv EA, val;
4081
    if (unlikely(!ctx->mem_idx)) {
4082
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4083
        return;
4084
    }
4085
    EA = tcg_temp_new();
4086
    gen_set_access_type(ctx, ACCESS_CACHE);
4087
    gen_addr_reg_index(ctx, EA);
4088
    val = tcg_temp_new();
4089
    /* XXX: specification says this should be treated as a store by the MMU */
4090
    gen_qemu_ld8u(ctx, val, EA);
4091
    gen_qemu_st8(ctx, val, EA);
4092
    tcg_temp_free(val);
4093
    tcg_temp_free(EA);
4094
#endif
4095
}
4096

    
4097
/* dcdst */
4098
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4099
{
4100
    /* XXX: specification say this is treated as a load by the MMU */
4101
    TCGv t0;
4102
    gen_set_access_type(ctx, ACCESS_CACHE);
4103
    t0 = tcg_temp_new();
4104
    gen_addr_reg_index(ctx, t0);
4105
    gen_qemu_ld8u(ctx, t0, t0);
4106
    tcg_temp_free(t0);
4107
}
4108

    
4109
/* dcbt */
4110
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4111
{
4112
    /* interpreted as no-op */
4113
    /* XXX: specification say this is treated as a load by the MMU
4114
     *      but does not generate any exception
4115
     */
4116
}
4117

    
4118
/* dcbtst */
4119
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4120
{
4121
    /* interpreted as no-op */
4122
    /* XXX: specification say this is treated as a load by the MMU
4123
     *      but does not generate any exception
4124
     */
4125
}
4126

    
4127
/* dcbz */
4128
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4129
{
4130
    TCGv t0;
4131
    gen_set_access_type(ctx, ACCESS_CACHE);
4132
    /* NIP cannot be restored if the memory exception comes from an helper */
4133
    gen_update_nip(ctx, ctx->nip - 4);
4134
    t0 = tcg_temp_new();
4135
    gen_addr_reg_index(ctx, t0);
4136
    gen_helper_dcbz(t0);
4137
    tcg_temp_free(t0);
4138
}
4139

    
4140
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4141
{
4142
    TCGv t0;
4143
    gen_set_access_type(ctx, ACCESS_CACHE);
4144
    /* NIP cannot be restored if the memory exception comes from an helper */
4145
    gen_update_nip(ctx, ctx->nip - 4);
4146
    t0 = tcg_temp_new();
4147
    gen_addr_reg_index(ctx, t0);
4148
    if (ctx->opcode & 0x00200000)
4149
        gen_helper_dcbz(t0);
4150
    else
4151
        gen_helper_dcbz_970(t0);
4152
    tcg_temp_free(t0);
4153
}
4154

    
4155
/* icbi */
4156
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4157
{
4158
    TCGv t0;
4159
    gen_set_access_type(ctx, ACCESS_CACHE);
4160
    /* NIP cannot be restored if the memory exception comes from an helper */
4161
    gen_update_nip(ctx, ctx->nip - 4);
4162
    t0 = tcg_temp_new();
4163
    gen_addr_reg_index(ctx, t0);
4164
    gen_helper_icbi(t0);
4165
    tcg_temp_free(t0);
4166
}
4167

    
4168
/* Optional: */
4169
/* dcba */
4170
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4171
{
4172
    /* interpreted as no-op */
4173
    /* XXX: specification say this is treated as a store by the MMU
4174
     *      but does not generate any exception
4175
     */
4176
}
4177

    
4178
/***                    Segment register manipulation                      ***/
4179
/* Supervisor only: */
4180
/* mfsr */
4181
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4182
{
4183
#if defined(CONFIG_USER_ONLY)
4184
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185
#else
4186
    TCGv t0;
4187
    if (unlikely(!ctx->mem_idx)) {
4188
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189
        return;
4190
    }
4191
    t0 = tcg_const_tl(SR(ctx->opcode));
4192
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4193
    tcg_temp_free(t0);
4194
#endif
4195
}
4196

    
4197
/* mfsrin */
4198
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4199
{
4200
#if defined(CONFIG_USER_ONLY)
4201
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202
#else
4203
    TCGv t0;
4204
    if (unlikely(!ctx->mem_idx)) {
4205
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4206
        return;
4207
    }
4208
    t0 = tcg_temp_new();
4209
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4210
    tcg_gen_andi_tl(t0, t0, 0xF);
4211
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4212
    tcg_temp_free(t0);
4213
#endif
4214
}
4215

    
4216
/* mtsr */
4217
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4218
{
4219
#if defined(CONFIG_USER_ONLY)
4220
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221
#else
4222
    TCGv t0;
4223
    if (unlikely(!ctx->mem_idx)) {
4224
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4225
        return;
4226
    }
4227
    t0 = tcg_const_tl(SR(ctx->opcode));
4228
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4229
    tcg_temp_free(t0);
4230
#endif
4231
}
4232

    
4233
/* mtsrin */
4234
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4235
{
4236
#if defined(CONFIG_USER_ONLY)
4237
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4238
#else
4239
    TCGv t0;
4240
    if (unlikely(!ctx->mem_idx)) {
4241
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4242
        return;
4243
    }
4244
    t0 = tcg_temp_new();
4245
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4246
    tcg_gen_andi_tl(t0, t0, 0xF);
4247
    gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4248
    tcg_temp_free(t0);
4249
#endif
4250
}
4251

    
4252
#if defined(TARGET_PPC64)
4253
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4254
/* mfsr */
4255
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4256
{
4257
#if defined(CONFIG_USER_ONLY)
4258
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259
#else
4260
    TCGv t0;
4261
    if (unlikely(!ctx->mem_idx)) {
4262
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4263
        return;
4264
    }
4265
    t0 = tcg_const_tl(SR(ctx->opcode));
4266
    gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4267
    tcg_temp_free(t0);
4268
#endif
4269
}
4270

    
4271
/* mfsrin */
4272
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4273
             PPC_SEGMENT_64B)
4274
{
4275
#if defined(CONFIG_USER_ONLY)
4276
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4277
#else
4278
    TCGv t0;
4279
    if (unlikely(!ctx->mem_idx)) {
4280
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4281
        return;
4282
    }
4283
    t0 = tcg_temp_new();
4284
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4285
    tcg_gen_andi_tl(t0, t0, 0xF);
4286
    gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4287
    tcg_temp_free(t0);
4288
#endif
4289
}
4290

    
4291
/* mtsr */
4292
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4293
{
4294
#if defined(CONFIG_USER_ONLY)
4295
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296
#else
4297
    TCGv t0;
4298
    if (unlikely(!ctx->mem_idx)) {
4299
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300
        return;
4301
    }
4302
    t0 = tcg_const_tl(SR(ctx->opcode));
4303
    gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4304
    tcg_temp_free(t0);
4305
#endif
4306
}
4307

    
4308
/* mtsrin */
4309
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4310
             PPC_SEGMENT_64B)
4311
{
4312
#if defined(CONFIG_USER_ONLY)
4313
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4314
#else
4315
    TCGv t0;
4316
    if (unlikely(!ctx->mem_idx)) {
4317
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4318
        return;
4319
    }
4320
    t0 = tcg_temp_new();
4321
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4322
    tcg_gen_andi_tl(t0, t0, 0xF);
4323
    gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4324
    tcg_temp_free(t0);
4325
#endif
4326
}
4327
#endif /* defined(TARGET_PPC64) */
4328

    
4329
/***                      Lookaside buffer management                      ***/
4330
/* Optional & mem_idx only: */
4331
/* tlbia */
4332
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4333
{
4334
#if defined(CONFIG_USER_ONLY)
4335
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4336
#else
4337
    if (unlikely(!ctx->mem_idx)) {
4338
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4339
        return;
4340
    }
4341
    gen_helper_tlbia();
4342
#endif
4343
}
4344

    
4345
/* tlbie */
4346
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4347
{
4348
#if defined(CONFIG_USER_ONLY)
4349
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4350
#else
4351
    if (unlikely(!ctx->mem_idx)) {
4352
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4353
        return;
4354
    }
4355
#if defined(TARGET_PPC64)
4356
    if (!ctx->sf_mode) {
4357
        TCGv t0 = tcg_temp_new();
4358
        tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4359
        gen_helper_tlbie(t0);
4360
        tcg_temp_free(t0);
4361
    } else
4362
#endif
4363
        gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4364
#endif
4365
}
4366

    
4367
/* tlbsync */
4368
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4369
{
4370
#if defined(CONFIG_USER_ONLY)
4371
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4372
#else
4373
    if (unlikely(!ctx->mem_idx)) {
4374
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4375
        return;
4376
    }
4377
    /* This has no effect: it should ensure that all previous
4378
     * tlbie have completed
4379
     */
4380
    gen_stop_exception(ctx);
4381
#endif
4382
}
4383

    
4384
#if defined(TARGET_PPC64)
4385
/* slbia */
4386
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4387
{
4388
#if defined(CONFIG_USER_ONLY)
4389
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4390
#else
4391
    if (unlikely(!ctx->mem_idx)) {
4392
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4393
        return;
4394
    }
4395
    gen_helper_slbia();
4396
#endif
4397
}
4398

    
4399
/* slbie */
4400
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4401
{
4402
#if defined(CONFIG_USER_ONLY)
4403
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4404
#else
4405
    if (unlikely(!ctx->mem_idx)) {
4406
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4407
        return;
4408
    }
4409
    gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4410
#endif
4411
}
4412
#endif
4413

    
4414
/***                              External control                         ***/
4415
/* Optional: */
4416
/* eciwx */
4417
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4418
{
4419
    TCGv t0;
4420
    /* Should check EAR[E] ! */
4421
    gen_set_access_type(ctx, ACCESS_EXT);
4422
    t0 = tcg_temp_new();
4423
    gen_addr_reg_index(ctx, t0);
4424
    gen_check_align(ctx, t0, 0x03);
4425
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4426
    tcg_temp_free(t0);
4427
}
4428

    
4429
/* ecowx */
4430
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4431
{
4432
    TCGv t0;
4433
    /* Should check EAR[E] ! */
4434
    gen_set_access_type(ctx, ACCESS_EXT);
4435
    t0 = tcg_temp_new();
4436
    gen_addr_reg_index(ctx, t0);
4437
    gen_check_align(ctx, t0, 0x03);
4438
    gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4439
    tcg_temp_free(t0);
4440
}
4441

    
4442
/* PowerPC 601 specific instructions */
4443
/* abs - abs. */
4444
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4445
{
4446
    int l1 = gen_new_label();
4447
    int l2 = gen_new_label();
4448
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4449
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4450
    tcg_gen_br(l2);
4451
    gen_set_label(l1);
4452
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4453
    gen_set_label(l2);
4454
    if (unlikely(Rc(ctx->opcode) != 0))
4455
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4456
}
4457

    
4458
/* abso - abso. */
4459
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4460
{
4461
    int l1 = gen_new_label();
4462
    int l2 = gen_new_label();
4463
    int l3 = gen_new_label();
4464
    /* Start with XER OV disabled, the most likely case */
4465
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4466
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4467
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4468
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4469
    tcg_gen_br(l2);
4470
    gen_set_label(l1);
4471
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4472
    tcg_gen_br(l3);
4473
    gen_set_label(l2);
4474
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4475
    gen_set_label(l3);
4476
    if (unlikely(Rc(ctx->opcode) != 0))
4477
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4478
}
4479

    
4480
/* clcs */
4481
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4482
{
4483
    TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4484
    gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4485
    tcg_temp_free_i32(t0);
4486
    /* Rc=1 sets CR0 to an undefined state */
4487
}
4488

    
4489
/* div - div. */
4490
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4491
{
4492
    gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4493
    if (unlikely(Rc(ctx->opcode) != 0))
4494
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4495
}
4496

    
4497
/* divo - divo. */
4498
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4499
{
4500
    gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4501
    if (unlikely(Rc(ctx->opcode) != 0))
4502
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4503
}
4504

    
4505
/* divs - divs. */
4506
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4507
{
4508
    gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4509
    if (unlikely(Rc(ctx->opcode) != 0))
4510
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4511
}
4512

    
4513
/* divso - divso. */
4514
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4515
{
4516
    gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4517
    if (unlikely(Rc(ctx->opcode) != 0))
4518
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4519
}
4520

    
4521
/* doz - doz. */
4522
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4523
{
4524
    int l1 = gen_new_label();
4525
    int l2 = gen_new_label();
4526
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4527
    tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4528
    tcg_gen_br(l2);
4529
    gen_set_label(l1);
4530
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4531
    gen_set_label(l2);
4532
    if (unlikely(Rc(ctx->opcode) != 0))
4533
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4534
}
4535

    
4536
/* dozo - dozo. */
4537
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4538
{
4539
    int l1 = gen_new_label();
4540
    int l2 = gen_new_label();
4541
    TCGv t0 = tcg_temp_new();
4542
    TCGv t1 = tcg_temp_new();
4543
    TCGv t2 = tcg_temp_new();
4544
    /* Start with XER OV disabled, the most likely case */
4545
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4546
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4547
    tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4548
    tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4549
    tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4550
    tcg_gen_andc_tl(t1, t1, t2);
4551
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4552
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4553
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4554
    tcg_gen_br(l2);
4555
    gen_set_label(l1);
4556
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4557
    gen_set_label(l2);
4558
    tcg_temp_free(t0);
4559
    tcg_temp_free(t1);
4560
    tcg_temp_free(t2);
4561
    if (unlikely(Rc(ctx->opcode) != 0))
4562
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4563
}
4564

    
4565
/* dozi */
4566
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4567
{
4568
    target_long simm = SIMM(ctx->opcode);
4569
    int l1 = gen_new_label();
4570
    int l2 = gen_new_label();
4571
    tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4572
    tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4573
    tcg_gen_br(l2);
4574
    gen_set_label(l1);
4575
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4576
    gen_set_label(l2);
4577
    if (unlikely(Rc(ctx->opcode) != 0))
4578
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4579
}
4580

    
4581
/* lscbx - lscbx. */
4582
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4583
{
4584
    TCGv t0 = tcg_temp_new();
4585
    TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4586
    TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4587
    TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4588

    
4589
    gen_addr_reg_index(ctx, t0);
4590
    /* NIP cannot be restored if the memory exception comes from an helper */
4591
    gen_update_nip(ctx, ctx->nip - 4);
4592
    gen_helper_lscbx(t0, t0, t1, t2, t3);
4593
    tcg_temp_free_i32(t1);
4594
    tcg_temp_free_i32(t2);
4595
    tcg_temp_free_i32(t3);
4596
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4597
    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4598
    if (unlikely(Rc(ctx->opcode) != 0))
4599
        gen_set_Rc0(ctx, t0);
4600
    tcg_temp_free(t0);
4601
}
4602

    
4603
/* maskg - maskg. */
4604
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4605
{
4606
    int l1 = gen_new_label();
4607
    TCGv t0 = tcg_temp_new();
4608
    TCGv t1 = tcg_temp_new();
4609
    TCGv t2 = tcg_temp_new();
4610
    TCGv t3 = tcg_temp_new();
4611
    tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4612
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4613
    tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4614
    tcg_gen_addi_tl(t2, t0, 1);
4615
    tcg_gen_shr_tl(t2, t3, t2);
4616
    tcg_gen_shr_tl(t3, t3, t1);
4617
    tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4618
    tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4619
    tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4620
    gen_set_label(l1);
4621
    tcg_temp_free(t0);
4622
    tcg_temp_free(t1);
4623
    tcg_temp_free(t2);
4624
    tcg_temp_free(t3);
4625
    if (unlikely(Rc(ctx->opcode) != 0))
4626
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4627
}
4628

    
4629
/* maskir - maskir. */
4630
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4631
{
4632
    TCGv t0 = tcg_temp_new();
4633
    TCGv t1 = tcg_temp_new();
4634
    tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4635
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4636
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4637
    tcg_temp_free(t0);
4638
    tcg_temp_free(t1);
4639
    if (unlikely(Rc(ctx->opcode) != 0))
4640
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4641
}
4642

    
4643
/* mul - mul. */
4644
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4645
{
4646
    TCGv_i64 t0 = tcg_temp_new_i64();
4647
    TCGv_i64 t1 = tcg_temp_new_i64();
4648
    TCGv t2 = tcg_temp_new();
4649
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4650
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4651
    tcg_gen_mul_i64(t0, t0, t1);
4652
    tcg_gen_trunc_i64_tl(t2, t0);
4653
    gen_store_spr(SPR_MQ, t2);
4654
    tcg_gen_shri_i64(t1, t0, 32);
4655
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4656
    tcg_temp_free_i64(t0);
4657
    tcg_temp_free_i64(t1);
4658
    tcg_temp_free(t2);
4659
    if (unlikely(Rc(ctx->opcode) != 0))
4660
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4661
}
4662

    
4663
/* mulo - mulo. */
4664
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4665
{
4666
    int l1 = gen_new_label();
4667
    TCGv_i64 t0 = tcg_temp_new_i64();
4668
    TCGv_i64 t1 = tcg_temp_new_i64();
4669
    TCGv t2 = tcg_temp_new();
4670
    /* Start with XER OV disabled, the most likely case */
4671
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4672
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4673
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4674
    tcg_gen_mul_i64(t0, t0, t1);
4675
    tcg_gen_trunc_i64_tl(t2, t0);
4676
    gen_store_spr(SPR_MQ, t2);
4677
    tcg_gen_shri_i64(t1, t0, 32);
4678
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4679
    tcg_gen_ext32s_i64(t1, t0);
4680
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4681
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4682
    gen_set_label(l1);
4683
    tcg_temp_free_i64(t0);
4684
    tcg_temp_free_i64(t1);
4685
    tcg_temp_free(t2);
4686
    if (unlikely(Rc(ctx->opcode) != 0))
4687
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4688
}
4689

    
4690
/* nabs - nabs. */
4691
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4692
{
4693
    int l1 = gen_new_label();
4694
    int l2 = gen_new_label();
4695
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4696
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4697
    tcg_gen_br(l2);
4698
    gen_set_label(l1);
4699
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4700
    gen_set_label(l2);
4701
    if (unlikely(Rc(ctx->opcode) != 0))
4702
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4703
}
4704

    
4705
/* nabso - nabso. */
4706
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4707
{
4708
    int l1 = gen_new_label();
4709
    int l2 = gen_new_label();
4710
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4711
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4712
    tcg_gen_br(l2);
4713
    gen_set_label(l1);
4714
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4715
    gen_set_label(l2);
4716
    /* nabs never overflows */
4717
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4718
    if (unlikely(Rc(ctx->opcode) != 0))
4719
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4720
}
4721

    
4722
/* rlmi - rlmi. */
4723
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4724
{
4725
    uint32_t mb = MB(ctx->opcode);
4726
    uint32_t me = ME(ctx->opcode);
4727
    TCGv t0 = tcg_temp_new();
4728
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4729
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4730
    tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4731
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4732
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4733
    tcg_temp_free(t0);
4734
    if (unlikely(Rc(ctx->opcode) != 0))
4735
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4736
}
4737

    
4738
/* rrib - rrib. */
4739
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4740
{
4741
    TCGv t0 = tcg_temp_new();
4742
    TCGv t1 = tcg_temp_new();
4743
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4744
    tcg_gen_movi_tl(t1, 0x80000000);
4745
    tcg_gen_shr_tl(t1, t1, t0);
4746
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4747
    tcg_gen_and_tl(t0, t0, t1);
4748
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4749
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4750
    tcg_temp_free(t0);
4751
    tcg_temp_free(t1);
4752
    if (unlikely(Rc(ctx->opcode) != 0))
4753
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4754
}
4755

    
4756
/* sle - sle. */
4757
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4758
{
4759
    TCGv t0 = tcg_temp_new();
4760
    TCGv t1 = tcg_temp_new();
4761
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4762
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4763
    tcg_gen_subfi_tl(t1, 32, t1);
4764
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4765
    tcg_gen_or_tl(t1, t0, t1);
4766
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4767
    gen_store_spr(SPR_MQ, t1);
4768
    tcg_temp_free(t0);
4769
    tcg_temp_free(t1);
4770
    if (unlikely(Rc(ctx->opcode) != 0))
4771
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4772
}
4773

    
4774
/* sleq - sleq. */
4775
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4776
{
4777
    TCGv t0 = tcg_temp_new();
4778
    TCGv t1 = tcg_temp_new();
4779
    TCGv t2 = tcg_temp_new();
4780
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4781
    tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4782
    tcg_gen_shl_tl(t2, t2, t0);
4783
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4784
    gen_load_spr(t1, SPR_MQ);
4785
    gen_store_spr(SPR_MQ, t0);
4786
    tcg_gen_and_tl(t0, t0, t2);
4787
    tcg_gen_andc_tl(t1, t1, t2);
4788
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4789
    tcg_temp_free(t0);
4790
    tcg_temp_free(t1);
4791
    tcg_temp_free(t2);
4792
    if (unlikely(Rc(ctx->opcode) != 0))
4793
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4794
}
4795

    
4796
/* sliq - sliq. */
4797
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4798
{
4799
    int sh = SH(ctx->opcode);
4800
    TCGv t0 = tcg_temp_new();
4801
    TCGv t1 = tcg_temp_new();
4802
    tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4803
    tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4804
    tcg_gen_or_tl(t1, t0, t1);
4805
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4806
    gen_store_spr(SPR_MQ, t1);
4807
    tcg_temp_free(t0);
4808
    tcg_temp_free(t1);
4809
    if (unlikely(Rc(ctx->opcode) != 0))
4810
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4811
}
4812

    
4813
/* slliq - slliq. */
4814
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4815
{
4816
    int sh = SH(ctx->opcode);
4817
    TCGv t0 = tcg_temp_new();
4818
    TCGv t1 = tcg_temp_new();
4819
    tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4820
    gen_load_spr(t1, SPR_MQ);
4821
    gen_store_spr(SPR_MQ, t0);
4822
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU << sh));
4823
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4824
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4825
    tcg_temp_free(t0);
4826
    tcg_temp_free(t1);
4827
    if (unlikely(Rc(ctx->opcode) != 0))
4828
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4829
}
4830

    
4831
/* sllq - sllq. */
4832
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4833
{
4834
    int l1 = gen_new_label();
4835
    int l2 = gen_new_label();
4836
    TCGv t0 = tcg_temp_local_new();
4837
    TCGv t1 = tcg_temp_local_new();
4838
    TCGv t2 = tcg_temp_local_new();
4839
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4840
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4841
    tcg_gen_shl_tl(t1, t1, t2);
4842
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4843
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4844
    gen_load_spr(t0, SPR_MQ);
4845
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4846
    tcg_gen_br(l2);
4847
    gen_set_label(l1);
4848
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4849
    gen_load_spr(t2, SPR_MQ);
4850
    tcg_gen_andc_tl(t1, t2, t1);
4851
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4852
    gen_set_label(l2);
4853
    tcg_temp_free(t0);
4854
    tcg_temp_free(t1);
4855
    tcg_temp_free(t2);
4856
    if (unlikely(Rc(ctx->opcode) != 0))
4857
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4858
}
4859

    
4860
/* slq - slq. */
4861
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4862
{
4863
    int l1 = gen_new_label();
4864
    TCGv t0 = tcg_temp_new();
4865
    TCGv t1 = tcg_temp_new();
4866
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4867
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4868
    tcg_gen_subfi_tl(t1, 32, t1);
4869
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4870
    tcg_gen_or_tl(t1, t0, t1);
4871
    gen_store_spr(SPR_MQ, t1);
4872
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4873
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4874
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4875
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4876
    gen_set_label(l1);
4877
    tcg_temp_free(t0);
4878
    tcg_temp_free(t1);
4879
    if (unlikely(Rc(ctx->opcode) != 0))
4880
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4881
}
4882

    
4883
/* sraiq - sraiq. */
4884
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4885
{
4886
    int sh = SH(ctx->opcode);
4887
    int l1 = gen_new_label();
4888
    TCGv t0 = tcg_temp_new();
4889
    TCGv t1 = tcg_temp_new();
4890
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4891
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4892
    tcg_gen_or_tl(t0, t0, t1);
4893
    gen_store_spr(SPR_MQ, t0);
4894
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4895
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4896
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4897
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4898
    gen_set_label(l1);
4899
    tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4900
    tcg_temp_free(t0);
4901
    tcg_temp_free(t1);
4902
    if (unlikely(Rc(ctx->opcode) != 0))
4903
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4904
}
4905

    
4906
/* sraq - sraq. */
4907
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4908
{
4909
    int l1 = gen_new_label();
4910
    int l2 = gen_new_label();
4911
    TCGv t0 = tcg_temp_new();
4912
    TCGv t1 = tcg_temp_local_new();
4913
    TCGv t2 = tcg_temp_local_new();
4914
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4915
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4916
    tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4917
    tcg_gen_subfi_tl(t2, 32, t2);
4918
    tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4919
    tcg_gen_or_tl(t0, t0, t2);
4920
    gen_store_spr(SPR_MQ, t0);
4921
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4922
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4923
    tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4924
    tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4925
    gen_set_label(l1);
4926
    tcg_temp_free(t0);
4927
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4928
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4929
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4930
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4931
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4932
    gen_set_label(l2);
4933
    tcg_temp_free(t1);
4934
    tcg_temp_free(t2);
4935
    if (unlikely(Rc(ctx->opcode) != 0))
4936
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4937
}
<