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root / hw / alpha_pci.c @ 1de7afc9

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/*
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 * QEMU Alpha PCI support functions.
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 *
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 * Some of this isn't very Alpha specific at all.
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 *
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 * ??? Sparse memory access not implemented.
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 */
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#include "config.h"
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#include "alpha_sys.h"
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#include "qemu/log.h"
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#include "sysemu.h"
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/* PCI IO reads/writes, to byte-word addressable memory.  */
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/* ??? Doesn't handle multiple PCI busses.  */
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static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size)
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{
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    switch (size) {
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    case 1:
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        return cpu_inb(addr);
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    case 2:
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        return cpu_inw(addr);
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    case 4:
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        return cpu_inl(addr);
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    }
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    abort();
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}
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static void bw_io_write(void *opaque, hwaddr addr,
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                        uint64_t val, unsigned size)
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{
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    switch (size) {
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    case 1:
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        cpu_outb(addr, val);
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        break;
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    case 2:
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        cpu_outw(addr, val);
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        break;
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    case 4:
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        cpu_outl(addr, val);
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        break;
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    default:
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        abort();
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    }
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}
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const MemoryRegionOps alpha_pci_bw_io_ops = {
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    .read = bw_io_read,
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    .write = bw_io_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .impl = {
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        .min_access_size = 1,
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        .max_access_size = 4,
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    },
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};
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/* PCI config space reads/writes, to byte-word addressable memory.  */
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static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
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                              unsigned size)
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{
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    PCIBus *b = opaque;
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    return pci_data_read(b, addr, size);
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}
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static void bw_conf1_write(void *opaque, hwaddr addr,
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                           uint64_t val, unsigned size)
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{
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    PCIBus *b = opaque;
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    pci_data_write(b, addr, val, size);
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}
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const MemoryRegionOps alpha_pci_conf1_ops = {
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    .read = bw_conf1_read,
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    .write = bw_conf1_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .impl = {
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        .min_access_size = 1,
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        .max_access_size = 4,
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    },
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};
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/* PCI/EISA Interrupt Acknowledge Cycle.  */
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static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
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{
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    return pic_read_irq(isa_pic);
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}
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static void special_write(void *opaque, hwaddr addr,
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                          uint64_t val, unsigned size)
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{
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    qemu_log("pci: special write cycle");
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}
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const MemoryRegionOps alpha_pci_iack_ops = {
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    .read = iack_read,
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    .write = special_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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    .impl = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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};