root / hw / ide / core.c @ 1de7afc9
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/*
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* QEMU IDE disk and CD/DVD-ROM Emulator
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h> |
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#include <hw/pc.h> |
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#include <hw/pci/pci.h> |
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#include <hw/isa.h> |
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#include "qemu/error-report.h" |
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#include "qemu/timer.h" |
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#include "sysemu.h" |
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#include "dma.h" |
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#include "hw/block-common.h" |
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#include "blockdev.h" |
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|
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#include <hw/ide/internal.h> |
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|
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/* These values were based on a Seagate ST3500418AS but have been modified
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to make more sense in QEMU */
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static const int smart_attributes[][12] = { |
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/* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
|
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/* raw read error rate*/
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{ 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
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/* spin up */
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{ 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
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/* start stop count */
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{ 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
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/* remapped sectors */
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{ 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
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/* power on hours */
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{ 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
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/* power cycle count */
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{ 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
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/* airflow-temperature-celsius */
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{ 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
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}; |
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|
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static int ide_handle_rw_error(IDEState *s, int error, int op); |
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static void ide_dummy_transfer_stop(IDEState *s); |
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|
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static void padstr(char *str, const char *src, int len) |
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{
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int i, v;
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for(i = 0; i < len; i++) { |
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if (*src)
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v = *src++; |
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else
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v = ' ';
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str[i^1] = v;
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} |
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} |
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|
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static void put_le16(uint16_t *p, unsigned int v) |
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{
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*p = cpu_to_le16(v); |
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} |
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static void ide_identify(IDEState *s) |
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{
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uint16_t *p; |
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unsigned int oldsize; |
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IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; |
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if (s->identify_set) {
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memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
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return;
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} |
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memset(s->io_buffer, 0, 512); |
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p = (uint16_t *)s->io_buffer; |
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put_le16(p + 0, 0x0040); |
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put_le16(p + 1, s->cylinders);
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put_le16(p + 3, s->heads);
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put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ |
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put_le16(p + 5, 512); /* XXX: retired, remove ? */ |
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put_le16(p + 6, s->sectors);
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padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
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put_le16(p + 20, 3); /* XXX: retired, remove ? */ |
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put_le16(p + 21, 512); /* cache size in sectors */ |
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put_le16(p + 22, 4); /* ecc bytes */ |
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padstr((char *)(p + 23), s->version, 8); /* firmware version */ |
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padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ |
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#if MAX_MULT_SECTORS > 1 |
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put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
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#endif
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put_le16(p + 48, 1); /* dword I/O */ |
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put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ |
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put_le16(p + 51, 0x200); /* PIO transfer cycle */ |
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put_le16(p + 52, 0x200); /* DMA transfer cycle */ |
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put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ |
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put_le16(p + 54, s->cylinders);
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put_le16(p + 55, s->heads);
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put_le16(p + 56, s->sectors);
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oldsize = s->cylinders * s->heads * s->sectors; |
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put_le16(p + 57, oldsize);
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put_le16(p + 58, oldsize >> 16); |
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if (s->mult_sectors)
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put_le16(p + 59, 0x100 | s->mult_sectors); |
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put_le16(p + 60, s->nb_sectors);
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put_le16(p + 61, s->nb_sectors >> 16); |
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put_le16(p + 62, 0x07); /* single word dma0-2 supported */ |
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put_le16(p + 63, 0x07); /* mdma0-2 supported */ |
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put_le16(p + 64, 0x03); /* pio3-4 supported */ |
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put_le16(p + 65, 120); |
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put_le16(p + 66, 120); |
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put_le16(p + 67, 120); |
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put_le16(p + 68, 120); |
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if (dev && dev->conf.discard_granularity) {
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put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ |
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} |
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|
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if (s->ncq_queues) {
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put_le16(p + 75, s->ncq_queues - 1); |
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/* NCQ supported */
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put_le16(p + 76, (1 << 8)); |
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} |
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|
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put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ |
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put_le16(p + 81, 0x16); /* conforms to ata5 */ |
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/* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
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put_le16(p + 82, (1 << 14) | (1 << 5) | 1); |
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/* 13=flush_cache_ext,12=flush_cache,10=lba48 */
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put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); |
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/* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
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if (s->wwn) {
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put_le16(p + 84, (1 << 14) | (1 << 8) | 0); |
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} else {
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put_le16(p + 84, (1 << 14) | 0); |
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} |
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/* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
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if (bdrv_enable_write_cache(s->bs))
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put_le16(p + 85, (1 << 14) | (1 << 5) | 1); |
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else
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put_le16(p + 85, (1 << 14) | 1); |
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/* 13=flush_cache_ext,12=flush_cache,10=lba48 */
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put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10)); |
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/* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
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if (s->wwn) {
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put_le16(p + 87, (1 << 14) | (1 << 8) | 0); |
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} else {
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put_le16(p + 87, (1 << 14) | 0); |
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} |
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put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
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put_le16(p + 93, 1 | (1 << 14) | 0x2000); |
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put_le16(p + 100, s->nb_sectors);
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put_le16(p + 101, s->nb_sectors >> 16); |
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put_le16(p + 102, s->nb_sectors >> 32); |
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put_le16(p + 103, s->nb_sectors >> 48); |
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|
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if (dev && dev->conf.physical_block_size)
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put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); |
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if (s->wwn) {
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/* LE 16-bit words 111-108 contain 64-bit World Wide Name */
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put_le16(p + 108, s->wwn >> 48); |
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put_le16(p + 109, s->wwn >> 32); |
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put_le16(p + 110, s->wwn >> 16); |
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put_le16(p + 111, s->wwn);
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} |
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if (dev && dev->conf.discard_granularity) {
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put_le16(p + 169, 1); /* TRIM support */ |
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} |
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|
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memcpy(s->identify_data, p, sizeof(s->identify_data));
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s->identify_set = 1;
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} |
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|
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static void ide_atapi_identify(IDEState *s) |
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{
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uint16_t *p; |
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|
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if (s->identify_set) {
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memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
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return;
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} |
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|
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memset(s->io_buffer, 0, 512); |
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p = (uint16_t *)s->io_buffer; |
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/* Removable CDROM, 50us response, 12 byte packets */
|
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put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); |
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padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
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put_le16(p + 20, 3); /* buffer type */ |
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put_le16(p + 21, 512); /* cache size in sectors */ |
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put_le16(p + 22, 4); /* ecc bytes */ |
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padstr((char *)(p + 23), s->version, 8); /* firmware version */ |
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padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ |
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put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ |
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#ifdef USE_DMA_CDROM
|
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put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ |
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put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ |
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put_le16(p + 62, 7); /* single word dma0-2 supported */ |
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put_le16(p + 63, 7); /* mdma0-2 supported */ |
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#else
|
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put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ |
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put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ |
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put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ |
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#endif
|
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put_le16(p + 64, 3); /* pio3-4 supported */ |
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put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ |
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put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ |
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put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ |
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put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ |
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|
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put_le16(p + 71, 30); /* in ns */ |
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put_le16(p + 72, 30); /* in ns */ |
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|
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if (s->ncq_queues) {
|
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put_le16(p + 75, s->ncq_queues - 1); |
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/* NCQ supported */
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put_le16(p + 76, (1 << 8)); |
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} |
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|
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put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ |
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#ifdef USE_DMA_CDROM
|
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put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
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#endif
|
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memcpy(s->identify_data, p, sizeof(s->identify_data));
|
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s->identify_set = 1;
|
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} |
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|
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static void ide_cfata_identify(IDEState *s) |
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{
|
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uint16_t *p; |
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uint32_t cur_sec; |
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|
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p = (uint16_t *) s->identify_data; |
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if (s->identify_set)
|
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goto fill_buffer;
|
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|
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memset(p, 0, sizeof(s->identify_data)); |
| 250 |
|
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cur_sec = s->cylinders * s->heads * s->sectors; |
| 252 |
|
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put_le16(p + 0, 0x848a); /* CF Storage Card signature */ |
| 254 |
put_le16(p + 1, s->cylinders); /* Default cylinders */ |
| 255 |
put_le16(p + 3, s->heads); /* Default heads */ |
| 256 |
put_le16(p + 6, s->sectors); /* Default sectors per track */ |
| 257 |
put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ |
| 258 |
put_le16(p + 8, s->nb_sectors); /* Sectors per card */ |
| 259 |
padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ |
| 260 |
put_le16(p + 22, 0x0004); /* ECC bytes */ |
| 261 |
padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ |
| 262 |
padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */ |
| 263 |
#if MAX_MULT_SECTORS > 1 |
| 264 |
put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
| 265 |
#else
|
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put_le16(p + 47, 0x0000); |
| 267 |
#endif
|
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put_le16(p + 49, 0x0f00); /* Capabilities */ |
| 269 |
put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ |
| 270 |
put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ |
| 271 |
put_le16(p + 53, 0x0003); /* Translation params valid */ |
| 272 |
put_le16(p + 54, s->cylinders); /* Current cylinders */ |
| 273 |
put_le16(p + 55, s->heads); /* Current heads */ |
| 274 |
put_le16(p + 56, s->sectors); /* Current sectors */ |
| 275 |
put_le16(p + 57, cur_sec); /* Current capacity */ |
| 276 |
put_le16(p + 58, cur_sec >> 16); /* Current capacity */ |
| 277 |
if (s->mult_sectors) /* Multiple sector setting */ |
| 278 |
put_le16(p + 59, 0x100 | s->mult_sectors); |
| 279 |
put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ |
| 280 |
put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ |
| 281 |
put_le16(p + 63, 0x0203); /* Multiword DMA capability */ |
| 282 |
put_le16(p + 64, 0x0001); /* Flow Control PIO support */ |
| 283 |
put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ |
| 284 |
put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ |
| 285 |
put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ |
| 286 |
put_le16(p + 82, 0x400c); /* Command Set supported */ |
| 287 |
put_le16(p + 83, 0x7068); /* Command Set supported */ |
| 288 |
put_le16(p + 84, 0x4000); /* Features supported */ |
| 289 |
put_le16(p + 85, 0x000c); /* Command Set enabled */ |
| 290 |
put_le16(p + 86, 0x7044); /* Command Set enabled */ |
| 291 |
put_le16(p + 87, 0x4000); /* Features enabled */ |
| 292 |
put_le16(p + 91, 0x4060); /* Current APM level */ |
| 293 |
put_le16(p + 129, 0x0002); /* Current features option */ |
| 294 |
put_le16(p + 130, 0x0005); /* Reassigned sectors */ |
| 295 |
put_le16(p + 131, 0x0001); /* Initial power mode */ |
| 296 |
put_le16(p + 132, 0x0000); /* User signature */ |
| 297 |
put_le16(p + 160, 0x8100); /* Power requirement */ |
| 298 |
put_le16(p + 161, 0x8001); /* CF command set */ |
| 299 |
|
| 300 |
s->identify_set = 1;
|
| 301 |
|
| 302 |
fill_buffer:
|
| 303 |
memcpy(s->io_buffer, p, sizeof(s->identify_data));
|
| 304 |
} |
| 305 |
|
| 306 |
static void ide_set_signature(IDEState *s) |
| 307 |
{
|
| 308 |
s->select &= 0xf0; /* clear head */ |
| 309 |
/* put signature */
|
| 310 |
s->nsector = 1;
|
| 311 |
s->sector = 1;
|
| 312 |
if (s->drive_kind == IDE_CD) {
|
| 313 |
s->lcyl = 0x14;
|
| 314 |
s->hcyl = 0xeb;
|
| 315 |
} else if (s->bs) { |
| 316 |
s->lcyl = 0;
|
| 317 |
s->hcyl = 0;
|
| 318 |
} else {
|
| 319 |
s->lcyl = 0xff;
|
| 320 |
s->hcyl = 0xff;
|
| 321 |
} |
| 322 |
} |
| 323 |
|
| 324 |
typedef struct TrimAIOCB { |
| 325 |
BlockDriverAIOCB common; |
| 326 |
QEMUBH *bh; |
| 327 |
int ret;
|
| 328 |
} TrimAIOCB; |
| 329 |
|
| 330 |
static void trim_aio_cancel(BlockDriverAIOCB *acb) |
| 331 |
{
|
| 332 |
TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); |
| 333 |
|
| 334 |
qemu_bh_delete(iocb->bh); |
| 335 |
iocb->bh = NULL;
|
| 336 |
qemu_aio_release(iocb); |
| 337 |
} |
| 338 |
|
| 339 |
static const AIOCBInfo trim_aiocb_info = { |
| 340 |
.aiocb_size = sizeof(TrimAIOCB),
|
| 341 |
.cancel = trim_aio_cancel, |
| 342 |
}; |
| 343 |
|
| 344 |
static void ide_trim_bh_cb(void *opaque) |
| 345 |
{
|
| 346 |
TrimAIOCB *iocb = opaque; |
| 347 |
|
| 348 |
iocb->common.cb(iocb->common.opaque, iocb->ret); |
| 349 |
|
| 350 |
qemu_bh_delete(iocb->bh); |
| 351 |
iocb->bh = NULL;
|
| 352 |
|
| 353 |
qemu_aio_release(iocb); |
| 354 |
} |
| 355 |
|
| 356 |
BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs, |
| 357 |
int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
|
| 358 |
BlockDriverCompletionFunc *cb, void *opaque)
|
| 359 |
{
|
| 360 |
TrimAIOCB *iocb; |
| 361 |
int i, j, ret;
|
| 362 |
|
| 363 |
iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque); |
| 364 |
iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); |
| 365 |
iocb->ret = 0;
|
| 366 |
|
| 367 |
for (j = 0; j < qiov->niov; j++) { |
| 368 |
uint64_t *buffer = qiov->iov[j].iov_base; |
| 369 |
|
| 370 |
for (i = 0; i < qiov->iov[j].iov_len / 8; i++) { |
| 371 |
/* 6-byte LBA + 2-byte range per entry */
|
| 372 |
uint64_t entry = le64_to_cpu(buffer[i]); |
| 373 |
uint64_t sector = entry & 0x0000ffffffffffffULL;
|
| 374 |
uint16_t count = entry >> 48;
|
| 375 |
|
| 376 |
if (count == 0) { |
| 377 |
break;
|
| 378 |
} |
| 379 |
|
| 380 |
ret = bdrv_discard(bs, sector, count); |
| 381 |
if (!iocb->ret) {
|
| 382 |
iocb->ret = ret; |
| 383 |
} |
| 384 |
} |
| 385 |
} |
| 386 |
|
| 387 |
qemu_bh_schedule(iocb->bh); |
| 388 |
|
| 389 |
return &iocb->common;
|
| 390 |
} |
| 391 |
|
| 392 |
static inline void ide_abort_command(IDEState *s) |
| 393 |
{
|
| 394 |
s->status = READY_STAT | ERR_STAT; |
| 395 |
s->error = ABRT_ERR; |
| 396 |
} |
| 397 |
|
| 398 |
/* prepare data transfer and tell what to do after */
|
| 399 |
void ide_transfer_start(IDEState *s, uint8_t *buf, int size, |
| 400 |
EndTransferFunc *end_transfer_func) |
| 401 |
{
|
| 402 |
s->end_transfer_func = end_transfer_func; |
| 403 |
s->data_ptr = buf; |
| 404 |
s->data_end = buf + size; |
| 405 |
if (!(s->status & ERR_STAT)) {
|
| 406 |
s->status |= DRQ_STAT; |
| 407 |
} |
| 408 |
s->bus->dma->ops->start_transfer(s->bus->dma); |
| 409 |
} |
| 410 |
|
| 411 |
void ide_transfer_stop(IDEState *s)
|
| 412 |
{
|
| 413 |
s->end_transfer_func = ide_transfer_stop; |
| 414 |
s->data_ptr = s->io_buffer; |
| 415 |
s->data_end = s->io_buffer; |
| 416 |
s->status &= ~DRQ_STAT; |
| 417 |
} |
| 418 |
|
| 419 |
int64_t ide_get_sector(IDEState *s) |
| 420 |
{
|
| 421 |
int64_t sector_num; |
| 422 |
if (s->select & 0x40) { |
| 423 |
/* lba */
|
| 424 |
if (!s->lba48) {
|
| 425 |
sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | |
| 426 |
(s->lcyl << 8) | s->sector;
|
| 427 |
} else {
|
| 428 |
sector_num = ((int64_t)s->hob_hcyl << 40) |
|
| 429 |
((int64_t) s->hob_lcyl << 32) |
|
| 430 |
((int64_t) s->hob_sector << 24) |
|
| 431 |
((int64_t) s->hcyl << 16) |
|
| 432 |
((int64_t) s->lcyl << 8) | s->sector;
|
| 433 |
} |
| 434 |
} else {
|
| 435 |
sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
|
| 436 |
(s->select & 0x0f) * s->sectors + (s->sector - 1); |
| 437 |
} |
| 438 |
return sector_num;
|
| 439 |
} |
| 440 |
|
| 441 |
void ide_set_sector(IDEState *s, int64_t sector_num)
|
| 442 |
{
|
| 443 |
unsigned int cyl, r; |
| 444 |
if (s->select & 0x40) { |
| 445 |
if (!s->lba48) {
|
| 446 |
s->select = (s->select & 0xf0) | (sector_num >> 24); |
| 447 |
s->hcyl = (sector_num >> 16);
|
| 448 |
s->lcyl = (sector_num >> 8);
|
| 449 |
s->sector = (sector_num); |
| 450 |
} else {
|
| 451 |
s->sector = sector_num; |
| 452 |
s->lcyl = sector_num >> 8;
|
| 453 |
s->hcyl = sector_num >> 16;
|
| 454 |
s->hob_sector = sector_num >> 24;
|
| 455 |
s->hob_lcyl = sector_num >> 32;
|
| 456 |
s->hob_hcyl = sector_num >> 40;
|
| 457 |
} |
| 458 |
} else {
|
| 459 |
cyl = sector_num / (s->heads * s->sectors); |
| 460 |
r = sector_num % (s->heads * s->sectors); |
| 461 |
s->hcyl = cyl >> 8;
|
| 462 |
s->lcyl = cyl; |
| 463 |
s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); |
| 464 |
s->sector = (r % s->sectors) + 1;
|
| 465 |
} |
| 466 |
} |
| 467 |
|
| 468 |
static void ide_rw_error(IDEState *s) { |
| 469 |
ide_abort_command(s); |
| 470 |
ide_set_irq(s->bus); |
| 471 |
} |
| 472 |
|
| 473 |
static void ide_sector_read_cb(void *opaque, int ret) |
| 474 |
{
|
| 475 |
IDEState *s = opaque; |
| 476 |
int n;
|
| 477 |
|
| 478 |
s->pio_aiocb = NULL;
|
| 479 |
s->status &= ~BUSY_STAT; |
| 480 |
|
| 481 |
bdrv_acct_done(s->bs, &s->acct); |
| 482 |
if (ret != 0) { |
| 483 |
if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
|
| 484 |
BM_STATUS_RETRY_READ)) {
|
| 485 |
return;
|
| 486 |
} |
| 487 |
} |
| 488 |
|
| 489 |
n = s->nsector; |
| 490 |
if (n > s->req_nb_sectors) {
|
| 491 |
n = s->req_nb_sectors; |
| 492 |
} |
| 493 |
|
| 494 |
/* Allow the guest to read the io_buffer */
|
| 495 |
ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read); |
| 496 |
|
| 497 |
ide_set_irq(s->bus); |
| 498 |
|
| 499 |
ide_set_sector(s, ide_get_sector(s) + n); |
| 500 |
s->nsector -= n; |
| 501 |
} |
| 502 |
|
| 503 |
void ide_sector_read(IDEState *s)
|
| 504 |
{
|
| 505 |
int64_t sector_num; |
| 506 |
int n;
|
| 507 |
|
| 508 |
s->status = READY_STAT | SEEK_STAT; |
| 509 |
s->error = 0; /* not needed by IDE spec, but needed by Windows */ |
| 510 |
sector_num = ide_get_sector(s); |
| 511 |
n = s->nsector; |
| 512 |
|
| 513 |
if (n == 0) { |
| 514 |
ide_transfer_stop(s); |
| 515 |
return;
|
| 516 |
} |
| 517 |
|
| 518 |
s->status |= BUSY_STAT; |
| 519 |
|
| 520 |
if (n > s->req_nb_sectors) {
|
| 521 |
n = s->req_nb_sectors; |
| 522 |
} |
| 523 |
|
| 524 |
#if defined(DEBUG_IDE)
|
| 525 |
printf("sector=%" PRId64 "\n", sector_num); |
| 526 |
#endif
|
| 527 |
|
| 528 |
s->iov.iov_base = s->io_buffer; |
| 529 |
s->iov.iov_len = n * BDRV_SECTOR_SIZE; |
| 530 |
qemu_iovec_init_external(&s->qiov, &s->iov, 1);
|
| 531 |
|
| 532 |
bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); |
| 533 |
s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n, |
| 534 |
ide_sector_read_cb, s); |
| 535 |
} |
| 536 |
|
| 537 |
static void dma_buf_commit(IDEState *s) |
| 538 |
{
|
| 539 |
qemu_sglist_destroy(&s->sg); |
| 540 |
} |
| 541 |
|
| 542 |
void ide_set_inactive(IDEState *s)
|
| 543 |
{
|
| 544 |
s->bus->dma->aiocb = NULL;
|
| 545 |
s->bus->dma->ops->set_inactive(s->bus->dma); |
| 546 |
} |
| 547 |
|
| 548 |
void ide_dma_error(IDEState *s)
|
| 549 |
{
|
| 550 |
ide_transfer_stop(s); |
| 551 |
s->error = ABRT_ERR; |
| 552 |
s->status = READY_STAT | ERR_STAT; |
| 553 |
ide_set_inactive(s); |
| 554 |
ide_set_irq(s->bus); |
| 555 |
} |
| 556 |
|
| 557 |
static int ide_handle_rw_error(IDEState *s, int error, int op) |
| 558 |
{
|
| 559 |
bool is_read = (op & BM_STATUS_RETRY_READ) != 0; |
| 560 |
BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error); |
| 561 |
|
| 562 |
if (action == BDRV_ACTION_STOP) {
|
| 563 |
s->bus->dma->ops->set_unit(s->bus->dma, s->unit); |
| 564 |
s->bus->error_status = op; |
| 565 |
} else if (action == BDRV_ACTION_REPORT) { |
| 566 |
if (op & BM_STATUS_DMA_RETRY) {
|
| 567 |
dma_buf_commit(s); |
| 568 |
ide_dma_error(s); |
| 569 |
} else {
|
| 570 |
ide_rw_error(s); |
| 571 |
} |
| 572 |
} |
| 573 |
bdrv_error_action(s->bs, action, is_read, error); |
| 574 |
return action != BDRV_ACTION_IGNORE;
|
| 575 |
} |
| 576 |
|
| 577 |
void ide_dma_cb(void *opaque, int ret) |
| 578 |
{
|
| 579 |
IDEState *s = opaque; |
| 580 |
int n;
|
| 581 |
int64_t sector_num; |
| 582 |
bool stay_active = false; |
| 583 |
|
| 584 |
if (ret < 0) { |
| 585 |
int op = BM_STATUS_DMA_RETRY;
|
| 586 |
|
| 587 |
if (s->dma_cmd == IDE_DMA_READ)
|
| 588 |
op |= BM_STATUS_RETRY_READ; |
| 589 |
else if (s->dma_cmd == IDE_DMA_TRIM) |
| 590 |
op |= BM_STATUS_RETRY_TRIM; |
| 591 |
|
| 592 |
if (ide_handle_rw_error(s, -ret, op)) {
|
| 593 |
return;
|
| 594 |
} |
| 595 |
} |
| 596 |
|
| 597 |
n = s->io_buffer_size >> 9;
|
| 598 |
if (n > s->nsector) {
|
| 599 |
/* The PRDs were longer than needed for this request. Shorten them so
|
| 600 |
* we don't get a negative remainder. The Active bit must remain set
|
| 601 |
* after the request completes. */
|
| 602 |
n = s->nsector; |
| 603 |
stay_active = true;
|
| 604 |
} |
| 605 |
|
| 606 |
sector_num = ide_get_sector(s); |
| 607 |
if (n > 0) { |
| 608 |
dma_buf_commit(s); |
| 609 |
sector_num += n; |
| 610 |
ide_set_sector(s, sector_num); |
| 611 |
s->nsector -= n; |
| 612 |
} |
| 613 |
|
| 614 |
/* end of transfer ? */
|
| 615 |
if (s->nsector == 0) { |
| 616 |
s->status = READY_STAT | SEEK_STAT; |
| 617 |
ide_set_irq(s->bus); |
| 618 |
goto eot;
|
| 619 |
} |
| 620 |
|
| 621 |
/* launch next transfer */
|
| 622 |
n = s->nsector; |
| 623 |
s->io_buffer_index = 0;
|
| 624 |
s->io_buffer_size = n * 512;
|
| 625 |
if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) { |
| 626 |
/* The PRDs were too short. Reset the Active bit, but don't raise an
|
| 627 |
* interrupt. */
|
| 628 |
s->status = READY_STAT | SEEK_STAT; |
| 629 |
goto eot;
|
| 630 |
} |
| 631 |
|
| 632 |
#ifdef DEBUG_AIO
|
| 633 |
printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", |
| 634 |
sector_num, n, s->dma_cmd); |
| 635 |
#endif
|
| 636 |
|
| 637 |
switch (s->dma_cmd) {
|
| 638 |
case IDE_DMA_READ:
|
| 639 |
s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, |
| 640 |
ide_dma_cb, s); |
| 641 |
break;
|
| 642 |
case IDE_DMA_WRITE:
|
| 643 |
s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, |
| 644 |
ide_dma_cb, s); |
| 645 |
break;
|
| 646 |
case IDE_DMA_TRIM:
|
| 647 |
s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num, |
| 648 |
ide_issue_trim, ide_dma_cb, s, |
| 649 |
DMA_DIRECTION_TO_DEVICE); |
| 650 |
break;
|
| 651 |
} |
| 652 |
return;
|
| 653 |
|
| 654 |
eot:
|
| 655 |
if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
|
| 656 |
bdrv_acct_done(s->bs, &s->acct); |
| 657 |
} |
| 658 |
ide_set_inactive(s); |
| 659 |
if (stay_active) {
|
| 660 |
s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING); |
| 661 |
} |
| 662 |
} |
| 663 |
|
| 664 |
static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) |
| 665 |
{
|
| 666 |
s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
| 667 |
s->io_buffer_index = 0;
|
| 668 |
s->io_buffer_size = 0;
|
| 669 |
s->dma_cmd = dma_cmd; |
| 670 |
|
| 671 |
switch (dma_cmd) {
|
| 672 |
case IDE_DMA_READ:
|
| 673 |
bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, |
| 674 |
BDRV_ACCT_READ); |
| 675 |
break;
|
| 676 |
case IDE_DMA_WRITE:
|
| 677 |
bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, |
| 678 |
BDRV_ACCT_WRITE); |
| 679 |
break;
|
| 680 |
default:
|
| 681 |
break;
|
| 682 |
} |
| 683 |
|
| 684 |
s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb); |
| 685 |
} |
| 686 |
|
| 687 |
static void ide_sector_write_timer_cb(void *opaque) |
| 688 |
{
|
| 689 |
IDEState *s = opaque; |
| 690 |
ide_set_irq(s->bus); |
| 691 |
} |
| 692 |
|
| 693 |
static void ide_sector_write_cb(void *opaque, int ret) |
| 694 |
{
|
| 695 |
IDEState *s = opaque; |
| 696 |
int n;
|
| 697 |
|
| 698 |
bdrv_acct_done(s->bs, &s->acct); |
| 699 |
|
| 700 |
s->pio_aiocb = NULL;
|
| 701 |
s->status &= ~BUSY_STAT; |
| 702 |
|
| 703 |
if (ret != 0) { |
| 704 |
if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
|
| 705 |
return;
|
| 706 |
} |
| 707 |
} |
| 708 |
|
| 709 |
n = s->nsector; |
| 710 |
if (n > s->req_nb_sectors) {
|
| 711 |
n = s->req_nb_sectors; |
| 712 |
} |
| 713 |
s->nsector -= n; |
| 714 |
if (s->nsector == 0) { |
| 715 |
/* no more sectors to write */
|
| 716 |
ide_transfer_stop(s); |
| 717 |
} else {
|
| 718 |
int n1 = s->nsector;
|
| 719 |
if (n1 > s->req_nb_sectors) {
|
| 720 |
n1 = s->req_nb_sectors; |
| 721 |
} |
| 722 |
ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE, |
| 723 |
ide_sector_write); |
| 724 |
} |
| 725 |
ide_set_sector(s, ide_get_sector(s) + n); |
| 726 |
|
| 727 |
if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { |
| 728 |
/* It seems there is a bug in the Windows 2000 installer HDD
|
| 729 |
IDE driver which fills the disk with empty logs when the
|
| 730 |
IDE write IRQ comes too early. This hack tries to correct
|
| 731 |
that at the expense of slower write performances. Use this
|
| 732 |
option _only_ to install Windows 2000. You must disable it
|
| 733 |
for normal use. */
|
| 734 |
qemu_mod_timer(s->sector_write_timer, |
| 735 |
qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
|
| 736 |
} else {
|
| 737 |
ide_set_irq(s->bus); |
| 738 |
} |
| 739 |
} |
| 740 |
|
| 741 |
void ide_sector_write(IDEState *s)
|
| 742 |
{
|
| 743 |
int64_t sector_num; |
| 744 |
int n;
|
| 745 |
|
| 746 |
s->status = READY_STAT | SEEK_STAT | BUSY_STAT; |
| 747 |
sector_num = ide_get_sector(s); |
| 748 |
#if defined(DEBUG_IDE)
|
| 749 |
printf("sector=%" PRId64 "\n", sector_num); |
| 750 |
#endif
|
| 751 |
n = s->nsector; |
| 752 |
if (n > s->req_nb_sectors) {
|
| 753 |
n = s->req_nb_sectors; |
| 754 |
} |
| 755 |
|
| 756 |
s->iov.iov_base = s->io_buffer; |
| 757 |
s->iov.iov_len = n * BDRV_SECTOR_SIZE; |
| 758 |
qemu_iovec_init_external(&s->qiov, &s->iov, 1);
|
| 759 |
|
| 760 |
bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); |
| 761 |
s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n, |
| 762 |
ide_sector_write_cb, s); |
| 763 |
} |
| 764 |
|
| 765 |
static void ide_flush_cb(void *opaque, int ret) |
| 766 |
{
|
| 767 |
IDEState *s = opaque; |
| 768 |
|
| 769 |
if (ret < 0) { |
| 770 |
/* XXX: What sector number to set here? */
|
| 771 |
if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
|
| 772 |
return;
|
| 773 |
} |
| 774 |
} |
| 775 |
|
| 776 |
bdrv_acct_done(s->bs, &s->acct); |
| 777 |
s->status = READY_STAT | SEEK_STAT; |
| 778 |
ide_set_irq(s->bus); |
| 779 |
} |
| 780 |
|
| 781 |
void ide_flush_cache(IDEState *s)
|
| 782 |
{
|
| 783 |
if (s->bs == NULL) { |
| 784 |
ide_flush_cb(s, 0);
|
| 785 |
return;
|
| 786 |
} |
| 787 |
|
| 788 |
bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
|
| 789 |
bdrv_aio_flush(s->bs, ide_flush_cb, s); |
| 790 |
} |
| 791 |
|
| 792 |
static void ide_cfata_metadata_inquiry(IDEState *s) |
| 793 |
{
|
| 794 |
uint16_t *p; |
| 795 |
uint32_t spd; |
| 796 |
|
| 797 |
p = (uint16_t *) s->io_buffer; |
| 798 |
memset(p, 0, 0x200); |
| 799 |
spd = ((s->mdata_size - 1) >> 9) + 1; |
| 800 |
|
| 801 |
put_le16(p + 0, 0x0001); /* Data format revision */ |
| 802 |
put_le16(p + 1, 0x0000); /* Media property: silicon */ |
| 803 |
put_le16(p + 2, s->media_changed); /* Media status */ |
| 804 |
put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ |
| 805 |
put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ |
| 806 |
put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ |
| 807 |
put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ |
| 808 |
} |
| 809 |
|
| 810 |
static void ide_cfata_metadata_read(IDEState *s) |
| 811 |
{
|
| 812 |
uint16_t *p; |
| 813 |
|
| 814 |
if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { |
| 815 |
s->status = ERR_STAT; |
| 816 |
s->error = ABRT_ERR; |
| 817 |
return;
|
| 818 |
} |
| 819 |
|
| 820 |
p = (uint16_t *) s->io_buffer; |
| 821 |
memset(p, 0, 0x200); |
| 822 |
|
| 823 |
put_le16(p + 0, s->media_changed); /* Media status */ |
| 824 |
memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), |
| 825 |
MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), |
| 826 |
s->nsector << 9), 0x200 - 2)); |
| 827 |
} |
| 828 |
|
| 829 |
static void ide_cfata_metadata_write(IDEState *s) |
| 830 |
{
|
| 831 |
if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { |
| 832 |
s->status = ERR_STAT; |
| 833 |
s->error = ABRT_ERR; |
| 834 |
return;
|
| 835 |
} |
| 836 |
|
| 837 |
s->media_changed = 0;
|
| 838 |
|
| 839 |
memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), |
| 840 |
s->io_buffer + 2,
|
| 841 |
MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), |
| 842 |
s->nsector << 9), 0x200 - 2)); |
| 843 |
} |
| 844 |
|
| 845 |
/* called when the inserted state of the media has changed */
|
| 846 |
static void ide_cd_change_cb(void *opaque, bool load) |
| 847 |
{
|
| 848 |
IDEState *s = opaque; |
| 849 |
uint64_t nb_sectors; |
| 850 |
|
| 851 |
s->tray_open = !load; |
| 852 |
bdrv_get_geometry(s->bs, &nb_sectors); |
| 853 |
s->nb_sectors = nb_sectors; |
| 854 |
|
| 855 |
/*
|
| 856 |
* First indicate to the guest that a CD has been removed. That's
|
| 857 |
* done on the next command the guest sends us.
|
| 858 |
*
|
| 859 |
* Then we set UNIT_ATTENTION, by which the guest will
|
| 860 |
* detect a new CD in the drive. See ide_atapi_cmd() for details.
|
| 861 |
*/
|
| 862 |
s->cdrom_changed = 1;
|
| 863 |
s->events.new_media = true;
|
| 864 |
s->events.eject_request = false;
|
| 865 |
ide_set_irq(s->bus); |
| 866 |
} |
| 867 |
|
| 868 |
static void ide_cd_eject_request_cb(void *opaque, bool force) |
| 869 |
{
|
| 870 |
IDEState *s = opaque; |
| 871 |
|
| 872 |
s->events.eject_request = true;
|
| 873 |
if (force) {
|
| 874 |
s->tray_locked = false;
|
| 875 |
} |
| 876 |
ide_set_irq(s->bus); |
| 877 |
} |
| 878 |
|
| 879 |
static void ide_cmd_lba48_transform(IDEState *s, int lba48) |
| 880 |
{
|
| 881 |
s->lba48 = lba48; |
| 882 |
|
| 883 |
/* handle the 'magic' 0 nsector count conversion here. to avoid
|
| 884 |
* fiddling with the rest of the read logic, we just store the
|
| 885 |
* full sector count in ->nsector and ignore ->hob_nsector from now
|
| 886 |
*/
|
| 887 |
if (!s->lba48) {
|
| 888 |
if (!s->nsector)
|
| 889 |
s->nsector = 256;
|
| 890 |
} else {
|
| 891 |
if (!s->nsector && !s->hob_nsector)
|
| 892 |
s->nsector = 65536;
|
| 893 |
else {
|
| 894 |
int lo = s->nsector;
|
| 895 |
int hi = s->hob_nsector;
|
| 896 |
|
| 897 |
s->nsector = (hi << 8) | lo;
|
| 898 |
} |
| 899 |
} |
| 900 |
} |
| 901 |
|
| 902 |
static void ide_clear_hob(IDEBus *bus) |
| 903 |
{
|
| 904 |
/* any write clears HOB high bit of device control register */
|
| 905 |
bus->ifs[0].select &= ~(1 << 7); |
| 906 |
bus->ifs[1].select &= ~(1 << 7); |
| 907 |
} |
| 908 |
|
| 909 |
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 910 |
{
|
| 911 |
IDEBus *bus = opaque; |
| 912 |
|
| 913 |
#ifdef DEBUG_IDE
|
| 914 |
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
|
| 915 |
#endif
|
| 916 |
|
| 917 |
addr &= 7;
|
| 918 |
|
| 919 |
/* ignore writes to command block while busy with previous command */
|
| 920 |
if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) |
| 921 |
return;
|
| 922 |
|
| 923 |
switch(addr) {
|
| 924 |
case 0: |
| 925 |
break;
|
| 926 |
case 1: |
| 927 |
ide_clear_hob(bus); |
| 928 |
/* NOTE: data is written to the two drives */
|
| 929 |
bus->ifs[0].hob_feature = bus->ifs[0].feature; |
| 930 |
bus->ifs[1].hob_feature = bus->ifs[1].feature; |
| 931 |
bus->ifs[0].feature = val;
|
| 932 |
bus->ifs[1].feature = val;
|
| 933 |
break;
|
| 934 |
case 2: |
| 935 |
ide_clear_hob(bus); |
| 936 |
bus->ifs[0].hob_nsector = bus->ifs[0].nsector; |
| 937 |
bus->ifs[1].hob_nsector = bus->ifs[1].nsector; |
| 938 |
bus->ifs[0].nsector = val;
|
| 939 |
bus->ifs[1].nsector = val;
|
| 940 |
break;
|
| 941 |
case 3: |
| 942 |
ide_clear_hob(bus); |
| 943 |
bus->ifs[0].hob_sector = bus->ifs[0].sector; |
| 944 |
bus->ifs[1].hob_sector = bus->ifs[1].sector; |
| 945 |
bus->ifs[0].sector = val;
|
| 946 |
bus->ifs[1].sector = val;
|
| 947 |
break;
|
| 948 |
case 4: |
| 949 |
ide_clear_hob(bus); |
| 950 |
bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; |
| 951 |
bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; |
| 952 |
bus->ifs[0].lcyl = val;
|
| 953 |
bus->ifs[1].lcyl = val;
|
| 954 |
break;
|
| 955 |
case 5: |
| 956 |
ide_clear_hob(bus); |
| 957 |
bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; |
| 958 |
bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; |
| 959 |
bus->ifs[0].hcyl = val;
|
| 960 |
bus->ifs[1].hcyl = val;
|
| 961 |
break;
|
| 962 |
case 6: |
| 963 |
/* FIXME: HOB readback uses bit 7 */
|
| 964 |
bus->ifs[0].select = (val & ~0x10) | 0xa0; |
| 965 |
bus->ifs[1].select = (val | 0x10) | 0xa0; |
| 966 |
/* select drive */
|
| 967 |
bus->unit = (val >> 4) & 1; |
| 968 |
break;
|
| 969 |
default:
|
| 970 |
case 7: |
| 971 |
/* command */
|
| 972 |
ide_exec_cmd(bus, val); |
| 973 |
break;
|
| 974 |
} |
| 975 |
} |
| 976 |
|
| 977 |
#define HD_OK (1u << IDE_HD) |
| 978 |
#define CD_OK (1u << IDE_CD) |
| 979 |
#define CFA_OK (1u << IDE_CFATA) |
| 980 |
#define HD_CFA_OK (HD_OK | CFA_OK)
|
| 981 |
#define ALL_OK (HD_OK | CD_OK | CFA_OK)
|
| 982 |
|
| 983 |
/* See ACS-2 T13/2015-D Table B.2 Command codes */
|
| 984 |
static const uint8_t ide_cmd_table[0x100] = { |
| 985 |
/* NOP not implemented, mandatory for CD */
|
| 986 |
[CFA_REQ_EXT_ERROR_CODE] = CFA_OK, |
| 987 |
[WIN_DSM] = ALL_OK, |
| 988 |
[WIN_DEVICE_RESET] = CD_OK, |
| 989 |
[WIN_RECAL] = HD_CFA_OK, |
| 990 |
[WIN_READ] = ALL_OK, |
| 991 |
[WIN_READ_ONCE] = ALL_OK, |
| 992 |
[WIN_READ_EXT] = HD_CFA_OK, |
| 993 |
[WIN_READDMA_EXT] = HD_CFA_OK, |
| 994 |
[WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK, |
| 995 |
[WIN_MULTREAD_EXT] = HD_CFA_OK, |
| 996 |
[WIN_WRITE] = HD_CFA_OK, |
| 997 |
[WIN_WRITE_ONCE] = HD_CFA_OK, |
| 998 |
[WIN_WRITE_EXT] = HD_CFA_OK, |
| 999 |
[WIN_WRITEDMA_EXT] = HD_CFA_OK, |
| 1000 |
[CFA_WRITE_SECT_WO_ERASE] = CFA_OK, |
| 1001 |
[WIN_MULTWRITE_EXT] = HD_CFA_OK, |
| 1002 |
[WIN_WRITE_VERIFY] = HD_CFA_OK, |
| 1003 |
[WIN_VERIFY] = HD_CFA_OK, |
| 1004 |
[WIN_VERIFY_ONCE] = HD_CFA_OK, |
| 1005 |
[WIN_VERIFY_EXT] = HD_CFA_OK, |
| 1006 |
[WIN_SEEK] = HD_CFA_OK, |
| 1007 |
[CFA_TRANSLATE_SECTOR] = CFA_OK, |
| 1008 |
[WIN_DIAGNOSE] = ALL_OK, |
| 1009 |
[WIN_SPECIFY] = HD_CFA_OK, |
| 1010 |
[WIN_STANDBYNOW2] = ALL_OK, |
| 1011 |
[WIN_IDLEIMMEDIATE2] = ALL_OK, |
| 1012 |
[WIN_STANDBY2] = ALL_OK, |
| 1013 |
[WIN_SETIDLE2] = ALL_OK, |
| 1014 |
[WIN_CHECKPOWERMODE2] = ALL_OK, |
| 1015 |
[WIN_SLEEPNOW2] = ALL_OK, |
| 1016 |
[WIN_PACKETCMD] = CD_OK, |
| 1017 |
[WIN_PIDENTIFY] = CD_OK, |
| 1018 |
[WIN_SMART] = HD_CFA_OK, |
| 1019 |
[CFA_ACCESS_METADATA_STORAGE] = CFA_OK, |
| 1020 |
[CFA_ERASE_SECTORS] = CFA_OK, |
| 1021 |
[WIN_MULTREAD] = HD_CFA_OK, |
| 1022 |
[WIN_MULTWRITE] = HD_CFA_OK, |
| 1023 |
[WIN_SETMULT] = HD_CFA_OK, |
| 1024 |
[WIN_READDMA] = HD_CFA_OK, |
| 1025 |
[WIN_READDMA_ONCE] = HD_CFA_OK, |
| 1026 |
[WIN_WRITEDMA] = HD_CFA_OK, |
| 1027 |
[WIN_WRITEDMA_ONCE] = HD_CFA_OK, |
| 1028 |
[CFA_WRITE_MULTI_WO_ERASE] = CFA_OK, |
| 1029 |
[WIN_STANDBYNOW1] = ALL_OK, |
| 1030 |
[WIN_IDLEIMMEDIATE] = ALL_OK, |
| 1031 |
[WIN_STANDBY] = ALL_OK, |
| 1032 |
[WIN_SETIDLE1] = ALL_OK, |
| 1033 |
[WIN_CHECKPOWERMODE1] = ALL_OK, |
| 1034 |
[WIN_SLEEPNOW1] = ALL_OK, |
| 1035 |
[WIN_FLUSH_CACHE] = ALL_OK, |
| 1036 |
[WIN_FLUSH_CACHE_EXT] = HD_CFA_OK, |
| 1037 |
[WIN_IDENTIFY] = ALL_OK, |
| 1038 |
[WIN_SETFEATURES] = ALL_OK, |
| 1039 |
[IBM_SENSE_CONDITION] = CFA_OK, |
| 1040 |
[CFA_WEAR_LEVEL] = HD_CFA_OK, |
| 1041 |
[WIN_READ_NATIVE_MAX] = ALL_OK, |
| 1042 |
}; |
| 1043 |
|
| 1044 |
static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) |
| 1045 |
{
|
| 1046 |
return cmd < ARRAY_SIZE(ide_cmd_table)
|
| 1047 |
&& (ide_cmd_table[cmd] & (1u << s->drive_kind));
|
| 1048 |
} |
| 1049 |
|
| 1050 |
void ide_exec_cmd(IDEBus *bus, uint32_t val)
|
| 1051 |
{
|
| 1052 |
uint16_t *identify_data; |
| 1053 |
IDEState *s; |
| 1054 |
int n;
|
| 1055 |
int lba48 = 0; |
| 1056 |
|
| 1057 |
#if defined(DEBUG_IDE)
|
| 1058 |
printf("ide: CMD=%02x\n", val);
|
| 1059 |
#endif
|
| 1060 |
s = idebus_active_if(bus); |
| 1061 |
/* ignore commands to non existent slave */
|
| 1062 |
if (s != bus->ifs && !s->bs)
|
| 1063 |
return;
|
| 1064 |
|
| 1065 |
/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
|
| 1066 |
if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
|
| 1067 |
return;
|
| 1068 |
|
| 1069 |
if (!ide_cmd_permitted(s, val)) {
|
| 1070 |
goto abort_cmd;
|
| 1071 |
} |
| 1072 |
|
| 1073 |
switch(val) {
|
| 1074 |
case WIN_DSM:
|
| 1075 |
switch (s->feature) {
|
| 1076 |
case DSM_TRIM:
|
| 1077 |
if (!s->bs) {
|
| 1078 |
goto abort_cmd;
|
| 1079 |
} |
| 1080 |
ide_sector_start_dma(s, IDE_DMA_TRIM); |
| 1081 |
break;
|
| 1082 |
default:
|
| 1083 |
goto abort_cmd;
|
| 1084 |
} |
| 1085 |
break;
|
| 1086 |
case WIN_IDENTIFY:
|
| 1087 |
if (s->bs && s->drive_kind != IDE_CD) {
|
| 1088 |
if (s->drive_kind != IDE_CFATA)
|
| 1089 |
ide_identify(s); |
| 1090 |
else
|
| 1091 |
ide_cfata_identify(s); |
| 1092 |
s->status = READY_STAT | SEEK_STAT; |
| 1093 |
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
| 1094 |
} else {
|
| 1095 |
if (s->drive_kind == IDE_CD) {
|
| 1096 |
ide_set_signature(s); |
| 1097 |
} |
| 1098 |
ide_abort_command(s); |
| 1099 |
} |
| 1100 |
ide_set_irq(s->bus); |
| 1101 |
break;
|
| 1102 |
case WIN_SPECIFY:
|
| 1103 |
case WIN_RECAL:
|
| 1104 |
s->error = 0;
|
| 1105 |
s->status = READY_STAT | SEEK_STAT; |
| 1106 |
ide_set_irq(s->bus); |
| 1107 |
break;
|
| 1108 |
case WIN_SETMULT:
|
| 1109 |
if (s->drive_kind == IDE_CFATA && s->nsector == 0) { |
| 1110 |
/* Disable Read and Write Multiple */
|
| 1111 |
s->mult_sectors = 0;
|
| 1112 |
s->status = READY_STAT | SEEK_STAT; |
| 1113 |
} else if ((s->nsector & 0xff) != 0 && |
| 1114 |
((s->nsector & 0xff) > MAX_MULT_SECTORS ||
|
| 1115 |
(s->nsector & (s->nsector - 1)) != 0)) { |
| 1116 |
ide_abort_command(s); |
| 1117 |
} else {
|
| 1118 |
s->mult_sectors = s->nsector & 0xff;
|
| 1119 |
s->status = READY_STAT | SEEK_STAT; |
| 1120 |
} |
| 1121 |
ide_set_irq(s->bus); |
| 1122 |
break;
|
| 1123 |
case WIN_VERIFY_EXT:
|
| 1124 |
lba48 = 1;
|
| 1125 |
case WIN_VERIFY:
|
| 1126 |
case WIN_VERIFY_ONCE:
|
| 1127 |
/* do sector number check ? */
|
| 1128 |
ide_cmd_lba48_transform(s, lba48); |
| 1129 |
s->status = READY_STAT | SEEK_STAT; |
| 1130 |
ide_set_irq(s->bus); |
| 1131 |
break;
|
| 1132 |
case WIN_READ_EXT:
|
| 1133 |
lba48 = 1;
|
| 1134 |
case WIN_READ:
|
| 1135 |
case WIN_READ_ONCE:
|
| 1136 |
if (s->drive_kind == IDE_CD) {
|
| 1137 |
ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
|
| 1138 |
goto abort_cmd;
|
| 1139 |
} |
| 1140 |
if (!s->bs) {
|
| 1141 |
goto abort_cmd;
|
| 1142 |
} |
| 1143 |
ide_cmd_lba48_transform(s, lba48); |
| 1144 |
s->req_nb_sectors = 1;
|
| 1145 |
ide_sector_read(s); |
| 1146 |
break;
|
| 1147 |
case WIN_WRITE_EXT:
|
| 1148 |
lba48 = 1;
|
| 1149 |
case WIN_WRITE:
|
| 1150 |
case WIN_WRITE_ONCE:
|
| 1151 |
case CFA_WRITE_SECT_WO_ERASE:
|
| 1152 |
case WIN_WRITE_VERIFY:
|
| 1153 |
if (!s->bs) {
|
| 1154 |
goto abort_cmd;
|
| 1155 |
} |
| 1156 |
ide_cmd_lba48_transform(s, lba48); |
| 1157 |
s->error = 0;
|
| 1158 |
s->status = SEEK_STAT | READY_STAT; |
| 1159 |
s->req_nb_sectors = 1;
|
| 1160 |
ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
|
| 1161 |
s->media_changed = 1;
|
| 1162 |
break;
|
| 1163 |
case WIN_MULTREAD_EXT:
|
| 1164 |
lba48 = 1;
|
| 1165 |
case WIN_MULTREAD:
|
| 1166 |
if (!s->bs) {
|
| 1167 |
goto abort_cmd;
|
| 1168 |
} |
| 1169 |
if (!s->mult_sectors) {
|
| 1170 |
goto abort_cmd;
|
| 1171 |
} |
| 1172 |
ide_cmd_lba48_transform(s, lba48); |
| 1173 |
s->req_nb_sectors = s->mult_sectors; |
| 1174 |
ide_sector_read(s); |
| 1175 |
break;
|
| 1176 |
case WIN_MULTWRITE_EXT:
|
| 1177 |
lba48 = 1;
|
| 1178 |
case WIN_MULTWRITE:
|
| 1179 |
case CFA_WRITE_MULTI_WO_ERASE:
|
| 1180 |
if (!s->bs) {
|
| 1181 |
goto abort_cmd;
|
| 1182 |
} |
| 1183 |
if (!s->mult_sectors) {
|
| 1184 |
goto abort_cmd;
|
| 1185 |
} |
| 1186 |
ide_cmd_lba48_transform(s, lba48); |
| 1187 |
s->error = 0;
|
| 1188 |
s->status = SEEK_STAT | READY_STAT; |
| 1189 |
s->req_nb_sectors = s->mult_sectors; |
| 1190 |
n = s->nsector; |
| 1191 |
if (n > s->req_nb_sectors)
|
| 1192 |
n = s->req_nb_sectors; |
| 1193 |
ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
|
| 1194 |
s->media_changed = 1;
|
| 1195 |
break;
|
| 1196 |
case WIN_READDMA_EXT:
|
| 1197 |
lba48 = 1;
|
| 1198 |
case WIN_READDMA:
|
| 1199 |
case WIN_READDMA_ONCE:
|
| 1200 |
if (!s->bs) {
|
| 1201 |
goto abort_cmd;
|
| 1202 |
} |
| 1203 |
ide_cmd_lba48_transform(s, lba48); |
| 1204 |
ide_sector_start_dma(s, IDE_DMA_READ); |
| 1205 |
break;
|
| 1206 |
case WIN_WRITEDMA_EXT:
|
| 1207 |
lba48 = 1;
|
| 1208 |
case WIN_WRITEDMA:
|
| 1209 |
case WIN_WRITEDMA_ONCE:
|
| 1210 |
if (!s->bs) {
|
| 1211 |
goto abort_cmd;
|
| 1212 |
} |
| 1213 |
ide_cmd_lba48_transform(s, lba48); |
| 1214 |
ide_sector_start_dma(s, IDE_DMA_WRITE); |
| 1215 |
s->media_changed = 1;
|
| 1216 |
break;
|
| 1217 |
case WIN_READ_NATIVE_MAX_EXT:
|
| 1218 |
lba48 = 1;
|
| 1219 |
case WIN_READ_NATIVE_MAX:
|
| 1220 |
ide_cmd_lba48_transform(s, lba48); |
| 1221 |
ide_set_sector(s, s->nb_sectors - 1);
|
| 1222 |
s->status = READY_STAT | SEEK_STAT; |
| 1223 |
ide_set_irq(s->bus); |
| 1224 |
break;
|
| 1225 |
case WIN_CHECKPOWERMODE1:
|
| 1226 |
case WIN_CHECKPOWERMODE2:
|
| 1227 |
s->error = 0;
|
| 1228 |
s->nsector = 0xff; /* device active or idle */ |
| 1229 |
s->status = READY_STAT | SEEK_STAT; |
| 1230 |
ide_set_irq(s->bus); |
| 1231 |
break;
|
| 1232 |
case WIN_SETFEATURES:
|
| 1233 |
if (!s->bs)
|
| 1234 |
goto abort_cmd;
|
| 1235 |
/* XXX: valid for CDROM ? */
|
| 1236 |
switch(s->feature) {
|
| 1237 |
case 0x02: /* write cache enable */ |
| 1238 |
bdrv_set_enable_write_cache(s->bs, true);
|
| 1239 |
identify_data = (uint16_t *)s->identify_data; |
| 1240 |
put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1); |
| 1241 |
s->status = READY_STAT | SEEK_STAT; |
| 1242 |
ide_set_irq(s->bus); |
| 1243 |
break;
|
| 1244 |
case 0x82: /* write cache disable */ |
| 1245 |
bdrv_set_enable_write_cache(s->bs, false);
|
| 1246 |
identify_data = (uint16_t *)s->identify_data; |
| 1247 |
put_le16(identify_data + 85, (1 << 14) | 1); |
| 1248 |
ide_flush_cache(s); |
| 1249 |
break;
|
| 1250 |
case 0xcc: /* reverting to power-on defaults enable */ |
| 1251 |
case 0x66: /* reverting to power-on defaults disable */ |
| 1252 |
case 0xaa: /* read look-ahead enable */ |
| 1253 |
case 0x55: /* read look-ahead disable */ |
| 1254 |
case 0x05: /* set advanced power management mode */ |
| 1255 |
case 0x85: /* disable advanced power management mode */ |
| 1256 |
case 0x69: /* NOP */ |
| 1257 |
case 0x67: /* NOP */ |
| 1258 |
case 0x96: /* NOP */ |
| 1259 |
case 0x9a: /* NOP */ |
| 1260 |
case 0x42: /* enable Automatic Acoustic Mode */ |
| 1261 |
case 0xc2: /* disable Automatic Acoustic Mode */ |
| 1262 |
s->status = READY_STAT | SEEK_STAT; |
| 1263 |
ide_set_irq(s->bus); |
| 1264 |
break;
|
| 1265 |
case 0x03: { /* set transfer mode */ |
| 1266 |
uint8_t val = s->nsector & 0x07;
|
| 1267 |
identify_data = (uint16_t *)s->identify_data; |
| 1268 |
|
| 1269 |
switch (s->nsector >> 3) { |
| 1270 |
case 0x00: /* pio default */ |
| 1271 |
case 0x01: /* pio mode */ |
| 1272 |
put_le16(identify_data + 62,0x07); |
| 1273 |
put_le16(identify_data + 63,0x07); |
| 1274 |
put_le16(identify_data + 88,0x3f); |
| 1275 |
break;
|
| 1276 |
case 0x02: /* sigle word dma mode*/ |
| 1277 |
put_le16(identify_data + 62,0x07 | (1 << (val + 8))); |
| 1278 |
put_le16(identify_data + 63,0x07); |
| 1279 |
put_le16(identify_data + 88,0x3f); |
| 1280 |
break;
|
| 1281 |
case 0x04: /* mdma mode */ |
| 1282 |
put_le16(identify_data + 62,0x07); |
| 1283 |
put_le16(identify_data + 63,0x07 | (1 << (val + 8))); |
| 1284 |
put_le16(identify_data + 88,0x3f); |
| 1285 |
break;
|
| 1286 |
case 0x08: /* udma mode */ |
| 1287 |
put_le16(identify_data + 62,0x07); |
| 1288 |
put_le16(identify_data + 63,0x07); |
| 1289 |
put_le16(identify_data + 88,0x3f | (1 << (val + 8))); |
| 1290 |
break;
|
| 1291 |
default:
|
| 1292 |
goto abort_cmd;
|
| 1293 |
} |
| 1294 |
s->status = READY_STAT | SEEK_STAT; |
| 1295 |
ide_set_irq(s->bus); |
| 1296 |
break;
|
| 1297 |
} |
| 1298 |
default:
|
| 1299 |
goto abort_cmd;
|
| 1300 |
} |
| 1301 |
break;
|
| 1302 |
case WIN_FLUSH_CACHE:
|
| 1303 |
case WIN_FLUSH_CACHE_EXT:
|
| 1304 |
ide_flush_cache(s); |
| 1305 |
break;
|
| 1306 |
case WIN_STANDBY:
|
| 1307 |
case WIN_STANDBY2:
|
| 1308 |
case WIN_STANDBYNOW1:
|
| 1309 |
case WIN_STANDBYNOW2:
|
| 1310 |
case WIN_IDLEIMMEDIATE:
|
| 1311 |
case WIN_IDLEIMMEDIATE2:
|
| 1312 |
case WIN_SETIDLE1:
|
| 1313 |
case WIN_SETIDLE2:
|
| 1314 |
case WIN_SLEEPNOW1:
|
| 1315 |
case WIN_SLEEPNOW2:
|
| 1316 |
s->status = READY_STAT; |
| 1317 |
ide_set_irq(s->bus); |
| 1318 |
break;
|
| 1319 |
case WIN_SEEK:
|
| 1320 |
/* XXX: Check that seek is within bounds */
|
| 1321 |
s->status = READY_STAT | SEEK_STAT; |
| 1322 |
ide_set_irq(s->bus); |
| 1323 |
break;
|
| 1324 |
/* ATAPI commands */
|
| 1325 |
case WIN_PIDENTIFY:
|
| 1326 |
ide_atapi_identify(s); |
| 1327 |
s->status = READY_STAT | SEEK_STAT; |
| 1328 |
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
| 1329 |
ide_set_irq(s->bus); |
| 1330 |
break;
|
| 1331 |
case WIN_DIAGNOSE:
|
| 1332 |
ide_set_signature(s); |
| 1333 |
if (s->drive_kind == IDE_CD)
|
| 1334 |
s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet |
| 1335 |
* devices to return a clear status register
|
| 1336 |
* with READY_STAT *not* set. */
|
| 1337 |
else
|
| 1338 |
s->status = READY_STAT | SEEK_STAT; |
| 1339 |
s->error = 0x01; /* Device 0 passed, Device 1 passed or not |
| 1340 |
* present.
|
| 1341 |
*/
|
| 1342 |
ide_set_irq(s->bus); |
| 1343 |
break;
|
| 1344 |
case WIN_DEVICE_RESET:
|
| 1345 |
ide_set_signature(s); |
| 1346 |
s->status = 0x00; /* NOTE: READY is _not_ set */ |
| 1347 |
s->error = 0x01;
|
| 1348 |
break;
|
| 1349 |
case WIN_PACKETCMD:
|
| 1350 |
/* overlapping commands not supported */
|
| 1351 |
if (s->feature & 0x02) |
| 1352 |
goto abort_cmd;
|
| 1353 |
s->status = READY_STAT | SEEK_STAT; |
| 1354 |
s->atapi_dma = s->feature & 1;
|
| 1355 |
s->nsector = 1;
|
| 1356 |
ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, |
| 1357 |
ide_atapi_cmd); |
| 1358 |
break;
|
| 1359 |
/* CF-ATA commands */
|
| 1360 |
case CFA_REQ_EXT_ERROR_CODE:
|
| 1361 |
s->error = 0x09; /* miscellaneous error */ |
| 1362 |
s->status = READY_STAT | SEEK_STAT; |
| 1363 |
ide_set_irq(s->bus); |
| 1364 |
break;
|
| 1365 |
case CFA_ERASE_SECTORS:
|
| 1366 |
case CFA_WEAR_LEVEL:
|
| 1367 |
#if 0
|
| 1368 |
/* This one has the same ID as CFA_WEAR_LEVEL and is required for
|
| 1369 |
Windows 8 to work with AHCI */
|
| 1370 |
case WIN_SECURITY_FREEZE_LOCK:
|
| 1371 |
#endif
|
| 1372 |
if (val == CFA_WEAR_LEVEL)
|
| 1373 |
s->nsector = 0;
|
| 1374 |
if (val == CFA_ERASE_SECTORS)
|
| 1375 |
s->media_changed = 1;
|
| 1376 |
s->error = 0x00;
|
| 1377 |
s->status = READY_STAT | SEEK_STAT; |
| 1378 |
ide_set_irq(s->bus); |
| 1379 |
break;
|
| 1380 |
case CFA_TRANSLATE_SECTOR:
|
| 1381 |
s->error = 0x00;
|
| 1382 |
s->status = READY_STAT | SEEK_STAT; |
| 1383 |
memset(s->io_buffer, 0, 0x200); |
| 1384 |
s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ |
| 1385 |
s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ |
| 1386 |
s->io_buffer[0x02] = s->select; /* Head */ |
| 1387 |
s->io_buffer[0x03] = s->sector; /* Sector */ |
| 1388 |
s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ |
| 1389 |
s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ |
| 1390 |
s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ |
| 1391 |
s->io_buffer[0x13] = 0x00; /* Erase flag */ |
| 1392 |
s->io_buffer[0x18] = 0x00; /* Hot count */ |
| 1393 |
s->io_buffer[0x19] = 0x00; /* Hot count */ |
| 1394 |
s->io_buffer[0x1a] = 0x01; /* Hot count */ |
| 1395 |
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
| 1396 |
ide_set_irq(s->bus); |
| 1397 |
break;
|
| 1398 |
case CFA_ACCESS_METADATA_STORAGE:
|
| 1399 |
switch (s->feature) {
|
| 1400 |
case 0x02: /* Inquiry Metadata Storage */ |
| 1401 |
ide_cfata_metadata_inquiry(s); |
| 1402 |
break;
|
| 1403 |
case 0x03: /* Read Metadata Storage */ |
| 1404 |
ide_cfata_metadata_read(s); |
| 1405 |
break;
|
| 1406 |
case 0x04: /* Write Metadata Storage */ |
| 1407 |
ide_cfata_metadata_write(s); |
| 1408 |
break;
|
| 1409 |
default:
|
| 1410 |
goto abort_cmd;
|
| 1411 |
} |
| 1412 |
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
| 1413 |
s->status = 0x00; /* NOTE: READY is _not_ set */ |
| 1414 |
ide_set_irq(s->bus); |
| 1415 |
break;
|
| 1416 |
case IBM_SENSE_CONDITION:
|
| 1417 |
switch (s->feature) {
|
| 1418 |
case 0x01: /* sense temperature in device */ |
| 1419 |
s->nsector = 0x50; /* +20 C */ |
| 1420 |
break;
|
| 1421 |
default:
|
| 1422 |
goto abort_cmd;
|
| 1423 |
} |
| 1424 |
s->status = READY_STAT | SEEK_STAT; |
| 1425 |
ide_set_irq(s->bus); |
| 1426 |
break;
|
| 1427 |
|
| 1428 |
case WIN_SMART:
|
| 1429 |
if (s->hcyl != 0xc2 || s->lcyl != 0x4f) |
| 1430 |
goto abort_cmd;
|
| 1431 |
if (!s->smart_enabled && s->feature != SMART_ENABLE)
|
| 1432 |
goto abort_cmd;
|
| 1433 |
switch (s->feature) {
|
| 1434 |
case SMART_DISABLE:
|
| 1435 |
s->smart_enabled = 0;
|
| 1436 |
s->status = READY_STAT | SEEK_STAT; |
| 1437 |
ide_set_irq(s->bus); |
| 1438 |
break;
|
| 1439 |
case SMART_ENABLE:
|
| 1440 |
s->smart_enabled = 1;
|
| 1441 |
s->status = READY_STAT | SEEK_STAT; |
| 1442 |
ide_set_irq(s->bus); |
| 1443 |
break;
|
| 1444 |
case SMART_ATTR_AUTOSAVE:
|
| 1445 |
switch (s->sector) {
|
| 1446 |
case 0x00: |
| 1447 |
s->smart_autosave = 0;
|
| 1448 |
break;
|
| 1449 |
case 0xf1: |
| 1450 |
s->smart_autosave = 1;
|
| 1451 |
break;
|
| 1452 |
default:
|
| 1453 |
goto abort_cmd;
|
| 1454 |
} |
| 1455 |
s->status = READY_STAT | SEEK_STAT; |
| 1456 |
ide_set_irq(s->bus); |
| 1457 |
break;
|
| 1458 |
case SMART_STATUS:
|
| 1459 |
if (!s->smart_errors) {
|
| 1460 |
s->hcyl = 0xc2;
|
| 1461 |
s->lcyl = 0x4f;
|
| 1462 |
} else {
|
| 1463 |
s->hcyl = 0x2c;
|
| 1464 |
s->lcyl = 0xf4;
|
| 1465 |
} |
| 1466 |
s->status = READY_STAT | SEEK_STAT; |
| 1467 |
ide_set_irq(s->bus); |
| 1468 |
break;
|
| 1469 |
case SMART_READ_THRESH:
|
| 1470 |
memset(s->io_buffer, 0, 0x200); |
| 1471 |
s->io_buffer[0] = 0x01; /* smart struct version */ |
| 1472 |
for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { |
| 1473 |
s->io_buffer[2+0+(n*12)] = smart_attributes[n][0]; |
| 1474 |
s->io_buffer[2+1+(n*12)] = smart_attributes[n][11]; |
| 1475 |
} |
| 1476 |
for (n=0; n<511; n++) /* checksum */ |
| 1477 |
s->io_buffer[511] += s->io_buffer[n];
|
| 1478 |
s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
| 1479 |
s->status = READY_STAT | SEEK_STAT; |
| 1480 |
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
| 1481 |
ide_set_irq(s->bus); |
| 1482 |
break;
|
| 1483 |
case SMART_READ_DATA:
|
| 1484 |
memset(s->io_buffer, 0, 0x200); |
| 1485 |
s->io_buffer[0] = 0x01; /* smart struct version */ |
| 1486 |
for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { |
| 1487 |
int i;
|
| 1488 |
for(i = 0; i < 11; i++) { |
| 1489 |
s->io_buffer[2+i+(n*12)] = smart_attributes[n][i]; |
| 1490 |
} |
| 1491 |
} |
| 1492 |
s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00); |
| 1493 |
if (s->smart_selftest_count == 0) { |
| 1494 |
s->io_buffer[363] = 0; |
| 1495 |
} else {
|
| 1496 |
s->io_buffer[363] =
|
| 1497 |
s->smart_selftest_data[3 +
|
| 1498 |
(s->smart_selftest_count - 1) *
|
| 1499 |
24];
|
| 1500 |
} |
| 1501 |
s->io_buffer[364] = 0x20; |
| 1502 |
s->io_buffer[365] = 0x01; |
| 1503 |
/* offline data collection capacity: execute + self-test*/
|
| 1504 |
s->io_buffer[367] = (1<<4 | 1<<3 | 1); |
| 1505 |
s->io_buffer[368] = 0x03; /* smart capability (1) */ |
| 1506 |
s->io_buffer[369] = 0x00; /* smart capability (2) */ |
| 1507 |
s->io_buffer[370] = 0x01; /* error logging supported */ |
| 1508 |
s->io_buffer[372] = 0x02; /* minutes for poll short test */ |
| 1509 |
s->io_buffer[373] = 0x36; /* minutes for poll ext test */ |
| 1510 |
s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ |
| 1511 |
|
| 1512 |
for (n=0; n<511; n++) |
| 1513 |
s->io_buffer[511] += s->io_buffer[n];
|
| 1514 |
s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
| 1515 |
s->status = READY_STAT | SEEK_STAT; |
| 1516 |
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
| 1517 |
ide_set_irq(s->bus); |
| 1518 |
break;
|
| 1519 |
case SMART_READ_LOG:
|
| 1520 |
switch (s->sector) {
|
| 1521 |
case 0x01: /* summary smart error log */ |
| 1522 |
memset(s->io_buffer, 0, 0x200); |
| 1523 |
s->io_buffer[0] = 0x01; |
| 1524 |
s->io_buffer[1] = 0x00; /* no error entries */ |
| 1525 |
s->io_buffer[452] = s->smart_errors & 0xff; |
| 1526 |
s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; |
| 1527 |
|
| 1528 |
for (n=0; n<511; n++) |
| 1529 |
s->io_buffer[511] += s->io_buffer[n];
|
| 1530 |
s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
| 1531 |
break;
|
| 1532 |
case 0x06: /* smart self test log */ |
| 1533 |
memset(s->io_buffer, 0, 0x200); |
| 1534 |
s->io_buffer[0] = 0x01; |
| 1535 |
if (s->smart_selftest_count == 0) { |
| 1536 |
s->io_buffer[508] = 0; |
| 1537 |
} else {
|
| 1538 |
s->io_buffer[508] = s->smart_selftest_count;
|
| 1539 |
for (n=2; n<506; n++) |
| 1540 |
s->io_buffer[n] = s->smart_selftest_data[n]; |
| 1541 |
} |
| 1542 |
for (n=0; n<511; n++) |
| 1543 |
s->io_buffer[511] += s->io_buffer[n];
|
| 1544 |
s->io_buffer[511] = 0x100 - s->io_buffer[511]; |
| 1545 |
break;
|
| 1546 |
default:
|
| 1547 |
goto abort_cmd;
|
| 1548 |
} |
| 1549 |
s->status = READY_STAT | SEEK_STAT; |
| 1550 |
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
| 1551 |
ide_set_irq(s->bus); |
| 1552 |
break;
|
| 1553 |
case SMART_EXECUTE_OFFLINE:
|
| 1554 |
switch (s->sector) {
|
| 1555 |
case 0: /* off-line routine */ |
| 1556 |
case 1: /* short self test */ |
| 1557 |
case 2: /* extended self test */ |
| 1558 |
s->smart_selftest_count++; |
| 1559 |
if(s->smart_selftest_count > 21) |
| 1560 |
s->smart_selftest_count = 0;
|
| 1561 |
n = 2 + (s->smart_selftest_count - 1) * 24; |
| 1562 |
s->smart_selftest_data[n] = s->sector; |
| 1563 |
s->smart_selftest_data[n+1] = 0x00; /* OK and finished */ |
| 1564 |
s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */ |
| 1565 |
s->smart_selftest_data[n+3] = 0x12; /* hour count msb */ |
| 1566 |
s->status = READY_STAT | SEEK_STAT; |
| 1567 |
ide_set_irq(s->bus); |
| 1568 |
break;
|
| 1569 |
default:
|
| 1570 |
goto abort_cmd;
|
| 1571 |
} |
| 1572 |
break;
|
| 1573 |
default:
|
| 1574 |
goto abort_cmd;
|
| 1575 |
} |
| 1576 |
break;
|
| 1577 |
default:
|
| 1578 |
/* should not be reachable */
|
| 1579 |
abort_cmd:
|
| 1580 |
ide_abort_command(s); |
| 1581 |
ide_set_irq(s->bus); |
| 1582 |
break;
|
| 1583 |
} |
| 1584 |
} |
| 1585 |
|
| 1586 |
uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
|
| 1587 |
{
|
| 1588 |
IDEBus *bus = opaque; |
| 1589 |
IDEState *s = idebus_active_if(bus); |
| 1590 |
uint32_t addr; |
| 1591 |
int ret, hob;
|
| 1592 |
|
| 1593 |
addr = addr1 & 7;
|
| 1594 |
/* FIXME: HOB readback uses bit 7, but it's always set right now */
|
| 1595 |
//hob = s->select & (1 << 7);
|
| 1596 |
hob = 0;
|
| 1597 |
switch(addr) {
|
| 1598 |
case 0: |
| 1599 |
ret = 0xff;
|
| 1600 |
break;
|
| 1601 |
case 1: |
| 1602 |
if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
| 1603 |
(s != bus->ifs && !s->bs)) |
| 1604 |
ret = 0;
|
| 1605 |
else if (!hob) |
| 1606 |
ret = s->error; |
| 1607 |
else
|
| 1608 |
ret = s->hob_feature; |
| 1609 |
break;
|
| 1610 |
case 2: |
| 1611 |
if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
| 1612 |
ret = 0;
|
| 1613 |
else if (!hob) |
| 1614 |
ret = s->nsector & 0xff;
|
| 1615 |
else
|
| 1616 |
ret = s->hob_nsector; |
| 1617 |
break;
|
| 1618 |
case 3: |
| 1619 |
if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
| 1620 |
ret = 0;
|
| 1621 |
else if (!hob) |
| 1622 |
ret = s->sector; |
| 1623 |
else
|
| 1624 |
ret = s->hob_sector; |
| 1625 |
break;
|
| 1626 |
case 4: |
| 1627 |
if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
| 1628 |
ret = 0;
|
| 1629 |
else if (!hob) |
| 1630 |
ret = s->lcyl; |
| 1631 |
else
|
| 1632 |
ret = s->hob_lcyl; |
| 1633 |
break;
|
| 1634 |
case 5: |
| 1635 |
if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
| 1636 |
ret = 0;
|
| 1637 |
else if (!hob) |
| 1638 |
ret = s->hcyl; |
| 1639 |
else
|
| 1640 |
ret = s->hob_hcyl; |
| 1641 |
break;
|
| 1642 |
case 6: |
| 1643 |
if (!bus->ifs[0].bs && !bus->ifs[1].bs) |
| 1644 |
ret = 0;
|
| 1645 |
else
|
| 1646 |
ret = s->select; |
| 1647 |
break;
|
| 1648 |
default:
|
| 1649 |
case 7: |
| 1650 |
if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
| 1651 |
(s != bus->ifs && !s->bs)) |
| 1652 |
ret = 0;
|
| 1653 |
else
|
| 1654 |
ret = s->status; |
| 1655 |
qemu_irq_lower(bus->irq); |
| 1656 |
break;
|
| 1657 |
} |
| 1658 |
#ifdef DEBUG_IDE
|
| 1659 |
printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
|
| 1660 |
#endif
|
| 1661 |
return ret;
|
| 1662 |
} |
| 1663 |
|
| 1664 |
uint32_t ide_status_read(void *opaque, uint32_t addr)
|
| 1665 |
{
|
| 1666 |
IDEBus *bus = opaque; |
| 1667 |
IDEState *s = idebus_active_if(bus); |
| 1668 |
int ret;
|
| 1669 |
|
| 1670 |
if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || |
| 1671 |
(s != bus->ifs && !s->bs)) |
| 1672 |
ret = 0;
|
| 1673 |
else
|
| 1674 |
ret = s->status; |
| 1675 |
#ifdef DEBUG_IDE
|
| 1676 |
printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
|
| 1677 |
#endif
|
| 1678 |
return ret;
|
| 1679 |
} |
| 1680 |
|
| 1681 |
void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) |
| 1682 |
{
|
| 1683 |
IDEBus *bus = opaque; |
| 1684 |
IDEState *s; |
| 1685 |
int i;
|
| 1686 |
|
| 1687 |
#ifdef DEBUG_IDE
|
| 1688 |
printf("ide: write control addr=0x%x val=%02x\n", addr, val);
|
| 1689 |
#endif
|
| 1690 |
/* common for both drives */
|
| 1691 |
if (!(bus->cmd & IDE_CMD_RESET) &&
|
| 1692 |
(val & IDE_CMD_RESET)) {
|
| 1693 |
/* reset low to high */
|
| 1694 |
for(i = 0;i < 2; i++) { |
| 1695 |
s = &bus->ifs[i]; |
| 1696 |
s->status = BUSY_STAT | SEEK_STAT; |
| 1697 |
s->error = 0x01;
|
| 1698 |
} |
| 1699 |
} else if ((bus->cmd & IDE_CMD_RESET) && |
| 1700 |
!(val & IDE_CMD_RESET)) {
|
| 1701 |
/* high to low */
|
| 1702 |
for(i = 0;i < 2; i++) { |
| 1703 |
s = &bus->ifs[i]; |
| 1704 |
if (s->drive_kind == IDE_CD)
|
| 1705 |
s->status = 0x00; /* NOTE: READY is _not_ set */ |
| 1706 |
else
|
| 1707 |
s->status = READY_STAT | SEEK_STAT; |
| 1708 |
ide_set_signature(s); |
| 1709 |
} |
| 1710 |
} |
| 1711 |
|
| 1712 |
bus->cmd = val; |
| 1713 |
} |
| 1714 |
|
| 1715 |
/*
|
| 1716 |
* Returns true if the running PIO transfer is a PIO out (i.e. data is
|
| 1717 |
* transferred from the device to the guest), false if it's a PIO in
|
| 1718 |
*/
|
| 1719 |
static bool ide_is_pio_out(IDEState *s) |
| 1720 |
{
|
| 1721 |
if (s->end_transfer_func == ide_sector_write ||
|
| 1722 |
s->end_transfer_func == ide_atapi_cmd) {
|
| 1723 |
return false; |
| 1724 |
} else if (s->end_transfer_func == ide_sector_read || |
| 1725 |
s->end_transfer_func == ide_transfer_stop || |
| 1726 |
s->end_transfer_func == ide_atapi_cmd_reply_end || |
| 1727 |
s->end_transfer_func == ide_dummy_transfer_stop) {
|
| 1728 |
return true; |
| 1729 |
} |
| 1730 |
|
| 1731 |
abort(); |
| 1732 |
} |
| 1733 |
|
| 1734 |
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) |
| 1735 |
{
|
| 1736 |
IDEBus *bus = opaque; |
| 1737 |
IDEState *s = idebus_active_if(bus); |
| 1738 |
uint8_t *p; |
| 1739 |
|
| 1740 |
/* PIO data access allowed only when DRQ bit is set. The result of a write
|
| 1741 |
* during PIO out is indeterminate, just ignore it. */
|
| 1742 |
if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
|
| 1743 |
return;
|
| 1744 |
} |
| 1745 |
|
| 1746 |
p = s->data_ptr; |
| 1747 |
*(uint16_t *)p = le16_to_cpu(val); |
| 1748 |
p += 2;
|
| 1749 |
s->data_ptr = p; |
| 1750 |
if (p >= s->data_end)
|
| 1751 |
s->end_transfer_func(s); |
| 1752 |
} |
| 1753 |
|
| 1754 |
uint32_t ide_data_readw(void *opaque, uint32_t addr)
|
| 1755 |
{
|
| 1756 |
IDEBus *bus = opaque; |
| 1757 |
IDEState *s = idebus_active_if(bus); |
| 1758 |
uint8_t *p; |
| 1759 |
int ret;
|
| 1760 |
|
| 1761 |
/* PIO data access allowed only when DRQ bit is set. The result of a read
|
| 1762 |
* during PIO in is indeterminate, return 0 and don't move forward. */
|
| 1763 |
if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
|
| 1764 |
return 0; |
| 1765 |
} |
| 1766 |
|
| 1767 |
p = s->data_ptr; |
| 1768 |
ret = cpu_to_le16(*(uint16_t *)p); |
| 1769 |
p += 2;
|
| 1770 |
s->data_ptr = p; |
| 1771 |
if (p >= s->data_end)
|
| 1772 |
s->end_transfer_func(s); |
| 1773 |
return ret;
|
| 1774 |
} |
| 1775 |
|
| 1776 |
void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) |
| 1777 |
{
|
| 1778 |
IDEBus *bus = opaque; |
| 1779 |
IDEState *s = idebus_active_if(bus); |
| 1780 |
uint8_t *p; |
| 1781 |
|
| 1782 |
/* PIO data access allowed only when DRQ bit is set. The result of a write
|
| 1783 |
* during PIO out is indeterminate, just ignore it. */
|
| 1784 |
if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
|
| 1785 |
return;
|
| 1786 |
} |
| 1787 |
|
| 1788 |
p = s->data_ptr; |
| 1789 |
*(uint32_t *)p = le32_to_cpu(val); |
| 1790 |
p += 4;
|
| 1791 |
s->data_ptr = p; |
| 1792 |
if (p >= s->data_end)
|
| 1793 |
s->end_transfer_func(s); |
| 1794 |
} |
| 1795 |
|
| 1796 |
uint32_t ide_data_readl(void *opaque, uint32_t addr)
|
| 1797 |
{
|
| 1798 |
IDEBus *bus = opaque; |
| 1799 |
IDEState *s = idebus_active_if(bus); |
| 1800 |
uint8_t *p; |
| 1801 |
int ret;
|
| 1802 |
|
| 1803 |
/* PIO data access allowed only when DRQ bit is set. The result of a read
|
| 1804 |
* during PIO in is indeterminate, return 0 and don't move forward. */
|
| 1805 |
if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
|
| 1806 |
return 0; |
| 1807 |
} |
| 1808 |
|
| 1809 |
p = s->data_ptr; |
| 1810 |
ret = cpu_to_le32(*(uint32_t *)p); |
| 1811 |
p += 4;
|
| 1812 |
s->data_ptr = p; |
| 1813 |
if (p >= s->data_end)
|
| 1814 |
s->end_transfer_func(s); |
| 1815 |
return ret;
|
| 1816 |
} |
| 1817 |
|
| 1818 |
static void ide_dummy_transfer_stop(IDEState *s) |
| 1819 |
{
|
| 1820 |
s->data_ptr = s->io_buffer; |
| 1821 |
s->data_end = s->io_buffer; |
| 1822 |
s->io_buffer[0] = 0xff; |
| 1823 |
s->io_buffer[1] = 0xff; |
| 1824 |
s->io_buffer[2] = 0xff; |
| 1825 |
s->io_buffer[3] = 0xff; |
| 1826 |
} |
| 1827 |
|
| 1828 |
static void ide_reset(IDEState *s) |
| 1829 |
{
|
| 1830 |
#ifdef DEBUG_IDE
|
| 1831 |
printf("ide: reset\n");
|
| 1832 |
#endif
|
| 1833 |
|
| 1834 |
if (s->pio_aiocb) {
|
| 1835 |
bdrv_aio_cancel(s->pio_aiocb); |
| 1836 |
s->pio_aiocb = NULL;
|
| 1837 |
} |
| 1838 |
|
| 1839 |
if (s->drive_kind == IDE_CFATA)
|
| 1840 |
s->mult_sectors = 0;
|
| 1841 |
else
|
| 1842 |
s->mult_sectors = MAX_MULT_SECTORS; |
| 1843 |
/* ide regs */
|
| 1844 |
s->feature = 0;
|
| 1845 |
s->error = 0;
|
| 1846 |
s->nsector = 0;
|
| 1847 |
s->sector = 0;
|
| 1848 |
s->lcyl = 0;
|
| 1849 |
s->hcyl = 0;
|
| 1850 |
|
| 1851 |
/* lba48 */
|
| 1852 |
s->hob_feature = 0;
|
| 1853 |
s->hob_sector = 0;
|
| 1854 |
s->hob_nsector = 0;
|
| 1855 |
s->hob_lcyl = 0;
|
| 1856 |
s->hob_hcyl = 0;
|
| 1857 |
|
| 1858 |
s->select = 0xa0;
|
| 1859 |
s->status = READY_STAT | SEEK_STAT; |
| 1860 |
|
| 1861 |
s->lba48 = 0;
|
| 1862 |
|
| 1863 |
/* ATAPI specific */
|
| 1864 |
s->sense_key = 0;
|
| 1865 |
s->asc = 0;
|
| 1866 |
s->cdrom_changed = 0;
|
| 1867 |
s->packet_transfer_size = 0;
|
| 1868 |
s->elementary_transfer_size = 0;
|
| 1869 |
s->io_buffer_index = 0;
|
| 1870 |
s->cd_sector_size = 0;
|
| 1871 |
s->atapi_dma = 0;
|
| 1872 |
s->tray_locked = 0;
|
| 1873 |
s->tray_open = 0;
|
| 1874 |
/* ATA DMA state */
|
| 1875 |
s->io_buffer_size = 0;
|
| 1876 |
s->req_nb_sectors = 0;
|
| 1877 |
|
| 1878 |
ide_set_signature(s); |
| 1879 |
/* init the transfer handler so that 0xffff is returned on data
|
| 1880 |
accesses */
|
| 1881 |
s->end_transfer_func = ide_dummy_transfer_stop; |
| 1882 |
ide_dummy_transfer_stop(s); |
| 1883 |
s->media_changed = 0;
|
| 1884 |
} |
| 1885 |
|
| 1886 |
void ide_bus_reset(IDEBus *bus)
|
| 1887 |
{
|
| 1888 |
bus->unit = 0;
|
| 1889 |
bus->cmd = 0;
|
| 1890 |
ide_reset(&bus->ifs[0]);
|
| 1891 |
ide_reset(&bus->ifs[1]);
|
| 1892 |
ide_clear_hob(bus); |
| 1893 |
|
| 1894 |
/* pending async DMA */
|
| 1895 |
if (bus->dma->aiocb) {
|
| 1896 |
#ifdef DEBUG_AIO
|
| 1897 |
printf("aio_cancel\n");
|
| 1898 |
#endif
|
| 1899 |
bdrv_aio_cancel(bus->dma->aiocb); |
| 1900 |
bus->dma->aiocb = NULL;
|
| 1901 |
} |
| 1902 |
|
| 1903 |
/* reset dma provider too */
|
| 1904 |
bus->dma->ops->reset(bus->dma); |
| 1905 |
} |
| 1906 |
|
| 1907 |
static bool ide_cd_is_tray_open(void *opaque) |
| 1908 |
{
|
| 1909 |
return ((IDEState *)opaque)->tray_open;
|
| 1910 |
} |
| 1911 |
|
| 1912 |
static bool ide_cd_is_medium_locked(void *opaque) |
| 1913 |
{
|
| 1914 |
return ((IDEState *)opaque)->tray_locked;
|
| 1915 |
} |
| 1916 |
|
| 1917 |
static const BlockDevOps ide_cd_block_ops = { |
| 1918 |
.change_media_cb = ide_cd_change_cb, |
| 1919 |
.eject_request_cb = ide_cd_eject_request_cb, |
| 1920 |
.is_tray_open = ide_cd_is_tray_open, |
| 1921 |
.is_medium_locked = ide_cd_is_medium_locked, |
| 1922 |
}; |
| 1923 |
|
| 1924 |
int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
|
| 1925 |
const char *version, const char *serial, const char *model, |
| 1926 |
uint64_t wwn, |
| 1927 |
uint32_t cylinders, uint32_t heads, uint32_t secs, |
| 1928 |
int chs_trans)
|
| 1929 |
{
|
| 1930 |
uint64_t nb_sectors; |
| 1931 |
|
| 1932 |
s->bs = bs; |
| 1933 |
s->drive_kind = kind; |
| 1934 |
|
| 1935 |
bdrv_get_geometry(bs, &nb_sectors); |
| 1936 |
s->cylinders = cylinders; |
| 1937 |
s->heads = heads; |
| 1938 |
s->sectors = secs; |
| 1939 |
s->chs_trans = chs_trans; |
| 1940 |
s->nb_sectors = nb_sectors; |
| 1941 |
s->wwn = wwn; |
| 1942 |
/* The SMART values should be preserved across power cycles
|
| 1943 |
but they aren't. */
|
| 1944 |
s->smart_enabled = 1;
|
| 1945 |
s->smart_autosave = 1;
|
| 1946 |
s->smart_errors = 0;
|
| 1947 |
s->smart_selftest_count = 0;
|
| 1948 |
if (kind == IDE_CD) {
|
| 1949 |
bdrv_set_dev_ops(bs, &ide_cd_block_ops, s); |
| 1950 |
bdrv_set_buffer_alignment(bs, 2048);
|
| 1951 |
} else {
|
| 1952 |
if (!bdrv_is_inserted(s->bs)) {
|
| 1953 |
error_report("Device needs media, but drive is empty");
|
| 1954 |
return -1; |
| 1955 |
} |
| 1956 |
if (bdrv_is_read_only(bs)) {
|
| 1957 |
error_report("Can't use a read-only drive");
|
| 1958 |
return -1; |
| 1959 |
} |
| 1960 |
} |
| 1961 |
if (serial) {
|
| 1962 |
pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
|
| 1963 |
} else {
|
| 1964 |
snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
|
| 1965 |
"QM%05d", s->drive_serial);
|
| 1966 |
} |
| 1967 |
if (model) {
|
| 1968 |
pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
|
| 1969 |
} else {
|
| 1970 |
switch (kind) {
|
| 1971 |
case IDE_CD:
|
| 1972 |
strcpy(s->drive_model_str, "QEMU DVD-ROM");
|
| 1973 |
break;
|
| 1974 |
case IDE_CFATA:
|
| 1975 |
strcpy(s->drive_model_str, "QEMU MICRODRIVE");
|
| 1976 |
break;
|
| 1977 |
default:
|
| 1978 |
strcpy(s->drive_model_str, "QEMU HARDDISK");
|
| 1979 |
break;
|
| 1980 |
} |
| 1981 |
} |
| 1982 |
|
| 1983 |
if (version) {
|
| 1984 |
pstrcpy(s->version, sizeof(s->version), version);
|
| 1985 |
} else {
|
| 1986 |
pstrcpy(s->version, sizeof(s->version), qemu_get_version());
|
| 1987 |
} |
| 1988 |
|
| 1989 |
ide_reset(s); |
| 1990 |
bdrv_iostatus_enable(bs); |
| 1991 |
return 0; |
| 1992 |
} |
| 1993 |
|
| 1994 |
static void ide_init1(IDEBus *bus, int unit) |
| 1995 |
{
|
| 1996 |
static int drive_serial = 1; |
| 1997 |
IDEState *s = &bus->ifs[unit]; |
| 1998 |
|
| 1999 |
s->bus = bus; |
| 2000 |
s->unit = unit; |
| 2001 |
s->drive_serial = drive_serial++; |
| 2002 |
/* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
|
| 2003 |
s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; |
| 2004 |
s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
|
| 2005 |
memset(s->io_buffer, 0, s->io_buffer_total_len);
|
| 2006 |
|
| 2007 |
s->smart_selftest_data = qemu_blockalign(s->bs, 512);
|
| 2008 |
memset(s->smart_selftest_data, 0, 512); |
| 2009 |
|
| 2010 |
s->sector_write_timer = qemu_new_timer_ns(vm_clock, |
| 2011 |
ide_sector_write_timer_cb, s); |
| 2012 |
} |
| 2013 |
|
| 2014 |
static void ide_nop_start(IDEDMA *dma, IDEState *s, |
| 2015 |
BlockDriverCompletionFunc *cb) |
| 2016 |
{
|
| 2017 |
} |
| 2018 |
|
| 2019 |
static int ide_nop(IDEDMA *dma) |
| 2020 |
{
|
| 2021 |
return 0; |
| 2022 |
} |
| 2023 |
|
| 2024 |
static int ide_nop_int(IDEDMA *dma, int x) |
| 2025 |
{
|
| 2026 |
return 0; |
| 2027 |
} |
| 2028 |
|
| 2029 |
static void ide_nop_restart(void *opaque, int x, RunState y) |
| 2030 |
{
|
| 2031 |
} |
| 2032 |
|
| 2033 |
static const IDEDMAOps ide_dma_nop_ops = { |
| 2034 |
.start_dma = ide_nop_start, |
| 2035 |
.start_transfer = ide_nop, |
| 2036 |
.prepare_buf = ide_nop_int, |
| 2037 |
.rw_buf = ide_nop_int, |
| 2038 |
.set_unit = ide_nop_int, |
| 2039 |
.add_status = ide_nop_int, |
| 2040 |
.set_inactive = ide_nop, |
| 2041 |
.restart_cb = ide_nop_restart, |
| 2042 |
.reset = ide_nop, |
| 2043 |
}; |
| 2044 |
|
| 2045 |
static IDEDMA ide_dma_nop = {
|
| 2046 |
.ops = &ide_dma_nop_ops, |
| 2047 |
.aiocb = NULL,
|
| 2048 |
}; |
| 2049 |
|
| 2050 |
void ide_init2(IDEBus *bus, qemu_irq irq)
|
| 2051 |
{
|
| 2052 |
int i;
|
| 2053 |
|
| 2054 |
for(i = 0; i < 2; i++) { |
| 2055 |
ide_init1(bus, i); |
| 2056 |
ide_reset(&bus->ifs[i]); |
| 2057 |
} |
| 2058 |
bus->irq = irq; |
| 2059 |
bus->dma = &ide_dma_nop; |
| 2060 |
} |
| 2061 |
|
| 2062 |
/* TODO convert users to qdev and remove */
|
| 2063 |
void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
|
| 2064 |
DriveInfo *hd1, qemu_irq irq) |
| 2065 |
{
|
| 2066 |
int i, trans;
|
| 2067 |
DriveInfo *dinfo; |
| 2068 |
uint32_t cyls, heads, secs; |
| 2069 |
|
| 2070 |
for(i = 0; i < 2; i++) { |
| 2071 |
dinfo = i == 0 ? hd0 : hd1;
|
| 2072 |
ide_init1(bus, i); |
| 2073 |
if (dinfo) {
|
| 2074 |
cyls = dinfo->cyls; |
| 2075 |
heads = dinfo->heads; |
| 2076 |
secs = dinfo->secs; |
| 2077 |
trans = dinfo->trans; |
| 2078 |
if (!cyls && !heads && !secs) {
|
| 2079 |
hd_geometry_guess(dinfo->bdrv, &cyls, &heads, &secs, &trans); |
| 2080 |
} else if (trans == BIOS_ATA_TRANSLATION_AUTO) { |
| 2081 |
trans = hd_bios_chs_auto_trans(cyls, heads, secs); |
| 2082 |
} |
| 2083 |
if (cyls < 1 || cyls > 65535) { |
| 2084 |
error_report("cyls must be between 1 and 65535");
|
| 2085 |
exit(1);
|
| 2086 |
} |
| 2087 |
if (heads < 1 || heads > 16) { |
| 2088 |
error_report("heads must be between 1 and 16");
|
| 2089 |
exit(1);
|
| 2090 |
} |
| 2091 |
if (secs < 1 || secs > 255) { |
| 2092 |
error_report("secs must be between 1 and 255");
|
| 2093 |
exit(1);
|
| 2094 |
} |
| 2095 |
if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
|
| 2096 |
dinfo->media_cd ? IDE_CD : IDE_HD, |
| 2097 |
NULL, dinfo->serial, NULL, 0, |
| 2098 |
cyls, heads, secs, trans) < 0) {
|
| 2099 |
error_report("Can't set up IDE drive %s", dinfo->id);
|
| 2100 |
exit(1);
|
| 2101 |
} |
| 2102 |
bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]); |
| 2103 |
} else {
|
| 2104 |
ide_reset(&bus->ifs[i]); |
| 2105 |
} |
| 2106 |
} |
| 2107 |
bus->irq = irq; |
| 2108 |
bus->dma = &ide_dma_nop; |
| 2109 |
} |
| 2110 |
|
| 2111 |
static const MemoryRegionPortio ide_portio_list[] = { |
| 2112 |
{ 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
|
| 2113 |
{ 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
|
| 2114 |
{ 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
|
| 2115 |
PORTIO_END_OF_LIST(), |
| 2116 |
}; |
| 2117 |
|
| 2118 |
static const MemoryRegionPortio ide_portio2_list[] = { |
| 2119 |
{ 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
|
| 2120 |
PORTIO_END_OF_LIST(), |
| 2121 |
}; |
| 2122 |
|
| 2123 |
void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2) |
| 2124 |
{
|
| 2125 |
/* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
|
| 2126 |
bridge has been setup properly to always register with ISA. */
|
| 2127 |
isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
|
| 2128 |
|
| 2129 |
if (iobase2) {
|
| 2130 |
isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
|
| 2131 |
} |
| 2132 |
} |
| 2133 |
|
| 2134 |
static bool is_identify_set(void *opaque, int version_id) |
| 2135 |
{
|
| 2136 |
IDEState *s = opaque; |
| 2137 |
|
| 2138 |
return s->identify_set != 0; |
| 2139 |
} |
| 2140 |
|
| 2141 |
static EndTransferFunc* transfer_end_table[] = {
|
| 2142 |
ide_sector_read, |
| 2143 |
ide_sector_write, |
| 2144 |
ide_transfer_stop, |
| 2145 |
ide_atapi_cmd_reply_end, |
| 2146 |
ide_atapi_cmd, |
| 2147 |
ide_dummy_transfer_stop, |
| 2148 |
}; |
| 2149 |
|
| 2150 |
static int transfer_end_table_idx(EndTransferFunc *fn) |
| 2151 |
{
|
| 2152 |
int i;
|
| 2153 |
|
| 2154 |
for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) |
| 2155 |
if (transfer_end_table[i] == fn)
|
| 2156 |
return i;
|
| 2157 |
|
| 2158 |
return -1; |
| 2159 |
} |
| 2160 |
|
| 2161 |
static int ide_drive_post_load(void *opaque, int version_id) |
| 2162 |
{
|
| 2163 |
IDEState *s = opaque; |
| 2164 |
|
| 2165 |
if (s->identify_set) {
|
| 2166 |
bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5))); |
| 2167 |
} |
| 2168 |
return 0; |
| 2169 |
} |
| 2170 |
|
| 2171 |
static int ide_drive_pio_post_load(void *opaque, int version_id) |
| 2172 |
{
|
| 2173 |
IDEState *s = opaque; |
| 2174 |
|
| 2175 |
if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
|
| 2176 |
return -EINVAL;
|
| 2177 |
} |
| 2178 |
s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; |
| 2179 |
s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; |
| 2180 |
s->data_end = s->data_ptr + s->cur_io_buffer_len; |
| 2181 |
|
| 2182 |
return 0; |
| 2183 |
} |
| 2184 |
|
| 2185 |
static void ide_drive_pio_pre_save(void *opaque) |
| 2186 |
{
|
| 2187 |
IDEState *s = opaque; |
| 2188 |
int idx;
|
| 2189 |
|
| 2190 |
s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; |
| 2191 |
s->cur_io_buffer_len = s->data_end - s->data_ptr; |
| 2192 |
|
| 2193 |
idx = transfer_end_table_idx(s->end_transfer_func); |
| 2194 |
if (idx == -1) { |
| 2195 |
fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
|
| 2196 |
__func__); |
| 2197 |
s->end_transfer_fn_idx = 2;
|
| 2198 |
} else {
|
| 2199 |
s->end_transfer_fn_idx = idx; |
| 2200 |
} |
| 2201 |
} |
| 2202 |
|
| 2203 |
static bool ide_drive_pio_state_needed(void *opaque) |
| 2204 |
{
|
| 2205 |
IDEState *s = opaque; |
| 2206 |
|
| 2207 |
return ((s->status & DRQ_STAT) != 0) |
| 2208 |
|| (s->bus->error_status & BM_STATUS_PIO_RETRY); |
| 2209 |
} |
| 2210 |
|
| 2211 |
static bool ide_tray_state_needed(void *opaque) |
| 2212 |
{
|
| 2213 |
IDEState *s = opaque; |
| 2214 |
|
| 2215 |
return s->tray_open || s->tray_locked;
|
| 2216 |
} |
| 2217 |
|
| 2218 |
static bool ide_atapi_gesn_needed(void *opaque) |
| 2219 |
{
|
| 2220 |
IDEState *s = opaque; |
| 2221 |
|
| 2222 |
return s->events.new_media || s->events.eject_request;
|
| 2223 |
} |
| 2224 |
|
| 2225 |
static bool ide_error_needed(void *opaque) |
| 2226 |
{
|
| 2227 |
IDEBus *bus = opaque; |
| 2228 |
|
| 2229 |
return (bus->error_status != 0); |
| 2230 |
} |
| 2231 |
|
| 2232 |
/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
|
| 2233 |
static const VMStateDescription vmstate_ide_atapi_gesn_state = { |
| 2234 |
.name ="ide_drive/atapi/gesn_state",
|
| 2235 |
.version_id = 1,
|
| 2236 |
.minimum_version_id = 1,
|
| 2237 |
.minimum_version_id_old = 1,
|
| 2238 |
.fields = (VMStateField []) {
|
| 2239 |
VMSTATE_BOOL(events.new_media, IDEState), |
| 2240 |
VMSTATE_BOOL(events.eject_request, IDEState), |
| 2241 |
VMSTATE_END_OF_LIST() |
| 2242 |
} |
| 2243 |
}; |
| 2244 |
|
| 2245 |
static const VMStateDescription vmstate_ide_tray_state = { |
| 2246 |
.name = "ide_drive/tray_state",
|
| 2247 |
.version_id = 1,
|
| 2248 |
.minimum_version_id = 1,
|
| 2249 |
.minimum_version_id_old = 1,
|
| 2250 |
.fields = (VMStateField[]) {
|
| 2251 |
VMSTATE_BOOL(tray_open, IDEState), |
| 2252 |
VMSTATE_BOOL(tray_locked, IDEState), |
| 2253 |
VMSTATE_END_OF_LIST() |
| 2254 |
} |
| 2255 |
}; |
| 2256 |
|
| 2257 |
static const VMStateDescription vmstate_ide_drive_pio_state = { |
| 2258 |
.name = "ide_drive/pio_state",
|
| 2259 |
.version_id = 1,
|
| 2260 |
.minimum_version_id = 1,
|
| 2261 |
.minimum_version_id_old = 1,
|
| 2262 |
.pre_save = ide_drive_pio_pre_save, |
| 2263 |
.post_load = ide_drive_pio_post_load, |
| 2264 |
.fields = (VMStateField []) {
|
| 2265 |
VMSTATE_INT32(req_nb_sectors, IDEState), |
| 2266 |
VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
|
| 2267 |
vmstate_info_uint8, uint8_t), |
| 2268 |
VMSTATE_INT32(cur_io_buffer_offset, IDEState), |
| 2269 |
VMSTATE_INT32(cur_io_buffer_len, IDEState), |
| 2270 |
VMSTATE_UINT8(end_transfer_fn_idx, IDEState), |
| 2271 |
VMSTATE_INT32(elementary_transfer_size, IDEState), |
| 2272 |
VMSTATE_INT32(packet_transfer_size, IDEState), |
| 2273 |
VMSTATE_END_OF_LIST() |
| 2274 |
} |
| 2275 |
}; |
| 2276 |
|
| 2277 |
const VMStateDescription vmstate_ide_drive = {
|
| 2278 |
.name = "ide_drive",
|
| 2279 |
.version_id = 3,
|
| 2280 |
.minimum_version_id = 0,
|
| 2281 |
.minimum_version_id_old = 0,
|
| 2282 |
.post_load = ide_drive_post_load, |
| 2283 |
.fields = (VMStateField []) {
|
| 2284 |
VMSTATE_INT32(mult_sectors, IDEState), |
| 2285 |
VMSTATE_INT32(identify_set, IDEState), |
| 2286 |
VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), |
| 2287 |
VMSTATE_UINT8(feature, IDEState), |
| 2288 |
VMSTATE_UINT8(error, IDEState), |
| 2289 |
VMSTATE_UINT32(nsector, IDEState), |
| 2290 |
VMSTATE_UINT8(sector, IDEState), |
| 2291 |
VMSTATE_UINT8(lcyl, IDEState), |
| 2292 |
VMSTATE_UINT8(hcyl, IDEState), |
| 2293 |
VMSTATE_UINT8(hob_feature, IDEState), |
| 2294 |
VMSTATE_UINT8(hob_sector, IDEState), |
| 2295 |
VMSTATE_UINT8(hob_nsector, IDEState), |
| 2296 |
VMSTATE_UINT8(hob_lcyl, IDEState), |
| 2297 |
VMSTATE_UINT8(hob_hcyl, IDEState), |
| 2298 |
VMSTATE_UINT8(select, IDEState), |
| 2299 |
VMSTATE_UINT8(status, IDEState), |
| 2300 |
VMSTATE_UINT8(lba48, IDEState), |
| 2301 |
VMSTATE_UINT8(sense_key, IDEState), |
| 2302 |
VMSTATE_UINT8(asc, IDEState), |
| 2303 |
VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
|
| 2304 |
VMSTATE_END_OF_LIST() |
| 2305 |
}, |
| 2306 |
.subsections = (VMStateSubsection []) {
|
| 2307 |
{
|
| 2308 |
.vmsd = &vmstate_ide_drive_pio_state, |
| 2309 |
.needed = ide_drive_pio_state_needed, |
| 2310 |
}, {
|
| 2311 |
.vmsd = &vmstate_ide_tray_state, |
| 2312 |
.needed = ide_tray_state_needed, |
| 2313 |
}, {
|
| 2314 |
.vmsd = &vmstate_ide_atapi_gesn_state, |
| 2315 |
.needed = ide_atapi_gesn_needed, |
| 2316 |
}, {
|
| 2317 |
/* empty */
|
| 2318 |
} |
| 2319 |
} |
| 2320 |
}; |
| 2321 |
|
| 2322 |
static const VMStateDescription vmstate_ide_error_status = { |
| 2323 |
.name ="ide_bus/error",
|
| 2324 |
.version_id = 1,
|
| 2325 |
.minimum_version_id = 1,
|
| 2326 |
.minimum_version_id_old = 1,
|
| 2327 |
.fields = (VMStateField []) {
|
| 2328 |
VMSTATE_INT32(error_status, IDEBus), |
| 2329 |
VMSTATE_END_OF_LIST() |
| 2330 |
} |
| 2331 |
}; |
| 2332 |
|
| 2333 |
const VMStateDescription vmstate_ide_bus = {
|
| 2334 |
.name = "ide_bus",
|
| 2335 |
.version_id = 1,
|
| 2336 |
.minimum_version_id = 1,
|
| 2337 |
.minimum_version_id_old = 1,
|
| 2338 |
.fields = (VMStateField []) {
|
| 2339 |
VMSTATE_UINT8(cmd, IDEBus), |
| 2340 |
VMSTATE_UINT8(unit, IDEBus), |
| 2341 |
VMSTATE_END_OF_LIST() |
| 2342 |
}, |
| 2343 |
.subsections = (VMStateSubsection []) {
|
| 2344 |
{
|
| 2345 |
.vmsd = &vmstate_ide_error_status, |
| 2346 |
.needed = ide_error_needed, |
| 2347 |
}, {
|
| 2348 |
/* empty */
|
| 2349 |
} |
| 2350 |
} |
| 2351 |
}; |
| 2352 |
|
| 2353 |
void ide_drive_get(DriveInfo **hd, int max_bus) |
| 2354 |
{
|
| 2355 |
int i;
|
| 2356 |
|
| 2357 |
if (drive_get_max_bus(IF_IDE) >= max_bus) {
|
| 2358 |
fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
|
| 2359 |
exit(1);
|
| 2360 |
} |
| 2361 |
|
| 2362 |
for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) { |
| 2363 |
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
| 2364 |
} |
| 2365 |
} |