root / hw / usb / hcd-ohci.c @ 1de7afc9
History | View | Annotate | Download (54.6 kB)
1 |
/*
|
---|---|
2 |
* QEMU USB OHCI Emulation
|
3 |
* Copyright (c) 2004 Gianni Tedesco
|
4 |
* Copyright (c) 2006 CodeSourcery
|
5 |
* Copyright (c) 2006 Openedhand Ltd.
|
6 |
*
|
7 |
* This library is free software; you can redistribute it and/or
|
8 |
* modify it under the terms of the GNU Lesser General Public
|
9 |
* License as published by the Free Software Foundation; either
|
10 |
* version 2 of the License, or (at your option) any later version.
|
11 |
*
|
12 |
* This library is distributed in the hope that it will be useful,
|
13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 |
* Lesser General Public License for more details.
|
16 |
*
|
17 |
* You should have received a copy of the GNU Lesser General Public
|
18 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
19 |
*
|
20 |
* TODO:
|
21 |
* o Isochronous transfers
|
22 |
* o Allocate bandwidth in frames properly
|
23 |
* o Disable timers when nothing needs to be done, or remove timer usage
|
24 |
* all together.
|
25 |
* o Handle unrecoverable errors properly
|
26 |
* o BIOS work to boot from USB storage
|
27 |
*/
|
28 |
|
29 |
#include "hw/hw.h" |
30 |
#include "qemu/timer.h" |
31 |
#include "hw/usb.h" |
32 |
#include "hw/pci/pci.h" |
33 |
#include "hw/sysbus.h" |
34 |
#include "hw/qdev-dma.h" |
35 |
|
36 |
//#define DEBUG_OHCI
|
37 |
/* Dump packet contents. */
|
38 |
//#define DEBUG_PACKET
|
39 |
//#define DEBUG_ISOCH
|
40 |
/* This causes frames to occur 1000x slower */
|
41 |
//#define OHCI_TIME_WARP 1
|
42 |
|
43 |
#ifdef DEBUG_OHCI
|
44 |
#define DPRINTF printf
|
45 |
#else
|
46 |
#define DPRINTF(...)
|
47 |
#endif
|
48 |
|
49 |
/* Number of Downstream Ports on the root hub. */
|
50 |
|
51 |
#define OHCI_MAX_PORTS 15 |
52 |
|
53 |
static int64_t usb_frame_time;
|
54 |
static int64_t usb_bit_time;
|
55 |
|
56 |
typedef struct OHCIPort { |
57 |
USBPort port; |
58 |
uint32_t ctrl; |
59 |
} OHCIPort; |
60 |
|
61 |
typedef struct { |
62 |
USBBus bus; |
63 |
qemu_irq irq; |
64 |
MemoryRegion mem; |
65 |
DMAContext *dma; |
66 |
int num_ports;
|
67 |
const char *name; |
68 |
|
69 |
QEMUTimer *eof_timer; |
70 |
int64_t sof_time; |
71 |
|
72 |
/* OHCI state */
|
73 |
/* Control partition */
|
74 |
uint32_t ctl, status; |
75 |
uint32_t intr_status; |
76 |
uint32_t intr; |
77 |
|
78 |
/* memory pointer partition */
|
79 |
uint32_t hcca; |
80 |
uint32_t ctrl_head, ctrl_cur; |
81 |
uint32_t bulk_head, bulk_cur; |
82 |
uint32_t per_cur; |
83 |
uint32_t done; |
84 |
int done_count;
|
85 |
|
86 |
/* Frame counter partition */
|
87 |
uint32_t fsmps:15;
|
88 |
uint32_t fit:1;
|
89 |
uint32_t fi:14;
|
90 |
uint32_t frt:1;
|
91 |
uint16_t frame_number; |
92 |
uint16_t padding; |
93 |
uint32_t pstart; |
94 |
uint32_t lst; |
95 |
|
96 |
/* Root Hub partition */
|
97 |
uint32_t rhdesc_a, rhdesc_b; |
98 |
uint32_t rhstatus; |
99 |
OHCIPort rhport[OHCI_MAX_PORTS]; |
100 |
|
101 |
/* PXA27x Non-OHCI events */
|
102 |
uint32_t hstatus; |
103 |
uint32_t hmask; |
104 |
uint32_t hreset; |
105 |
uint32_t htest; |
106 |
|
107 |
/* SM501 local memory offset */
|
108 |
dma_addr_t localmem_base; |
109 |
|
110 |
/* Active packets. */
|
111 |
uint32_t old_ctl; |
112 |
USBPacket usb_packet; |
113 |
uint8_t usb_buf[8192];
|
114 |
uint32_t async_td; |
115 |
int async_complete;
|
116 |
|
117 |
} OHCIState; |
118 |
|
119 |
/* Host Controller Communications Area */
|
120 |
struct ohci_hcca {
|
121 |
uint32_t intr[32];
|
122 |
uint16_t frame, pad; |
123 |
uint32_t done; |
124 |
}; |
125 |
#define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) |
126 |
#define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ |
127 |
|
128 |
#define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) |
129 |
#define ED_WBACK_SIZE 4 |
130 |
|
131 |
static void ohci_bus_stop(OHCIState *ohci); |
132 |
static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); |
133 |
|
134 |
/* Bitfields for the first word of an Endpoint Desciptor. */
|
135 |
#define OHCI_ED_FA_SHIFT 0 |
136 |
#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) |
137 |
#define OHCI_ED_EN_SHIFT 7 |
138 |
#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) |
139 |
#define OHCI_ED_D_SHIFT 11 |
140 |
#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) |
141 |
#define OHCI_ED_S (1<<13) |
142 |
#define OHCI_ED_K (1<<14) |
143 |
#define OHCI_ED_F (1<<15) |
144 |
#define OHCI_ED_MPS_SHIFT 16 |
145 |
#define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) |
146 |
|
147 |
/* Flags in the head field of an Endpoint Desciptor. */
|
148 |
#define OHCI_ED_H 1 |
149 |
#define OHCI_ED_C 2 |
150 |
|
151 |
/* Bitfields for the first word of a Transfer Desciptor. */
|
152 |
#define OHCI_TD_R (1<<18) |
153 |
#define OHCI_TD_DP_SHIFT 19 |
154 |
#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) |
155 |
#define OHCI_TD_DI_SHIFT 21 |
156 |
#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) |
157 |
#define OHCI_TD_T0 (1<<24) |
158 |
#define OHCI_TD_T1 (1<<25) |
159 |
#define OHCI_TD_EC_SHIFT 26 |
160 |
#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) |
161 |
#define OHCI_TD_CC_SHIFT 28 |
162 |
#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) |
163 |
|
164 |
/* Bitfields for the first word of an Isochronous Transfer Desciptor. */
|
165 |
/* CC & DI - same as in the General Transfer Desciptor */
|
166 |
#define OHCI_TD_SF_SHIFT 0 |
167 |
#define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) |
168 |
#define OHCI_TD_FC_SHIFT 24 |
169 |
#define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) |
170 |
|
171 |
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
|
172 |
#define OHCI_TD_PSW_CC_SHIFT 12 |
173 |
#define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) |
174 |
#define OHCI_TD_PSW_SIZE_SHIFT 0 |
175 |
#define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) |
176 |
|
177 |
#define OHCI_PAGE_MASK 0xfffff000 |
178 |
#define OHCI_OFFSET_MASK 0xfff |
179 |
|
180 |
#define OHCI_DPTR_MASK 0xfffffff0 |
181 |
|
182 |
#define OHCI_BM(val, field) \
|
183 |
(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) |
184 |
|
185 |
#define OHCI_SET_BM(val, field, newval) do { \ |
186 |
val &= ~OHCI_##field##_MASK; \ |
187 |
val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ |
188 |
} while(0) |
189 |
|
190 |
/* endpoint descriptor */
|
191 |
struct ohci_ed {
|
192 |
uint32_t flags; |
193 |
uint32_t tail; |
194 |
uint32_t head; |
195 |
uint32_t next; |
196 |
}; |
197 |
|
198 |
/* General transfer descriptor */
|
199 |
struct ohci_td {
|
200 |
uint32_t flags; |
201 |
uint32_t cbp; |
202 |
uint32_t next; |
203 |
uint32_t be; |
204 |
}; |
205 |
|
206 |
/* Isochronous transfer descriptor */
|
207 |
struct ohci_iso_td {
|
208 |
uint32_t flags; |
209 |
uint32_t bp; |
210 |
uint32_t next; |
211 |
uint32_t be; |
212 |
uint16_t offset[8];
|
213 |
}; |
214 |
|
215 |
#define USB_HZ 12000000 |
216 |
|
217 |
/* OHCI Local stuff */
|
218 |
#define OHCI_CTL_CBSR ((1<<0)|(1<<1)) |
219 |
#define OHCI_CTL_PLE (1<<2) |
220 |
#define OHCI_CTL_IE (1<<3) |
221 |
#define OHCI_CTL_CLE (1<<4) |
222 |
#define OHCI_CTL_BLE (1<<5) |
223 |
#define OHCI_CTL_HCFS ((1<<6)|(1<<7)) |
224 |
#define OHCI_USB_RESET 0x00 |
225 |
#define OHCI_USB_RESUME 0x40 |
226 |
#define OHCI_USB_OPERATIONAL 0x80 |
227 |
#define OHCI_USB_SUSPEND 0xc0 |
228 |
#define OHCI_CTL_IR (1<<8) |
229 |
#define OHCI_CTL_RWC (1<<9) |
230 |
#define OHCI_CTL_RWE (1<<10) |
231 |
|
232 |
#define OHCI_STATUS_HCR (1<<0) |
233 |
#define OHCI_STATUS_CLF (1<<1) |
234 |
#define OHCI_STATUS_BLF (1<<2) |
235 |
#define OHCI_STATUS_OCR (1<<3) |
236 |
#define OHCI_STATUS_SOC ((1<<6)|(1<<7)) |
237 |
|
238 |
#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ |
239 |
#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ |
240 |
#define OHCI_INTR_SF (1<<2) /* Start of frame */ |
241 |
#define OHCI_INTR_RD (1<<3) /* Resume detect */ |
242 |
#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ |
243 |
#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ |
244 |
#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ |
245 |
#define OHCI_INTR_OC (1<<30) /* Ownership change */ |
246 |
#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ |
247 |
|
248 |
#define OHCI_HCCA_SIZE 0x100 |
249 |
#define OHCI_HCCA_MASK 0xffffff00 |
250 |
|
251 |
#define OHCI_EDPTR_MASK 0xfffffff0 |
252 |
|
253 |
#define OHCI_FMI_FI 0x00003fff |
254 |
#define OHCI_FMI_FSMPS 0xffff0000 |
255 |
#define OHCI_FMI_FIT 0x80000000 |
256 |
|
257 |
#define OHCI_FR_RT (1<<31) |
258 |
|
259 |
#define OHCI_LS_THRESH 0x628 |
260 |
|
261 |
#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ |
262 |
#define OHCI_RHA_PSM (1<<8) |
263 |
#define OHCI_RHA_NPS (1<<9) |
264 |
#define OHCI_RHA_DT (1<<10) |
265 |
#define OHCI_RHA_OCPM (1<<11) |
266 |
#define OHCI_RHA_NOCP (1<<12) |
267 |
#define OHCI_RHA_POTPGT_MASK 0xff000000 |
268 |
|
269 |
#define OHCI_RHS_LPS (1<<0) |
270 |
#define OHCI_RHS_OCI (1<<1) |
271 |
#define OHCI_RHS_DRWE (1<<15) |
272 |
#define OHCI_RHS_LPSC (1<<16) |
273 |
#define OHCI_RHS_OCIC (1<<17) |
274 |
#define OHCI_RHS_CRWE (1<<31) |
275 |
|
276 |
#define OHCI_PORT_CCS (1<<0) |
277 |
#define OHCI_PORT_PES (1<<1) |
278 |
#define OHCI_PORT_PSS (1<<2) |
279 |
#define OHCI_PORT_POCI (1<<3) |
280 |
#define OHCI_PORT_PRS (1<<4) |
281 |
#define OHCI_PORT_PPS (1<<8) |
282 |
#define OHCI_PORT_LSDA (1<<9) |
283 |
#define OHCI_PORT_CSC (1<<16) |
284 |
#define OHCI_PORT_PESC (1<<17) |
285 |
#define OHCI_PORT_PSSC (1<<18) |
286 |
#define OHCI_PORT_OCIC (1<<19) |
287 |
#define OHCI_PORT_PRSC (1<<20) |
288 |
#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
|
289 |
|OHCI_PORT_OCIC|OHCI_PORT_PRSC) |
290 |
|
291 |
#define OHCI_TD_DIR_SETUP 0x0 |
292 |
#define OHCI_TD_DIR_OUT 0x1 |
293 |
#define OHCI_TD_DIR_IN 0x2 |
294 |
#define OHCI_TD_DIR_RESERVED 0x3 |
295 |
|
296 |
#define OHCI_CC_NOERROR 0x0 |
297 |
#define OHCI_CC_CRC 0x1 |
298 |
#define OHCI_CC_BITSTUFFING 0x2 |
299 |
#define OHCI_CC_DATATOGGLEMISMATCH 0x3 |
300 |
#define OHCI_CC_STALL 0x4 |
301 |
#define OHCI_CC_DEVICENOTRESPONDING 0x5 |
302 |
#define OHCI_CC_PIDCHECKFAILURE 0x6 |
303 |
#define OHCI_CC_UNDEXPETEDPID 0x7 |
304 |
#define OHCI_CC_DATAOVERRUN 0x8 |
305 |
#define OHCI_CC_DATAUNDERRUN 0x9 |
306 |
#define OHCI_CC_BUFFEROVERRUN 0xc |
307 |
#define OHCI_CC_BUFFERUNDERRUN 0xd |
308 |
|
309 |
#define OHCI_HRESET_FSBIR (1 << 0) |
310 |
|
311 |
/* Update IRQ levels */
|
312 |
static inline void ohci_intr_update(OHCIState *ohci) |
313 |
{ |
314 |
int level = 0; |
315 |
|
316 |
if ((ohci->intr & OHCI_INTR_MIE) &&
|
317 |
(ohci->intr_status & ohci->intr)) |
318 |
level = 1;
|
319 |
|
320 |
qemu_set_irq(ohci->irq, level); |
321 |
} |
322 |
|
323 |
/* Set an interrupt */
|
324 |
static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) |
325 |
{ |
326 |
ohci->intr_status |= intr; |
327 |
ohci_intr_update(ohci); |
328 |
} |
329 |
|
330 |
/* Attach or detach a device on a root hub port. */
|
331 |
static void ohci_attach(USBPort *port1) |
332 |
{ |
333 |
OHCIState *s = port1->opaque; |
334 |
OHCIPort *port = &s->rhport[port1->index]; |
335 |
uint32_t old_state = port->ctrl; |
336 |
|
337 |
/* set connect status */
|
338 |
port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; |
339 |
|
340 |
/* update speed */
|
341 |
if (port->port.dev->speed == USB_SPEED_LOW) {
|
342 |
port->ctrl |= OHCI_PORT_LSDA; |
343 |
} else {
|
344 |
port->ctrl &= ~OHCI_PORT_LSDA; |
345 |
} |
346 |
|
347 |
/* notify of remote-wakeup */
|
348 |
if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
|
349 |
ohci_set_interrupt(s, OHCI_INTR_RD); |
350 |
} |
351 |
|
352 |
DPRINTF("usb-ohci: Attached port %d\n", port1->index);
|
353 |
|
354 |
if (old_state != port->ctrl) {
|
355 |
ohci_set_interrupt(s, OHCI_INTR_RHSC); |
356 |
} |
357 |
} |
358 |
|
359 |
static void ohci_detach(USBPort *port1) |
360 |
{ |
361 |
OHCIState *s = port1->opaque; |
362 |
OHCIPort *port = &s->rhport[port1->index]; |
363 |
uint32_t old_state = port->ctrl; |
364 |
|
365 |
ohci_async_cancel_device(s, port1->dev); |
366 |
|
367 |
/* set connect status */
|
368 |
if (port->ctrl & OHCI_PORT_CCS) {
|
369 |
port->ctrl &= ~OHCI_PORT_CCS; |
370 |
port->ctrl |= OHCI_PORT_CSC; |
371 |
} |
372 |
/* disable port */
|
373 |
if (port->ctrl & OHCI_PORT_PES) {
|
374 |
port->ctrl &= ~OHCI_PORT_PES; |
375 |
port->ctrl |= OHCI_PORT_PESC; |
376 |
} |
377 |
DPRINTF("usb-ohci: Detached port %d\n", port1->index);
|
378 |
|
379 |
if (old_state != port->ctrl) {
|
380 |
ohci_set_interrupt(s, OHCI_INTR_RHSC); |
381 |
} |
382 |
} |
383 |
|
384 |
static void ohci_wakeup(USBPort *port1) |
385 |
{ |
386 |
OHCIState *s = port1->opaque; |
387 |
OHCIPort *port = &s->rhport[port1->index]; |
388 |
uint32_t intr = 0;
|
389 |
if (port->ctrl & OHCI_PORT_PSS) {
|
390 |
DPRINTF("usb-ohci: port %d: wakeup\n", port1->index);
|
391 |
port->ctrl |= OHCI_PORT_PSSC; |
392 |
port->ctrl &= ~OHCI_PORT_PSS; |
393 |
intr = OHCI_INTR_RHSC; |
394 |
} |
395 |
/* Note that the controller can be suspended even if this port is not */
|
396 |
if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
|
397 |
DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
|
398 |
/* This is the one state transition the controller can do by itself */
|
399 |
s->ctl &= ~OHCI_CTL_HCFS; |
400 |
s->ctl |= OHCI_USB_RESUME; |
401 |
/* In suspend mode only ResumeDetected is possible, not RHSC:
|
402 |
* see the OHCI spec 5.1.2.3.
|
403 |
*/
|
404 |
intr = OHCI_INTR_RD; |
405 |
} |
406 |
ohci_set_interrupt(s, intr); |
407 |
} |
408 |
|
409 |
static void ohci_child_detach(USBPort *port1, USBDevice *child) |
410 |
{ |
411 |
OHCIState *s = port1->opaque; |
412 |
|
413 |
ohci_async_cancel_device(s, child); |
414 |
} |
415 |
|
416 |
static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr)
|
417 |
{ |
418 |
USBDevice *dev; |
419 |
int i;
|
420 |
|
421 |
for (i = 0; i < ohci->num_ports; i++) { |
422 |
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { |
423 |
continue;
|
424 |
} |
425 |
dev = usb_find_device(&ohci->rhport[i].port, addr); |
426 |
if (dev != NULL) { |
427 |
return dev;
|
428 |
} |
429 |
} |
430 |
return NULL; |
431 |
} |
432 |
|
433 |
/* Reset the controller */
|
434 |
static void ohci_reset(void *opaque) |
435 |
{ |
436 |
OHCIState *ohci = opaque; |
437 |
OHCIPort *port; |
438 |
int i;
|
439 |
|
440 |
ohci_bus_stop(ohci); |
441 |
ohci->ctl = 0;
|
442 |
ohci->old_ctl = 0;
|
443 |
ohci->status = 0;
|
444 |
ohci->intr_status = 0;
|
445 |
ohci->intr = OHCI_INTR_MIE; |
446 |
|
447 |
ohci->hcca = 0;
|
448 |
ohci->ctrl_head = ohci->ctrl_cur = 0;
|
449 |
ohci->bulk_head = ohci->bulk_cur = 0;
|
450 |
ohci->per_cur = 0;
|
451 |
ohci->done = 0;
|
452 |
ohci->done_count = 7;
|
453 |
|
454 |
/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
|
455 |
* I took the value linux sets ...
|
456 |
*/
|
457 |
ohci->fsmps = 0x2778;
|
458 |
ohci->fi = 0x2edf;
|
459 |
ohci->fit = 0;
|
460 |
ohci->frt = 0;
|
461 |
ohci->frame_number = 0;
|
462 |
ohci->pstart = 0;
|
463 |
ohci->lst = OHCI_LS_THRESH; |
464 |
|
465 |
ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; |
466 |
ohci->rhdesc_b = 0x0; /* Impl. specific */ |
467 |
ohci->rhstatus = 0;
|
468 |
|
469 |
for (i = 0; i < ohci->num_ports; i++) |
470 |
{ |
471 |
port = &ohci->rhport[i]; |
472 |
port->ctrl = 0;
|
473 |
if (port->port.dev && port->port.dev->attached) {
|
474 |
usb_port_reset(&port->port); |
475 |
} |
476 |
} |
477 |
if (ohci->async_td) {
|
478 |
usb_cancel_packet(&ohci->usb_packet); |
479 |
ohci->async_td = 0;
|
480 |
} |
481 |
DPRINTF("usb-ohci: Reset %s\n", ohci->name);
|
482 |
} |
483 |
|
484 |
/* Get an array of dwords from main memory */
|
485 |
static inline int get_dwords(OHCIState *ohci, |
486 |
dma_addr_t addr, uint32_t *buf, int num)
|
487 |
{ |
488 |
int i;
|
489 |
|
490 |
addr += ohci->localmem_base; |
491 |
|
492 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
493 |
dma_memory_read(ohci->dma, addr, buf, sizeof(*buf));
|
494 |
*buf = le32_to_cpu(*buf); |
495 |
} |
496 |
|
497 |
return 1; |
498 |
} |
499 |
|
500 |
/* Put an array of dwords in to main memory */
|
501 |
static inline int put_dwords(OHCIState *ohci, |
502 |
dma_addr_t addr, uint32_t *buf, int num)
|
503 |
{ |
504 |
int i;
|
505 |
|
506 |
addr += ohci->localmem_base; |
507 |
|
508 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
509 |
uint32_t tmp = cpu_to_le32(*buf); |
510 |
dma_memory_write(ohci->dma, addr, &tmp, sizeof(tmp));
|
511 |
} |
512 |
|
513 |
return 1; |
514 |
} |
515 |
|
516 |
/* Get an array of words from main memory */
|
517 |
static inline int get_words(OHCIState *ohci, |
518 |
dma_addr_t addr, uint16_t *buf, int num)
|
519 |
{ |
520 |
int i;
|
521 |
|
522 |
addr += ohci->localmem_base; |
523 |
|
524 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
525 |
dma_memory_read(ohci->dma, addr, buf, sizeof(*buf));
|
526 |
*buf = le16_to_cpu(*buf); |
527 |
} |
528 |
|
529 |
return 1; |
530 |
} |
531 |
|
532 |
/* Put an array of words in to main memory */
|
533 |
static inline int put_words(OHCIState *ohci, |
534 |
dma_addr_t addr, uint16_t *buf, int num)
|
535 |
{ |
536 |
int i;
|
537 |
|
538 |
addr += ohci->localmem_base; |
539 |
|
540 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
541 |
uint16_t tmp = cpu_to_le16(*buf); |
542 |
dma_memory_write(ohci->dma, addr, &tmp, sizeof(tmp));
|
543 |
} |
544 |
|
545 |
return 1; |
546 |
} |
547 |
|
548 |
static inline int ohci_read_ed(OHCIState *ohci, |
549 |
dma_addr_t addr, struct ohci_ed *ed)
|
550 |
{ |
551 |
return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
552 |
} |
553 |
|
554 |
static inline int ohci_read_td(OHCIState *ohci, |
555 |
dma_addr_t addr, struct ohci_td *td)
|
556 |
{ |
557 |
return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
558 |
} |
559 |
|
560 |
static inline int ohci_read_iso_td(OHCIState *ohci, |
561 |
dma_addr_t addr, struct ohci_iso_td *td)
|
562 |
{ |
563 |
return (get_dwords(ohci, addr, (uint32_t *)td, 4) && |
564 |
get_words(ohci, addr + 16, td->offset, 8)); |
565 |
} |
566 |
|
567 |
static inline int ohci_read_hcca(OHCIState *ohci, |
568 |
dma_addr_t addr, struct ohci_hcca *hcca)
|
569 |
{ |
570 |
dma_memory_read(ohci->dma, addr + ohci->localmem_base, hcca, sizeof(*hcca));
|
571 |
return 1; |
572 |
} |
573 |
|
574 |
static inline int ohci_put_ed(OHCIState *ohci, |
575 |
dma_addr_t addr, struct ohci_ed *ed)
|
576 |
{ |
577 |
/* ed->tail is under control of the HCD.
|
578 |
* Since just ed->head is changed by HC, just write back this
|
579 |
*/
|
580 |
|
581 |
return put_dwords(ohci, addr + ED_WBACK_OFFSET,
|
582 |
(uint32_t *)((char *)ed + ED_WBACK_OFFSET),
|
583 |
ED_WBACK_SIZE >> 2);
|
584 |
} |
585 |
|
586 |
static inline int ohci_put_td(OHCIState *ohci, |
587 |
dma_addr_t addr, struct ohci_td *td)
|
588 |
{ |
589 |
return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
590 |
} |
591 |
|
592 |
static inline int ohci_put_iso_td(OHCIState *ohci, |
593 |
dma_addr_t addr, struct ohci_iso_td *td)
|
594 |
{ |
595 |
return (put_dwords(ohci, addr, (uint32_t *)td, 4) && |
596 |
put_words(ohci, addr + 16, td->offset, 8)); |
597 |
} |
598 |
|
599 |
static inline int ohci_put_hcca(OHCIState *ohci, |
600 |
dma_addr_t addr, struct ohci_hcca *hcca)
|
601 |
{ |
602 |
dma_memory_write(ohci->dma, |
603 |
addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, |
604 |
(char *)hcca + HCCA_WRITEBACK_OFFSET,
|
605 |
HCCA_WRITEBACK_SIZE); |
606 |
return 1; |
607 |
} |
608 |
|
609 |
/* Read/Write the contents of a TD from/to main memory. */
|
610 |
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td, |
611 |
uint8_t *buf, int len, DMADirection dir)
|
612 |
{ |
613 |
dma_addr_t ptr, n; |
614 |
|
615 |
ptr = td->cbp; |
616 |
n = 0x1000 - (ptr & 0xfff); |
617 |
if (n > len)
|
618 |
n = len; |
619 |
dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, n, dir); |
620 |
if (n == len)
|
621 |
return;
|
622 |
ptr = td->be & ~0xfffu;
|
623 |
buf += n; |
624 |
dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, len - n, dir); |
625 |
} |
626 |
|
627 |
/* Read/Write the contents of an ISO TD from/to main memory. */
|
628 |
static void ohci_copy_iso_td(OHCIState *ohci, |
629 |
uint32_t start_addr, uint32_t end_addr, |
630 |
uint8_t *buf, int len, DMADirection dir)
|
631 |
{ |
632 |
dma_addr_t ptr, n; |
633 |
|
634 |
ptr = start_addr; |
635 |
n = 0x1000 - (ptr & 0xfff); |
636 |
if (n > len)
|
637 |
n = len; |
638 |
dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, n, dir); |
639 |
if (n == len)
|
640 |
return;
|
641 |
ptr = end_addr & ~0xfffu;
|
642 |
buf += n; |
643 |
dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, len - n, dir); |
644 |
} |
645 |
|
646 |
static void ohci_process_lists(OHCIState *ohci, int completion); |
647 |
|
648 |
static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) |
649 |
{ |
650 |
OHCIState *ohci = container_of(packet, OHCIState, usb_packet); |
651 |
#ifdef DEBUG_PACKET
|
652 |
DPRINTF("Async packet complete\n");
|
653 |
#endif
|
654 |
ohci->async_complete = 1;
|
655 |
ohci_process_lists(ohci, 1);
|
656 |
} |
657 |
|
658 |
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
|
659 |
|
660 |
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, |
661 |
int completion)
|
662 |
{ |
663 |
int dir;
|
664 |
size_t len = 0;
|
665 |
#ifdef DEBUG_ISOCH
|
666 |
const char *str = NULL; |
667 |
#endif
|
668 |
int pid;
|
669 |
int ret;
|
670 |
int i;
|
671 |
USBDevice *dev; |
672 |
USBEndpoint *ep; |
673 |
struct ohci_iso_td iso_td;
|
674 |
uint32_t addr; |
675 |
uint16_t starting_frame; |
676 |
int16_t relative_frame_number; |
677 |
int frame_count;
|
678 |
uint32_t start_offset, next_offset, end_offset = 0;
|
679 |
uint32_t start_addr, end_addr; |
680 |
|
681 |
addr = ed->head & OHCI_DPTR_MASK; |
682 |
|
683 |
if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
|
684 |
printf("usb-ohci: ISO_TD read error at %x\n", addr);
|
685 |
return 0; |
686 |
} |
687 |
|
688 |
starting_frame = OHCI_BM(iso_td.flags, TD_SF); |
689 |
frame_count = OHCI_BM(iso_td.flags, TD_FC); |
690 |
relative_frame_number = USUB(ohci->frame_number, starting_frame); |
691 |
|
692 |
#ifdef DEBUG_ISOCH
|
693 |
printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
|
694 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
695 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
696 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
697 |
"frame_number 0x%.8x starting_frame 0x%.8x\n"
|
698 |
"frame_count 0x%.8x relative %d\n"
|
699 |
"di 0x%.8x cc 0x%.8x\n",
|
700 |
ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, |
701 |
iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, |
702 |
iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3], |
703 |
iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7], |
704 |
ohci->frame_number, starting_frame, |
705 |
frame_count, relative_frame_number, |
706 |
OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC)); |
707 |
#endif
|
708 |
|
709 |
if (relative_frame_number < 0) { |
710 |
DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
|
711 |
return 1; |
712 |
} else if (relative_frame_number > frame_count) { |
713 |
/* ISO TD expired - retire the TD to the Done Queue and continue with
|
714 |
the next ISO TD of the same ED */
|
715 |
DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
|
716 |
frame_count); |
717 |
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
718 |
ed->head &= ~OHCI_DPTR_MASK; |
719 |
ed->head |= (iso_td.next & OHCI_DPTR_MASK); |
720 |
iso_td.next = ohci->done; |
721 |
ohci->done = addr; |
722 |
i = OHCI_BM(iso_td.flags, TD_DI); |
723 |
if (i < ohci->done_count)
|
724 |
ohci->done_count = i; |
725 |
ohci_put_iso_td(ohci, addr, &iso_td); |
726 |
return 0; |
727 |
} |
728 |
|
729 |
dir = OHCI_BM(ed->flags, ED_D); |
730 |
switch (dir) {
|
731 |
case OHCI_TD_DIR_IN:
|
732 |
#ifdef DEBUG_ISOCH
|
733 |
str = "in";
|
734 |
#endif
|
735 |
pid = USB_TOKEN_IN; |
736 |
break;
|
737 |
case OHCI_TD_DIR_OUT:
|
738 |
#ifdef DEBUG_ISOCH
|
739 |
str = "out";
|
740 |
#endif
|
741 |
pid = USB_TOKEN_OUT; |
742 |
break;
|
743 |
case OHCI_TD_DIR_SETUP:
|
744 |
#ifdef DEBUG_ISOCH
|
745 |
str = "setup";
|
746 |
#endif
|
747 |
pid = USB_TOKEN_SETUP; |
748 |
break;
|
749 |
default:
|
750 |
printf("usb-ohci: Bad direction %d\n", dir);
|
751 |
return 1; |
752 |
} |
753 |
|
754 |
if (!iso_td.bp || !iso_td.be) {
|
755 |
printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
|
756 |
return 1; |
757 |
} |
758 |
|
759 |
start_offset = iso_td.offset[relative_frame_number]; |
760 |
next_offset = iso_td.offset[relative_frame_number + 1];
|
761 |
|
762 |
if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || |
763 |
((relative_frame_number < frame_count) && |
764 |
!(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
|
765 |
printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
|
766 |
start_offset, next_offset); |
767 |
return 1; |
768 |
} |
769 |
|
770 |
if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
|
771 |
printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
|
772 |
start_offset, next_offset); |
773 |
return 1; |
774 |
} |
775 |
|
776 |
if ((start_offset & 0x1000) == 0) { |
777 |
start_addr = (iso_td.bp & OHCI_PAGE_MASK) | |
778 |
(start_offset & OHCI_OFFSET_MASK); |
779 |
} else {
|
780 |
start_addr = (iso_td.be & OHCI_PAGE_MASK) | |
781 |
(start_offset & OHCI_OFFSET_MASK); |
782 |
} |
783 |
|
784 |
if (relative_frame_number < frame_count) {
|
785 |
end_offset = next_offset - 1;
|
786 |
if ((end_offset & 0x1000) == 0) { |
787 |
end_addr = (iso_td.bp & OHCI_PAGE_MASK) | |
788 |
(end_offset & OHCI_OFFSET_MASK); |
789 |
} else {
|
790 |
end_addr = (iso_td.be & OHCI_PAGE_MASK) | |
791 |
(end_offset & OHCI_OFFSET_MASK); |
792 |
} |
793 |
} else {
|
794 |
/* Last packet in the ISO TD */
|
795 |
end_addr = iso_td.be; |
796 |
} |
797 |
|
798 |
if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
|
799 |
len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
|
800 |
- (start_addr & OHCI_OFFSET_MASK); |
801 |
} else {
|
802 |
len = end_addr - start_addr + 1;
|
803 |
} |
804 |
|
805 |
if (len && dir != OHCI_TD_DIR_IN) {
|
806 |
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, |
807 |
DMA_DIRECTION_TO_DEVICE); |
808 |
} |
809 |
|
810 |
if (!completion) {
|
811 |
bool int_req = relative_frame_number == frame_count &&
|
812 |
OHCI_BM(iso_td.flags, TD_DI) == 0;
|
813 |
dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); |
814 |
ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); |
815 |
usb_packet_setup(&ohci->usb_packet, pid, ep, addr, false, int_req);
|
816 |
usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); |
817 |
usb_handle_packet(dev, &ohci->usb_packet); |
818 |
if (ohci->usb_packet.status == USB_RET_ASYNC) {
|
819 |
usb_device_flush_ep_queue(dev, ep); |
820 |
return 1; |
821 |
} |
822 |
} |
823 |
if (ohci->usb_packet.status == USB_RET_SUCCESS) {
|
824 |
ret = ohci->usb_packet.actual_length; |
825 |
} else {
|
826 |
ret = ohci->usb_packet.status; |
827 |
} |
828 |
|
829 |
#ifdef DEBUG_ISOCH
|
830 |
printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
|
831 |
start_offset, end_offset, start_addr, end_addr, str, len, ret); |
832 |
#endif
|
833 |
|
834 |
/* Writeback */
|
835 |
if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { |
836 |
/* IN transfer succeeded */
|
837 |
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, |
838 |
DMA_DIRECTION_FROM_DEVICE); |
839 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
840 |
OHCI_CC_NOERROR); |
841 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); |
842 |
} else if (dir == OHCI_TD_DIR_OUT && ret == len) { |
843 |
/* OUT transfer succeeded */
|
844 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
845 |
OHCI_CC_NOERROR); |
846 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
|
847 |
} else {
|
848 |
if (ret > (ssize_t) len) {
|
849 |
printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
|
850 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
851 |
OHCI_CC_DATAOVERRUN); |
852 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
853 |
len); |
854 |
} else if (ret >= 0) { |
855 |
printf("usb-ohci: DataUnderrun %d\n", ret);
|
856 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
857 |
OHCI_CC_DATAUNDERRUN); |
858 |
} else {
|
859 |
switch (ret) {
|
860 |
case USB_RET_IOERROR:
|
861 |
case USB_RET_NODEV:
|
862 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
863 |
OHCI_CC_DEVICENOTRESPONDING); |
864 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
865 |
0);
|
866 |
break;
|
867 |
case USB_RET_NAK:
|
868 |
case USB_RET_STALL:
|
869 |
printf("usb-ohci: got NAK/STALL %d\n", ret);
|
870 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
871 |
OHCI_CC_STALL); |
872 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
873 |
0);
|
874 |
break;
|
875 |
default:
|
876 |
printf("usb-ohci: Bad device response %d\n", ret);
|
877 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
878 |
OHCI_CC_UNDEXPETEDPID); |
879 |
break;
|
880 |
} |
881 |
} |
882 |
} |
883 |
|
884 |
if (relative_frame_number == frame_count) {
|
885 |
/* Last data packet of ISO TD - retire the TD to the Done Queue */
|
886 |
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); |
887 |
ed->head &= ~OHCI_DPTR_MASK; |
888 |
ed->head |= (iso_td.next & OHCI_DPTR_MASK); |
889 |
iso_td.next = ohci->done; |
890 |
ohci->done = addr; |
891 |
i = OHCI_BM(iso_td.flags, TD_DI); |
892 |
if (i < ohci->done_count)
|
893 |
ohci->done_count = i; |
894 |
} |
895 |
ohci_put_iso_td(ohci, addr, &iso_td); |
896 |
return 1; |
897 |
} |
898 |
|
899 |
/* Service a transport descriptor.
|
900 |
Returns nonzero to terminate processing of this endpoint. */
|
901 |
|
902 |
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) |
903 |
{ |
904 |
int dir;
|
905 |
size_t len = 0, pktlen = 0; |
906 |
#ifdef DEBUG_PACKET
|
907 |
const char *str = NULL; |
908 |
#endif
|
909 |
int pid;
|
910 |
int ret;
|
911 |
int i;
|
912 |
USBDevice *dev; |
913 |
USBEndpoint *ep; |
914 |
struct ohci_td td;
|
915 |
uint32_t addr; |
916 |
int flag_r;
|
917 |
int completion;
|
918 |
|
919 |
addr = ed->head & OHCI_DPTR_MASK; |
920 |
/* See if this TD has already been submitted to the device. */
|
921 |
completion = (addr == ohci->async_td); |
922 |
if (completion && !ohci->async_complete) {
|
923 |
#ifdef DEBUG_PACKET
|
924 |
DPRINTF("Skipping async TD\n");
|
925 |
#endif
|
926 |
return 1; |
927 |
} |
928 |
if (!ohci_read_td(ohci, addr, &td)) {
|
929 |
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
|
930 |
return 0; |
931 |
} |
932 |
|
933 |
dir = OHCI_BM(ed->flags, ED_D); |
934 |
switch (dir) {
|
935 |
case OHCI_TD_DIR_OUT:
|
936 |
case OHCI_TD_DIR_IN:
|
937 |
/* Same value. */
|
938 |
break;
|
939 |
default:
|
940 |
dir = OHCI_BM(td.flags, TD_DP); |
941 |
break;
|
942 |
} |
943 |
|
944 |
switch (dir) {
|
945 |
case OHCI_TD_DIR_IN:
|
946 |
#ifdef DEBUG_PACKET
|
947 |
str = "in";
|
948 |
#endif
|
949 |
pid = USB_TOKEN_IN; |
950 |
break;
|
951 |
case OHCI_TD_DIR_OUT:
|
952 |
#ifdef DEBUG_PACKET
|
953 |
str = "out";
|
954 |
#endif
|
955 |
pid = USB_TOKEN_OUT; |
956 |
break;
|
957 |
case OHCI_TD_DIR_SETUP:
|
958 |
#ifdef DEBUG_PACKET
|
959 |
str = "setup";
|
960 |
#endif
|
961 |
pid = USB_TOKEN_SETUP; |
962 |
break;
|
963 |
default:
|
964 |
fprintf(stderr, "usb-ohci: Bad direction\n");
|
965 |
return 1; |
966 |
} |
967 |
if (td.cbp && td.be) {
|
968 |
if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
969 |
len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); |
970 |
} else {
|
971 |
len = (td.be - td.cbp) + 1;
|
972 |
} |
973 |
|
974 |
pktlen = len; |
975 |
if (len && dir != OHCI_TD_DIR_IN) {
|
976 |
/* The endpoint may not allow us to transfer it all now */
|
977 |
pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; |
978 |
if (pktlen > len) {
|
979 |
pktlen = len; |
980 |
} |
981 |
if (!completion) {
|
982 |
ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, |
983 |
DMA_DIRECTION_TO_DEVICE); |
984 |
} |
985 |
} |
986 |
} |
987 |
|
988 |
flag_r = (td.flags & OHCI_TD_R) != 0;
|
989 |
#ifdef DEBUG_PACKET
|
990 |
DPRINTF(" TD @ 0x%.8x %" PRId64 " of %" PRId64 |
991 |
" bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
|
992 |
addr, (int64_t)pktlen, (int64_t)len, str, flag_r, td.cbp, td.be); |
993 |
|
994 |
if (pktlen > 0 && dir != OHCI_TD_DIR_IN) { |
995 |
DPRINTF(" data:");
|
996 |
for (i = 0; i < pktlen; i++) { |
997 |
printf(" %.2x", ohci->usb_buf[i]);
|
998 |
} |
999 |
DPRINTF("\n");
|
1000 |
} |
1001 |
#endif
|
1002 |
if (completion) {
|
1003 |
ohci->async_td = 0;
|
1004 |
ohci->async_complete = 0;
|
1005 |
} else {
|
1006 |
if (ohci->async_td) {
|
1007 |
/* ??? The hardware should allow one active packet per
|
1008 |
endpoint. We only allow one active packet per controller.
|
1009 |
This should be sufficient as long as devices respond in a
|
1010 |
timely manner.
|
1011 |
*/
|
1012 |
#ifdef DEBUG_PACKET
|
1013 |
DPRINTF("Too many pending packets\n");
|
1014 |
#endif
|
1015 |
return 1; |
1016 |
} |
1017 |
dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); |
1018 |
ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); |
1019 |
usb_packet_setup(&ohci->usb_packet, pid, ep, addr, !flag_r, |
1020 |
OHCI_BM(td.flags, TD_DI) == 0);
|
1021 |
usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); |
1022 |
usb_handle_packet(dev, &ohci->usb_packet); |
1023 |
#ifdef DEBUG_PACKET
|
1024 |
DPRINTF("status=%d\n", ohci->usb_packet.status);
|
1025 |
#endif
|
1026 |
if (ohci->usb_packet.status == USB_RET_ASYNC) {
|
1027 |
usb_device_flush_ep_queue(dev, ep); |
1028 |
ohci->async_td = addr; |
1029 |
return 1; |
1030 |
} |
1031 |
} |
1032 |
if (ohci->usb_packet.status == USB_RET_SUCCESS) {
|
1033 |
ret = ohci->usb_packet.actual_length; |
1034 |
} else {
|
1035 |
ret = ohci->usb_packet.status; |
1036 |
} |
1037 |
|
1038 |
if (ret >= 0) { |
1039 |
if (dir == OHCI_TD_DIR_IN) {
|
1040 |
ohci_copy_td(ohci, &td, ohci->usb_buf, ret, |
1041 |
DMA_DIRECTION_FROM_DEVICE); |
1042 |
#ifdef DEBUG_PACKET
|
1043 |
DPRINTF(" data:");
|
1044 |
for (i = 0; i < ret; i++) |
1045 |
printf(" %.2x", ohci->usb_buf[i]);
|
1046 |
DPRINTF("\n");
|
1047 |
#endif
|
1048 |
} else {
|
1049 |
ret = pktlen; |
1050 |
} |
1051 |
} |
1052 |
|
1053 |
/* Writeback */
|
1054 |
if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { |
1055 |
/* Transmission succeeded. */
|
1056 |
if (ret == len) {
|
1057 |
td.cbp = 0;
|
1058 |
} else {
|
1059 |
if ((td.cbp & 0xfff) + ret > 0xfff) { |
1060 |
td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); |
1061 |
} else {
|
1062 |
td.cbp += ret; |
1063 |
} |
1064 |
} |
1065 |
td.flags |= OHCI_TD_T1; |
1066 |
td.flags ^= OHCI_TD_T0; |
1067 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); |
1068 |
OHCI_SET_BM(td.flags, TD_EC, 0);
|
1069 |
|
1070 |
if ((dir != OHCI_TD_DIR_IN) && (ret != len)) {
|
1071 |
/* Partial packet transfer: TD not ready to retire yet */
|
1072 |
goto exit_no_retire;
|
1073 |
} |
1074 |
|
1075 |
/* Setting ED_C is part of the TD retirement process */
|
1076 |
ed->head &= ~OHCI_ED_C; |
1077 |
if (td.flags & OHCI_TD_T0)
|
1078 |
ed->head |= OHCI_ED_C; |
1079 |
} else {
|
1080 |
if (ret >= 0) { |
1081 |
DPRINTF("usb-ohci: Underrun\n");
|
1082 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
1083 |
} else {
|
1084 |
switch (ret) {
|
1085 |
case USB_RET_IOERROR:
|
1086 |
case USB_RET_NODEV:
|
1087 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); |
1088 |
case USB_RET_NAK:
|
1089 |
DPRINTF("usb-ohci: got NAK\n");
|
1090 |
return 1; |
1091 |
case USB_RET_STALL:
|
1092 |
DPRINTF("usb-ohci: got STALL\n");
|
1093 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
1094 |
break;
|
1095 |
case USB_RET_BABBLE:
|
1096 |
DPRINTF("usb-ohci: got BABBLE\n");
|
1097 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
1098 |
break;
|
1099 |
default:
|
1100 |
fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
|
1101 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); |
1102 |
OHCI_SET_BM(td.flags, TD_EC, 3);
|
1103 |
break;
|
1104 |
} |
1105 |
} |
1106 |
ed->head |= OHCI_ED_H; |
1107 |
} |
1108 |
|
1109 |
/* Retire this TD */
|
1110 |
ed->head &= ~OHCI_DPTR_MASK; |
1111 |
ed->head |= td.next & OHCI_DPTR_MASK; |
1112 |
td.next = ohci->done; |
1113 |
ohci->done = addr; |
1114 |
i = OHCI_BM(td.flags, TD_DI); |
1115 |
if (i < ohci->done_count)
|
1116 |
ohci->done_count = i; |
1117 |
exit_no_retire:
|
1118 |
ohci_put_td(ohci, addr, &td); |
1119 |
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
|
1120 |
} |
1121 |
|
1122 |
/* Service an endpoint list. Returns nonzero if active TD were found. */
|
1123 |
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) |
1124 |
{ |
1125 |
struct ohci_ed ed;
|
1126 |
uint32_t next_ed; |
1127 |
uint32_t cur; |
1128 |
int active;
|
1129 |
|
1130 |
active = 0;
|
1131 |
|
1132 |
if (head == 0) |
1133 |
return 0; |
1134 |
|
1135 |
for (cur = head; cur; cur = next_ed) {
|
1136 |
if (!ohci_read_ed(ohci, cur, &ed)) {
|
1137 |
fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
|
1138 |
return 0; |
1139 |
} |
1140 |
|
1141 |
next_ed = ed.next & OHCI_DPTR_MASK; |
1142 |
|
1143 |
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
|
1144 |
uint32_t addr; |
1145 |
/* Cancel pending packets for ED that have been paused. */
|
1146 |
addr = ed.head & OHCI_DPTR_MASK; |
1147 |
if (ohci->async_td && addr == ohci->async_td) {
|
1148 |
usb_cancel_packet(&ohci->usb_packet); |
1149 |
ohci->async_td = 0;
|
1150 |
} |
1151 |
continue;
|
1152 |
} |
1153 |
|
1154 |
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
|
1155 |
#ifdef DEBUG_PACKET
|
1156 |
DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
|
1157 |
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
|
1158 |
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), |
1159 |
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
|
1160 |
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, |
1161 |
OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
|
1162 |
(ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
|
1163 |
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); |
1164 |
#endif
|
1165 |
active = 1;
|
1166 |
|
1167 |
if ((ed.flags & OHCI_ED_F) == 0) { |
1168 |
if (ohci_service_td(ohci, &ed))
|
1169 |
break;
|
1170 |
} else {
|
1171 |
/* Handle isochronous endpoints */
|
1172 |
if (ohci_service_iso_td(ohci, &ed, completion))
|
1173 |
break;
|
1174 |
} |
1175 |
} |
1176 |
|
1177 |
ohci_put_ed(ohci, cur, &ed); |
1178 |
} |
1179 |
|
1180 |
return active;
|
1181 |
} |
1182 |
|
1183 |
/* Generate a SOF event, and set a timer for EOF */
|
1184 |
static void ohci_sof(OHCIState *ohci) |
1185 |
{ |
1186 |
ohci->sof_time = qemu_get_clock_ns(vm_clock); |
1187 |
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); |
1188 |
ohci_set_interrupt(ohci, OHCI_INTR_SF); |
1189 |
} |
1190 |
|
1191 |
/* Process Control and Bulk lists. */
|
1192 |
static void ohci_process_lists(OHCIState *ohci, int completion) |
1193 |
{ |
1194 |
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
|
1195 |
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
|
1196 |
DPRINTF("usb-ohci: head %x, cur %x\n",
|
1197 |
ohci->ctrl_head, ohci->ctrl_cur); |
1198 |
} |
1199 |
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
|
1200 |
ohci->ctrl_cur = 0;
|
1201 |
ohci->status &= ~OHCI_STATUS_CLF; |
1202 |
} |
1203 |
} |
1204 |
|
1205 |
if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
|
1206 |
if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
|
1207 |
ohci->bulk_cur = 0;
|
1208 |
ohci->status &= ~OHCI_STATUS_BLF; |
1209 |
} |
1210 |
} |
1211 |
} |
1212 |
|
1213 |
/* Do frame processing on frame boundary */
|
1214 |
static void ohci_frame_boundary(void *opaque) |
1215 |
{ |
1216 |
OHCIState *ohci = opaque; |
1217 |
struct ohci_hcca hcca;
|
1218 |
|
1219 |
ohci_read_hcca(ohci, ohci->hcca, &hcca); |
1220 |
|
1221 |
/* Process all the lists at the end of the frame */
|
1222 |
if (ohci->ctl & OHCI_CTL_PLE) {
|
1223 |
int n;
|
1224 |
|
1225 |
n = ohci->frame_number & 0x1f;
|
1226 |
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
|
1227 |
} |
1228 |
|
1229 |
/* Cancel all pending packets if either of the lists has been disabled. */
|
1230 |
if (ohci->async_td &&
|
1231 |
ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { |
1232 |
usb_cancel_packet(&ohci->usb_packet); |
1233 |
ohci->async_td = 0;
|
1234 |
} |
1235 |
ohci->old_ctl = ohci->ctl; |
1236 |
ohci_process_lists(ohci, 0);
|
1237 |
|
1238 |
/* Frame boundary, so do EOF stuf here */
|
1239 |
ohci->frt = ohci->fit; |
1240 |
|
1241 |
/* Increment frame number and take care of endianness. */
|
1242 |
ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
1243 |
hcca.frame = cpu_to_le16(ohci->frame_number); |
1244 |
|
1245 |
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { |
1246 |
if (!ohci->done)
|
1247 |
abort(); |
1248 |
if (ohci->intr & ohci->intr_status)
|
1249 |
ohci->done |= 1;
|
1250 |
hcca.done = cpu_to_le32(ohci->done); |
1251 |
ohci->done = 0;
|
1252 |
ohci->done_count = 7;
|
1253 |
ohci_set_interrupt(ohci, OHCI_INTR_WD); |
1254 |
} |
1255 |
|
1256 |
if (ohci->done_count != 7 && ohci->done_count != 0) |
1257 |
ohci->done_count--; |
1258 |
|
1259 |
/* Do SOF stuff here */
|
1260 |
ohci_sof(ohci); |
1261 |
|
1262 |
/* Writeback HCCA */
|
1263 |
ohci_put_hcca(ohci, ohci->hcca, &hcca); |
1264 |
} |
1265 |
|
1266 |
/* Start sending SOF tokens across the USB bus, lists are processed in
|
1267 |
* next frame
|
1268 |
*/
|
1269 |
static int ohci_bus_start(OHCIState *ohci) |
1270 |
{ |
1271 |
ohci->eof_timer = qemu_new_timer_ns(vm_clock, |
1272 |
ohci_frame_boundary, |
1273 |
ohci); |
1274 |
|
1275 |
if (ohci->eof_timer == NULL) { |
1276 |
fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
|
1277 |
/* TODO: Signal unrecoverable error */
|
1278 |
return 0; |
1279 |
} |
1280 |
|
1281 |
DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
|
1282 |
|
1283 |
ohci_sof(ohci); |
1284 |
|
1285 |
return 1; |
1286 |
} |
1287 |
|
1288 |
/* Stop sending SOF tokens on the bus */
|
1289 |
static void ohci_bus_stop(OHCIState *ohci) |
1290 |
{ |
1291 |
if (ohci->eof_timer)
|
1292 |
qemu_del_timer(ohci->eof_timer); |
1293 |
ohci->eof_timer = NULL;
|
1294 |
} |
1295 |
|
1296 |
/* Sets a flag in a port status register but only set it if the port is
|
1297 |
* connected, if not set ConnectStatusChange flag. If flag is enabled
|
1298 |
* return 1.
|
1299 |
*/
|
1300 |
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) |
1301 |
{ |
1302 |
int ret = 1; |
1303 |
|
1304 |
/* writing a 0 has no effect */
|
1305 |
if (val == 0) |
1306 |
return 0; |
1307 |
|
1308 |
/* If CurrentConnectStatus is cleared we set
|
1309 |
* ConnectStatusChange
|
1310 |
*/
|
1311 |
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
|
1312 |
ohci->rhport[i].ctrl |= OHCI_PORT_CSC; |
1313 |
if (ohci->rhstatus & OHCI_RHS_DRWE) {
|
1314 |
/* TODO: CSC is a wakeup event */
|
1315 |
} |
1316 |
return 0; |
1317 |
} |
1318 |
|
1319 |
if (ohci->rhport[i].ctrl & val)
|
1320 |
ret = 0;
|
1321 |
|
1322 |
/* set the bit */
|
1323 |
ohci->rhport[i].ctrl |= val; |
1324 |
|
1325 |
return ret;
|
1326 |
} |
1327 |
|
1328 |
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
|
1329 |
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) |
1330 |
{ |
1331 |
val &= OHCI_FMI_FI; |
1332 |
|
1333 |
if (val != ohci->fi) {
|
1334 |
DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
|
1335 |
ohci->name, ohci->fi, ohci->fi); |
1336 |
} |
1337 |
|
1338 |
ohci->fi = val; |
1339 |
} |
1340 |
|
1341 |
static void ohci_port_power(OHCIState *ohci, int i, int p) |
1342 |
{ |
1343 |
if (p) {
|
1344 |
ohci->rhport[i].ctrl |= OHCI_PORT_PPS; |
1345 |
} else {
|
1346 |
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| |
1347 |
OHCI_PORT_CCS| |
1348 |
OHCI_PORT_PSS| |
1349 |
OHCI_PORT_PRS); |
1350 |
} |
1351 |
} |
1352 |
|
1353 |
/* Set HcControlRegister */
|
1354 |
static void ohci_set_ctl(OHCIState *ohci, uint32_t val) |
1355 |
{ |
1356 |
uint32_t old_state; |
1357 |
uint32_t new_state; |
1358 |
|
1359 |
old_state = ohci->ctl & OHCI_CTL_HCFS; |
1360 |
ohci->ctl = val; |
1361 |
new_state = ohci->ctl & OHCI_CTL_HCFS; |
1362 |
|
1363 |
/* no state change */
|
1364 |
if (old_state == new_state)
|
1365 |
return;
|
1366 |
|
1367 |
switch (new_state) {
|
1368 |
case OHCI_USB_OPERATIONAL:
|
1369 |
ohci_bus_start(ohci); |
1370 |
break;
|
1371 |
case OHCI_USB_SUSPEND:
|
1372 |
ohci_bus_stop(ohci); |
1373 |
DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
|
1374 |
break;
|
1375 |
case OHCI_USB_RESUME:
|
1376 |
DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
|
1377 |
break;
|
1378 |
case OHCI_USB_RESET:
|
1379 |
ohci_reset(ohci); |
1380 |
DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
|
1381 |
break;
|
1382 |
} |
1383 |
} |
1384 |
|
1385 |
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
|
1386 |
{ |
1387 |
uint16_t fr; |
1388 |
int64_t tks; |
1389 |
|
1390 |
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
|
1391 |
return (ohci->frt << 31); |
1392 |
|
1393 |
/* Being in USB operational state guarnatees sof_time was
|
1394 |
* set already.
|
1395 |
*/
|
1396 |
tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time; |
1397 |
|
1398 |
/* avoid muldiv if possible */
|
1399 |
if (tks >= usb_frame_time)
|
1400 |
return (ohci->frt << 31); |
1401 |
|
1402 |
tks = muldiv64(1, tks, usb_bit_time);
|
1403 |
fr = (uint16_t)(ohci->fi - tks); |
1404 |
|
1405 |
return (ohci->frt << 31) | fr; |
1406 |
} |
1407 |
|
1408 |
|
1409 |
/* Set root hub status */
|
1410 |
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) |
1411 |
{ |
1412 |
uint32_t old_state; |
1413 |
|
1414 |
old_state = ohci->rhstatus; |
1415 |
|
1416 |
/* write 1 to clear OCIC */
|
1417 |
if (val & OHCI_RHS_OCIC)
|
1418 |
ohci->rhstatus &= ~OHCI_RHS_OCIC; |
1419 |
|
1420 |
if (val & OHCI_RHS_LPS) {
|
1421 |
int i;
|
1422 |
|
1423 |
for (i = 0; i < ohci->num_ports; i++) |
1424 |
ohci_port_power(ohci, i, 0);
|
1425 |
DPRINTF("usb-ohci: powered down all ports\n");
|
1426 |
} |
1427 |
|
1428 |
if (val & OHCI_RHS_LPSC) {
|
1429 |
int i;
|
1430 |
|
1431 |
for (i = 0; i < ohci->num_ports; i++) |
1432 |
ohci_port_power(ohci, i, 1);
|
1433 |
DPRINTF("usb-ohci: powered up all ports\n");
|
1434 |
} |
1435 |
|
1436 |
if (val & OHCI_RHS_DRWE)
|
1437 |
ohci->rhstatus |= OHCI_RHS_DRWE; |
1438 |
|
1439 |
if (val & OHCI_RHS_CRWE)
|
1440 |
ohci->rhstatus &= ~OHCI_RHS_DRWE; |
1441 |
|
1442 |
if (old_state != ohci->rhstatus)
|
1443 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
1444 |
} |
1445 |
|
1446 |
/* Set root hub port status */
|
1447 |
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) |
1448 |
{ |
1449 |
uint32_t old_state; |
1450 |
OHCIPort *port; |
1451 |
|
1452 |
port = &ohci->rhport[portnum]; |
1453 |
old_state = port->ctrl; |
1454 |
|
1455 |
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
|
1456 |
if (val & OHCI_PORT_WTC)
|
1457 |
port->ctrl &= ~(val & OHCI_PORT_WTC); |
1458 |
|
1459 |
if (val & OHCI_PORT_CCS)
|
1460 |
port->ctrl &= ~OHCI_PORT_PES; |
1461 |
|
1462 |
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); |
1463 |
|
1464 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
|
1465 |
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
|
1466 |
} |
1467 |
|
1468 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
|
1469 |
DPRINTF("usb-ohci: port %d: RESET\n", portnum);
|
1470 |
usb_device_reset(port->port.dev); |
1471 |
port->ctrl &= ~OHCI_PORT_PRS; |
1472 |
/* ??? Should this also set OHCI_PORT_PESC. */
|
1473 |
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; |
1474 |
} |
1475 |
|
1476 |
/* Invert order here to ensure in ambiguous case, device is
|
1477 |
* powered up...
|
1478 |
*/
|
1479 |
if (val & OHCI_PORT_LSDA)
|
1480 |
ohci_port_power(ohci, portnum, 0);
|
1481 |
if (val & OHCI_PORT_PPS)
|
1482 |
ohci_port_power(ohci, portnum, 1);
|
1483 |
|
1484 |
if (old_state != port->ctrl)
|
1485 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
1486 |
} |
1487 |
|
1488 |
static uint64_t ohci_mem_read(void *opaque, |
1489 |
hwaddr addr, |
1490 |
unsigned size)
|
1491 |
{ |
1492 |
OHCIState *ohci = opaque; |
1493 |
uint32_t retval; |
1494 |
|
1495 |
/* Only aligned reads are allowed on OHCI */
|
1496 |
if (addr & 3) { |
1497 |
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
|
1498 |
return 0xffffffff; |
1499 |
} else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1500 |
/* HcRhPortStatus */
|
1501 |
retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
1502 |
} else {
|
1503 |
switch (addr >> 2) { |
1504 |
case 0: /* HcRevision */ |
1505 |
retval = 0x10;
|
1506 |
break;
|
1507 |
|
1508 |
case 1: /* HcControl */ |
1509 |
retval = ohci->ctl; |
1510 |
break;
|
1511 |
|
1512 |
case 2: /* HcCommandStatus */ |
1513 |
retval = ohci->status; |
1514 |
break;
|
1515 |
|
1516 |
case 3: /* HcInterruptStatus */ |
1517 |
retval = ohci->intr_status; |
1518 |
break;
|
1519 |
|
1520 |
case 4: /* HcInterruptEnable */ |
1521 |
case 5: /* HcInterruptDisable */ |
1522 |
retval = ohci->intr; |
1523 |
break;
|
1524 |
|
1525 |
case 6: /* HcHCCA */ |
1526 |
retval = ohci->hcca; |
1527 |
break;
|
1528 |
|
1529 |
case 7: /* HcPeriodCurrentED */ |
1530 |
retval = ohci->per_cur; |
1531 |
break;
|
1532 |
|
1533 |
case 8: /* HcControlHeadED */ |
1534 |
retval = ohci->ctrl_head; |
1535 |
break;
|
1536 |
|
1537 |
case 9: /* HcControlCurrentED */ |
1538 |
retval = ohci->ctrl_cur; |
1539 |
break;
|
1540 |
|
1541 |
case 10: /* HcBulkHeadED */ |
1542 |
retval = ohci->bulk_head; |
1543 |
break;
|
1544 |
|
1545 |
case 11: /* HcBulkCurrentED */ |
1546 |
retval = ohci->bulk_cur; |
1547 |
break;
|
1548 |
|
1549 |
case 12: /* HcDoneHead */ |
1550 |
retval = ohci->done; |
1551 |
break;
|
1552 |
|
1553 |
case 13: /* HcFmInterretval */ |
1554 |
retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); |
1555 |
break;
|
1556 |
|
1557 |
case 14: /* HcFmRemaining */ |
1558 |
retval = ohci_get_frame_remaining(ohci); |
1559 |
break;
|
1560 |
|
1561 |
case 15: /* HcFmNumber */ |
1562 |
retval = ohci->frame_number; |
1563 |
break;
|
1564 |
|
1565 |
case 16: /* HcPeriodicStart */ |
1566 |
retval = ohci->pstart; |
1567 |
break;
|
1568 |
|
1569 |
case 17: /* HcLSThreshold */ |
1570 |
retval = ohci->lst; |
1571 |
break;
|
1572 |
|
1573 |
case 18: /* HcRhDescriptorA */ |
1574 |
retval = ohci->rhdesc_a; |
1575 |
break;
|
1576 |
|
1577 |
case 19: /* HcRhDescriptorB */ |
1578 |
retval = ohci->rhdesc_b; |
1579 |
break;
|
1580 |
|
1581 |
case 20: /* HcRhStatus */ |
1582 |
retval = ohci->rhstatus; |
1583 |
break;
|
1584 |
|
1585 |
/* PXA27x specific registers */
|
1586 |
case 24: /* HcStatus */ |
1587 |
retval = ohci->hstatus & ohci->hmask; |
1588 |
break;
|
1589 |
|
1590 |
case 25: /* HcHReset */ |
1591 |
retval = ohci->hreset; |
1592 |
break;
|
1593 |
|
1594 |
case 26: /* HcHInterruptEnable */ |
1595 |
retval = ohci->hmask; |
1596 |
break;
|
1597 |
|
1598 |
case 27: /* HcHInterruptTest */ |
1599 |
retval = ohci->htest; |
1600 |
break;
|
1601 |
|
1602 |
default:
|
1603 |
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); |
1604 |
retval = 0xffffffff;
|
1605 |
} |
1606 |
} |
1607 |
|
1608 |
return retval;
|
1609 |
} |
1610 |
|
1611 |
static void ohci_mem_write(void *opaque, |
1612 |
hwaddr addr, |
1613 |
uint64_t val, |
1614 |
unsigned size)
|
1615 |
{ |
1616 |
OHCIState *ohci = opaque; |
1617 |
|
1618 |
/* Only aligned reads are allowed on OHCI */
|
1619 |
if (addr & 3) { |
1620 |
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
|
1621 |
return;
|
1622 |
} |
1623 |
|
1624 |
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1625 |
/* HcRhPortStatus */
|
1626 |
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); |
1627 |
return;
|
1628 |
} |
1629 |
|
1630 |
switch (addr >> 2) { |
1631 |
case 1: /* HcControl */ |
1632 |
ohci_set_ctl(ohci, val); |
1633 |
break;
|
1634 |
|
1635 |
case 2: /* HcCommandStatus */ |
1636 |
/* SOC is read-only */
|
1637 |
val = (val & ~OHCI_STATUS_SOC); |
1638 |
|
1639 |
/* Bits written as '0' remain unchanged in the register */
|
1640 |
ohci->status |= val; |
1641 |
|
1642 |
if (ohci->status & OHCI_STATUS_HCR)
|
1643 |
ohci_reset(ohci); |
1644 |
break;
|
1645 |
|
1646 |
case 3: /* HcInterruptStatus */ |
1647 |
ohci->intr_status &= ~val; |
1648 |
ohci_intr_update(ohci); |
1649 |
break;
|
1650 |
|
1651 |
case 4: /* HcInterruptEnable */ |
1652 |
ohci->intr |= val; |
1653 |
ohci_intr_update(ohci); |
1654 |
break;
|
1655 |
|
1656 |
case 5: /* HcInterruptDisable */ |
1657 |
ohci->intr &= ~val; |
1658 |
ohci_intr_update(ohci); |
1659 |
break;
|
1660 |
|
1661 |
case 6: /* HcHCCA */ |
1662 |
ohci->hcca = val & OHCI_HCCA_MASK; |
1663 |
break;
|
1664 |
|
1665 |
case 7: /* HcPeriodCurrentED */ |
1666 |
/* Ignore writes to this read-only register, Linux does them */
|
1667 |
break;
|
1668 |
|
1669 |
case 8: /* HcControlHeadED */ |
1670 |
ohci->ctrl_head = val & OHCI_EDPTR_MASK; |
1671 |
break;
|
1672 |
|
1673 |
case 9: /* HcControlCurrentED */ |
1674 |
ohci->ctrl_cur = val & OHCI_EDPTR_MASK; |
1675 |
break;
|
1676 |
|
1677 |
case 10: /* HcBulkHeadED */ |
1678 |
ohci->bulk_head = val & OHCI_EDPTR_MASK; |
1679 |
break;
|
1680 |
|
1681 |
case 11: /* HcBulkCurrentED */ |
1682 |
ohci->bulk_cur = val & OHCI_EDPTR_MASK; |
1683 |
break;
|
1684 |
|
1685 |
case 13: /* HcFmInterval */ |
1686 |
ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
|
1687 |
ohci->fit = (val & OHCI_FMI_FIT) >> 31;
|
1688 |
ohci_set_frame_interval(ohci, val); |
1689 |
break;
|
1690 |
|
1691 |
case 15: /* HcFmNumber */ |
1692 |
break;
|
1693 |
|
1694 |
case 16: /* HcPeriodicStart */ |
1695 |
ohci->pstart = val & 0xffff;
|
1696 |
break;
|
1697 |
|
1698 |
case 17: /* HcLSThreshold */ |
1699 |
ohci->lst = val & 0xffff;
|
1700 |
break;
|
1701 |
|
1702 |
case 18: /* HcRhDescriptorA */ |
1703 |
ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; |
1704 |
ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; |
1705 |
break;
|
1706 |
|
1707 |
case 19: /* HcRhDescriptorB */ |
1708 |
break;
|
1709 |
|
1710 |
case 20: /* HcRhStatus */ |
1711 |
ohci_set_hub_status(ohci, val); |
1712 |
break;
|
1713 |
|
1714 |
/* PXA27x specific registers */
|
1715 |
case 24: /* HcStatus */ |
1716 |
ohci->hstatus &= ~(val & ohci->hmask); |
1717 |
|
1718 |
case 25: /* HcHReset */ |
1719 |
ohci->hreset = val & ~OHCI_HRESET_FSBIR; |
1720 |
if (val & OHCI_HRESET_FSBIR)
|
1721 |
ohci_reset(ohci); |
1722 |
break;
|
1723 |
|
1724 |
case 26: /* HcHInterruptEnable */ |
1725 |
ohci->hmask = val; |
1726 |
break;
|
1727 |
|
1728 |
case 27: /* HcHInterruptTest */ |
1729 |
ohci->htest = val; |
1730 |
break;
|
1731 |
|
1732 |
default:
|
1733 |
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr); |
1734 |
break;
|
1735 |
} |
1736 |
} |
1737 |
|
1738 |
static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) |
1739 |
{ |
1740 |
if (ohci->async_td &&
|
1741 |
usb_packet_is_inflight(&ohci->usb_packet) && |
1742 |
ohci->usb_packet.ep->dev == dev) { |
1743 |
usb_cancel_packet(&ohci->usb_packet); |
1744 |
ohci->async_td = 0;
|
1745 |
} |
1746 |
} |
1747 |
|
1748 |
static const MemoryRegionOps ohci_mem_ops = { |
1749 |
.read = ohci_mem_read, |
1750 |
.write = ohci_mem_write, |
1751 |
.endianness = DEVICE_LITTLE_ENDIAN, |
1752 |
}; |
1753 |
|
1754 |
static USBPortOps ohci_port_ops = {
|
1755 |
.attach = ohci_attach, |
1756 |
.detach = ohci_detach, |
1757 |
.child_detach = ohci_child_detach, |
1758 |
.wakeup = ohci_wakeup, |
1759 |
.complete = ohci_async_complete_packet, |
1760 |
}; |
1761 |
|
1762 |
static USBBusOps ohci_bus_ops = {
|
1763 |
}; |
1764 |
|
1765 |
static int usb_ohci_init(OHCIState *ohci, DeviceState *dev, |
1766 |
int num_ports, dma_addr_t localmem_base,
|
1767 |
char *masterbus, uint32_t firstport,
|
1768 |
DMAContext *dma) |
1769 |
{ |
1770 |
int i;
|
1771 |
|
1772 |
ohci->dma = dma; |
1773 |
|
1774 |
if (usb_frame_time == 0) { |
1775 |
#ifdef OHCI_TIME_WARP
|
1776 |
usb_frame_time = get_ticks_per_sec(); |
1777 |
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); |
1778 |
#else
|
1779 |
usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); |
1780 |
if (get_ticks_per_sec() >= USB_HZ) {
|
1781 |
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
|
1782 |
} else {
|
1783 |
usb_bit_time = 1;
|
1784 |
} |
1785 |
#endif
|
1786 |
DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n", |
1787 |
usb_frame_time, usb_bit_time); |
1788 |
} |
1789 |
|
1790 |
ohci->num_ports = num_ports; |
1791 |
if (masterbus) {
|
1792 |
USBPort *ports[OHCI_MAX_PORTS]; |
1793 |
for(i = 0; i < num_ports; i++) { |
1794 |
ports[i] = &ohci->rhport[i].port; |
1795 |
} |
1796 |
if (usb_register_companion(masterbus, ports, num_ports,
|
1797 |
firstport, ohci, &ohci_port_ops, |
1798 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
|
1799 |
return -1; |
1800 |
} |
1801 |
} else {
|
1802 |
usb_bus_new(&ohci->bus, &ohci_bus_ops, dev); |
1803 |
for (i = 0; i < num_ports; i++) { |
1804 |
usb_register_port(&ohci->bus, &ohci->rhport[i].port, |
1805 |
ohci, i, &ohci_port_ops, |
1806 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
1807 |
} |
1808 |
} |
1809 |
|
1810 |
memory_region_init_io(&ohci->mem, &ohci_mem_ops, ohci, "ohci", 256); |
1811 |
ohci->localmem_base = localmem_base; |
1812 |
|
1813 |
ohci->name = object_get_typename(OBJECT(dev)); |
1814 |
usb_packet_init(&ohci->usb_packet); |
1815 |
|
1816 |
ohci->async_td = 0;
|
1817 |
qemu_register_reset(ohci_reset, ohci); |
1818 |
|
1819 |
return 0; |
1820 |
} |
1821 |
|
1822 |
typedef struct { |
1823 |
PCIDevice pci_dev; |
1824 |
OHCIState state; |
1825 |
char *masterbus;
|
1826 |
uint32_t num_ports; |
1827 |
uint32_t firstport; |
1828 |
} OHCIPCIState; |
1829 |
|
1830 |
static int usb_ohci_initfn_pci(struct PCIDevice *dev) |
1831 |
{ |
1832 |
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev); |
1833 |
|
1834 |
ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */ |
1835 |
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ |
1836 |
|
1837 |
if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0, |
1838 |
ohci->masterbus, ohci->firstport, |
1839 |
pci_dma_context(dev)) != 0) {
|
1840 |
return -1; |
1841 |
} |
1842 |
ohci->state.irq = ohci->pci_dev.irq[0];
|
1843 |
|
1844 |
/* TODO: avoid cast below by using dev */
|
1845 |
pci_register_bar(&ohci->pci_dev, 0, 0, &ohci->state.mem); |
1846 |
return 0; |
1847 |
} |
1848 |
|
1849 |
typedef struct { |
1850 |
SysBusDevice busdev; |
1851 |
OHCIState ohci; |
1852 |
uint32_t num_ports; |
1853 |
dma_addr_t dma_offset; |
1854 |
} OHCISysBusState; |
1855 |
|
1856 |
static int ohci_init_pxa(SysBusDevice *dev) |
1857 |
{ |
1858 |
OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev); |
1859 |
|
1860 |
/* Cannot fail as we pass NULL for masterbus */
|
1861 |
usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0, |
1862 |
&dma_context_memory); |
1863 |
sysbus_init_irq(dev, &s->ohci.irq); |
1864 |
sysbus_init_mmio(dev, &s->ohci.mem); |
1865 |
|
1866 |
return 0; |
1867 |
} |
1868 |
|
1869 |
static Property ohci_pci_properties[] = {
|
1870 |
DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
|
1871 |
DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), |
1872 |
DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), |
1873 |
DEFINE_PROP_END_OF_LIST(), |
1874 |
}; |
1875 |
|
1876 |
static void ohci_pci_class_init(ObjectClass *klass, void *data) |
1877 |
{ |
1878 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1879 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1880 |
|
1881 |
k->init = usb_ohci_initfn_pci; |
1882 |
k->vendor_id = PCI_VENDOR_ID_APPLE; |
1883 |
k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; |
1884 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1885 |
k->no_hotplug = 1;
|
1886 |
dc->desc = "Apple USB Controller";
|
1887 |
dc->props = ohci_pci_properties; |
1888 |
} |
1889 |
|
1890 |
static TypeInfo ohci_pci_info = {
|
1891 |
.name = "pci-ohci",
|
1892 |
.parent = TYPE_PCI_DEVICE, |
1893 |
.instance_size = sizeof(OHCIPCIState),
|
1894 |
.class_init = ohci_pci_class_init, |
1895 |
}; |
1896 |
|
1897 |
static Property ohci_sysbus_properties[] = {
|
1898 |
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), |
1899 |
DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 3), |
1900 |
DEFINE_PROP_END_OF_LIST(), |
1901 |
}; |
1902 |
|
1903 |
static void ohci_sysbus_class_init(ObjectClass *klass, void *data) |
1904 |
{ |
1905 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1906 |
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
1907 |
|
1908 |
sbc->init = ohci_init_pxa; |
1909 |
dc->desc = "OHCI USB Controller";
|
1910 |
dc->props = ohci_sysbus_properties; |
1911 |
} |
1912 |
|
1913 |
static TypeInfo ohci_sysbus_info = {
|
1914 |
.name = "sysbus-ohci",
|
1915 |
.parent = TYPE_SYS_BUS_DEVICE, |
1916 |
.instance_size = sizeof(OHCISysBusState),
|
1917 |
.class_init = ohci_sysbus_class_init, |
1918 |
}; |
1919 |
|
1920 |
static void ohci_register_types(void) |
1921 |
{ |
1922 |
type_register_static(&ohci_pci_info); |
1923 |
type_register_static(&ohci_sysbus_info); |
1924 |
} |
1925 |
|
1926 |
type_init(ohci_register_types) |